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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 22:31:08 2019 +0000
Revision:: 189:f392fc9709a3
Parent:: 187:0387e8f68319

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f1xx_hal_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief Header file of RCC HAL module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
<>	144:ef7eb2e8f9f7	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	37	#ifndef __STM32F1xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	38	#define __STM32F1xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	45	#include "stm32f1xx_hal_def.h"
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/** @addtogroup STM32F1xx_HAL_Driver
<>	144:ef7eb2e8f9f7	48	* @{
<>	144:ef7eb2e8f9f7	49	*/
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	/** @addtogroup RCC
<>	144:ef7eb2e8f9f7	52	* @{
<>	144:ef7eb2e8f9f7	53	*/
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/** @defgroup RCC_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	58	* @{
<>	144:ef7eb2e8f9f7	59	*/
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	/**
<>	144:ef7eb2e8f9f7	62	* @brief RCC PLL configuration structure definition
<>	144:ef7eb2e8f9f7	63	*/
<>	144:ef7eb2e8f9f7	64	typedef struct
<>	144:ef7eb2e8f9f7	65	{
<>	144:ef7eb2e8f9f7	66	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
<>	144:ef7eb2e8f9f7	67	This parameter can be a value of @ref RCC_PLL_Config */
<>	144:ef7eb2e8f9f7	68
<>	144:ef7eb2e8f9f7	69	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
<>	144:ef7eb2e8f9f7	70	This parameter must be a value of @ref RCC_PLL_Clock_Source */
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	73	This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
<>	144:ef7eb2e8f9f7	74	} RCC_PLLInitTypeDef;
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	/**
<>	144:ef7eb2e8f9f7	77	* @brief RCC System, AHB and APB busses clock configuration structure definition
<>	144:ef7eb2e8f9f7	78	*/
<>	144:ef7eb2e8f9f7	79	typedef struct
<>	144:ef7eb2e8f9f7	80	{
<>	144:ef7eb2e8f9f7	81	uint32_t ClockType; /*!< The clock to be configured.
<>	144:ef7eb2e8f9f7	82	This parameter can be a value of @ref RCC_System_Clock_Type */
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<>	144:ef7eb2e8f9f7	85	This parameter can be a value of @ref RCC_System_Clock_Source */
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	88	This parameter can be a value of @ref RCC_AHB_Clock_Source */
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	91	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	92
<>	144:ef7eb2e8f9f7	93	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	94	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	95	} RCC_ClkInitTypeDef;
<>	144:ef7eb2e8f9f7	96
<>	144:ef7eb2e8f9f7	97	/**
<>	144:ef7eb2e8f9f7	98	* @}
<>	144:ef7eb2e8f9f7	99	*/
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	102	/** @defgroup RCC_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	103	* @{
<>	144:ef7eb2e8f9f7	104	*/
<>	144:ef7eb2e8f9f7	105
<>	144:ef7eb2e8f9f7	106	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<>	144:ef7eb2e8f9f7	107	* @{
<>	144:ef7eb2e8f9f7	108	*/
<>	144:ef7eb2e8f9f7	109
AnnaBridge	165:e614a9f1c9e2	110	#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /!< HSI clock divided by 2 selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	111	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE clock selected as PLL entry clock source /
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	/**
<>	144:ef7eb2e8f9f7	114	* @}
<>	144:ef7eb2e8f9f7	115	*/
<>	144:ef7eb2e8f9f7	116
<>	144:ef7eb2e8f9f7	117	/** @defgroup RCC_Oscillator_Type Oscillator Type
<>	144:ef7eb2e8f9f7	118	* @{
<>	144:ef7eb2e8f9f7	119	*/
AnnaBridge	165:e614a9f1c9e2	120	#define RCC_OSCILLATORTYPE_NONE 0x00000000U
AnnaBridge	165:e614a9f1c9e2	121	#define RCC_OSCILLATORTYPE_HSE 0x00000001U
AnnaBridge	165:e614a9f1c9e2	122	#define RCC_OSCILLATORTYPE_HSI 0x00000002U
AnnaBridge	165:e614a9f1c9e2	123	#define RCC_OSCILLATORTYPE_LSE 0x00000004U
AnnaBridge	165:e614a9f1c9e2	124	#define RCC_OSCILLATORTYPE_LSI 0x00000008U
<>	144:ef7eb2e8f9f7	125	/**
<>	144:ef7eb2e8f9f7	126	* @}
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/** @defgroup RCC_HSE_Config HSE Config
<>	144:ef7eb2e8f9f7	130	* @{
<>	144:ef7eb2e8f9f7	131	*/
AnnaBridge	165:e614a9f1c9e2	132	#define RCC_HSE_OFF 0x00000000U /!< HSE clock deactivation /
<>	144:ef7eb2e8f9f7	133	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
<>	144:ef7eb2e8f9f7	134	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
<>	144:ef7eb2e8f9f7	135	/**
<>	144:ef7eb2e8f9f7	136	* @}
<>	144:ef7eb2e8f9f7	137	*/
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	/** @defgroup RCC_LSE_Config LSE Config
<>	144:ef7eb2e8f9f7	140	* @{
<>	144:ef7eb2e8f9f7	141	*/
AnnaBridge	165:e614a9f1c9e2	142	#define RCC_LSE_OFF 0x00000000U /!< LSE clock deactivation /
AnnaBridge	165:e614a9f1c9e2	143	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
<>	144:ef7eb2e8f9f7	144	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	/**
<>	144:ef7eb2e8f9f7	147	* @}
<>	144:ef7eb2e8f9f7	148	*/
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	/** @defgroup RCC_HSI_Config HSI Config
<>	144:ef7eb2e8f9f7	151	* @{
<>	144:ef7eb2e8f9f7	152	*/
AnnaBridge	165:e614a9f1c9e2	153	#define RCC_HSI_OFF 0x00000000U /!< HSI clock deactivation /
<>	144:ef7eb2e8f9f7	154	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
<>	144:ef7eb2e8f9f7	155
AnnaBridge	165:e614a9f1c9e2	156	#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
<>	144:ef7eb2e8f9f7	157
<>	144:ef7eb2e8f9f7	158	/**
<>	144:ef7eb2e8f9f7	159	* @}
<>	144:ef7eb2e8f9f7	160	*/
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	/** @defgroup RCC_LSI_Config LSI Config
<>	144:ef7eb2e8f9f7	163	* @{
<>	144:ef7eb2e8f9f7	164	*/
AnnaBridge	165:e614a9f1c9e2	165	#define RCC_LSI_OFF 0x00000000U /!< LSI clock deactivation /
<>	144:ef7eb2e8f9f7	166	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	/**
<>	144:ef7eb2e8f9f7	169	* @}
<>	144:ef7eb2e8f9f7	170	*/
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	/** @defgroup RCC_PLL_Config PLL Config
<>	144:ef7eb2e8f9f7	173	* @{
<>	144:ef7eb2e8f9f7	174	*/
AnnaBridge	165:e614a9f1c9e2	175	#define RCC_PLL_NONE 0x00000000U /!< PLL is not configured /
AnnaBridge	165:e614a9f1c9e2	176	#define RCC_PLL_OFF 0x00000001U /!< PLL deactivation /
AnnaBridge	165:e614a9f1c9e2	177	#define RCC_PLL_ON 0x00000002U /!< PLL activation /
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	/**
<>	144:ef7eb2e8f9f7	180	* @}
<>	144:ef7eb2e8f9f7	181	*/
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	/** @defgroup RCC_System_Clock_Type System Clock Type
<>	144:ef7eb2e8f9f7	184	* @{
<>	144:ef7eb2e8f9f7	185	*/
AnnaBridge	165:e614a9f1c9e2	186	#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /!< SYSCLK to configure /
AnnaBridge	165:e614a9f1c9e2	187	#define RCC_CLOCKTYPE_HCLK 0x00000002U /!< HCLK to configure /
AnnaBridge	165:e614a9f1c9e2	188	#define RCC_CLOCKTYPE_PCLK1 0x00000004U /!< PCLK1 to configure /
AnnaBridge	165:e614a9f1c9e2	189	#define RCC_CLOCKTYPE_PCLK2 0x00000008U /!< PCLK2 to configure /
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	/**
<>	144:ef7eb2e8f9f7	192	* @}
<>	144:ef7eb2e8f9f7	193	*/
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	/** @defgroup RCC_System_Clock_Source System Clock Source
<>	144:ef7eb2e8f9f7	196	* @{
<>	144:ef7eb2e8f9f7	197	*/
<>	144:ef7eb2e8f9f7	198	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
<>	144:ef7eb2e8f9f7	199	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
<>	144:ef7eb2e8f9f7	200	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	/**
<>	144:ef7eb2e8f9f7	203	* @}
<>	144:ef7eb2e8f9f7	204	*/
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
<>	144:ef7eb2e8f9f7	207	* @{
<>	144:ef7eb2e8f9f7	208	*/
<>	144:ef7eb2e8f9f7	209	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	144:ef7eb2e8f9f7	210	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	144:ef7eb2e8f9f7	211	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	212
<>	144:ef7eb2e8f9f7	213	/**
<>	144:ef7eb2e8f9f7	214	* @}
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
<>	144:ef7eb2e8f9f7	218	* @{
<>	144:ef7eb2e8f9f7	219	*/
<>	144:ef7eb2e8f9f7	220	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	144:ef7eb2e8f9f7	221	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	144:ef7eb2e8f9f7	222	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	144:ef7eb2e8f9f7	223	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	144:ef7eb2e8f9f7	224	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	144:ef7eb2e8f9f7	225	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	144:ef7eb2e8f9f7	226	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	144:ef7eb2e8f9f7	227	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	144:ef7eb2e8f9f7	228	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	144:ef7eb2e8f9f7	229
<>	144:ef7eb2e8f9f7	230	/**
<>	144:ef7eb2e8f9f7	231	* @}
<>	144:ef7eb2e8f9f7	232	*/
<>	144:ef7eb2e8f9f7	233
<>	144:ef7eb2e8f9f7	234	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
<>	144:ef7eb2e8f9f7	235	* @{
<>	144:ef7eb2e8f9f7	236	*/
<>	144:ef7eb2e8f9f7	237	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
<>	144:ef7eb2e8f9f7	238	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
<>	144:ef7eb2e8f9f7	239	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
<>	144:ef7eb2e8f9f7	240	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
<>	144:ef7eb2e8f9f7	241	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	/**
<>	144:ef7eb2e8f9f7	244	* @}
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246
<>	144:ef7eb2e8f9f7	247	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
<>	144:ef7eb2e8f9f7	248	* @{
<>	144:ef7eb2e8f9f7	249	*/
AnnaBridge	165:e614a9f1c9e2	250	#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /!< No clock /
<>	144:ef7eb2e8f9f7	251	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	252	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
<>	144:ef7eb2e8f9f7	253	#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /!< HSE oscillator clock divided by 128 used as RTC clock /
<>	144:ef7eb2e8f9f7	254	/**
<>	144:ef7eb2e8f9f7	255	* @}
<>	144:ef7eb2e8f9f7	256	*/
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258
<>	144:ef7eb2e8f9f7	259	/** @defgroup RCC_MCO_Index MCO Index
<>	144:ef7eb2e8f9f7	260	* @{
<>	144:ef7eb2e8f9f7	261	*/
AnnaBridge	165:e614a9f1c9e2	262	#define RCC_MCO1 0x00000000U
<>	144:ef7eb2e8f9f7	263	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
<>	144:ef7eb2e8f9f7	264
<>	144:ef7eb2e8f9f7	265	/**
<>	144:ef7eb2e8f9f7	266	* @}
<>	144:ef7eb2e8f9f7	267	*/
<>	144:ef7eb2e8f9f7	268
<>	144:ef7eb2e8f9f7	269	/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
<>	144:ef7eb2e8f9f7	270	* @{
<>	144:ef7eb2e8f9f7	271	*/
AnnaBridge	165:e614a9f1c9e2	272	#define RCC_MCODIV_1 0x00000000U
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/**
<>	144:ef7eb2e8f9f7	275	* @}
<>	144:ef7eb2e8f9f7	276	*/
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278	/** @defgroup RCC_Interrupt Interrupts
<>	144:ef7eb2e8f9f7	279	* @{
<>	144:ef7eb2e8f9f7	280	*/
<>	144:ef7eb2e8f9f7	281	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	282	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	283	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	284	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	285	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
<>	144:ef7eb2e8f9f7	286	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
<>	144:ef7eb2e8f9f7	287	/**
<>	144:ef7eb2e8f9f7	288	* @}
<>	144:ef7eb2e8f9f7	289	*/
<>	144:ef7eb2e8f9f7	290
<>	144:ef7eb2e8f9f7	291	/** @defgroup RCC_Flag Flags
<>	144:ef7eb2e8f9f7	292	* Elements values convention: XXXYYYYYb
<>	144:ef7eb2e8f9f7	293	* - YYYYY : Flag position in the register
<>	144:ef7eb2e8f9f7	294	* - XXX : Register index
<>	144:ef7eb2e8f9f7	295	* - 001: CR register
<>	144:ef7eb2e8f9f7	296	* - 010: BDCR register
<>	144:ef7eb2e8f9f7	297	* - 011: CSR register
<>	144:ef7eb2e8f9f7	298	* @{
<>	144:ef7eb2e8f9f7	299	*/
<>	144:ef7eb2e8f9f7	300	/* Flags in the CR register */
AnnaBridge	165:e614a9f1c9e2	301	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSIRDY_Pos)) /!< Internal High Speed clock ready flag /
AnnaBridge	165:e614a9f1c9e2	302	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSERDY_Pos)) /!< External High Speed clock ready flag /
AnnaBridge	165:e614a9f1c9e2	303	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_PLLRDY_Pos)) /!< PLL clock ready flag /
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	/* Flags in the CSR register */
AnnaBridge	165:e614a9f1c9e2	306	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LSIRDY_Pos)) /!< Internal Low Speed oscillator Ready /
AnnaBridge	165:e614a9f1c9e2	307	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PINRSTF_Pos)) /!< PIN reset flag /
AnnaBridge	165:e614a9f1c9e2	308	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PORRSTF_Pos)) /!< POR/PDR reset flag /
AnnaBridge	165:e614a9f1c9e2	309	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_SFTRSTF_Pos)) /!< Software Reset flag /
AnnaBridge	165:e614a9f1c9e2	310	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_IWDGRSTF_Pos)) /!< Independent Watchdog reset flag /
AnnaBridge	165:e614a9f1c9e2	311	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_WWDGRSTF_Pos)) /!< Window watchdog reset flag /
AnnaBridge	165:e614a9f1c9e2	312	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LPWRRSTF_Pos)) /!< Low-Power reset flag /
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Flags in the BDCR register */
AnnaBridge	165:e614a9f1c9e2	315	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) \| RCC_BDCR_LSERDY_Pos)) /!< External Low Speed oscillator Ready /
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/**
<>	144:ef7eb2e8f9f7	318	* @}
<>	144:ef7eb2e8f9f7	319	*/
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/**
<>	144:ef7eb2e8f9f7	322	* @}
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	326
<>	144:ef7eb2e8f9f7	327	/** @defgroup RCC_Exported_Macros RCC Exported Macros
<>	144:ef7eb2e8f9f7	328	* @{
<>	144:ef7eb2e8f9f7	329	*/
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	332	* @brief Enable or disable the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	333	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	334	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	335	* using it.
<>	144:ef7eb2e8f9f7	336	* @{
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	339	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	340	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	341	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	342	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	343	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	344	} while(0U)
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	347	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	348	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
<>	144:ef7eb2e8f9f7	349	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	350	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
<>	144:ef7eb2e8f9f7	351	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	352	} while(0U)
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	355	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	356	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
<>	144:ef7eb2e8f9f7	357	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	358	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
<>	144:ef7eb2e8f9f7	359	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	360	} while(0U)
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	363	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	364	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<>	144:ef7eb2e8f9f7	365	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	366	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<>	144:ef7eb2e8f9f7	367	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	368	} while(0U)
<>	144:ef7eb2e8f9f7	369
<>	144:ef7eb2e8f9f7	370	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
<>	144:ef7eb2e8f9f7	371	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
<>	144:ef7eb2e8f9f7	372	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
<>	144:ef7eb2e8f9f7	373	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	/**
<>	144:ef7eb2e8f9f7	376	* @}
<>	144:ef7eb2e8f9f7	377	*/
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	380	* @brief Get the enable or disable status of the AHB peripheral clock.
<>	144:ef7eb2e8f9f7	381	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	382	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	383	* using it.
<>	144:ef7eb2e8f9f7	384	* @{
<>	144:ef7eb2e8f9f7	385	*/
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
<>	144:ef7eb2e8f9f7	388	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
<>	144:ef7eb2e8f9f7	389	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
<>	144:ef7eb2e8f9f7	390	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
<>	144:ef7eb2e8f9f7	391	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
<>	144:ef7eb2e8f9f7	392	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
<>	144:ef7eb2e8f9f7	393	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
<>	144:ef7eb2e8f9f7	394	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/**
<>	144:ef7eb2e8f9f7	397	* @}
<>	144:ef7eb2e8f9f7	398	*/
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
<>	144:ef7eb2e8f9f7	401	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<>	144:ef7eb2e8f9f7	402	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	403	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	404	* using it.
<>	144:ef7eb2e8f9f7	405	* @{
<>	144:ef7eb2e8f9f7	406	*/
<>	144:ef7eb2e8f9f7	407	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	408	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	409	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<>	144:ef7eb2e8f9f7	410	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	411	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<>	144:ef7eb2e8f9f7	412	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	413	} while(0U)
<>	144:ef7eb2e8f9f7	414
<>	144:ef7eb2e8f9f7	415	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	416	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	417	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<>	144:ef7eb2e8f9f7	418	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	419	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<>	144:ef7eb2e8f9f7	420	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	421	} while(0U)
<>	144:ef7eb2e8f9f7	422
<>	144:ef7eb2e8f9f7	423	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	424	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	425	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	426	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	427	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	428	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	429	} while(0U)
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	432	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	433	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	434	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	435	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	436	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	437	} while(0U)
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	440	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	441	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	442	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	443	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	444	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	445	} while(0U)
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	#define __HAL_RCC_BKP_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	448	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	449	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
<>	144:ef7eb2e8f9f7	450	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	451	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
<>	144:ef7eb2e8f9f7	452	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	453	} while(0U)
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	456	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	457	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	458	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	459	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	460	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	461	} while(0U)
<>	144:ef7eb2e8f9f7	462
<>	144:ef7eb2e8f9f7	463	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<>	144:ef7eb2e8f9f7	464	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<>	144:ef7eb2e8f9f7	465	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	466	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<>	144:ef7eb2e8f9f7	467	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
<>	144:ef7eb2e8f9f7	470	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472	/**
<>	144:ef7eb2e8f9f7	473	* @}
<>	144:ef7eb2e8f9f7	474	*/
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	477	* @brief Get the enable or disable status of the APB1 peripheral clock.
<>	144:ef7eb2e8f9f7	478	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	479	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	480	* using it.
<>	144:ef7eb2e8f9f7	481	* @{
<>	144:ef7eb2e8f9f7	482	*/
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<>	144:ef7eb2e8f9f7	485	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<>	144:ef7eb2e8f9f7	486	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
<>	144:ef7eb2e8f9f7	487	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
<>	144:ef7eb2e8f9f7	488	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
<>	144:ef7eb2e8f9f7	489	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	490	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	491	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
<>	144:ef7eb2e8f9f7	492	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
<>	144:ef7eb2e8f9f7	493	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	494	#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	495	#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	496	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	497	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
<>	144:ef7eb2e8f9f7	498
<>	144:ef7eb2e8f9f7	499	/**
<>	144:ef7eb2e8f9f7	500	* @}
<>	144:ef7eb2e8f9f7	501	*/
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
<>	144:ef7eb2e8f9f7	504	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<>	144:ef7eb2e8f9f7	505	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	506	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	507	* using it.
<>	144:ef7eb2e8f9f7	508	* @{
<>	144:ef7eb2e8f9f7	509	*/
<>	144:ef7eb2e8f9f7	510	#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	511	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	512	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
<>	144:ef7eb2e8f9f7	513	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	514	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
<>	144:ef7eb2e8f9f7	515	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	516	} while(0U)
<>	144:ef7eb2e8f9f7	517
<>	144:ef7eb2e8f9f7	518	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	519	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	520	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
<>	144:ef7eb2e8f9f7	521	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	522	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
<>	144:ef7eb2e8f9f7	523	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	524	} while(0U)
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	527	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	528	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
<>	144:ef7eb2e8f9f7	529	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	530	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
<>	144:ef7eb2e8f9f7	531	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	532	} while(0U)
<>	144:ef7eb2e8f9f7	533
<>	144:ef7eb2e8f9f7	534	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	535	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	536	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
<>	144:ef7eb2e8f9f7	537	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	538	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
<>	144:ef7eb2e8f9f7	539	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	540	} while(0U)
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	543	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	544	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
<>	144:ef7eb2e8f9f7	545	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	546	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
<>	144:ef7eb2e8f9f7	547	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	548	} while(0U)
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	551	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	552	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	553	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	554	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	555	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	556	} while(0U)
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	559	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	560	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	561	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	562	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	563	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	564	} while(0U)
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	567	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	568	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	569	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	570	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	571	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	572	} while(0U)
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	575	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	576	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	577	/* Delay after an RCC peripheral clock enabling */\
<>	144:ef7eb2e8f9f7	578	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	579	UNUSED(tmpreg); \
AnnaBridge	165:e614a9f1c9e2	580	} while(0U)
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
<>	144:ef7eb2e8f9f7	583	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
<>	144:ef7eb2e8f9f7	584	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
<>	144:ef7eb2e8f9f7	585	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
<>	144:ef7eb2e8f9f7	586	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
<>	144:ef7eb2e8f9f7	587	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
<>	144:ef7eb2e8f9f7	590	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
<>	144:ef7eb2e8f9f7	591	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	/**
<>	144:ef7eb2e8f9f7	594	* @}
<>	144:ef7eb2e8f9f7	595	*/
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	598	* @brief Get the enable or disable status of the APB2 peripheral clock.
<>	144:ef7eb2e8f9f7	599	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	600	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	601	* using it.
<>	144:ef7eb2e8f9f7	602	* @{
<>	144:ef7eb2e8f9f7	603	*/
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
<>	144:ef7eb2e8f9f7	606	#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	607	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	608	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	609	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	610	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	611	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	612	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	613	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	614	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
<>	144:ef7eb2e8f9f7	615	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
<>	144:ef7eb2e8f9f7	616	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
<>	144:ef7eb2e8f9f7	617	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
<>	144:ef7eb2e8f9f7	618	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
<>	144:ef7eb2e8f9f7	619	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
<>	144:ef7eb2e8f9f7	620	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge	165:e614a9f1c9e2	621	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge	165:e614a9f1c9e2	622	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	/**
<>	144:ef7eb2e8f9f7	625	* @}
<>	144:ef7eb2e8f9f7	626	*/
<>	144:ef7eb2e8f9f7	627
<>	144:ef7eb2e8f9f7	628	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
<>	144:ef7eb2e8f9f7	629	* @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	630	* @{
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	633	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
<>	144:ef7eb2e8f9f7	634	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
<>	144:ef7eb2e8f9f7	635	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	636	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	637	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	638
<>	144:ef7eb2e8f9f7	639	#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_BKPRST))
<>	144:ef7eb2e8f9f7	640	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
<>	144:ef7eb2e8f9f7	643	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
<>	144:ef7eb2e8f9f7	644	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
<>	144:ef7eb2e8f9f7	645	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	646	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	647	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	648
<>	144:ef7eb2e8f9f7	649	#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
<>	144:ef7eb2e8f9f7	650	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/**
<>	144:ef7eb2e8f9f7	653	* @}
<>	144:ef7eb2e8f9f7	654	*/
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
<>	144:ef7eb2e8f9f7	657	* @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	658	* @{
<>	144:ef7eb2e8f9f7	659	*/
<>	144:ef7eb2e8f9f7	660	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	661	#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_AFIORST))
<>	144:ef7eb2e8f9f7	662	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPARST))
<>	144:ef7eb2e8f9f7	663	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPBRST))
<>	144:ef7eb2e8f9f7	664	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPCRST))
<>	144:ef7eb2e8f9f7	665	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPDRST))
<>	144:ef7eb2e8f9f7	666	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
<>	144:ef7eb2e8f9f7	667
<>	144:ef7eb2e8f9f7	668	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	669	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	670	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	671
<>	144:ef7eb2e8f9f7	672	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
<>	144:ef7eb2e8f9f7	673	#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
<>	144:ef7eb2e8f9f7	674	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
<>	144:ef7eb2e8f9f7	675	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
<>	144:ef7eb2e8f9f7	676	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
<>	144:ef7eb2e8f9f7	677	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
<>	144:ef7eb2e8f9f7	678	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	681	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	682	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	683
<>	144:ef7eb2e8f9f7	684	/**
<>	144:ef7eb2e8f9f7	685	* @}
<>	144:ef7eb2e8f9f7	686	*/
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	/** @defgroup RCC_HSI_Configuration HSI Configuration
<>	144:ef7eb2e8f9f7	689	* @{
<>	144:ef7eb2e8f9f7	690	*/
<>	144:ef7eb2e8f9f7	691
<>	144:ef7eb2e8f9f7	692	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<>	144:ef7eb2e8f9f7	693	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	694	* @note HSI can not be stopped if it is used as system clock source. In this case,
<>	144:ef7eb2e8f9f7	695	* you have to select another source of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	696	* @note After enabling the HSI, the application software should wait on HSIRDY
<>	144:ef7eb2e8f9f7	697	* flag to be set indicating that HSI clock is stable and can be used as
<>	144:ef7eb2e8f9f7	698	* system clock source.
<>	144:ef7eb2e8f9f7	699	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	700	* clock cycles.
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
<>	144:ef7eb2e8f9f7	703	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
<>	144:ef7eb2e8f9f7	704
<>	144:ef7eb2e8f9f7	705	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<>	144:ef7eb2e8f9f7	706	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	707	* and temperature that influence the frequency of the internal HSI RC.
<>	144:ef7eb2e8f9f7	708	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
<>	144:ef7eb2e8f9f7	709	* (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	710	* This parameter must be a number between 0 and 0x1F.
<>	144:ef7eb2e8f9f7	711	*/
<>	144:ef7eb2e8f9f7	712	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
AnnaBridge	165:e614a9f1c9e2	713	(MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
<>	144:ef7eb2e8f9f7	714
<>	144:ef7eb2e8f9f7	715	/**
<>	144:ef7eb2e8f9f7	716	* @}
<>	144:ef7eb2e8f9f7	717	*/
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	/** @defgroup RCC_LSI_Configuration LSI Configuration
<>	144:ef7eb2e8f9f7	720	* @{
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	724	* @note After enabling the LSI, the application software should wait on
<>	144:ef7eb2e8f9f7	725	* LSIRDY flag to be set indicating that LSI clock is stable and can
<>	144:ef7eb2e8f9f7	726	* be used to clock the IWDG and/or the RTC.
<>	144:ef7eb2e8f9f7	727	*/
<>	144:ef7eb2e8f9f7	728	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
<>	144:ef7eb2e8f9f7	729
<>	144:ef7eb2e8f9f7	730	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	731	* @note LSI can not be disabled if the IWDG is running.
<>	144:ef7eb2e8f9f7	732	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<>	144:ef7eb2e8f9f7	733	* clock cycles.
<>	144:ef7eb2e8f9f7	734	*/
<>	144:ef7eb2e8f9f7	735	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/**
<>	144:ef7eb2e8f9f7	738	* @}
<>	144:ef7eb2e8f9f7	739	*/
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/** @defgroup RCC_HSE_Configuration HSE Configuration
<>	144:ef7eb2e8f9f7	742	* @{
<>	144:ef7eb2e8f9f7	743	*/
<>	144:ef7eb2e8f9f7	744
<>	144:ef7eb2e8f9f7	745	/**
<>	144:ef7eb2e8f9f7	746	* @brief Macro to configure the External High Speed oscillator (HSE).
<>	144:ef7eb2e8f9f7	747	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<>	144:ef7eb2e8f9f7	748	* supported by this macro. User should request a transition to HSE Off
<>	144:ef7eb2e8f9f7	749	* first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	750	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<>	144:ef7eb2e8f9f7	751	* software should wait on HSERDY flag to be set indicating that HSE clock
<>	144:ef7eb2e8f9f7	752	* is stable and can be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	753	* @note HSE state can not be changed if it is used directly or through the
<>	144:ef7eb2e8f9f7	754	* PLL as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	755	* of the system clock then change the HSE state (ex. disable it).
<>	144:ef7eb2e8f9f7	756	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	757	* @note This function reset the CSSON bit, so if the clock security system(CSS)
<>	144:ef7eb2e8f9f7	758	* was previously enabled you have to enable it again after calling this
<>	144:ef7eb2e8f9f7	759	* function.
<>	144:ef7eb2e8f9f7	760	* @param __STATE__ specifies the new state of the HSE.
<>	144:ef7eb2e8f9f7	761	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	762	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
<>	144:ef7eb2e8f9f7	763	* 6 HSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	764	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
<>	144:ef7eb2e8f9f7	765	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
<>	144:ef7eb2e8f9f7	766	*/
<>	144:ef7eb2e8f9f7	767	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	768	do{ \
<>	144:ef7eb2e8f9f7	769	if ((__STATE__) == RCC_HSE_ON) \
<>	144:ef7eb2e8f9f7	770	{ \
<>	144:ef7eb2e8f9f7	771	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	772	} \
<>	144:ef7eb2e8f9f7	773	else if ((__STATE__) == RCC_HSE_OFF) \
<>	144:ef7eb2e8f9f7	774	{ \
<>	144:ef7eb2e8f9f7	775	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	776	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	777	} \
<>	144:ef7eb2e8f9f7	778	else if ((__STATE__) == RCC_HSE_BYPASS) \
<>	144:ef7eb2e8f9f7	779	{ \
<>	144:ef7eb2e8f9f7	780	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	781	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	782	} \
<>	144:ef7eb2e8f9f7	783	else \
<>	144:ef7eb2e8f9f7	784	{ \
<>	144:ef7eb2e8f9f7	785	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	786	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	787	} \
AnnaBridge	165:e614a9f1c9e2	788	}while(0U)
<>	144:ef7eb2e8f9f7	789
<>	144:ef7eb2e8f9f7	790	/**
<>	144:ef7eb2e8f9f7	791	* @}
<>	144:ef7eb2e8f9f7	792	*/
<>	144:ef7eb2e8f9f7	793
<>	144:ef7eb2e8f9f7	794	/** @defgroup RCC_LSE_Configuration LSE Configuration
<>	144:ef7eb2e8f9f7	795	* @{
<>	144:ef7eb2e8f9f7	796	*/
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	/**
<>	144:ef7eb2e8f9f7	799	* @brief Macro to configure the External Low Speed oscillator (LSE).
<>	144:ef7eb2e8f9f7	800	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
<>	144:ef7eb2e8f9f7	801	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	802	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	803	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	804	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	805	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<>	144:ef7eb2e8f9f7	806	* software should wait on LSERDY flag to be set indicating that LSE clock
<>	144:ef7eb2e8f9f7	807	* is stable and can be used to clock the RTC.
<>	144:ef7eb2e8f9f7	808	* @param __STATE__ specifies the new state of the LSE.
<>	144:ef7eb2e8f9f7	809	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	810	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
<>	144:ef7eb2e8f9f7	811	* 6 LSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	812	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
<>	144:ef7eb2e8f9f7	813	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	814	*/
<>	144:ef7eb2e8f9f7	815	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	816	do{ \
<>	144:ef7eb2e8f9f7	817	if ((__STATE__) == RCC_LSE_ON) \
<>	144:ef7eb2e8f9f7	818	{ \
<>	144:ef7eb2e8f9f7	819	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	820	} \
<>	144:ef7eb2e8f9f7	821	else if ((__STATE__) == RCC_LSE_OFF) \
<>	144:ef7eb2e8f9f7	822	{ \
<>	144:ef7eb2e8f9f7	823	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	824	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	825	} \
<>	144:ef7eb2e8f9f7	826	else if ((__STATE__) == RCC_LSE_BYPASS) \
<>	144:ef7eb2e8f9f7	827	{ \
<>	144:ef7eb2e8f9f7	828	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	829	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	830	} \
<>	144:ef7eb2e8f9f7	831	else \
<>	144:ef7eb2e8f9f7	832	{ \
<>	144:ef7eb2e8f9f7	833	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	834	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	835	} \
AnnaBridge	165:e614a9f1c9e2	836	}while(0U)
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/**
<>	144:ef7eb2e8f9f7	839	* @}
<>	144:ef7eb2e8f9f7	840	*/
<>	144:ef7eb2e8f9f7	841
<>	144:ef7eb2e8f9f7	842	/** @defgroup RCC_PLL_Configuration PLL Configuration
<>	144:ef7eb2e8f9f7	843	* @{
<>	144:ef7eb2e8f9f7	844	*/
<>	144:ef7eb2e8f9f7	845
<>	144:ef7eb2e8f9f7	846	/** @brief Macro to enable the main PLL.
<>	144:ef7eb2e8f9f7	847	* @note After enabling the main PLL, the application software should wait on
<>	144:ef7eb2e8f9f7	848	* PLLRDY flag to be set indicating that PLL clock is stable and can
<>	144:ef7eb2e8f9f7	849	* be used as system clock source.
<>	144:ef7eb2e8f9f7	850	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	851	*/
<>	144:ef7eb2e8f9f7	852	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	/** @brief Macro to disable the main PLL.
<>	144:ef7eb2e8f9f7	855	* @note The main PLL can not be disabled if it is used as system clock source
<>	144:ef7eb2e8f9f7	856	*/
<>	144:ef7eb2e8f9f7	857	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859	/** @brief Macro to configure the main PLL clock source and multiplication factors.
<>	144:ef7eb2e8f9f7	860	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	861	*
<>	144:ef7eb2e8f9f7	862	* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	863	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	864	* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	865	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	866	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
<>	144:ef7eb2e8f9f7	867	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	868	* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
<>	144:ef7eb2e8f9f7	869	* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
<>	144:ef7eb2e8f9f7	870	@if STM32F105xC
<>	144:ef7eb2e8f9f7	871	* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
<>	144:ef7eb2e8f9f7	872	@elseif STM32F107xC
<>	144:ef7eb2e8f9f7	873	* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
<>	144:ef7eb2e8f9f7	874	@else
<>	144:ef7eb2e8f9f7	875	* @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
<>	144:ef7eb2e8f9f7	876	* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
<>	144:ef7eb2e8f9f7	877	* @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
<>	144:ef7eb2e8f9f7	878	* @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
<>	144:ef7eb2e8f9f7	879	* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
<>	144:ef7eb2e8f9f7	880	* @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
<>	144:ef7eb2e8f9f7	881	* @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
<>	144:ef7eb2e8f9f7	882	* @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
<>	144:ef7eb2e8f9f7	883	* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
<>	144:ef7eb2e8f9f7	884	@endif
<>	144:ef7eb2e8f9f7	885	* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
<>	144:ef7eb2e8f9f7	886	* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
<>	144:ef7eb2e8f9f7	887	*
<>	144:ef7eb2e8f9f7	888	*/
<>	144:ef7eb2e8f9f7	889	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
<>	144:ef7eb2e8f9f7	890	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) \| (__PLLMUL__) ))
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	/** @brief Get oscillator clock selected as PLL input clock
<>	144:ef7eb2e8f9f7	893	* @retval The clock source used for PLL entry. The returned value can be one
<>	144:ef7eb2e8f9f7	894	* of the following:
<>	144:ef7eb2e8f9f7	895	* @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
<>	144:ef7eb2e8f9f7	896	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
<>	144:ef7eb2e8f9f7	897	*/
<>	144:ef7eb2e8f9f7	898	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
<>	144:ef7eb2e8f9f7	899
<>	144:ef7eb2e8f9f7	900	/**
<>	144:ef7eb2e8f9f7	901	* @}
<>	144:ef7eb2e8f9f7	902	*/
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	/** @defgroup RCC_Get_Clock_source Get Clock source
<>	144:ef7eb2e8f9f7	905	* @{
<>	144:ef7eb2e8f9f7	906	*/
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908	/**
<>	144:ef7eb2e8f9f7	909	* @brief Macro to configure the system clock source.
<>	144:ef7eb2e8f9f7	910	* @param __SYSCLKSOURCE__ specifies the system clock source.
<>	144:ef7eb2e8f9f7	911	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	912	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	913	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	914	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
<>	144:ef7eb2e8f9f7	915	*/
<>	144:ef7eb2e8f9f7	916	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
<>	144:ef7eb2e8f9f7	917	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	/** @brief Macro to get the clock source used as system clock.
<>	144:ef7eb2e8f9f7	920	* @retval The clock source used as system clock. The returned value can be one
<>	144:ef7eb2e8f9f7	921	* of the following:
<>	144:ef7eb2e8f9f7	922	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
<>	144:ef7eb2e8f9f7	923	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
<>	144:ef7eb2e8f9f7	924	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
<>	144:ef7eb2e8f9f7	925	*/
<>	144:ef7eb2e8f9f7	926	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	/**
<>	144:ef7eb2e8f9f7	929	* @}
<>	144:ef7eb2e8f9f7	930	*/
<>	144:ef7eb2e8f9f7	931
<>	144:ef7eb2e8f9f7	932	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
<>	144:ef7eb2e8f9f7	933	* @{
<>	144:ef7eb2e8f9f7	934	*/
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	#if defined(RCC_CFGR_MCO_3)
<>	144:ef7eb2e8f9f7	937	/** @brief Macro to configure the MCO clock.
<>	144:ef7eb2e8f9f7	938	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	939	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	940	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<>	144:ef7eb2e8f9f7	941	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
<>	144:ef7eb2e8f9f7	942	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<>	144:ef7eb2e8f9f7	943	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<>	144:ef7eb2e8f9f7	944	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
<>	144:ef7eb2e8f9f7	945	* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
<>	144:ef7eb2e8f9f7	946	* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
<>	144:ef7eb2e8f9f7	947	* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
<>	144:ef7eb2e8f9f7	948	* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
<>	144:ef7eb2e8f9f7	949	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	950	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	951	* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
<>	144:ef7eb2e8f9f7	952	*/
<>	144:ef7eb2e8f9f7	953	#else
<>	144:ef7eb2e8f9f7	954	/** @brief Macro to configure the MCO clock.
<>	144:ef7eb2e8f9f7	955	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	956	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	957	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<>	144:ef7eb2e8f9f7	958	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
<>	144:ef7eb2e8f9f7	959	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<>	144:ef7eb2e8f9f7	960	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<>	144:ef7eb2e8f9f7	961	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
<>	144:ef7eb2e8f9f7	962	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	963	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	964	* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
<>	144:ef7eb2e8f9f7	965	*/
<>	144:ef7eb2e8f9f7	966	#endif
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	969	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	/**
<>	144:ef7eb2e8f9f7	973	* @}
<>	144:ef7eb2e8f9f7	974	*/
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
<>	144:ef7eb2e8f9f7	977	* @{
<>	144:ef7eb2e8f9f7	978	*/
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	/** @brief Macro to configure the RTC clock (RTCCLK).
<>	144:ef7eb2e8f9f7	981	* @note As the RTC clock configuration bits are in the Backup domain and write
<>	144:ef7eb2e8f9f7	982	* access is denied to this domain after reset, you have to enable write
<>	144:ef7eb2e8f9f7	983	* access using the Power Backup Access macro before to configure
<>	144:ef7eb2e8f9f7	984	* the RTC clock source (to be done once after reset).
<>	144:ef7eb2e8f9f7	985	* @note Once the RTC clock is configured it can't be changed unless the
<>	144:ef7eb2e8f9f7	986	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
<>	144:ef7eb2e8f9f7	987	* a Power On Reset (POR).
<>	144:ef7eb2e8f9f7	988	*
<>	144:ef7eb2e8f9f7	989	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
<>	144:ef7eb2e8f9f7	990	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	991	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
<>	144:ef7eb2e8f9f7	992	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
<>	144:ef7eb2e8f9f7	993	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
<>	144:ef7eb2e8f9f7	994	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
<>	144:ef7eb2e8f9f7	995	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<>	144:ef7eb2e8f9f7	996	* work in STOP and STANDBY modes, and can be used as wakeup source.
<>	144:ef7eb2e8f9f7	997	* However, when the HSE clock is used as RTC clock source, the RTC
<>	144:ef7eb2e8f9f7	998	* cannot be used in STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	999	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
<>	144:ef7eb2e8f9f7	1000	* RTC clock source).
<>	144:ef7eb2e8f9f7	1001	*/
<>	144:ef7eb2e8f9f7	1002	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	1003
<>	144:ef7eb2e8f9f7	1004	/** @brief Macro to get the RTC clock source.
<>	144:ef7eb2e8f9f7	1005	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	1006	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
<>	144:ef7eb2e8f9f7	1007	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
<>	144:ef7eb2e8f9f7	1008	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
<>	144:ef7eb2e8f9f7	1009	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
<>	144:ef7eb2e8f9f7	1010	*/
<>	144:ef7eb2e8f9f7	1011	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	/** @brief Macro to enable the the RTC clock.
<>	144:ef7eb2e8f9f7	1014	* @note These macros must be used only after the RTC clock source was selected.
<>	144:ef7eb2e8f9f7	1015	*/
<>	144:ef7eb2e8f9f7	1016	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	/** @brief Macro to disable the the RTC clock.
<>	144:ef7eb2e8f9f7	1019	* @note These macros must be used only after the RTC clock source was selected.
<>	144:ef7eb2e8f9f7	1020	*/
<>	144:ef7eb2e8f9f7	1021	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	/** @brief Macro to force the Backup domain reset.
<>	144:ef7eb2e8f9f7	1024	* @note This function resets the RTC peripheral (including the backup registers)
<>	144:ef7eb2e8f9f7	1025	* and the RTC clock source selection in RCC_BDCR register.
<>	144:ef7eb2e8f9f7	1026	*/
<>	144:ef7eb2e8f9f7	1027	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/** @brief Macros to release the Backup domain reset.
<>	144:ef7eb2e8f9f7	1030	*/
<>	144:ef7eb2e8f9f7	1031	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1032
<>	144:ef7eb2e8f9f7	1033	/**
<>	144:ef7eb2e8f9f7	1034	* @}
<>	144:ef7eb2e8f9f7	1035	*/
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<>	144:ef7eb2e8f9f7	1038	* @brief macros to manage the specified RCC Flags and interrupts.
<>	144:ef7eb2e8f9f7	1039	* @{
<>	144:ef7eb2e8f9f7	1040	*/
<>	144:ef7eb2e8f9f7	1041
<>	144:ef7eb2e8f9f7	1042	/** @brief Enable RCC interrupt.
<>	144:ef7eb2e8f9f7	1043	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	1044	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1045	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<>	144:ef7eb2e8f9f7	1046	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
<>	144:ef7eb2e8f9f7	1047	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	1048	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
<>	144:ef7eb2e8f9f7	1049	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
<>	144:ef7eb2e8f9f7	1050	@if STM32F105xx
<>	144:ef7eb2e8f9f7	1051	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1052	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1053	@elsif STM32F107xx
<>	144:ef7eb2e8f9f7	1054	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1055	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1056	@endif
<>	144:ef7eb2e8f9f7	1057	*/
<>	144:ef7eb2e8f9f7	1058	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/** @brief Disable RCC interrupt.
<>	144:ef7eb2e8f9f7	1061	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	1062	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1063	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
<>	144:ef7eb2e8f9f7	1064	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
<>	144:ef7eb2e8f9f7	1065	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
<>	144:ef7eb2e8f9f7	1066	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
<>	144:ef7eb2e8f9f7	1067	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
<>	144:ef7eb2e8f9f7	1068	@if STM32F105xx
<>	144:ef7eb2e8f9f7	1069	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1070	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1071	@elsif STM32F107xx
<>	144:ef7eb2e8f9f7	1072	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1073	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1074	@endif
<>	144:ef7eb2e8f9f7	1075	*/
<>	144:ef7eb2e8f9f7	1076	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	/** @brief Clear the RCC's interrupt pending bits.
<>	144:ef7eb2e8f9f7	1079	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	1080	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1081	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1082	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1083	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1084	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1085	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1086	@if STM32F105xx
<>	144:ef7eb2e8f9f7	1087	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1088	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1089	@elsif STM32F107xx
<>	144:ef7eb2e8f9f7	1090	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1091	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1092	@endif
<>	144:ef7eb2e8f9f7	1093	* @arg @ref RCC_IT_CSS Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1094	*/
<>	144:ef7eb2e8f9f7	1095	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	/** @brief Check the RCC's interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	1098	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
<>	144:ef7eb2e8f9f7	1099	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1100	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1101	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1102	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1103	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1104	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1105	@if STM32F105xx
<>	144:ef7eb2e8f9f7	1106	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1107	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1108	@elsif STM32F107xx
<>	144:ef7eb2e8f9f7	1109	* @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
<>	144:ef7eb2e8f9f7	1110	* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1111	@endif
<>	144:ef7eb2e8f9f7	1112	* @arg @ref RCC_IT_CSS Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1113	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1114	*/
<>	144:ef7eb2e8f9f7	1115	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1116
<>	144:ef7eb2e8f9f7	1117	/** @brief Set RMVF bit to clear the reset flags.
<>	144:ef7eb2e8f9f7	1118	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
<>	144:ef7eb2e8f9f7	1119	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
<>	144:ef7eb2e8f9f7	1120	*/
<>	144:ef7eb2e8f9f7	1121	#define __HAL_RCC_CLEAR_RESET_FLAGS() ((__IO uint32_t )RCC_CSR_RMVF_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/** @brief Check RCC flag is set or not.
<>	144:ef7eb2e8f9f7	1124	* @param __FLAG__ specifies the flag to check.
<>	144:ef7eb2e8f9f7	1125	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1126	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1127	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1128	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
<>	144:ef7eb2e8f9f7	1129	@if STM32F105xx
<>	144:ef7eb2e8f9f7	1130	* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
<>	144:ef7eb2e8f9f7	1131	* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
<>	144:ef7eb2e8f9f7	1132	@elsif STM32F107xx
<>	144:ef7eb2e8f9f7	1133	* @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
<>	144:ef7eb2e8f9f7	1134	* @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
<>	144:ef7eb2e8f9f7	1135	@endif
<>	144:ef7eb2e8f9f7	1136	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1137	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1138	* @arg @ref RCC_FLAG_PINRST Pin reset.
<>	144:ef7eb2e8f9f7	1139	* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
<>	144:ef7eb2e8f9f7	1140	* @arg @ref RCC_FLAG_SFTRST Software reset.
<>	144:ef7eb2e8f9f7	1141	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
<>	144:ef7eb2e8f9f7	1142	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
<>	144:ef7eb2e8f9f7	1143	* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
<>	144:ef7eb2e8f9f7	1144	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1145	*/
AnnaBridge	165:e614a9f1c9e2	1146	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
AnnaBridge	165:e614a9f1c9e2	1147	((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
AnnaBridge	165:e614a9f1c9e2	1148	RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	/**
<>	144:ef7eb2e8f9f7	1151	* @}
<>	144:ef7eb2e8f9f7	1152	*/
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/**
<>	144:ef7eb2e8f9f7	1155	* @}
<>	144:ef7eb2e8f9f7	1156	*/
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	/* Include RCC HAL Extension module */
<>	144:ef7eb2e8f9f7	1159	#include "stm32f1xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1162	/** @addtogroup RCC_Exported_Functions
<>	144:ef7eb2e8f9f7	1163	* @{
<>	144:ef7eb2e8f9f7	1164	*/
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	/** @addtogroup RCC_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1167	* @{
<>	144:ef7eb2e8f9f7	1168	*/
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/* Initialization and de-initialization functions ******************************/
AnnaBridge	187:0387e8f68319	1171	HAL_StatusTypeDef HAL_RCC_DeInit(void);
<>	144:ef7eb2e8f9f7	1172	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1173	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	/**
<>	144:ef7eb2e8f9f7	1176	* @}
<>	144:ef7eb2e8f9f7	1177	*/
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/** @addtogroup RCC_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	1180	* @{
<>	144:ef7eb2e8f9f7	1181	*/
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1184	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<>	144:ef7eb2e8f9f7	1185	void HAL_RCC_EnableCSS(void);
<>	144:ef7eb2e8f9f7	1186	void HAL_RCC_DisableCSS(void);
<>	144:ef7eb2e8f9f7	1187	uint32_t HAL_RCC_GetSysClockFreq(void);
<>	144:ef7eb2e8f9f7	1188	uint32_t HAL_RCC_GetHCLKFreq(void);
<>	144:ef7eb2e8f9f7	1189	uint32_t HAL_RCC_GetPCLK1Freq(void);
<>	144:ef7eb2e8f9f7	1190	uint32_t HAL_RCC_GetPCLK2Freq(void);
<>	144:ef7eb2e8f9f7	1191	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1192	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	/* CSS NMI IRQ handler */
<>	144:ef7eb2e8f9f7	1195	void HAL_RCC_NMI_IRQHandler(void);
<>	144:ef7eb2e8f9f7	1196
<>	144:ef7eb2e8f9f7	1197	/* User Callbacks in non blocking mode (IT mode) */
<>	144:ef7eb2e8f9f7	1198	void HAL_RCC_CSSCallback(void);
<>	144:ef7eb2e8f9f7	1199
<>	144:ef7eb2e8f9f7	1200	/**
<>	144:ef7eb2e8f9f7	1201	* @}
<>	144:ef7eb2e8f9f7	1202	*/
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	/**
<>	144:ef7eb2e8f9f7	1205	* @}
<>	144:ef7eb2e8f9f7	1206	*/
<>	144:ef7eb2e8f9f7	1207
AnnaBridge	165:e614a9f1c9e2	1208	/** @addtogroup RCC_Private_Constants
AnnaBridge	165:e614a9f1c9e2	1209	* @{
AnnaBridge	165:e614a9f1c9e2	1210	*/
AnnaBridge	165:e614a9f1c9e2	1211
AnnaBridge	165:e614a9f1c9e2	1212	/** @defgroup RCC_Timeout RCC Timeout
AnnaBridge	165:e614a9f1c9e2	1213	* @{
AnnaBridge	165:e614a9f1c9e2	1214	*/
AnnaBridge	165:e614a9f1c9e2	1215
AnnaBridge	165:e614a9f1c9e2	1216	/* Disable Backup domain write protection state change timeout */
AnnaBridge	165:e614a9f1c9e2	1217	#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
AnnaBridge	165:e614a9f1c9e2	1218	/* LSE state change timeout */
AnnaBridge	165:e614a9f1c9e2	1219	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	165:e614a9f1c9e2	1220	#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
AnnaBridge	165:e614a9f1c9e2	1221	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge	165:e614a9f1c9e2	1222	#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
AnnaBridge	165:e614a9f1c9e2	1223	#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
AnnaBridge	165:e614a9f1c9e2	1224	#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
AnnaBridge	165:e614a9f1c9e2	1225
AnnaBridge	165:e614a9f1c9e2	1226	/**
AnnaBridge	165:e614a9f1c9e2	1227	* @}
AnnaBridge	165:e614a9f1c9e2	1228	*/
AnnaBridge	165:e614a9f1c9e2	1229
AnnaBridge	165:e614a9f1c9e2	1230	/** @defgroup RCC_Register_Offset Register offsets
AnnaBridge	165:e614a9f1c9e2	1231	* @{
AnnaBridge	165:e614a9f1c9e2	1232	*/
AnnaBridge	165:e614a9f1c9e2	1233	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge	165:e614a9f1c9e2	1234	#define RCC_CR_OFFSET 0x00U
AnnaBridge	165:e614a9f1c9e2	1235	#define RCC_CFGR_OFFSET 0x04U
AnnaBridge	165:e614a9f1c9e2	1236	#define RCC_CIR_OFFSET 0x08U
AnnaBridge	165:e614a9f1c9e2	1237	#define RCC_BDCR_OFFSET 0x20U
AnnaBridge	165:e614a9f1c9e2	1238	#define RCC_CSR_OFFSET 0x24U
AnnaBridge	165:e614a9f1c9e2	1239
AnnaBridge	165:e614a9f1c9e2	1240	/**
AnnaBridge	165:e614a9f1c9e2	1241	* @}
AnnaBridge	165:e614a9f1c9e2	1242	*/
AnnaBridge	165:e614a9f1c9e2	1243
AnnaBridge	165:e614a9f1c9e2	1244	/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
AnnaBridge	165:e614a9f1c9e2	1245	* @brief RCC registers bit address in the alias region
AnnaBridge	165:e614a9f1c9e2	1246	* @{
AnnaBridge	165:e614a9f1c9e2	1247	*/
AnnaBridge	165:e614a9f1c9e2	1248	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
AnnaBridge	165:e614a9f1c9e2	1249	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
AnnaBridge	165:e614a9f1c9e2	1250	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
AnnaBridge	165:e614a9f1c9e2	1251	#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
AnnaBridge	165:e614a9f1c9e2	1252	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
AnnaBridge	165:e614a9f1c9e2	1253
AnnaBridge	165:e614a9f1c9e2	1254	/* --- CR Register ---*/
AnnaBridge	165:e614a9f1c9e2	1255	/* Alias word address of HSION bit */
AnnaBridge	165:e614a9f1c9e2	1256	#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
AnnaBridge	165:e614a9f1c9e2	1257	#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1258	/* Alias word address of HSEON bit */
AnnaBridge	165:e614a9f1c9e2	1259	#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
AnnaBridge	165:e614a9f1c9e2	1260	#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1261	/* Alias word address of CSSON bit */
AnnaBridge	165:e614a9f1c9e2	1262	#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
AnnaBridge	165:e614a9f1c9e2	1263	#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1264	/* Alias word address of PLLON bit */
AnnaBridge	165:e614a9f1c9e2	1265	#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
AnnaBridge	165:e614a9f1c9e2	1266	#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1267
AnnaBridge	165:e614a9f1c9e2	1268	/* --- CSR Register ---*/
AnnaBridge	165:e614a9f1c9e2	1269	/* Alias word address of LSION bit */
AnnaBridge	165:e614a9f1c9e2	1270	#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
AnnaBridge	165:e614a9f1c9e2	1271	#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1272
AnnaBridge	165:e614a9f1c9e2	1273	/* Alias word address of RMVF bit */
AnnaBridge	165:e614a9f1c9e2	1274	#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
AnnaBridge	165:e614a9f1c9e2	1275	#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1276
AnnaBridge	165:e614a9f1c9e2	1277	/* --- BDCR Registers ---*/
AnnaBridge	165:e614a9f1c9e2	1278	/* Alias word address of LSEON bit */
AnnaBridge	165:e614a9f1c9e2	1279	#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
AnnaBridge	165:e614a9f1c9e2	1280	#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1281
AnnaBridge	165:e614a9f1c9e2	1282	/* Alias word address of LSEON bit */
AnnaBridge	165:e614a9f1c9e2	1283	#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
AnnaBridge	165:e614a9f1c9e2	1284	#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1285
AnnaBridge	165:e614a9f1c9e2	1286	/* Alias word address of RTCEN bit */
AnnaBridge	165:e614a9f1c9e2	1287	#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
AnnaBridge	165:e614a9f1c9e2	1288	#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1289
AnnaBridge	165:e614a9f1c9e2	1290	/* Alias word address of BDRST bit */
AnnaBridge	165:e614a9f1c9e2	1291	#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
AnnaBridge	165:e614a9f1c9e2	1292	#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
AnnaBridge	165:e614a9f1c9e2	1293
AnnaBridge	165:e614a9f1c9e2	1294	/**
AnnaBridge	165:e614a9f1c9e2	1295	* @}
AnnaBridge	165:e614a9f1c9e2	1296	*/
AnnaBridge	165:e614a9f1c9e2	1297
AnnaBridge	165:e614a9f1c9e2	1298	/* CR register byte 2 (Bits[23:16]) base address */
AnnaBridge	165:e614a9f1c9e2	1299	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
AnnaBridge	165:e614a9f1c9e2	1300
AnnaBridge	165:e614a9f1c9e2	1301	/* CIR register byte 1 (Bits[15:8]) base address */
AnnaBridge	165:e614a9f1c9e2	1302	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
AnnaBridge	165:e614a9f1c9e2	1303
AnnaBridge	165:e614a9f1c9e2	1304	/* CIR register byte 2 (Bits[23:16]) base address */
AnnaBridge	165:e614a9f1c9e2	1305	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
AnnaBridge	165:e614a9f1c9e2	1306
AnnaBridge	165:e614a9f1c9e2	1307	/* Defines used for Flags */
AnnaBridge	165:e614a9f1c9e2	1308	#define CR_REG_INDEX ((uint8_t)1)
AnnaBridge	165:e614a9f1c9e2	1309	#define BDCR_REG_INDEX ((uint8_t)2)
AnnaBridge	165:e614a9f1c9e2	1310	#define CSR_REG_INDEX ((uint8_t)3)
AnnaBridge	165:e614a9f1c9e2	1311
AnnaBridge	165:e614a9f1c9e2	1312	#define RCC_FLAG_MASK ((uint8_t)0x1F)
AnnaBridge	165:e614a9f1c9e2	1313
AnnaBridge	165:e614a9f1c9e2	1314	/**
AnnaBridge	165:e614a9f1c9e2	1315	* @}
AnnaBridge	165:e614a9f1c9e2	1316	*/
AnnaBridge	165:e614a9f1c9e2	1317
AnnaBridge	165:e614a9f1c9e2	1318	/** @addtogroup RCC_Private_Macros
AnnaBridge	165:e614a9f1c9e2	1319	* @{
AnnaBridge	165:e614a9f1c9e2	1320	*/
AnnaBridge	165:e614a9f1c9e2	1321	/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
AnnaBridge	165:e614a9f1c9e2	1322	* @{
AnnaBridge	165:e614a9f1c9e2	1323	*/
AnnaBridge	165:e614a9f1c9e2	1324	#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
AnnaBridge	165:e614a9f1c9e2	1325	#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
AnnaBridge	165:e614a9f1c9e2	1326	#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
AnnaBridge	165:e614a9f1c9e2	1327	#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
AnnaBridge	165:e614a9f1c9e2	1328	/**
AnnaBridge	165:e614a9f1c9e2	1329	* @}
AnnaBridge	165:e614a9f1c9e2	1330	*/
AnnaBridge	165:e614a9f1c9e2	1331
AnnaBridge	165:e614a9f1c9e2	1332	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) \|\| \
AnnaBridge	165:e614a9f1c9e2	1333	((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge	165:e614a9f1c9e2	1334	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	165:e614a9f1c9e2	1335	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	165:e614a9f1c9e2	1336	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	165:e614a9f1c9e2	1337	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	165:e614a9f1c9e2	1338	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge	165:e614a9f1c9e2	1339	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	165:e614a9f1c9e2	1340	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	165:e614a9f1c9e2	1341	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	165:e614a9f1c9e2	1342	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	165:e614a9f1c9e2	1343	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
AnnaBridge	165:e614a9f1c9e2	1344	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
AnnaBridge	165:e614a9f1c9e2	1345	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	165:e614a9f1c9e2	1346	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
AnnaBridge	165:e614a9f1c9e2	1347	((__PLL__) == RCC_PLL_ON))
AnnaBridge	165:e614a9f1c9e2	1348
AnnaBridge	165:e614a9f1c9e2	1349	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
AnnaBridge	165:e614a9f1c9e2	1350	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
AnnaBridge	165:e614a9f1c9e2	1351	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
AnnaBridge	165:e614a9f1c9e2	1352	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
AnnaBridge	165:e614a9f1c9e2	1353	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	165:e614a9f1c9e2	1354	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	165:e614a9f1c9e2	1355	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	165:e614a9f1c9e2	1356	#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
AnnaBridge	165:e614a9f1c9e2	1357	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
AnnaBridge	165:e614a9f1c9e2	1358	((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
AnnaBridge	165:e614a9f1c9e2	1359	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	165:e614a9f1c9e2	1360	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	165:e614a9f1c9e2	1361	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	165:e614a9f1c9e2	1362	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	165:e614a9f1c9e2	1363	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	165:e614a9f1c9e2	1364	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	165:e614a9f1c9e2	1365	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	165:e614a9f1c9e2	1366	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	165:e614a9f1c9e2	1367	#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
AnnaBridge	165:e614a9f1c9e2	1368	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
AnnaBridge	165:e614a9f1c9e2	1369	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
AnnaBridge	165:e614a9f1c9e2	1370	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	165:e614a9f1c9e2	1371	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	165:e614a9f1c9e2	1372	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
AnnaBridge	165:e614a9f1c9e2	1373
AnnaBridge	165:e614a9f1c9e2	1374	/**
AnnaBridge	165:e614a9f1c9e2	1375	* @}
AnnaBridge	165:e614a9f1c9e2	1376	*/
AnnaBridge	165:e614a9f1c9e2	1377
<>	144:ef7eb2e8f9f7	1378	/**
<>	144:ef7eb2e8f9f7	1379	* @}
<>	144:ef7eb2e8f9f7	1380	*/
<>	144:ef7eb2e8f9f7	1381
<>	144:ef7eb2e8f9f7	1382	/**
<>	144:ef7eb2e8f9f7	1383	* @}
<>	144:ef7eb2e8f9f7	1384	*/
<>	144:ef7eb2e8f9f7	1385
<>	144:ef7eb2e8f9f7	1386	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1387	}
<>	144:ef7eb2e8f9f7	1388	#endif
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	#endif /* __STM32F1xx_HAL_RCC_H */
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	1393