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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_pcd.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of PCD HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F1xx_HAL_PCD_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F1xx_HAL_PCD_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if defined(STM32F102x6) || defined(STM32F102xB) || \
<> 144:ef7eb2e8f9f7 45 defined(STM32F103x6) || defined(STM32F103xB) || \
<> 144:ef7eb2e8f9f7 46 defined(STM32F103xE) || defined(STM32F103xG) || \
<> 144:ef7eb2e8f9f7 47 defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 50 #include "stm32f1xx_ll_usb.h"
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 53 * @{
<> 144:ef7eb2e8f9f7 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /** @addtogroup PCD
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61 /** @defgroup PCD_Exported_Types PCD Exported Types
<> 144:ef7eb2e8f9f7 62 * @{
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @brief PCD State structure definition
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68 typedef enum
<> 144:ef7eb2e8f9f7 69 {
AnnaBridge 165:e614a9f1c9e2 70 HAL_PCD_STATE_RESET = 0x00U,
AnnaBridge 165:e614a9f1c9e2 71 HAL_PCD_STATE_READY = 0x01U,
AnnaBridge 165:e614a9f1c9e2 72 HAL_PCD_STATE_ERROR = 0x02U,
AnnaBridge 165:e614a9f1c9e2 73 HAL_PCD_STATE_BUSY = 0x03U,
AnnaBridge 165:e614a9f1c9e2 74 HAL_PCD_STATE_TIMEOUT = 0x04U
<> 144:ef7eb2e8f9f7 75 } PCD_StateTypeDef;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #if defined (USB)
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @brief PCD double buffered endpoint direction
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 typedef enum
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 PCD_EP_DBUF_OUT,
<> 144:ef7eb2e8f9f7 84 PCD_EP_DBUF_IN,
<> 144:ef7eb2e8f9f7 85 PCD_EP_DBUF_ERR,
<> 144:ef7eb2e8f9f7 86 }PCD_EP_DBUF_DIR;
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /**
<> 144:ef7eb2e8f9f7 89 * @brief PCD endpoint buffer number
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91 typedef enum
<> 144:ef7eb2e8f9f7 92 {
<> 144:ef7eb2e8f9f7 93 PCD_EP_NOBUF,
<> 144:ef7eb2e8f9f7 94 PCD_EP_BUF0,
<> 144:ef7eb2e8f9f7 95 PCD_EP_BUF1
<> 144:ef7eb2e8f9f7 96 }PCD_EP_BUF_NUM;
<> 144:ef7eb2e8f9f7 97 #endif /* USB */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #if defined (USB_OTG_FS)
<> 144:ef7eb2e8f9f7 100 typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
<> 144:ef7eb2e8f9f7 101 typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
<> 144:ef7eb2e8f9f7 102 typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
<> 144:ef7eb2e8f9f7 103 #endif /* USB_OTG_FS */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 #if defined (USB)
<> 144:ef7eb2e8f9f7 106 typedef USB_TypeDef PCD_TypeDef;
<> 144:ef7eb2e8f9f7 107 typedef USB_CfgTypeDef PCD_InitTypeDef;
<> 144:ef7eb2e8f9f7 108 typedef USB_EPTypeDef PCD_EPTypeDef;
<> 144:ef7eb2e8f9f7 109 #endif /* USB */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /**
<> 144:ef7eb2e8f9f7 112 * @brief PCD Handle Structure definition
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 typedef struct
<> 144:ef7eb2e8f9f7 115 {
<> 144:ef7eb2e8f9f7 116 PCD_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 117 PCD_InitTypeDef Init; /*!< PCD required parameters */
<> 144:ef7eb2e8f9f7 118 __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */
AnnaBridge 165:e614a9f1c9e2 119 PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
AnnaBridge 165:e614a9f1c9e2 120 PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
<> 144:ef7eb2e8f9f7 121 HAL_LockTypeDef Lock; /*!< PCD peripheral status */
<> 144:ef7eb2e8f9f7 122 __IO PCD_StateTypeDef State; /*!< PCD communication state */
AnnaBridge 165:e614a9f1c9e2 123 uint32_t Setup[12U]; /*!< Setup packet buffer */
<> 144:ef7eb2e8f9f7 124 void *pData; /*!< Pointer to upper stack Handler */
<> 144:ef7eb2e8f9f7 125 } PCD_HandleTypeDef;
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @}
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Include PCD HAL Extension module */
<> 144:ef7eb2e8f9f7 132 #include "stm32f1xx_hal_pcd_ex.h"
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 135 /** @defgroup PCD_Exported_Constants PCD Exported Constants
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** @defgroup PCD_Speed PCD Speed
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
AnnaBridge 165:e614a9f1c9e2 142 #define PCD_SPEED_HIGH 0U /* Not Supported */
AnnaBridge 165:e614a9f1c9e2 143 #define PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */
AnnaBridge 165:e614a9f1c9e2 144 #define PCD_SPEED_FULL 2U
<> 144:ef7eb2e8f9f7 145 /**
<> 144:ef7eb2e8f9f7 146 * @}
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @defgroup PCD_PHY_Module PCD PHY Module
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
AnnaBridge 165:e614a9f1c9e2 152 #define PCD_PHY_EMBEDDED 2U
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @}
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
<> 144:ef7eb2e8f9f7 158 * @{
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160 #ifndef USBD_FS_TRDT_VALUE
AnnaBridge 165:e614a9f1c9e2 161 #define USBD_FS_TRDT_VALUE 5U
<> 144:ef7eb2e8f9f7 162 #endif /* USBD_FS_TRDT_VALUE */
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @}
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /**
<> 144:ef7eb2e8f9f7 168 * @}
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 172 /** @defgroup PCD_Exported_Macros PCD Exported Macros
<> 144:ef7eb2e8f9f7 173 * @brief macros to handle interrupts and specific clock configurations
<> 144:ef7eb2e8f9f7 174 * @{
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 #if defined (USB_OTG_FS)
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 #define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 179 #define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 182 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
AnnaBridge 165:e614a9f1c9e2 183 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
<> 144:ef7eb2e8f9f7 186 ~(USB_OTG_PCGCCTL_STOPCLK)
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
<> 144:ef7eb2e8f9f7 189
AnnaBridge 165:e614a9f1c9e2 190 #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
<> 144:ef7eb2e8f9f7 193 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
<> 144:ef7eb2e8f9f7 194 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
<> 144:ef7eb2e8f9f7 195 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
<> 144:ef7eb2e8f9f7 198 do{ \
<> 144:ef7eb2e8f9f7 199 EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 200 EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
AnnaBridge 165:e614a9f1c9e2 201 } while(0U)
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 204 do{ \
<> 144:ef7eb2e8f9f7 205 EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 206 EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
AnnaBridge 165:e614a9f1c9e2 207 } while(0U)
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 210 do{ \
<> 144:ef7eb2e8f9f7 211 EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 212 EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 213 EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
<> 144:ef7eb2e8f9f7 214 EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
AnnaBridge 165:e614a9f1c9e2 215 } while(0U)
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
<> 144:ef7eb2e8f9f7 218 #endif /* USB_OTG_FS */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 #if defined (USB)
<> 144:ef7eb2e8f9f7 221 #define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 222 #define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
<> 144:ef7eb2e8f9f7 223 #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 224 #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
<> 144:ef7eb2e8f9f7 227 #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
<> 144:ef7eb2e8f9f7 228 #define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
<> 144:ef7eb2e8f9f7 229 #define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
<> 144:ef7eb2e8f9f7 232 do{ \
<> 144:ef7eb2e8f9f7 233 EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 234 EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
AnnaBridge 165:e614a9f1c9e2 235 } while(0U)
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 #define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 238 do{ \
<> 144:ef7eb2e8f9f7 239 EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 240 EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
AnnaBridge 165:e614a9f1c9e2 241 } while(0U)
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
<> 144:ef7eb2e8f9f7 244 do{ \
<> 144:ef7eb2e8f9f7 245 EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 246 EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
<> 144:ef7eb2e8f9f7 247 EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
<> 144:ef7eb2e8f9f7 248 EXTI->FTSR |= USB_WAKEUP_EXTI_LINE; \
AnnaBridge 165:e614a9f1c9e2 249 } while(0U)
<> 144:ef7eb2e8f9f7 250 #endif /* USB */
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @}
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 257 /** @addtogroup PCD_Exported_Functions PCD Exported Functions
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /* Initialization/de-initialization functions ********************************/
<> 144:ef7eb2e8f9f7 262 /** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 263 * @{
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 266 HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 267 void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 268 void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 274 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 275 /** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 276 * @{
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 279 HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 280 void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
<> 144:ef7eb2e8f9f7 283 void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
<> 144:ef7eb2e8f9f7 284 void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 285 void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 286 void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 287 void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 288 void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 289 void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
<> 144:ef7eb2e8f9f7 290 void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
<> 144:ef7eb2e8f9f7 291 void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 292 void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @}
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 298 /** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 299 * @{
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 302 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 303 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
<> 144:ef7eb2e8f9f7 304 HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
<> 144:ef7eb2e8f9f7 305 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
<> 144:ef7eb2e8f9f7 306 HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
<> 144:ef7eb2e8f9f7 307 HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
<> 144:ef7eb2e8f9f7 308 uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
<> 144:ef7eb2e8f9f7 309 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
<> 144:ef7eb2e8f9f7 310 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
<> 144:ef7eb2e8f9f7 311 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
<> 144:ef7eb2e8f9f7 312 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 313 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @}
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 319 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @}
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 332 /** @defgroup PCD_Private_Constants PCD Private Constants
<> 144:ef7eb2e8f9f7 333 * @{
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 /** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
<> 144:ef7eb2e8f9f7 336 * @{
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 #if defined (USB_OTG_FS)
AnnaBridge 165:e614a9f1c9e2 339 #define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
AnnaBridge 165:e614a9f1c9e2 340 #define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
AnnaBridge 165:e614a9f1c9e2 341 #define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
<> 144:ef7eb2e8f9f7 342
AnnaBridge 165:e614a9f1c9e2 343 #define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
<> 144:ef7eb2e8f9f7 344 #endif /* USB_OTG_FS */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 #if defined (USB)
AnnaBridge 165:e614a9f1c9e2 347 #define USB_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
<> 144:ef7eb2e8f9f7 348 #endif /* USB */
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 #if defined (USB)
<> 144:ef7eb2e8f9f7 354 /** @defgroup PCD_EP0_MPS PCD EP0 MPS
<> 144:ef7eb2e8f9f7 355 * @{
<> 144:ef7eb2e8f9f7 356 */
<> 144:ef7eb2e8f9f7 357 #define PCD_EP0MPS_64 DEP0CTL_MPS_64
<> 144:ef7eb2e8f9f7 358 #define PCD_EP0MPS_32 DEP0CTL_MPS_32
<> 144:ef7eb2e8f9f7 359 #define PCD_EP0MPS_16 DEP0CTL_MPS_16
<> 144:ef7eb2e8f9f7 360 #define PCD_EP0MPS_08 DEP0CTL_MPS_8
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @defgroup PCD_ENDP PCD ENDP
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 #define PCD_ENDP0 ((uint8_t)0)
<> 144:ef7eb2e8f9f7 369 #define PCD_ENDP1 ((uint8_t)1)
<> 144:ef7eb2e8f9f7 370 #define PCD_ENDP2 ((uint8_t)2)
<> 144:ef7eb2e8f9f7 371 #define PCD_ENDP3 ((uint8_t)3)
<> 144:ef7eb2e8f9f7 372 #define PCD_ENDP4 ((uint8_t)4)
<> 144:ef7eb2e8f9f7 373 #define PCD_ENDP5 ((uint8_t)5)
<> 144:ef7eb2e8f9f7 374 #define PCD_ENDP6 ((uint8_t)6)
<> 144:ef7eb2e8f9f7 375 #define PCD_ENDP7 ((uint8_t)7)
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 * @}
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
<> 144:ef7eb2e8f9f7 381 * @{
<> 144:ef7eb2e8f9f7 382 */
AnnaBridge 165:e614a9f1c9e2 383 #define PCD_SNG_BUF 0U
AnnaBridge 165:e614a9f1c9e2 384 #define PCD_DBL_BUF 1U
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 #endif /* USB */
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @}
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 394 /** @addtogroup PCD_Private_Macros PCD Private Macros
<> 144:ef7eb2e8f9f7 395 * @{
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 #if defined (USB)
<> 144:ef7eb2e8f9f7 398 /* SetENDPOINT */
AnnaBridge 165:e614a9f1c9e2 399 #define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* GetENDPOINT */
AnnaBridge 165:e614a9f1c9e2 402 #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2U))
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* ENDPOINT transfer */
<> 144:ef7eb2e8f9f7 405 #define USB_EP0StartXfer USB_EPStartXfer
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /**
<> 144:ef7eb2e8f9f7 408 * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
<> 144:ef7eb2e8f9f7 409 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 410 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 411 * @param wType: Endpoint Type.
<> 144:ef7eb2e8f9f7 412 * @retval None
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
AnnaBridge 165:e614a9f1c9e2 415 ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /**
<> 144:ef7eb2e8f9f7 418 * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
<> 144:ef7eb2e8f9f7 419 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 420 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 421 * @retval Endpoint Type
<> 144:ef7eb2e8f9f7 422 */
<> 144:ef7eb2e8f9f7 423 #define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /**
<> 144:ef7eb2e8f9f7 426 * @brief free buffer used from the application realizing it to the line
<> 144:ef7eb2e8f9f7 427 toggles bit SW_BUF in the double buffered endpoint register
<> 144:ef7eb2e8f9f7 428 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 429 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 430 * @param bDir: Direction
<> 144:ef7eb2e8f9f7 431 * @retval None
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 #define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
<> 144:ef7eb2e8f9f7 434 {\
<> 144:ef7eb2e8f9f7 435 if ((bDir) == PCD_EP_DBUF_OUT)\
<> 144:ef7eb2e8f9f7 436 { /* OUT double buffered endpoint */\
<> 144:ef7eb2e8f9f7 437 PCD_TX_DTOG((USBx), (bEpNum));\
<> 144:ef7eb2e8f9f7 438 }\
<> 144:ef7eb2e8f9f7 439 else if ((bDir) == PCD_EP_DBUF_IN)\
<> 144:ef7eb2e8f9f7 440 { /* IN double buffered endpoint */\
<> 144:ef7eb2e8f9f7 441 PCD_RX_DTOG((USBx), (bEpNum));\
<> 144:ef7eb2e8f9f7 442 }\
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /**
<> 144:ef7eb2e8f9f7 446 * @brief gets direction of the double buffered endpoint
<> 144:ef7eb2e8f9f7 447 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 448 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 449 * @retval EP_DBUF_OUT, EP_DBUF_IN,
<> 144:ef7eb2e8f9f7 450 * EP_DBUF_ERR if the endpoint counter not yet programmed.
<> 144:ef7eb2e8f9f7 451 */
<> 144:ef7eb2e8f9f7 452 #define PCD_GET_DB_DIR(USBx, bEpNum)\
<> 144:ef7eb2e8f9f7 453 {\
<> 144:ef7eb2e8f9f7 454 if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
<> 144:ef7eb2e8f9f7 455 return(PCD_EP_DBUF_OUT);\
<> 144:ef7eb2e8f9f7 456 else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
<> 144:ef7eb2e8f9f7 457 return(PCD_EP_DBUF_IN);\
<> 144:ef7eb2e8f9f7 458 else\
<> 144:ef7eb2e8f9f7 459 return(PCD_EP_DBUF_ERR);\
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
<> 144:ef7eb2e8f9f7 464 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 465 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 466 * @param wState: new state
<> 144:ef7eb2e8f9f7 467 * @retval None
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
<> 144:ef7eb2e8f9f7 470 \
<> 144:ef7eb2e8f9f7 471 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
<> 144:ef7eb2e8f9f7 472 /* toggle first bit ? */ \
AnnaBridge 165:e614a9f1c9e2 473 if((USB_EPTX_DTOG1 & (wState))!= 0U)\
<> 144:ef7eb2e8f9f7 474 { \
<> 144:ef7eb2e8f9f7 475 _wRegVal ^= USB_EPTX_DTOG1; \
<> 144:ef7eb2e8f9f7 476 } \
<> 144:ef7eb2e8f9f7 477 /* toggle second bit ? */ \
AnnaBridge 165:e614a9f1c9e2 478 if((USB_EPTX_DTOG2 & (wState))!= 0U) \
<> 144:ef7eb2e8f9f7 479 { \
<> 144:ef7eb2e8f9f7 480 _wRegVal ^= USB_EPTX_DTOG2; \
<> 144:ef7eb2e8f9f7 481 } \
<> 144:ef7eb2e8f9f7 482 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
<> 144:ef7eb2e8f9f7 483 } /* PCD_SET_EP_TX_STATUS */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /**
<> 144:ef7eb2e8f9f7 486 * @brief sets the status for rx transfer (bits STAT_TX[1:0])
<> 144:ef7eb2e8f9f7 487 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 488 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 489 * @param wState: new state
<> 144:ef7eb2e8f9f7 490 * @retval None
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
<> 144:ef7eb2e8f9f7 493 register uint16_t _wRegVal; \
<> 144:ef7eb2e8f9f7 494 \
<> 144:ef7eb2e8f9f7 495 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
<> 144:ef7eb2e8f9f7 496 /* toggle first bit ? */ \
AnnaBridge 165:e614a9f1c9e2 497 if((USB_EPRX_DTOG1 & (wState))!= 0U) \
<> 144:ef7eb2e8f9f7 498 { \
<> 144:ef7eb2e8f9f7 499 _wRegVal ^= USB_EPRX_DTOG1; \
<> 144:ef7eb2e8f9f7 500 } \
<> 144:ef7eb2e8f9f7 501 /* toggle second bit ? */ \
AnnaBridge 165:e614a9f1c9e2 502 if((USB_EPRX_DTOG2 & (wState))!= 0U) \
<> 144:ef7eb2e8f9f7 503 { \
<> 144:ef7eb2e8f9f7 504 _wRegVal ^= USB_EPRX_DTOG2; \
<> 144:ef7eb2e8f9f7 505 } \
<> 144:ef7eb2e8f9f7 506 PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
<> 144:ef7eb2e8f9f7 507 } /* PCD_SET_EP_RX_STATUS */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
<> 144:ef7eb2e8f9f7 511 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 512 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 513 * @param wStaterx: new state.
<> 144:ef7eb2e8f9f7 514 * @param wStatetx: new state.
<> 144:ef7eb2e8f9f7 515 * @retval None
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 #define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
<> 144:ef7eb2e8f9f7 518 register uint32_t _wRegVal; \
<> 144:ef7eb2e8f9f7 519 \
<> 144:ef7eb2e8f9f7 520 _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
<> 144:ef7eb2e8f9f7 521 /* toggle first bit ? */ \
AnnaBridge 165:e614a9f1c9e2 522 if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
<> 144:ef7eb2e8f9f7 523 { \
<> 144:ef7eb2e8f9f7 524 _wRegVal ^= USB_EPRX_DTOG1; \
<> 144:ef7eb2e8f9f7 525 } \
<> 144:ef7eb2e8f9f7 526 /* toggle second bit ? */ \
AnnaBridge 165:e614a9f1c9e2 527 if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
<> 144:ef7eb2e8f9f7 528 { \
<> 144:ef7eb2e8f9f7 529 _wRegVal ^= USB_EPRX_DTOG2; \
<> 144:ef7eb2e8f9f7 530 } \
<> 144:ef7eb2e8f9f7 531 /* toggle first bit ? */ \
AnnaBridge 165:e614a9f1c9e2 532 if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
<> 144:ef7eb2e8f9f7 533 { \
<> 144:ef7eb2e8f9f7 534 _wRegVal ^= USB_EPTX_DTOG1; \
<> 144:ef7eb2e8f9f7 535 } \
<> 144:ef7eb2e8f9f7 536 /* toggle second bit ? */ \
AnnaBridge 165:e614a9f1c9e2 537 if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
<> 144:ef7eb2e8f9f7 538 { \
<> 144:ef7eb2e8f9f7 539 _wRegVal ^= USB_EPTX_DTOG2; \
<> 144:ef7eb2e8f9f7 540 } \
<> 144:ef7eb2e8f9f7 541 PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
<> 144:ef7eb2e8f9f7 542 } /* PCD_SET_EP_TXRX_STATUS */
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /**
<> 144:ef7eb2e8f9f7 545 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
<> 144:ef7eb2e8f9f7 546 * /STAT_RX[1:0])
<> 144:ef7eb2e8f9f7 547 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 548 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 549 * @retval status
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 #define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
<> 144:ef7eb2e8f9f7 552 #define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /**
<> 144:ef7eb2e8f9f7 555 * @brief sets directly the VALID tx/rx-status into the endpoint register
<> 144:ef7eb2e8f9f7 556 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 557 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 558 * @retval None
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 #define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
<> 144:ef7eb2e8f9f7 561 #define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @brief checks stall condition in an endpoint.
<> 144:ef7eb2e8f9f7 565 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 566 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 567 * @retval TRUE = endpoint in stall condition.
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569 #define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
<> 144:ef7eb2e8f9f7 570 == USB_EP_TX_STALL)
<> 144:ef7eb2e8f9f7 571 #define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
<> 144:ef7eb2e8f9f7 572 == USB_EP_RX_STALL)
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /**
<> 144:ef7eb2e8f9f7 575 * @brief set & clear EP_KIND bit.
<> 144:ef7eb2e8f9f7 576 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 577 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 578 * @retval None
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 #define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
<> 144:ef7eb2e8f9f7 581 (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
<> 144:ef7eb2e8f9f7 582 #define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
<> 144:ef7eb2e8f9f7 583 (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /**
<> 144:ef7eb2e8f9f7 586 * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
<> 144:ef7eb2e8f9f7 587 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 588 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 589 * @retval None
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 #define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
<> 144:ef7eb2e8f9f7 592 #define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /**
<> 144:ef7eb2e8f9f7 595 * @brief Sets/clears directly EP_KIND bit in the endpoint register.
<> 144:ef7eb2e8f9f7 596 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 597 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 598 * @retval None
<> 144:ef7eb2e8f9f7 599 */
<> 144:ef7eb2e8f9f7 600 #define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
<> 144:ef7eb2e8f9f7 601 #define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
<> 144:ef7eb2e8f9f7 605 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 606 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 607 * @retval None
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
AnnaBridge 165:e614a9f1c9e2 610 PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
<> 144:ef7eb2e8f9f7 611 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
AnnaBridge 165:e614a9f1c9e2 612 PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /**
<> 144:ef7eb2e8f9f7 615 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
<> 144:ef7eb2e8f9f7 616 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 617 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 618 * @retval None
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 #define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
<> 144:ef7eb2e8f9f7 621 USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
<> 144:ef7eb2e8f9f7 622 #define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
<> 144:ef7eb2e8f9f7 623 USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /**
<> 144:ef7eb2e8f9f7 626 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
<> 144:ef7eb2e8f9f7 627 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 628 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 629 * @retval None
<> 144:ef7eb2e8f9f7 630 */
AnnaBridge 165:e614a9f1c9e2 631 #define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0U)\
<> 144:ef7eb2e8f9f7 632 { \
<> 144:ef7eb2e8f9f7 633 PCD_RX_DTOG((USBx), (bEpNum)); \
<> 144:ef7eb2e8f9f7 634 }
AnnaBridge 165:e614a9f1c9e2 635 #define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0U)\
<> 144:ef7eb2e8f9f7 636 { \
<> 144:ef7eb2e8f9f7 637 PCD_TX_DTOG((USBx), (bEpNum)); \
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /**
<> 144:ef7eb2e8f9f7 641 * @brief Sets address in an endpoint register.
<> 144:ef7eb2e8f9f7 642 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 643 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 644 * @param bAddr: Address.
<> 144:ef7eb2e8f9f7 645 * @retval None
<> 144:ef7eb2e8f9f7 646 */
<> 144:ef7eb2e8f9f7 647 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
<> 144:ef7eb2e8f9f7 648 USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
<> 144:ef7eb2e8f9f7 651
AnnaBridge 165:e614a9f1c9e2 652 #define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U)))
AnnaBridge 165:e614a9f1c9e2 653 #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U)))
AnnaBridge 165:e614a9f1c9e2 654 #define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U)))
AnnaBridge 165:e614a9f1c9e2 655 #define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U)))
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
<> 144:ef7eb2e8f9f7 658 uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
<> 144:ef7eb2e8f9f7 659 PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /**
<> 144:ef7eb2e8f9f7 663 * @brief sets address of the tx/rx buffer.
<> 144:ef7eb2e8f9f7 664 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 665 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 666 * @param wAddr: address to be set (must be word aligned).
<> 144:ef7eb2e8f9f7 667 * @retval None
<> 144:ef7eb2e8f9f7 668 */
AnnaBridge 165:e614a9f1c9e2 669 #define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
AnnaBridge 165:e614a9f1c9e2 670 #define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @brief Gets address of the tx/rx buffer.
<> 144:ef7eb2e8f9f7 674 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 675 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 676 * @retval address of the buffer.
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678 #define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
<> 144:ef7eb2e8f9f7 679 #define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @brief Sets counter of rx buffer with no. of blocks.
<> 144:ef7eb2e8f9f7 683 * @param dwReg: Register
<> 144:ef7eb2e8f9f7 684 * @param wCount: Counter.
<> 144:ef7eb2e8f9f7 685 * @param wNBlocks: no. of Blocks.
<> 144:ef7eb2e8f9f7 686 * @retval None
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688 #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
AnnaBridge 165:e614a9f1c9e2 689 (wNBlocks) = (wCount) >> 5U;\
AnnaBridge 165:e614a9f1c9e2 690 if(((wCount) & 0x1FU) == 0U)\
<> 144:ef7eb2e8f9f7 691 { \
<> 144:ef7eb2e8f9f7 692 (wNBlocks)--;\
<> 144:ef7eb2e8f9f7 693 } \
AnnaBridge 165:e614a9f1c9e2 694 *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | 0x8000U); \
<> 144:ef7eb2e8f9f7 695 }/* PCD_CALC_BLK32 */
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
AnnaBridge 165:e614a9f1c9e2 698 (wNBlocks) = (wCount) >> 1U;\
AnnaBridge 165:e614a9f1c9e2 699 if(((wCount) & 0x01U) != 0U)\
<> 144:ef7eb2e8f9f7 700 { \
<> 144:ef7eb2e8f9f7 701 (wNBlocks)++;\
<> 144:ef7eb2e8f9f7 702 } \
AnnaBridge 165:e614a9f1c9e2 703 *pdwReg = (uint16_t)((wNBlocks) << 10U);\
<> 144:ef7eb2e8f9f7 704 }/* PCD_CALC_BLK2 */
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
<> 144:ef7eb2e8f9f7 707 uint16_t wNBlocks;\
AnnaBridge 165:e614a9f1c9e2 708 if((wCount) > 62U) \
<> 144:ef7eb2e8f9f7 709 { \
<> 144:ef7eb2e8f9f7 710 PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \
<> 144:ef7eb2e8f9f7 711 } \
<> 144:ef7eb2e8f9f7 712 else \
<> 144:ef7eb2e8f9f7 713 { \
<> 144:ef7eb2e8f9f7 714 PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \
<> 144:ef7eb2e8f9f7 715 } \
<> 144:ef7eb2e8f9f7 716 }/* PCD_SET_EP_CNT_RX_REG */
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
<> 144:ef7eb2e8f9f7 719 uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
<> 144:ef7eb2e8f9f7 720 PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /**
<> 144:ef7eb2e8f9f7 724 * @brief sets counter for the tx/rx buffer.
<> 144:ef7eb2e8f9f7 725 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 726 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 727 * @param wCount: Counter value.
<> 144:ef7eb2e8f9f7 728 * @retval None
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730 #define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /**
<> 144:ef7eb2e8f9f7 734 * @brief gets counter of the tx buffer.
<> 144:ef7eb2e8f9f7 735 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 736 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 737 * @retval Counter value
<> 144:ef7eb2e8f9f7 738 */
AnnaBridge 165:e614a9f1c9e2 739 #define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)
AnnaBridge 165:e614a9f1c9e2 740 #define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /**
<> 144:ef7eb2e8f9f7 743 * @brief Sets buffer 0/1 address in a double buffer endpoint.
<> 144:ef7eb2e8f9f7 744 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 745 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 746 * @param wBuf0Addr: buffer 0 address.
<> 144:ef7eb2e8f9f7 747 * @retval Counter value
<> 144:ef7eb2e8f9f7 748 */
<> 144:ef7eb2e8f9f7 749 #define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
<> 144:ef7eb2e8f9f7 750 #define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /**
<> 144:ef7eb2e8f9f7 753 * @brief Sets addresses in a double buffer endpoint.
<> 144:ef7eb2e8f9f7 754 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 755 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 756 * @param wBuf0Addr: buffer 0 address.
<> 144:ef7eb2e8f9f7 757 * @param wBuf1Addr = buffer 1 address.
<> 144:ef7eb2e8f9f7 758 * @retval None
<> 144:ef7eb2e8f9f7 759 */
<> 144:ef7eb2e8f9f7 760 #define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
<> 144:ef7eb2e8f9f7 761 PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
<> 144:ef7eb2e8f9f7 762 PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
<> 144:ef7eb2e8f9f7 763 } /* PCD_SET_EP_DBUF_ADDR */
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /**
<> 144:ef7eb2e8f9f7 766 * @brief Gets buffer 0/1 address of a double buffer endpoint.
<> 144:ef7eb2e8f9f7 767 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 768 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 769 * @retval None
<> 144:ef7eb2e8f9f7 770 */
<> 144:ef7eb2e8f9f7 771 #define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
<> 144:ef7eb2e8f9f7 772 #define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /**
<> 144:ef7eb2e8f9f7 775 * @brief Gets buffer 0/1 address of a double buffer endpoint.
<> 144:ef7eb2e8f9f7 776 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 777 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 778 * @param bDir: endpoint dir EP_DBUF_OUT = OUT
<> 144:ef7eb2e8f9f7 779 * EP_DBUF_IN = IN
<> 144:ef7eb2e8f9f7 780 * @param wCount: Counter value
<> 144:ef7eb2e8f9f7 781 * @retval None
<> 144:ef7eb2e8f9f7 782 */
<> 144:ef7eb2e8f9f7 783 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
<> 144:ef7eb2e8f9f7 784 if((bDir) == PCD_EP_DBUF_OUT)\
<> 144:ef7eb2e8f9f7 785 /* OUT endpoint */ \
<> 144:ef7eb2e8f9f7 786 {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
<> 144:ef7eb2e8f9f7 787 else if((bDir) == PCD_EP_DBUF_IN)\
<> 144:ef7eb2e8f9f7 788 /* IN endpoint */ \
<> 144:ef7eb2e8f9f7 789 *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
<> 144:ef7eb2e8f9f7 790 } /* SetEPDblBuf0Count*/
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
<> 144:ef7eb2e8f9f7 793 if((bDir) == PCD_EP_DBUF_OUT)\
<> 144:ef7eb2e8f9f7 794 {/* OUT endpoint */ \
<> 144:ef7eb2e8f9f7 795 PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \
<> 144:ef7eb2e8f9f7 796 } \
<> 144:ef7eb2e8f9f7 797 else if((bDir) == PCD_EP_DBUF_IN)\
<> 144:ef7eb2e8f9f7 798 {/* IN endpoint */ \
<> 144:ef7eb2e8f9f7 799 *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
<> 144:ef7eb2e8f9f7 800 } \
<> 144:ef7eb2e8f9f7 801 } /* SetEPDblBuf1Count */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
<> 144:ef7eb2e8f9f7 804 PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
<> 144:ef7eb2e8f9f7 805 PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
<> 144:ef7eb2e8f9f7 806 } /* PCD_SET_EP_DBUF_CNT */
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /**
<> 144:ef7eb2e8f9f7 809 * @brief Gets buffer 0/1 rx/tx counter for double buffering.
<> 144:ef7eb2e8f9f7 810 * @param USBx: USB peripheral instance register address.
<> 144:ef7eb2e8f9f7 811 * @param bEpNum: Endpoint Number.
<> 144:ef7eb2e8f9f7 812 * @retval None
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814 #define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
<> 144:ef7eb2e8f9f7 815 #define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 #endif /* USB */
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /** @defgroup PCD_Instance_definition PCD Instance definition
<> 144:ef7eb2e8f9f7 820 * @{
<> 144:ef7eb2e8f9f7 821 */
<> 144:ef7eb2e8f9f7 822 #define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
<> 144:ef7eb2e8f9f7 823 /**
<> 144:ef7eb2e8f9f7 824 * @}
<> 144:ef7eb2e8f9f7 825 */
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /**
<> 144:ef7eb2e8f9f7 828 * @}
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /**
<> 144:ef7eb2e8f9f7 832 * @}
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /**
<> 144:ef7eb2e8f9f7 836 * @}
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 #endif /* STM32F102x6 || STM32F102xB || */
<> 144:ef7eb2e8f9f7 840 /* STM32F103x6 || STM32F103xB || */
<> 144:ef7eb2e8f9f7 841 /* STM32F103xE || STM32F103xG || */
<> 144:ef7eb2e8f9f7 842 /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846 #endif
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 #endif /* __STM32F1xx_HAL_PCD_H */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/