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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_nor.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief NOR HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides a generic firmware to drive NOR memories mounted
<> 144:ef7eb2e8f9f7 7 * as external device.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 @verbatim
<> 144:ef7eb2e8f9f7 10 ==============================================================================
<> 144:ef7eb2e8f9f7 11 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 [..]
<> 144:ef7eb2e8f9f7 14 This driver is a generic layered driver which contains a set of APIs used to
<> 144:ef7eb2e8f9f7 15 control NOR flash memories. It uses the FSMC layer functions to interface
<> 144:ef7eb2e8f9f7 16 with NOR devices. This driver is used as follows:
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
<> 144:ef7eb2e8f9f7 19 with control and timing parameters for both normal and extended mode.
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 (+) Read NOR flash memory manufacturer code and device IDs using the function
<> 144:ef7eb2e8f9f7 22 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
<> 144:ef7eb2e8f9f7 23 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (+) Access NOR flash memory by read/write data unit operations using the functions
<> 144:ef7eb2e8f9f7 26 HAL_NOR_Read(), HAL_NOR_Program().
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 (+) Perform NOR flash erase block/chip operations using the functions
<> 144:ef7eb2e8f9f7 29 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 (+) Read the NOR flash CFI (common flash interface) IDs using the function
<> 144:ef7eb2e8f9f7 32 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
<> 144:ef7eb2e8f9f7 33 structure declared by the function caller.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
<> 144:ef7eb2e8f9f7 36 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (+) You can monitor the NOR device HAL state by calling the function
<> 144:ef7eb2e8f9f7 39 HAL_NOR_GetState()
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
<> 144:ef7eb2e8f9f7 42 If a NOR flash device contains different operations and/or implementations,
<> 144:ef7eb2e8f9f7 43 it should be implemented separately.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 *** NOR HAL driver macros list ***
<> 144:ef7eb2e8f9f7 46 =============================================
<> 144:ef7eb2e8f9f7 47 [..]
<> 144:ef7eb2e8f9f7 48 Below the list of most used macros in NOR HAL driver.
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 (+) NOR_WRITE : NOR memory write data to specified address
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 @endverbatim
<> 144:ef7eb2e8f9f7 53 ******************************************************************************
<> 144:ef7eb2e8f9f7 54 * @attention
<> 144:ef7eb2e8f9f7 55 *
<> 144:ef7eb2e8f9f7 56 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 57 *
<> 144:ef7eb2e8f9f7 58 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 59 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 60 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 61 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 62 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 63 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 64 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 65 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 66 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 67 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 70 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 72 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 73 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 74 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 75 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 76 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 77 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 78 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 ******************************************************************************
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 84 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 87 * @{
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #ifdef HAL_NOR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 91 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /** @defgroup NOR NOR
<> 144:ef7eb2e8f9f7 94 * @brief NOR driver modules
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 /** @defgroup NOR_Private_Constants NOR Private Constants
<> 144:ef7eb2e8f9f7 100 * @{
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /* Constants to define address to set to write a command */
<> 144:ef7eb2e8f9f7 104 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 105 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 106 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
<> 144:ef7eb2e8f9f7 107 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 108 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 109 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
<> 144:ef7eb2e8f9f7 110 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /* Constants to define data to program a command */
<> 144:ef7eb2e8f9f7 113 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
<> 144:ef7eb2e8f9f7 114 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
<> 144:ef7eb2e8f9f7 115 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 116 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
<> 144:ef7eb2e8f9f7 117 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
<> 144:ef7eb2e8f9f7 118 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
<> 144:ef7eb2e8f9f7 119 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
<> 144:ef7eb2e8f9f7 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
<> 144:ef7eb2e8f9f7 121 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
<> 144:ef7eb2e8f9f7 122 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
<> 144:ef7eb2e8f9f7 125 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
<> 144:ef7eb2e8f9f7 126 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Mask on NOR STATUS REGISTER */
<> 144:ef7eb2e8f9f7 129 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
<> 144:ef7eb2e8f9f7 130 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @}
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /** @defgroup NOR_Private_Macros NOR Private Macros
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @defgroup NOR_Private_Variables NOR Private Variables
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /**
<> 144:ef7eb2e8f9f7 154 * @}
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** @defgroup NOR_Exported_Functions NOR Exported Functions
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 165 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 166 *
<> 144:ef7eb2e8f9f7 167 @verbatim
<> 144:ef7eb2e8f9f7 168 ==============================================================================
<> 144:ef7eb2e8f9f7 169 ##### NOR Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 170 ==============================================================================
<> 144:ef7eb2e8f9f7 171 [..]
<> 144:ef7eb2e8f9f7 172 This section provides functions allowing to initialize/de-initialize
<> 144:ef7eb2e8f9f7 173 the NOR memory
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 @endverbatim
<> 144:ef7eb2e8f9f7 176 * @{
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief Perform the NOR memory Initialization sequence
<> 144:ef7eb2e8f9f7 181 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 182 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 183 * @param Timing: pointer to NOR control timing structure
<> 144:ef7eb2e8f9f7 184 * @param ExtTiming: pointer to NOR extended mode timing structure
<> 144:ef7eb2e8f9f7 185 * @retval HAL status
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Check the NOR handle parameter */
<> 144:ef7eb2e8f9f7 190 if(hnor == NULL)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 if(hnor->State == HAL_NOR_STATE_RESET)
<> 144:ef7eb2e8f9f7 196 {
<> 144:ef7eb2e8f9f7 197 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 198 hnor->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 201 HAL_NOR_MspInit(hnor);
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Initialize NOR control Interface */
<> 144:ef7eb2e8f9f7 205 FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Initialize NOR timing Interface */
<> 144:ef7eb2e8f9f7 208 FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Initialize NOR extended mode timing Interface */
<> 144:ef7eb2e8f9f7 211 FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Enable the NORSRAM device */
<> 144:ef7eb2e8f9f7 214 __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Initialize NOR Memory Data Width*/
<> 144:ef7eb2e8f9f7 217 if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
<> 144:ef7eb2e8f9f7 218 {
<> 144:ef7eb2e8f9f7 219 uwNORMemoryDataWidth = NOR_MEMORY_8B;
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221 else
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 uwNORMemoryDataWidth = NOR_MEMORY_16B;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 227 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 return HAL_OK;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @brief Perform NOR memory De-Initialization sequence
<> 144:ef7eb2e8f9f7 234 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 235 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 236 * @retval HAL status
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 /* De-Initialize the low level hardware (MSP) */
<> 144:ef7eb2e8f9f7 241 HAL_NOR_MspDeInit(hnor);
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Configure the NOR registers with their reset values */
<> 144:ef7eb2e8f9f7 244 FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 247 hnor->State = HAL_NOR_STATE_RESET;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Release Lock */
<> 144:ef7eb2e8f9f7 250 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 return HAL_OK;
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief NOR MSP Init
<> 144:ef7eb2e8f9f7 257 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 258 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 259 * @retval None
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 264 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 265 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 266 the HAL_NOR_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @brief NOR MSP DeInit
<> 144:ef7eb2e8f9f7 272 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 273 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 274 * @retval None
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 277 {
<> 144:ef7eb2e8f9f7 278 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 279 UNUSED(hnor);
<> 144:ef7eb2e8f9f7 280 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 281 the HAL_NOR_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 282 */
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief NOR MSP Wait fro Ready/Busy signal
<> 144:ef7eb2e8f9f7 287 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 288 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 289 * @param Timeout: Maximum timeout value
<> 144:ef7eb2e8f9f7 290 * @retval None
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 293 {
<> 144:ef7eb2e8f9f7 294 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 295 UNUSED(hnor);
AnnaBridge 165:e614a9f1c9e2 296 UNUSED(Timeout);
<> 144:ef7eb2e8f9f7 297 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 298 the HAL_NOR_MspWait could be implemented in the user file
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 307 * @brief Input Output and memory control functions
<> 144:ef7eb2e8f9f7 308 *
<> 144:ef7eb2e8f9f7 309 @verbatim
<> 144:ef7eb2e8f9f7 310 ==============================================================================
<> 144:ef7eb2e8f9f7 311 ##### NOR Input and Output functions #####
<> 144:ef7eb2e8f9f7 312 ==============================================================================
<> 144:ef7eb2e8f9f7 313 [..]
<> 144:ef7eb2e8f9f7 314 This section provides functions allowing to use and control the NOR memory
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 @endverbatim
<> 144:ef7eb2e8f9f7 317 * @{
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /**
<> 144:ef7eb2e8f9f7 321 * @brief Read NOR flash IDs
<> 144:ef7eb2e8f9f7 322 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 323 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 324 * @param pNOR_ID : pointer to NOR ID structure
<> 144:ef7eb2e8f9f7 325 * @retval HAL status
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
<> 144:ef7eb2e8f9f7 328 {
AnnaBridge 165:e614a9f1c9e2 329 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Process Locked */
<> 144:ef7eb2e8f9f7 332 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 335 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 341 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 348 }
<> 144:ef7eb2e8f9f7 349 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 359 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Send read ID command */
<> 144:ef7eb2e8f9f7 362 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 363 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 364 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Read the NOR IDs */
<> 144:ef7eb2e8f9f7 367 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
<> 144:ef7eb2e8f9f7 368 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
<> 144:ef7eb2e8f9f7 369 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
<> 144:ef7eb2e8f9f7 370 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 373 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Process unlocked */
<> 144:ef7eb2e8f9f7 376 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 return HAL_OK;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @brief Returns the NOR memory to Read mode.
<> 144:ef7eb2e8f9f7 383 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 384 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 385 * @retval HAL status
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 388 {
AnnaBridge 165:e614a9f1c9e2 389 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Process Locked */
<> 144:ef7eb2e8f9f7 392 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 395 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 398 }
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 401 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 414 {
<> 144:ef7eb2e8f9f7 415 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 421 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Process unlocked */
<> 144:ef7eb2e8f9f7 424 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 return HAL_OK;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Read data from NOR memory
<> 144:ef7eb2e8f9f7 431 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 432 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 433 * @param pAddress: pointer to Device address
<> 144:ef7eb2e8f9f7 434 * @param pData : pointer to read data
<> 144:ef7eb2e8f9f7 435 * @retval HAL status
<> 144:ef7eb2e8f9f7 436 */
<> 144:ef7eb2e8f9f7 437 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 438 {
AnnaBridge 165:e614a9f1c9e2 439 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Process Locked */
<> 144:ef7eb2e8f9f7 442 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 445 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 451 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 452 {
<> 144:ef7eb2e8f9f7 453 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 454 }
<> 144:ef7eb2e8f9f7 455 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 464 {
<> 144:ef7eb2e8f9f7 465 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 469 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Send read data command */
<> 144:ef7eb2e8f9f7 472 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 473 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 474 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Read the data */
<> 144:ef7eb2e8f9f7 477 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 480 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Process unlocked */
<> 144:ef7eb2e8f9f7 483 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 return HAL_OK;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Program data to NOR memory
<> 144:ef7eb2e8f9f7 490 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 491 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 492 * @param pAddress: Device address
<> 144:ef7eb2e8f9f7 493 * @param pData : pointer to the data to write
<> 144:ef7eb2e8f9f7 494 * @retval HAL status
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
<> 144:ef7eb2e8f9f7 497 {
AnnaBridge 165:e614a9f1c9e2 498 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Process Locked */
<> 144:ef7eb2e8f9f7 501 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 504 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 510 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 525 }
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 528 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Send program data command */
<> 144:ef7eb2e8f9f7 531 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 532 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 533 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Write the data */
<> 144:ef7eb2e8f9f7 536 NOR_WRITE(pAddress, *pData);
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 539 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Process unlocked */
<> 144:ef7eb2e8f9f7 542 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 return HAL_OK;
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @brief Reads a block of data from the FSMC NOR memory.
<> 144:ef7eb2e8f9f7 549 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 550 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 551 * @param uwAddress: NOR memory internal address to read from.
<> 144:ef7eb2e8f9f7 552 * @param pData: pointer to the buffer that receives the data read from the
<> 144:ef7eb2e8f9f7 553 * NOR memory.
<> 144:ef7eb2e8f9f7 554 * @param uwBufferSize : number of Half word to read.
<> 144:ef7eb2e8f9f7 555 * @retval HAL status
<> 144:ef7eb2e8f9f7 556 */
<> 144:ef7eb2e8f9f7 557 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 558 {
AnnaBridge 165:e614a9f1c9e2 559 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /* Process Locked */
<> 144:ef7eb2e8f9f7 562 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 565 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 571 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 589 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Send read data command */
<> 144:ef7eb2e8f9f7 592 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 593 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 594 NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Read buffer */
AnnaBridge 165:e614a9f1c9e2 597 while( uwBufferSize > 0U)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 *pData++ = *(__IO uint16_t *)uwAddress;
AnnaBridge 165:e614a9f1c9e2 600 uwAddress += 2U;
<> 144:ef7eb2e8f9f7 601 uwBufferSize--;
<> 144:ef7eb2e8f9f7 602 }
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 605 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Process unlocked */
<> 144:ef7eb2e8f9f7 608 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 return HAL_OK;
<> 144:ef7eb2e8f9f7 611 }
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 /**
<> 144:ef7eb2e8f9f7 614 * @brief Writes a half-word buffer to the FSMC NOR memory. This function
<> 144:ef7eb2e8f9f7 615 * must be used only with S29GL128P NOR memory.
<> 144:ef7eb2e8f9f7 616 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 617 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 618 * @param uwAddress: NOR memory internal address from which the data
<> 144:ef7eb2e8f9f7 619 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
<> 144:ef7eb2e8f9f7 620 * 64 bytes boundary for example).
<> 144:ef7eb2e8f9f7 621 * @param pData: pointer to source data buffer.
<> 144:ef7eb2e8f9f7 622 * @param uwBufferSize: number of Half words to write.
<> 144:ef7eb2e8f9f7 623 * @note The maximum buffer size allowed is NOR memory dependent
<> 144:ef7eb2e8f9f7 624 * (can be 64 Bytes max for example).
<> 144:ef7eb2e8f9f7 625 * @retval HAL status
<> 144:ef7eb2e8f9f7 626 */
<> 144:ef7eb2e8f9f7 627 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 uint16_t * p_currentaddress = (uint16_t *)NULL;
<> 144:ef7eb2e8f9f7 630 uint16_t * p_endaddress = (uint16_t *)NULL;
AnnaBridge 165:e614a9f1c9e2 631 uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Process Locked */
<> 144:ef7eb2e8f9f7 634 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 637 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 643 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 661 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /* Initialize variables */
<> 144:ef7eb2e8f9f7 664 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
AnnaBridge 165:e614a9f1c9e2 665 p_endaddress = p_currentaddress + (uwBufferSize-1U);
<> 144:ef7eb2e8f9f7 666 lastloadedaddress = (uint32_t)(uwAddress);
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Issue unlock command sequence */
<> 144:ef7eb2e8f9f7 669 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 670 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Write Buffer Load Command */
<> 144:ef7eb2e8f9f7 673 NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
AnnaBridge 165:e614a9f1c9e2 674 NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Load Data into NOR Buffer */
<> 144:ef7eb2e8f9f7 677 while(p_currentaddress <= p_endaddress)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 /* Store last loaded address & data value (for polling) */
<> 144:ef7eb2e8f9f7 680 lastloadedaddress = (uint32_t)p_currentaddress;
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 NOR_WRITE(p_currentaddress, *pData++);
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 p_currentaddress++;
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 690 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /* Process unlocked */
<> 144:ef7eb2e8f9f7 693 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 return HAL_OK;
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /**
<> 144:ef7eb2e8f9f7 700 * @brief Erase the specified block of the NOR memory
<> 144:ef7eb2e8f9f7 701 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 702 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 703 * @param BlockAddress : Block to erase address
<> 144:ef7eb2e8f9f7 704 * @param Address: Device address
<> 144:ef7eb2e8f9f7 705 * @retval HAL status
<> 144:ef7eb2e8f9f7 706 */
<> 144:ef7eb2e8f9f7 707 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
<> 144:ef7eb2e8f9f7 708 {
AnnaBridge 165:e614a9f1c9e2 709 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 710
<> 144:ef7eb2e8f9f7 711 /* Process Locked */
<> 144:ef7eb2e8f9f7 712 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 715 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 721 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 724 }
<> 144:ef7eb2e8f9f7 725 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 732 }
<> 144:ef7eb2e8f9f7 733 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 739 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* Send block erase command sequence */
<> 144:ef7eb2e8f9f7 742 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 743 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 744 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 745 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 746 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 747 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 750 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Process unlocked */
<> 144:ef7eb2e8f9f7 753 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 return HAL_OK;
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 }
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /**
<> 144:ef7eb2e8f9f7 760 * @brief Erase the entire NOR chip.
<> 144:ef7eb2e8f9f7 761 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 762 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 763 * @param Address : Device address
<> 144:ef7eb2e8f9f7 764 * @retval HAL status
<> 144:ef7eb2e8f9f7 765 */
<> 144:ef7eb2e8f9f7 766 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
<> 144:ef7eb2e8f9f7 767 {
AnnaBridge 165:e614a9f1c9e2 768 /* Prevent unused argument(s) compilation warning */
AnnaBridge 165:e614a9f1c9e2 769 UNUSED(Address);
AnnaBridge 165:e614a9f1c9e2 770
AnnaBridge 165:e614a9f1c9e2 771 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Process Locked */
<> 144:ef7eb2e8f9f7 774 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 777 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 783 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 784 {
<> 144:ef7eb2e8f9f7 785 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 788 {
<> 144:ef7eb2e8f9f7 789 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 796 {
<> 144:ef7eb2e8f9f7 797 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 801 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* Send NOR chip erase command sequence */
<> 144:ef7eb2e8f9f7 804 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
<> 144:ef7eb2e8f9f7 805 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
<> 144:ef7eb2e8f9f7 806 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
<> 144:ef7eb2e8f9f7 807 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
<> 144:ef7eb2e8f9f7 808 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
<> 144:ef7eb2e8f9f7 809 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Check the NOR memory status and update the controller state */
<> 144:ef7eb2e8f9f7 812 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Process unlocked */
<> 144:ef7eb2e8f9f7 815 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 return HAL_OK;
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /**
<> 144:ef7eb2e8f9f7 821 * @brief Read NOR flash CFI IDs
<> 144:ef7eb2e8f9f7 822 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 823 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 824 * @param pNOR_CFI : pointer to NOR CFI IDs structure
<> 144:ef7eb2e8f9f7 825 * @retval HAL status
<> 144:ef7eb2e8f9f7 826 */
<> 144:ef7eb2e8f9f7 827 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
<> 144:ef7eb2e8f9f7 828 {
AnnaBridge 165:e614a9f1c9e2 829 uint32_t deviceaddress = 0U;
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Process Locked */
<> 144:ef7eb2e8f9f7 832 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 835 if(hnor->State == HAL_NOR_STATE_BUSY)
<> 144:ef7eb2e8f9f7 836 {
<> 144:ef7eb2e8f9f7 837 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Select the NOR device address */
<> 144:ef7eb2e8f9f7 841 if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 deviceaddress = NOR_MEMORY_ADRESS1;
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 deviceaddress = NOR_MEMORY_ADRESS2;
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 deviceaddress = NOR_MEMORY_ADRESS3;
<> 144:ef7eb2e8f9f7 852 }
<> 144:ef7eb2e8f9f7 853 else /* FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 854 {
<> 144:ef7eb2e8f9f7 855 deviceaddress = NOR_MEMORY_ADRESS4;
<> 144:ef7eb2e8f9f7 856 }
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 859 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Send read CFI query command */
<> 144:ef7eb2e8f9f7 862 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* read the NOR CFI information */
<> 144:ef7eb2e8f9f7 865 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
<> 144:ef7eb2e8f9f7 866 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
<> 144:ef7eb2e8f9f7 867 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
<> 144:ef7eb2e8f9f7 868 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
<> 144:ef7eb2e8f9f7 869
<> 144:ef7eb2e8f9f7 870 /* Check the NOR controller state */
<> 144:ef7eb2e8f9f7 871 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Process unlocked */
<> 144:ef7eb2e8f9f7 874 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 return HAL_OK;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /**
<> 144:ef7eb2e8f9f7 880 * @}
<> 144:ef7eb2e8f9f7 881 */
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /** @defgroup NOR_Exported_Functions_Group3 Control functions
<> 144:ef7eb2e8f9f7 884 * @brief management functions
<> 144:ef7eb2e8f9f7 885 *
<> 144:ef7eb2e8f9f7 886 @verbatim
<> 144:ef7eb2e8f9f7 887 ==============================================================================
<> 144:ef7eb2e8f9f7 888 ##### NOR Control functions #####
<> 144:ef7eb2e8f9f7 889 ==============================================================================
<> 144:ef7eb2e8f9f7 890 [..]
<> 144:ef7eb2e8f9f7 891 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 892 the NOR interface.
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 @endverbatim
<> 144:ef7eb2e8f9f7 895 * @{
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /**
<> 144:ef7eb2e8f9f7 899 * @brief Enables dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 900 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 901 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 902 * @retval HAL status
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 905 {
<> 144:ef7eb2e8f9f7 906 /* Process Locked */
<> 144:ef7eb2e8f9f7 907 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 /* Enable write operation */
<> 144:ef7eb2e8f9f7 910 FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 913 hnor->State = HAL_NOR_STATE_READY;
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /* Process unlocked */
<> 144:ef7eb2e8f9f7 916 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 return HAL_OK;
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /**
<> 144:ef7eb2e8f9f7 922 * @brief Disables dynamically NOR write operation.
<> 144:ef7eb2e8f9f7 923 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 924 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 925 * @retval HAL status
<> 144:ef7eb2e8f9f7 926 */
<> 144:ef7eb2e8f9f7 927 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 928 {
<> 144:ef7eb2e8f9f7 929 /* Process Locked */
<> 144:ef7eb2e8f9f7 930 __HAL_LOCK(hnor);
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Update the SRAM controller state */
<> 144:ef7eb2e8f9f7 933 hnor->State = HAL_NOR_STATE_BUSY;
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Disable write operation */
<> 144:ef7eb2e8f9f7 936 FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Update the NOR controller state */
<> 144:ef7eb2e8f9f7 939 hnor->State = HAL_NOR_STATE_PROTECTED;
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /* Process unlocked */
<> 144:ef7eb2e8f9f7 942 __HAL_UNLOCK(hnor);
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 return HAL_OK;
<> 144:ef7eb2e8f9f7 945 }
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @}
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /** @defgroup NOR_Exported_Functions_Group4 State functions
<> 144:ef7eb2e8f9f7 952 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 953 *
<> 144:ef7eb2e8f9f7 954 @verbatim
<> 144:ef7eb2e8f9f7 955 ==============================================================================
<> 144:ef7eb2e8f9f7 956 ##### NOR State functions #####
<> 144:ef7eb2e8f9f7 957 ==============================================================================
<> 144:ef7eb2e8f9f7 958 [..]
<> 144:ef7eb2e8f9f7 959 This subsection permits to get in run-time the status of the NOR controller
<> 144:ef7eb2e8f9f7 960 and the data flow.
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 @endverbatim
<> 144:ef7eb2e8f9f7 963 * @{
<> 144:ef7eb2e8f9f7 964 */
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 /**
<> 144:ef7eb2e8f9f7 967 * @brief return the NOR controller state
<> 144:ef7eb2e8f9f7 968 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 969 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 970 * @retval NOR controller state
<> 144:ef7eb2e8f9f7 971 */
<> 144:ef7eb2e8f9f7 972 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
<> 144:ef7eb2e8f9f7 973 {
<> 144:ef7eb2e8f9f7 974 return hnor->State;
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /**
<> 144:ef7eb2e8f9f7 978 * @brief Returns the NOR operation status.
<> 144:ef7eb2e8f9f7 979 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 980 * the configuration information for NOR module.
<> 144:ef7eb2e8f9f7 981 * @param Address: Device address
<> 144:ef7eb2e8f9f7 982 * @param Timeout: NOR progamming Timeout
<> 144:ef7eb2e8f9f7 983 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
<> 144:ef7eb2e8f9f7 984 * or HAL_NOR_STATUS_TIMEOUT
<> 144:ef7eb2e8f9f7 985 */
<> 144:ef7eb2e8f9f7 986 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 987 {
<> 144:ef7eb2e8f9f7 988 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 989 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
AnnaBridge 165:e614a9f1c9e2 990 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
<> 144:ef7eb2e8f9f7 993 HAL_NOR_MspWait(hnor, Timeout);
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /* Get tick */
<> 144:ef7eb2e8f9f7 996 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 997 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1000 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1001 {
AnnaBridge 165:e614a9f1c9e2 1002 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 status = HAL_NOR_STATUS_TIMEOUT;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006 }
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Read NOR status register (DQ6 and DQ5) */
<> 144:ef7eb2e8f9f7 1009 tmp_sr1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1010 tmp_sr2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 144:ef7eb2e8f9f7 1013 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1014 {
<> 144:ef7eb2e8f9f7 1015 return HAL_NOR_STATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 1016 }
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1019 {
<> 144:ef7eb2e8f9f7 1020 status = HAL_NOR_STATUS_ONGOING;
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 tmp_sr1 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1024 tmp_sr2 = *(__IO uint16_t *)Address;
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* If DQ6 did not toggle between the two reads then return NOR_Success */
<> 144:ef7eb2e8f9f7 1027 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
<> 144:ef7eb2e8f9f7 1028 {
<> 144:ef7eb2e8f9f7 1029 return HAL_NOR_STATUS_SUCCESS;
<> 144:ef7eb2e8f9f7 1030 }
<> 144:ef7eb2e8f9f7 1031 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
<> 144:ef7eb2e8f9f7 1032 {
<> 144:ef7eb2e8f9f7 1033 return HAL_NOR_STATUS_ERROR;
<> 144:ef7eb2e8f9f7 1034 }
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Return the operation status */
<> 144:ef7eb2e8f9f7 1038 return status;
<> 144:ef7eb2e8f9f7 1039 }
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /**
<> 144:ef7eb2e8f9f7 1042 * @}
<> 144:ef7eb2e8f9f7 1043 */
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /**
<> 144:ef7eb2e8f9f7 1046 * @}
<> 144:ef7eb2e8f9f7 1047 */
<> 144:ef7eb2e8f9f7 1048 /**
<> 144:ef7eb2e8f9f7 1049 * @}
<> 144:ef7eb2e8f9f7 1050 */
<> 144:ef7eb2e8f9f7 1051 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
<> 144:ef7eb2e8f9f7 1052 #endif /* HAL_NOR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /**
<> 144:ef7eb2e8f9f7 1055 * @}
<> 144:ef7eb2e8f9f7 1056 */
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/