mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_i2s.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief I2S HAL module driver.
AnnaBridge 165:e614a9f1c9e2 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ===============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 The I2S HAL driver can be used as follow:
AnnaBridge 165:e614a9f1c9e2 17
<> 144:ef7eb2e8f9f7 18 (#) Declare a I2S_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 19 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
AnnaBridge 165:e614a9f1c9e2 20 (##) Enable the SPIx interface clock.
<> 144:ef7eb2e8f9f7 21 (##) I2S pins configuration:
<> 144:ef7eb2e8f9f7 22 (+++) Enable the clock for the I2S GPIOs.
<> 144:ef7eb2e8f9f7 23 (+++) Configure these I2S pins as alternate function.
<> 144:ef7eb2e8f9f7 24 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 25 and HAL_I2S_Receive_IT() APIs).
<> 144:ef7eb2e8f9f7 26 (+++) Configure the I2Sx interrupt priority.
<> 144:ef7eb2e8f9f7 27 (+++) Enable the NVIC I2S IRQ handle.
<> 144:ef7eb2e8f9f7 28 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 29 and HAL_I2S_Receive_DMA() APIs:
<> 144:ef7eb2e8f9f7 30 (+++) Declare a DMA handle structure for the Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 31 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 32 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 33 (+++) Configure the DMA Tx/Rx Channel.
AnnaBridge 165:e614a9f1c9e2 34 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
<> 144:ef7eb2e8f9f7 36 DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
<> 144:ef7eb2e8f9f7 39 using HAL_I2S_Init() function.
<> 144:ef7eb2e8f9f7 40
AnnaBridge 165:e614a9f1c9e2 41 -@- The specific I2S interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 42 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 43 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 44 -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
<> 144:ef7eb2e8f9f7 45 For connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO (2 x PLL3CLK) clock
<> 144:ef7eb2e8f9f7 46 in order to achieve the maximum accuracy.
<> 144:ef7eb2e8f9f7 47 -@- Make sure that either:
<> 144:ef7eb2e8f9f7 48 (+@) External clock source is configured after setting correctly
<> 144:ef7eb2e8f9f7 49 the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
<> 144:ef7eb2e8f9f7 50
AnnaBridge 165:e614a9f1c9e2 51 (#) Three operation modes are available within this driver :
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 54 =================================
AnnaBridge 165:e614a9f1c9e2 55 [..]
AnnaBridge 165:e614a9f1c9e2 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
AnnaBridge 165:e614a9f1c9e2 58
<> 144:ef7eb2e8f9f7 59 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 60 ===================================
AnnaBridge 165:e614a9f1c9e2 61 [..]
AnnaBridge 165:e614a9f1c9e2 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
AnnaBridge 165:e614a9f1c9e2 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
AnnaBridge 165:e614a9f1c9e2 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
AnnaBridge 165:e614a9f1c9e2 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
AnnaBridge 165:e614a9f1c9e2 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
AnnaBridge 165:e614a9f1c9e2 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
AnnaBridge 165:e614a9f1c9e2 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
AnnaBridge 165:e614a9f1c9e2 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
AnnaBridge 165:e614a9f1c9e2 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 76 ==============================
AnnaBridge 165:e614a9f1c9e2 77 [..]
AnnaBridge 165:e614a9f1c9e2 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
AnnaBridge 165:e614a9f1c9e2 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
AnnaBridge 165:e614a9f1c9e2 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
AnnaBridge 165:e614a9f1c9e2 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
AnnaBridge 165:e614a9f1c9e2 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
AnnaBridge 165:e614a9f1c9e2 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
AnnaBridge 165:e614a9f1c9e2 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
AnnaBridge 165:e614a9f1c9e2 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
AnnaBridge 165:e614a9f1c9e2 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
<> 144:ef7eb2e8f9f7 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
<> 144:ef7eb2e8f9f7 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** I2S HAL driver macros list ***
<> 144:ef7eb2e8f9f7 95 =============================================
<> 144:ef7eb2e8f9f7 96 [..]
AnnaBridge 165:e614a9f1c9e2 97 Below the list of most used macros in I2S HAL driver.
AnnaBridge 165:e614a9f1c9e2 98
AnnaBridge 165:e614a9f1c9e2 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 [..]
<> 144:ef7eb2e8f9f7 106 (@) You can refer to the I2S HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 *** I2C Workarounds linked to Silicon Limitation ***
<> 144:ef7eb2e8f9f7 110 ====================================================
<> 144:ef7eb2e8f9f7 111 [..]
<> 144:ef7eb2e8f9f7 112 (@) Only the 16-bit mode with no data extension can be used when the I2S
<> 144:ef7eb2e8f9f7 113 is in Master and used the PCM long synchronization mode.
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 @endverbatim
<> 144:ef7eb2e8f9f7 117 ******************************************************************************
<> 144:ef7eb2e8f9f7 118 * @attention
<> 144:ef7eb2e8f9f7 119 *
AnnaBridge 165:e614a9f1c9e2 120 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 121 *
<> 144:ef7eb2e8f9f7 122 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 123 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 124 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 125 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 126 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 127 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 128 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 129 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 130 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 131 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 134 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 135 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 136 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 137 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 138 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 139 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 140 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 141 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 142 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 143 *
<> 144:ef7eb2e8f9f7 144 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 148 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
AnnaBridge 165:e614a9f1c9e2 153
<> 144:ef7eb2e8f9f7 154 #ifdef HAL_I2S_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 155 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** @defgroup I2S I2S
<> 144:ef7eb2e8f9f7 158 * @brief I2S HAL module driver
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 163 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 164 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 166 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 167 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 168 * @{
<> 144:ef7eb2e8f9f7 169 */
<> 144:ef7eb2e8f9f7 170 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 165:e614a9f1c9e2 171 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 172 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 173 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 174 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 175 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 176 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
AnnaBridge 165:e614a9f1c9e2 177 static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
AnnaBridge 165:e614a9f1c9e2 178 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
AnnaBridge 165:e614a9f1c9e2 179 uint32_t Timeout);
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @}
<> 144:ef7eb2e8f9f7 182 */
AnnaBridge 165:e614a9f1c9e2 183
<> 144:ef7eb2e8f9f7 184 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 185 /** @defgroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 190 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 191 *
AnnaBridge 165:e614a9f1c9e2 192 @verbatim
<> 144:ef7eb2e8f9f7 193 ===============================================================================
<> 144:ef7eb2e8f9f7 194 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 195 ===============================================================================
AnnaBridge 165:e614a9f1c9e2 196 [..] This subsection provides a set of functions allowing to initialize and
AnnaBridge 165:e614a9f1c9e2 197 de-initialize the I2Sx peripheral in simplex mode:
<> 144:ef7eb2e8f9f7 198
AnnaBridge 165:e614a9f1c9e2 199 (+) User must Implement HAL_I2S_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 200 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 201
AnnaBridge 165:e614a9f1c9e2 202 (+) Call the function HAL_I2S_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 203 the selected configuration:
<> 144:ef7eb2e8f9f7 204 (++) Mode
AnnaBridge 165:e614a9f1c9e2 205 (++) Standard
<> 144:ef7eb2e8f9f7 206 (++) Data Format
<> 144:ef7eb2e8f9f7 207 (++) MCLK Output
<> 144:ef7eb2e8f9f7 208 (++) Audio frequency
<> 144:ef7eb2e8f9f7 209 (++) Polarity
<> 144:ef7eb2e8f9f7 210
AnnaBridge 165:e614a9f1c9e2 211 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
AnnaBridge 165:e614a9f1c9e2 212 of the selected I2Sx peripheral.
AnnaBridge 165:e614a9f1c9e2 213 @endverbatim
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
AnnaBridge 165:e614a9f1c9e2 218 * @brief Initializes the I2S according to the specified parameters
<> 144:ef7eb2e8f9f7 219 * in the I2S_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 220 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 221 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 222 * @retval HAL status
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 225 {
AnnaBridge 165:e614a9f1c9e2 226 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U;
AnnaBridge 165:e614a9f1c9e2 227 uint32_t tmp = 0U, i2sclk = 0U;
AnnaBridge 165:e614a9f1c9e2 228
<> 144:ef7eb2e8f9f7 229 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 230 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 233 }
AnnaBridge 165:e614a9f1c9e2 234
<> 144:ef7eb2e8f9f7 235 /* Check the I2S parameters */
<> 144:ef7eb2e8f9f7 236 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 237 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
<> 144:ef7eb2e8f9f7 238 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
<> 144:ef7eb2e8f9f7 239 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
<> 144:ef7eb2e8f9f7 240 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 241 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
AnnaBridge 165:e614a9f1c9e2 242 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
AnnaBridge 165:e614a9f1c9e2 243
<> 144:ef7eb2e8f9f7 244 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 245
AnnaBridge 165:e614a9f1c9e2 246 /* Initialize Default I2S IrqHandler ISR */
AnnaBridge 165:e614a9f1c9e2 247 hi2s->IrqHandlerISR = I2S_IRQHandler;
AnnaBridge 165:e614a9f1c9e2 248
AnnaBridge 165:e614a9f1c9e2 249 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
AnnaBridge 165:e614a9f1c9e2 250 HAL_I2S_MspInit(hi2s);
AnnaBridge 165:e614a9f1c9e2 251
AnnaBridge 165:e614a9f1c9e2 252 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
AnnaBridge 165:e614a9f1c9e2 253 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
AnnaBridge 165:e614a9f1c9e2 254 CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
AnnaBridge 165:e614a9f1c9e2 255 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
AnnaBridge 165:e614a9f1c9e2 256 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
AnnaBridge 165:e614a9f1c9e2 257 hi2s->Instance->I2SPR = 0x0002U;
AnnaBridge 165:e614a9f1c9e2 258
AnnaBridge 165:e614a9f1c9e2 259 /* Get the I2SCFGR register value */
AnnaBridge 165:e614a9f1c9e2 260 tmpreg = hi2s->Instance->I2SCFGR;
AnnaBridge 165:e614a9f1c9e2 261
AnnaBridge 165:e614a9f1c9e2 262 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
<> 144:ef7eb2e8f9f7 263 /* If the requested audio frequency is not the default, compute the prescaler */
AnnaBridge 165:e614a9f1c9e2 264 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 /* Check the frame length (For the Prescaler computing) *******************/
AnnaBridge 165:e614a9f1c9e2 267 /* Set I2S Packet Length value*/
AnnaBridge 165:e614a9f1c9e2 268 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
<> 144:ef7eb2e8f9f7 269 {
AnnaBridge 165:e614a9f1c9e2 270 /* Packet length is 32 bits */
AnnaBridge 165:e614a9f1c9e2 271 packetlength = 32U;
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273 else
<> 144:ef7eb2e8f9f7 274 {
AnnaBridge 165:e614a9f1c9e2 275 /* Packet length is 16 bits */
AnnaBridge 165:e614a9f1c9e2 276 packetlength = 16U;
<> 144:ef7eb2e8f9f7 277 }
AnnaBridge 165:e614a9f1c9e2 278
AnnaBridge 165:e614a9f1c9e2 279 /* I2S standard */
AnnaBridge 165:e614a9f1c9e2 280 if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
AnnaBridge 165:e614a9f1c9e2 281 {
AnnaBridge 165:e614a9f1c9e2 282 /* In I2S standard packet lenght is multiplied by 2 */
AnnaBridge 165:e614a9f1c9e2 283 packetlength = packetlength * 2U;
AnnaBridge 165:e614a9f1c9e2 284 }
AnnaBridge 165:e614a9f1c9e2 285
<> 144:ef7eb2e8f9f7 286 if(hi2s->Instance == SPI2)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 /* Get the source clock value: based on SPI2 Instance */
<> 144:ef7eb2e8f9f7 289 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S2);
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 else if(hi2s->Instance == SPI3)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* Get the source clock value: based on SPI3 Instance */
<> 144:ef7eb2e8f9f7 294 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S3);
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296 else
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Get the source clock value: based on System Clock value */
AnnaBridge 165:e614a9f1c9e2 299 i2sclk = HAL_RCC_GetSysClockFreq();
<> 144:ef7eb2e8f9f7 300 }
AnnaBridge 165:e614a9f1c9e2 301
<> 144:ef7eb2e8f9f7 302 /* Compute the Real divider depending on the MCLK output state, with a floating point */
<> 144:ef7eb2e8f9f7 303 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* MCLK output is enabled */
AnnaBridge 165:e614a9f1c9e2 306 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
AnnaBridge 165:e614a9f1c9e2 307 {
AnnaBridge 165:e614a9f1c9e2 308 tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
AnnaBridge 165:e614a9f1c9e2 309 }
AnnaBridge 165:e614a9f1c9e2 310 else
AnnaBridge 165:e614a9f1c9e2 311 {
AnnaBridge 165:e614a9f1c9e2 312 tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
AnnaBridge 165:e614a9f1c9e2 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 else
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 /* MCLK output is disabled */
AnnaBridge 165:e614a9f1c9e2 318 tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Remove the flatting point */
AnnaBridge 165:e614a9f1c9e2 322 tmp = tmp / 10U;
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Check the parity of the divider */
AnnaBridge 165:e614a9f1c9e2 325 i2sodd = (uint16_t)(tmp & (uint16_t)1U);
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Compute the i2sdiv prescaler */
AnnaBridge 165:e614a9f1c9e2 328 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
AnnaBridge 165:e614a9f1c9e2 331 i2sodd = (uint32_t) (i2sodd << 8U);
<> 144:ef7eb2e8f9f7 332 }
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Test if the divider is 1 or 0 or greater than 0xFF */
AnnaBridge 165:e614a9f1c9e2 335 if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 /* Set the default values */
AnnaBridge 165:e614a9f1c9e2 338 i2sdiv = 2U;
AnnaBridge 165:e614a9f1c9e2 339 i2sodd = 0U;
<> 144:ef7eb2e8f9f7 340
AnnaBridge 165:e614a9f1c9e2 341 /* Set the error code and execute error callback*/
AnnaBridge 165:e614a9f1c9e2 342 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
AnnaBridge 165:e614a9f1c9e2 343 HAL_I2S_ErrorCallback(hi2s);
AnnaBridge 165:e614a9f1c9e2 344 return HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 345 }
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* Write to SPIx I2SPR register the computed value */
<> 144:ef7eb2e8f9f7 348 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 349
AnnaBridge 165:e614a9f1c9e2 350 /* Configure the I2S with the I2S_InitStruct values */
AnnaBridge 165:e614a9f1c9e2 351 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
AnnaBridge 165:e614a9f1c9e2 352 (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
AnnaBridge 165:e614a9f1c9e2 353 (uint16_t)hi2s->Init.CPOL))));
AnnaBridge 165:e614a9f1c9e2 354 /* Write to SPIx I2SCFGR */
AnnaBridge 165:e614a9f1c9e2 355 WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg);
<> 144:ef7eb2e8f9f7 356 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 357 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 return HAL_OK;
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
AnnaBridge 165:e614a9f1c9e2 363 * @brief DeInitializes the I2S peripheral
<> 144:ef7eb2e8f9f7 364 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 365 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 366 * @retval HAL status
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 371 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 374 }
AnnaBridge 165:e614a9f1c9e2 375
<> 144:ef7eb2e8f9f7 376 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 379 HAL_I2S_MspDeInit(hi2s);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 382 hi2s->State = HAL_I2S_STATE_RESET;
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Release Lock */
<> 144:ef7eb2e8f9f7 385 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 return HAL_OK;
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief I2S MSP Init
<> 144:ef7eb2e8f9f7 392 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 393 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 394 * @retval None
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 399 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 400 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 401 the HAL_I2S_MspInit could be implemented in the user file
AnnaBridge 165:e614a9f1c9e2 402 */
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @brief I2S MSP DeInit
<> 144:ef7eb2e8f9f7 407 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 408 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 409 * @retval None
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 414 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 415 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 416 the HAL_I2S_MspDeInit could be implemented in the user file
AnnaBridge 165:e614a9f1c9e2 417 */
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @}
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 424 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 425 *
AnnaBridge 165:e614a9f1c9e2 426 @verbatim
<> 144:ef7eb2e8f9f7 427 ===============================================================================
<> 144:ef7eb2e8f9f7 428 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 429 ===============================================================================
<> 144:ef7eb2e8f9f7 430 [..]
AnnaBridge 165:e614a9f1c9e2 431 This subsection provides a set of functions allowing to manage the I2S data
<> 144:ef7eb2e8f9f7 432 transfers.
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 (#) There are two modes of transfer:
AnnaBridge 165:e614a9f1c9e2 435 (++) Blocking mode : The communication is performed in the polling mode.
AnnaBridge 165:e614a9f1c9e2 436 The status of all data processing is returned by the same function
AnnaBridge 165:e614a9f1c9e2 437 after finishing transfer.
AnnaBridge 165:e614a9f1c9e2 438 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 439 or DMA. These functions return the status of the transfer startup.
AnnaBridge 165:e614a9f1c9e2 440 The end of the data processing will be indicated through the
AnnaBridge 165:e614a9f1c9e2 441 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 442 using DMA mode.
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 445 (++) HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 446 (++) HAL_I2S_Receive()
AnnaBridge 165:e614a9f1c9e2 447
<> 144:ef7eb2e8f9f7 448 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 449 (++) HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 450 (++) HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 453 (++) HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 454 (++) HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 457 (++) HAL_I2S_TxCpltCallback()
<> 144:ef7eb2e8f9f7 458 (++) HAL_I2S_RxCpltCallback()
<> 144:ef7eb2e8f9f7 459 (++) HAL_I2S_ErrorCallback()
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 @endverbatim
<> 144:ef7eb2e8f9f7 462 * @{
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 467 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 468 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 469 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 470 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 471 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
AnnaBridge 165:e614a9f1c9e2 472 * configuration phase, the Size parameter means the number of 16-bit data length
AnnaBridge 165:e614a9f1c9e2 473 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
AnnaBridge 165:e614a9f1c9e2 474 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 475 * @param Timeout: Timeout duration
AnnaBridge 165:e614a9f1c9e2 476 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 477 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 478 * @retval HAL status
<> 144:ef7eb2e8f9f7 479 */
<> 144:ef7eb2e8f9f7 480 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 481 {
AnnaBridge 165:e614a9f1c9e2 482 uint32_t tmp1 = 0U;
AnnaBridge 165:e614a9f1c9e2 483
AnnaBridge 165:e614a9f1c9e2 484 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 485 {
AnnaBridge 165:e614a9f1c9e2 486 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 if(hi2s->State == HAL_I2S_STATE_READY)
AnnaBridge 165:e614a9f1c9e2 490 {
AnnaBridge 165:e614a9f1c9e2 491 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
AnnaBridge 165:e614a9f1c9e2 492
AnnaBridge 165:e614a9f1c9e2 493 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 494 {
AnnaBridge 165:e614a9f1c9e2 495 hi2s->TxXferSize = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 496 hi2s->TxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498 else
<> 144:ef7eb2e8f9f7 499 {
AnnaBridge 165:e614a9f1c9e2 500 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 501 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 502 }
AnnaBridge 165:e614a9f1c9e2 503
AnnaBridge 165:e614a9f1c9e2 504 /* Process Locked */
AnnaBridge 165:e614a9f1c9e2 505 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 506
<> 144:ef7eb2e8f9f7 507 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 508 hi2s->State = HAL_I2S_STATE_BUSY_TX;
AnnaBridge 165:e614a9f1c9e2 509
AnnaBridge 165:e614a9f1c9e2 510 /* Check if the I2S is already enabled */
AnnaBridge 165:e614a9f1c9e2 511 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 514 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 515 }
AnnaBridge 165:e614a9f1c9e2 516
AnnaBridge 165:e614a9f1c9e2 517 while(hi2s->TxXferCount > 0U)
<> 144:ef7eb2e8f9f7 518 {
AnnaBridge 165:e614a9f1c9e2 519 hi2s->Instance->DR = (*pData++);
AnnaBridge 165:e614a9f1c9e2 520 hi2s->TxXferCount--;
AnnaBridge 165:e614a9f1c9e2 521
<> 144:ef7eb2e8f9f7 522 /* Wait until TXE flag is set */
AnnaBridge 165:e614a9f1c9e2 523 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 524 {
AnnaBridge 165:e614a9f1c9e2 525 /* Set the error code and execute error callback*/
AnnaBridge 165:e614a9f1c9e2 526 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
AnnaBridge 165:e614a9f1c9e2 527 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 528 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Check if an underrun occurs */
AnnaBridge 165:e614a9f1c9e2 532 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
<> 144:ef7eb2e8f9f7 533 {
AnnaBridge 165:e614a9f1c9e2 534 /* Clear underrun flag */
AnnaBridge 165:e614a9f1c9e2 535 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 536 /* Set the I2S State ready */
AnnaBridge 165:e614a9f1c9e2 537 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 540 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Set the error code and execute error callback*/
AnnaBridge 165:e614a9f1c9e2 543 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
AnnaBridge 165:e614a9f1c9e2 544 HAL_I2S_ErrorCallback(hi2s);
AnnaBridge 165:e614a9f1c9e2 545
<> 144:ef7eb2e8f9f7 546 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 547 }
AnnaBridge 165:e614a9f1c9e2 548 }
AnnaBridge 165:e614a9f1c9e2 549 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 552 __HAL_UNLOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 553
<> 144:ef7eb2e8f9f7 554 return HAL_OK;
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556 else
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /**
AnnaBridge 165:e614a9f1c9e2 563 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 564 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 565 * the configuration information for I2S module
AnnaBridge 165:e614a9f1c9e2 566 * @param pData: a 16-bit pointer to data buffer
<> 144:ef7eb2e8f9f7 567 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 568 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
AnnaBridge 165:e614a9f1c9e2 569 * configuration phase, the Size parameter means the number of 16-bit data length
AnnaBridge 165:e614a9f1c9e2 570 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
AnnaBridge 165:e614a9f1c9e2 571 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 572 * @param Timeout: Timeout duration
AnnaBridge 165:e614a9f1c9e2 573 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
AnnaBridge 165:e614a9f1c9e2 574 * between Master and Slave(example: audio streaming)
<> 144:ef7eb2e8f9f7 575 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
AnnaBridge 165:e614a9f1c9e2 576 * in continuous way and as the I2S is not disabled at the end of the I2S transaction
<> 144:ef7eb2e8f9f7 577 * @retval HAL status
<> 144:ef7eb2e8f9f7 578 */
<> 144:ef7eb2e8f9f7 579 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 580 {
AnnaBridge 165:e614a9f1c9e2 581 uint32_t tmp1 = 0U;
AnnaBridge 165:e614a9f1c9e2 582
AnnaBridge 165:e614a9f1c9e2 583 if((pData == NULL ) || (Size == 0U))
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 586 }
AnnaBridge 165:e614a9f1c9e2 587
<> 144:ef7eb2e8f9f7 588 if(hi2s->State == HAL_I2S_STATE_READY)
AnnaBridge 165:e614a9f1c9e2 589 {
AnnaBridge 165:e614a9f1c9e2 590 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
AnnaBridge 165:e614a9f1c9e2 591 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 592 {
AnnaBridge 165:e614a9f1c9e2 593 hi2s->RxXferSize = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 594 hi2s->RxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 else
<> 144:ef7eb2e8f9f7 597 {
AnnaBridge 165:e614a9f1c9e2 598 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 599 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 600 }
AnnaBridge 165:e614a9f1c9e2 601 /* Process Locked */
AnnaBridge 165:e614a9f1c9e2 602 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 603
<> 144:ef7eb2e8f9f7 604 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 605 hi2s->State = HAL_I2S_STATE_BUSY_RX;
AnnaBridge 165:e614a9f1c9e2 606
AnnaBridge 165:e614a9f1c9e2 607 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 608 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 611 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 612 }
AnnaBridge 165:e614a9f1c9e2 613
AnnaBridge 165:e614a9f1c9e2 614 /* Check if Master Receiver mode is selected */
AnnaBridge 165:e614a9f1c9e2 615 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 616 {
AnnaBridge 165:e614a9f1c9e2 617 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
AnnaBridge 165:e614a9f1c9e2 618 access to the SPI_SR register. */
AnnaBridge 165:e614a9f1c9e2 619 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
AnnaBridge 165:e614a9f1c9e2 620 }
AnnaBridge 165:e614a9f1c9e2 621
AnnaBridge 165:e614a9f1c9e2 622 /* Receive data */
AnnaBridge 165:e614a9f1c9e2 623 while(hi2s->RxXferCount > 0U)
AnnaBridge 165:e614a9f1c9e2 624 {
AnnaBridge 165:e614a9f1c9e2 625 /* Wait until RXNE flag is set */
AnnaBridge 165:e614a9f1c9e2 626 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 627 {
AnnaBridge 165:e614a9f1c9e2 628 /* Set the error code and execute error callback*/
AnnaBridge 165:e614a9f1c9e2 629 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
AnnaBridge 165:e614a9f1c9e2 630 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 631 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Check if an overrun occurs */
AnnaBridge 165:e614a9f1c9e2 635 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
<> 144:ef7eb2e8f9f7 636 {
AnnaBridge 165:e614a9f1c9e2 637 /* Clear overrun flag */
AnnaBridge 165:e614a9f1c9e2 638 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
AnnaBridge 165:e614a9f1c9e2 639
<> 144:ef7eb2e8f9f7 640 /* Set the I2S State ready */
AnnaBridge 165:e614a9f1c9e2 641 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 644 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Set the error code and execute error callback*/
AnnaBridge 165:e614a9f1c9e2 647 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
AnnaBridge 165:e614a9f1c9e2 648 HAL_I2S_ErrorCallback(hi2s);
AnnaBridge 165:e614a9f1c9e2 649
<> 144:ef7eb2e8f9f7 650 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 651 }
AnnaBridge 165:e614a9f1c9e2 652
AnnaBridge 165:e614a9f1c9e2 653 (*pData++) = hi2s->Instance->DR;
AnnaBridge 165:e614a9f1c9e2 654 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 655 }
AnnaBridge 165:e614a9f1c9e2 656
AnnaBridge 165:e614a9f1c9e2 657 hi2s->State = HAL_I2S_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 658
<> 144:ef7eb2e8f9f7 659 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 660 __HAL_UNLOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 661
<> 144:ef7eb2e8f9f7 662 return HAL_OK;
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 else
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668 }
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /**
<> 144:ef7eb2e8f9f7 671 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 672 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 673 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 674 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 675 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 676 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
AnnaBridge 165:e614a9f1c9e2 677 * configuration phase, the Size parameter means the number of 16-bit data length
AnnaBridge 165:e614a9f1c9e2 678 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
AnnaBridge 165:e614a9f1c9e2 679 * the Size parameter means the number of 16-bit data length.
AnnaBridge 165:e614a9f1c9e2 680 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 681 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 682 * @retval HAL status
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 685 {
AnnaBridge 165:e614a9f1c9e2 686 uint32_t tmp1 = 0U;
AnnaBridge 165:e614a9f1c9e2 687
<> 144:ef7eb2e8f9f7 688 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 689 {
AnnaBridge 165:e614a9f1c9e2 690 if((pData == NULL) || (Size == 0U))
AnnaBridge 165:e614a9f1c9e2 691 {
AnnaBridge 165:e614a9f1c9e2 692 return HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 693 }
<> 144:ef7eb2e8f9f7 694
AnnaBridge 165:e614a9f1c9e2 695 hi2s->pTxBuffPtr = pData;
AnnaBridge 165:e614a9f1c9e2 696 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
AnnaBridge 165:e614a9f1c9e2 697 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 698 {
AnnaBridge 165:e614a9f1c9e2 699 hi2s->TxXferSize = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 700 hi2s->TxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702 else
<> 144:ef7eb2e8f9f7 703 {
AnnaBridge 165:e614a9f1c9e2 704 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 705 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
AnnaBridge 165:e614a9f1c9e2 708 /* Process Locked */
AnnaBridge 165:e614a9f1c9e2 709 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 710
AnnaBridge 165:e614a9f1c9e2 711 hi2s->State = HAL_I2S_STATE_BUSY_TX;
AnnaBridge 165:e614a9f1c9e2 712 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 713
<> 144:ef7eb2e8f9f7 714 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 715 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 716
AnnaBridge 165:e614a9f1c9e2 717 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 718 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 721 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 725 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 return HAL_OK;
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 else
<> 144:ef7eb2e8f9f7 730 {
AnnaBridge 165:e614a9f1c9e2 731 return HAL_BUSY;
AnnaBridge 165:e614a9f1c9e2 732 }
AnnaBridge 165:e614a9f1c9e2 733 }
AnnaBridge 165:e614a9f1c9e2 734
AnnaBridge 165:e614a9f1c9e2 735 /**
AnnaBridge 165:e614a9f1c9e2 736 * @brief Receive an amount of data in non-blocking mode with Interrupt
AnnaBridge 165:e614a9f1c9e2 737 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 738 * the configuration information for I2S module
AnnaBridge 165:e614a9f1c9e2 739 * @param pData: a 16-bit pointer to the Receive data buffer.
AnnaBridge 165:e614a9f1c9e2 740 * @param Size: number of data sample to be sent:
AnnaBridge 165:e614a9f1c9e2 741 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
AnnaBridge 165:e614a9f1c9e2 742 * configuration phase, the Size parameter means the number of 16-bit data length
AnnaBridge 165:e614a9f1c9e2 743 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
AnnaBridge 165:e614a9f1c9e2 744 * the Size parameter means the number of 16-bit data length.
AnnaBridge 165:e614a9f1c9e2 745 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
AnnaBridge 165:e614a9f1c9e2 746 * between Master and Slave(example: audio streaming).
AnnaBridge 165:e614a9f1c9e2 747 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
AnnaBridge 165:e614a9f1c9e2 748 * between Master and Slave otherwise the I2S interrupt should be optimized.
AnnaBridge 165:e614a9f1c9e2 749 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 750 */
AnnaBridge 165:e614a9f1c9e2 751 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
AnnaBridge 165:e614a9f1c9e2 752 {
AnnaBridge 165:e614a9f1c9e2 753 uint32_t tmp1 = 0U;
AnnaBridge 165:e614a9f1c9e2 754
AnnaBridge 165:e614a9f1c9e2 755 if(hi2s->State == HAL_I2S_STATE_READY)
AnnaBridge 165:e614a9f1c9e2 756 {
AnnaBridge 165:e614a9f1c9e2 757 if((pData == NULL) || (Size == 0U))
AnnaBridge 165:e614a9f1c9e2 758 {
AnnaBridge 165:e614a9f1c9e2 759 return HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 760 }
AnnaBridge 165:e614a9f1c9e2 761
AnnaBridge 165:e614a9f1c9e2 762 hi2s->pRxBuffPtr = pData;
AnnaBridge 165:e614a9f1c9e2 763 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
AnnaBridge 165:e614a9f1c9e2 764 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
AnnaBridge 165:e614a9f1c9e2 765 {
AnnaBridge 165:e614a9f1c9e2 766 hi2s->RxXferSize = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 767 hi2s->RxXferCount = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 768 }
AnnaBridge 165:e614a9f1c9e2 769 else
AnnaBridge 165:e614a9f1c9e2 770 {
AnnaBridge 165:e614a9f1c9e2 771 hi2s->RxXferSize = Size;
AnnaBridge 165:e614a9f1c9e2 772 hi2s->RxXferCount = Size;
AnnaBridge 165:e614a9f1c9e2 773 }
AnnaBridge 165:e614a9f1c9e2 774 /* Process Locked */
AnnaBridge 165:e614a9f1c9e2 775 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 776
AnnaBridge 165:e614a9f1c9e2 777 hi2s->State = HAL_I2S_STATE_BUSY_RX;
AnnaBridge 165:e614a9f1c9e2 778 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 779
AnnaBridge 165:e614a9f1c9e2 780 /* Enable TXE and ERR interrupt */
AnnaBridge 165:e614a9f1c9e2 781 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
AnnaBridge 165:e614a9f1c9e2 782
AnnaBridge 165:e614a9f1c9e2 783 /* Check if the I2S is already enabled */
AnnaBridge 165:e614a9f1c9e2 784 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
AnnaBridge 165:e614a9f1c9e2 785 {
AnnaBridge 165:e614a9f1c9e2 786 /* Enable I2S peripheral */
AnnaBridge 165:e614a9f1c9e2 787 __HAL_I2S_ENABLE(hi2s);
AnnaBridge 165:e614a9f1c9e2 788 }
AnnaBridge 165:e614a9f1c9e2 789
<> 144:ef7eb2e8f9f7 790 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 791 __HAL_UNLOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 792
AnnaBridge 165:e614a9f1c9e2 793 return HAL_OK;
AnnaBridge 165:e614a9f1c9e2 794 }
AnnaBridge 165:e614a9f1c9e2 795
AnnaBridge 165:e614a9f1c9e2 796 else
AnnaBridge 165:e614a9f1c9e2 797 {
AnnaBridge 165:e614a9f1c9e2 798 return HAL_BUSY;
AnnaBridge 165:e614a9f1c9e2 799 }
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /**
<> 144:ef7eb2e8f9f7 803 * @brief Transmit an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 804 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 805 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 806 * @param pData: a 16-bit pointer to the Transmit data buffer.
<> 144:ef7eb2e8f9f7 807 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 808 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
AnnaBridge 165:e614a9f1c9e2 809 * configuration phase, the Size parameter means the number of 16-bit data length
AnnaBridge 165:e614a9f1c9e2 810 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
AnnaBridge 165:e614a9f1c9e2 811 * the Size parameter means the number of 16-bit data length.
AnnaBridge 165:e614a9f1c9e2 812 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 813 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 814 * @retval HAL status
<> 144:ef7eb2e8f9f7 815 */
<> 144:ef7eb2e8f9f7 816 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 817 {
AnnaBridge 165:e614a9f1c9e2 818 uint32_t *tmp = NULL;
AnnaBridge 165:e614a9f1c9e2 819 uint32_t tmp1 = 0U;
AnnaBridge 165:e614a9f1c9e2 820
AnnaBridge 165:e614a9f1c9e2 821 if((pData == NULL) || (Size == 0U))
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 if(hi2s->State == HAL_I2S_STATE_READY)
AnnaBridge 165:e614a9f1c9e2 827 {
<> 144:ef7eb2e8f9f7 828 hi2s->pTxBuffPtr = pData;
AnnaBridge 165:e614a9f1c9e2 829 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
AnnaBridge 165:e614a9f1c9e2 830 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 831 {
AnnaBridge 165:e614a9f1c9e2 832 hi2s->TxXferSize = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 833 hi2s->TxXferCount = (Size << 1U);
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 else
<> 144:ef7eb2e8f9f7 836 {
AnnaBridge 165:e614a9f1c9e2 837 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 838 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840
AnnaBridge 165:e614a9f1c9e2 841 /* Process Locked */
AnnaBridge 165:e614a9f1c9e2 842 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 843
AnnaBridge 165:e614a9f1c9e2 844 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 845 hi2s->State = HAL_I2S_STATE_BUSY_TX;
AnnaBridge 165:e614a9f1c9e2 846
AnnaBridge 165:e614a9f1c9e2 847 /* Set the I2S Tx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 848 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 849
AnnaBridge 165:e614a9f1c9e2 850 /* Set the I2S Tx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 851 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 854 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 855
AnnaBridge 165:e614a9f1c9e2 856 /* Enable the Tx DMA Stream */
AnnaBridge 165:e614a9f1c9e2 857 tmp = (uint32_t*)&pData;
AnnaBridge 165:e614a9f1c9e2 858 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
<> 144:ef7eb2e8f9f7 859
AnnaBridge 165:e614a9f1c9e2 860 /* Check if the I2S is already enabled */
AnnaBridge 165:e614a9f1c9e2 861 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 864 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 865 }
<> 144:ef7eb2e8f9f7 866
AnnaBridge 165:e614a9f1c9e2 867 /* Check if the I2S Tx request is already enabled */
AnnaBridge 165:e614a9f1c9e2 868 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
<> 144:ef7eb2e8f9f7 869 {
AnnaBridge 165:e614a9f1c9e2 870 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 871 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 875 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 return HAL_OK;
<> 144:ef7eb2e8f9f7 878 }
<> 144:ef7eb2e8f9f7 879 else
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 882 }
<> 144:ef7eb2e8f9f7 883 }
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /**
AnnaBridge 165:e614a9f1c9e2 886 * @brief Receive an amount of data in non-blocking mode with DMA
AnnaBridge 165:e614a9f1c9e2 887 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 888 * the configuration information for I2S module
AnnaBridge 165:e614a9f1c9e2 889 * @param pData: a 16-bit pointer to the Receive data buffer.
AnnaBridge 165:e614a9f1c9e2 890 * @param Size: number of data sample to be sent:
AnnaBridge 165:e614a9f1c9e2 891 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
AnnaBridge 165:e614a9f1c9e2 892 * configuration phase, the Size parameter means the number of 16-bit data length
AnnaBridge 165:e614a9f1c9e2 893 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
AnnaBridge 165:e614a9f1c9e2 894 * the Size parameter means the number of 16-bit data length.
AnnaBridge 165:e614a9f1c9e2 895 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
AnnaBridge 165:e614a9f1c9e2 896 * between Master and Slave(example: audio streaming).
AnnaBridge 165:e614a9f1c9e2 897 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 898 */
AnnaBridge 165:e614a9f1c9e2 899 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
AnnaBridge 165:e614a9f1c9e2 900 {
AnnaBridge 165:e614a9f1c9e2 901 uint32_t *tmp = NULL;
AnnaBridge 165:e614a9f1c9e2 902 uint32_t tmp1 = 0U;
AnnaBridge 165:e614a9f1c9e2 903
AnnaBridge 165:e614a9f1c9e2 904 if((pData == NULL) || (Size == 0U))
AnnaBridge 165:e614a9f1c9e2 905 {
AnnaBridge 165:e614a9f1c9e2 906 return HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 907 }
AnnaBridge 165:e614a9f1c9e2 908
AnnaBridge 165:e614a9f1c9e2 909 if(hi2s->State == HAL_I2S_STATE_READY)
AnnaBridge 165:e614a9f1c9e2 910 {
AnnaBridge 165:e614a9f1c9e2 911 hi2s->pRxBuffPtr = pData;
AnnaBridge 165:e614a9f1c9e2 912 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
AnnaBridge 165:e614a9f1c9e2 913 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
AnnaBridge 165:e614a9f1c9e2 914 {
AnnaBridge 165:e614a9f1c9e2 915 hi2s->RxXferSize = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 916 hi2s->RxXferCount = (Size << 1U);
AnnaBridge 165:e614a9f1c9e2 917 }
AnnaBridge 165:e614a9f1c9e2 918 else
AnnaBridge 165:e614a9f1c9e2 919 {
AnnaBridge 165:e614a9f1c9e2 920 hi2s->RxXferSize = Size;
AnnaBridge 165:e614a9f1c9e2 921 hi2s->RxXferCount = Size;
AnnaBridge 165:e614a9f1c9e2 922 }
AnnaBridge 165:e614a9f1c9e2 923 /* Process Locked */
AnnaBridge 165:e614a9f1c9e2 924 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 925
AnnaBridge 165:e614a9f1c9e2 926 hi2s->State = HAL_I2S_STATE_BUSY_RX;
AnnaBridge 165:e614a9f1c9e2 927 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 928
AnnaBridge 165:e614a9f1c9e2 929 /* Set the I2S Rx DMA Half transfer complete callback */
AnnaBridge 165:e614a9f1c9e2 930 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
AnnaBridge 165:e614a9f1c9e2 931
AnnaBridge 165:e614a9f1c9e2 932 /* Set the I2S Rx DMA transfer complete callback */
AnnaBridge 165:e614a9f1c9e2 933 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
AnnaBridge 165:e614a9f1c9e2 934
AnnaBridge 165:e614a9f1c9e2 935 /* Set the DMA error callback */
AnnaBridge 165:e614a9f1c9e2 936 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
AnnaBridge 165:e614a9f1c9e2 937
AnnaBridge 165:e614a9f1c9e2 938 /* Check if Master Receiver mode is selected */
AnnaBridge 165:e614a9f1c9e2 939 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
AnnaBridge 165:e614a9f1c9e2 940 {
AnnaBridge 165:e614a9f1c9e2 941 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
AnnaBridge 165:e614a9f1c9e2 942 access to the SPI_SR register. */
AnnaBridge 165:e614a9f1c9e2 943 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
AnnaBridge 165:e614a9f1c9e2 944 }
AnnaBridge 165:e614a9f1c9e2 945
AnnaBridge 165:e614a9f1c9e2 946 /* Enable the Rx DMA Stream */
AnnaBridge 165:e614a9f1c9e2 947 tmp = (uint32_t*)&pData;
AnnaBridge 165:e614a9f1c9e2 948 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
AnnaBridge 165:e614a9f1c9e2 949
AnnaBridge 165:e614a9f1c9e2 950 /* Check if the I2S is already enabled */
AnnaBridge 165:e614a9f1c9e2 951 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
AnnaBridge 165:e614a9f1c9e2 952 {
AnnaBridge 165:e614a9f1c9e2 953 /* Enable I2S peripheral */
AnnaBridge 165:e614a9f1c9e2 954 __HAL_I2S_ENABLE(hi2s);
AnnaBridge 165:e614a9f1c9e2 955 }
AnnaBridge 165:e614a9f1c9e2 956
AnnaBridge 165:e614a9f1c9e2 957 /* Check if the I2S Rx request is already enabled */
AnnaBridge 165:e614a9f1c9e2 958 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
AnnaBridge 165:e614a9f1c9e2 959 {
AnnaBridge 165:e614a9f1c9e2 960 /* Enable Rx DMA Request */
AnnaBridge 165:e614a9f1c9e2 961 SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
AnnaBridge 165:e614a9f1c9e2 962 }
AnnaBridge 165:e614a9f1c9e2 963
AnnaBridge 165:e614a9f1c9e2 964 /* Process Unlocked */
AnnaBridge 165:e614a9f1c9e2 965 __HAL_UNLOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 966
AnnaBridge 165:e614a9f1c9e2 967 return HAL_OK;
AnnaBridge 165:e614a9f1c9e2 968 }
AnnaBridge 165:e614a9f1c9e2 969 else
AnnaBridge 165:e614a9f1c9e2 970 {
AnnaBridge 165:e614a9f1c9e2 971 return HAL_BUSY;
AnnaBridge 165:e614a9f1c9e2 972 }
AnnaBridge 165:e614a9f1c9e2 973 }
AnnaBridge 165:e614a9f1c9e2 974
AnnaBridge 165:e614a9f1c9e2 975 /**
AnnaBridge 165:e614a9f1c9e2 976 * @brief Pauses the audio channel playing from the Media.
<> 144:ef7eb2e8f9f7 977 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 978 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 979 * @retval HAL status
<> 144:ef7eb2e8f9f7 980 */
<> 144:ef7eb2e8f9f7 981 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 982 {
<> 144:ef7eb2e8f9f7 983 /* Process Locked */
<> 144:ef7eb2e8f9f7 984 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 985
<> 144:ef7eb2e8f9f7 986 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 987 {
<> 144:ef7eb2e8f9f7 988 /* Disable the I2S DMA Tx request */
AnnaBridge 165:e614a9f1c9e2 989 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* Disable the I2S DMA Rx request */
AnnaBridge 165:e614a9f1c9e2 994 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 995 }
AnnaBridge 165:e614a9f1c9e2 996
<> 144:ef7eb2e8f9f7 997 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 998 __HAL_UNLOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 999
AnnaBridge 165:e614a9f1c9e2 1000 return HAL_OK;
<> 144:ef7eb2e8f9f7 1001 }
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /**
AnnaBridge 165:e614a9f1c9e2 1004 * @brief Resumes the audio channel playing from the Media.
<> 144:ef7eb2e8f9f7 1005 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1006 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1007 * @retval HAL status
<> 144:ef7eb2e8f9f7 1008 */
<> 144:ef7eb2e8f9f7 1009 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1010 {
<> 144:ef7eb2e8f9f7 1011 /* Process Locked */
<> 144:ef7eb2e8f9f7 1012 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 1013
<> 144:ef7eb2e8f9f7 1014 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 /* Enable the I2S DMA Tx request */
AnnaBridge 165:e614a9f1c9e2 1017 SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1020 {
<> 144:ef7eb2e8f9f7 1021 /* Enable the I2S DMA Rx request */
AnnaBridge 165:e614a9f1c9e2 1022 SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /* If the I2S peripheral is still not enabled, enable it */
AnnaBridge 165:e614a9f1c9e2 1026 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
<> 144:ef7eb2e8f9f7 1027 {
AnnaBridge 165:e614a9f1c9e2 1028 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 1029 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 1030 }
AnnaBridge 165:e614a9f1c9e2 1031
<> 144:ef7eb2e8f9f7 1032 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1033 __HAL_UNLOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 1034
<> 144:ef7eb2e8f9f7 1035 return HAL_OK;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /**
AnnaBridge 165:e614a9f1c9e2 1039 * @brief Resumes the audio channel playing from the Media.
<> 144:ef7eb2e8f9f7 1040 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1041 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1042 * @retval HAL status
<> 144:ef7eb2e8f9f7 1043 */
<> 144:ef7eb2e8f9f7 1044 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1045 {
<> 144:ef7eb2e8f9f7 1046 /* Process Locked */
<> 144:ef7eb2e8f9f7 1047 __HAL_LOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 1048
AnnaBridge 165:e614a9f1c9e2 1049 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1050 {
AnnaBridge 165:e614a9f1c9e2 1051 /* Disable the I2S DMA requests */
AnnaBridge 165:e614a9f1c9e2 1052 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
AnnaBridge 165:e614a9f1c9e2 1053
AnnaBridge 165:e614a9f1c9e2 1054 /* Disable the I2S DMA Channel */
<> 144:ef7eb2e8f9f7 1055 HAL_DMA_Abort(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1056 }
AnnaBridge 165:e614a9f1c9e2 1057 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1058 {
AnnaBridge 165:e614a9f1c9e2 1059 /* Disable the I2S DMA requests */
AnnaBridge 165:e614a9f1c9e2 1060 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
AnnaBridge 165:e614a9f1c9e2 1061
AnnaBridge 165:e614a9f1c9e2 1062 /* Disable the I2S DMA Channel */
<> 144:ef7eb2e8f9f7 1063 HAL_DMA_Abort(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065 /* Disable I2S peripheral */
<> 144:ef7eb2e8f9f7 1066 __HAL_I2S_DISABLE(hi2s);
AnnaBridge 165:e614a9f1c9e2 1067
<> 144:ef7eb2e8f9f7 1068 hi2s->State = HAL_I2S_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 1069
<> 144:ef7eb2e8f9f7 1070 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1071 __HAL_UNLOCK(hi2s);
AnnaBridge 165:e614a9f1c9e2 1072
<> 144:ef7eb2e8f9f7 1073 return HAL_OK;
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /**
<> 144:ef7eb2e8f9f7 1077 * @brief This function handles I2S interrupt request.
<> 144:ef7eb2e8f9f7 1078 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1079 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1080 * @retval None
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
AnnaBridge 165:e614a9f1c9e2 1083 {
AnnaBridge 165:e614a9f1c9e2 1084 /* Call the IrqHandler ISR set during HAL_I2S_INIT */
AnnaBridge 165:e614a9f1c9e2 1085 hi2s->IrqHandlerISR(hi2s);
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /**
<> 144:ef7eb2e8f9f7 1089 * @brief Tx Transfer Half completed callbacks
<> 144:ef7eb2e8f9f7 1090 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1091 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1092 * @retval None
<> 144:ef7eb2e8f9f7 1093 */
<> 144:ef7eb2e8f9f7 1094 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1095 {
<> 144:ef7eb2e8f9f7 1096 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1097 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1098 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1099 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
AnnaBridge 165:e614a9f1c9e2 1100 */
<> 144:ef7eb2e8f9f7 1101 }
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /**
<> 144:ef7eb2e8f9f7 1104 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1105 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1106 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1107 * @retval None
<> 144:ef7eb2e8f9f7 1108 */
<> 144:ef7eb2e8f9f7 1109 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1110 {
<> 144:ef7eb2e8f9f7 1111 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1112 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1113 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1114 the HAL_I2S_TxCpltCallback could be implemented in the user file
AnnaBridge 165:e614a9f1c9e2 1115 */
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /**
<> 144:ef7eb2e8f9f7 1119 * @brief Rx Transfer half completed callbacks
<> 144:ef7eb2e8f9f7 1120 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1121 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1122 * @retval None
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1127 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1128 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1129 the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1130 */
<> 144:ef7eb2e8f9f7 1131 }
<> 144:ef7eb2e8f9f7 1132
<> 144:ef7eb2e8f9f7 1133 /**
<> 144:ef7eb2e8f9f7 1134 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1135 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1136 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1137 * @retval None
<> 144:ef7eb2e8f9f7 1138 */
<> 144:ef7eb2e8f9f7 1139 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1140 {
<> 144:ef7eb2e8f9f7 1141 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1142 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1143 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1144 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1145 */
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /**
<> 144:ef7eb2e8f9f7 1149 * @brief I2S error callbacks
<> 144:ef7eb2e8f9f7 1150 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1151 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1152 * @retval None
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1157 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1158 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1159 the HAL_I2S_ErrorCallback could be implemented in the user file
AnnaBridge 165:e614a9f1c9e2 1160 */
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /**
<> 144:ef7eb2e8f9f7 1164 * @}
<> 144:ef7eb2e8f9f7 1165 */
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1168 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1169 *
AnnaBridge 165:e614a9f1c9e2 1170 @verbatim
<> 144:ef7eb2e8f9f7 1171 ===============================================================================
<> 144:ef7eb2e8f9f7 1172 ##### Peripheral State and Errors functions #####
AnnaBridge 165:e614a9f1c9e2 1173 ===============================================================================
<> 144:ef7eb2e8f9f7 1174 [..]
AnnaBridge 165:e614a9f1c9e2 1175 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1176 and the data flow.
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 @endverbatim
<> 144:ef7eb2e8f9f7 1179 * @{
<> 144:ef7eb2e8f9f7 1180 */
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /**
<> 144:ef7eb2e8f9f7 1183 * @brief Return the I2S state
<> 144:ef7eb2e8f9f7 1184 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1185 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1186 * @retval HAL state
<> 144:ef7eb2e8f9f7 1187 */
<> 144:ef7eb2e8f9f7 1188 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1189 {
<> 144:ef7eb2e8f9f7 1190 return hi2s->State;
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /**
<> 144:ef7eb2e8f9f7 1194 * @brief Return the I2S error code
<> 144:ef7eb2e8f9f7 1195 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1196 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1197 * @retval I2S Error Code
<> 144:ef7eb2e8f9f7 1198 */
<> 144:ef7eb2e8f9f7 1199 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1200 {
<> 144:ef7eb2e8f9f7 1201 return hi2s->ErrorCode;
<> 144:ef7eb2e8f9f7 1202 }
<> 144:ef7eb2e8f9f7 1203 /**
<> 144:ef7eb2e8f9f7 1204 * @}
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /**
<> 144:ef7eb2e8f9f7 1208 * @}
<> 144:ef7eb2e8f9f7 1209 */
<> 144:ef7eb2e8f9f7 1210
<> 144:ef7eb2e8f9f7 1211 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1212 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 1213 * @{
<> 144:ef7eb2e8f9f7 1214 */
<> 144:ef7eb2e8f9f7 1215 /**
AnnaBridge 165:e614a9f1c9e2 1216 * @brief DMA I2S transmit process complete callback
<> 144:ef7eb2e8f9f7 1217 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1218 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1219 * @retval None
<> 144:ef7eb2e8f9f7 1220 */
<> 144:ef7eb2e8f9f7 1221 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1222 {
AnnaBridge 165:e614a9f1c9e2 1223 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
AnnaBridge 165:e614a9f1c9e2 1224
<> 144:ef7eb2e8f9f7 1225 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 1226 {
<> 144:ef7eb2e8f9f7 1227 /* Disable Tx DMA Request */
AnnaBridge 165:e614a9f1c9e2 1228 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1229
AnnaBridge 165:e614a9f1c9e2 1230 hi2s->TxXferCount = 0U;
AnnaBridge 165:e614a9f1c9e2 1231 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1234 }
<> 144:ef7eb2e8f9f7 1235 /**
AnnaBridge 165:e614a9f1c9e2 1236 * @brief DMA I2S transmit process half complete callback
<> 144:ef7eb2e8f9f7 1237 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1238 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1239 * @retval None
<> 144:ef7eb2e8f9f7 1240 */
<> 144:ef7eb2e8f9f7 1241 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 HAL_I2S_TxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1246 }
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 /**
AnnaBridge 165:e614a9f1c9e2 1249 * @brief DMA I2S receive process complete callback
<> 144:ef7eb2e8f9f7 1250 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1251 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1252 * @retval None
<> 144:ef7eb2e8f9f7 1253 */
<> 144:ef7eb2e8f9f7 1254 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1255 {
AnnaBridge 165:e614a9f1c9e2 1256 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
<> 144:ef7eb2e8f9f7 1259 {
<> 144:ef7eb2e8f9f7 1260 /* Disable Rx DMA Request */
AnnaBridge 165:e614a9f1c9e2 1261 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
AnnaBridge 165:e614a9f1c9e2 1262 hi2s->RxXferCount = 0U;
AnnaBridge 165:e614a9f1c9e2 1263 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1264 }
AnnaBridge 165:e614a9f1c9e2 1265 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1266 }
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /**
AnnaBridge 165:e614a9f1c9e2 1269 * @brief DMA I2S receive process half complete callback
<> 144:ef7eb2e8f9f7 1270 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1271 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1272 * @retval None
<> 144:ef7eb2e8f9f7 1273 */
<> 144:ef7eb2e8f9f7 1274 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1277
AnnaBridge 165:e614a9f1c9e2 1278 HAL_I2S_RxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1279 }
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /**
AnnaBridge 165:e614a9f1c9e2 1282 * @brief DMA I2S communication error callback
<> 144:ef7eb2e8f9f7 1283 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1284 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1285 * @retval None
<> 144:ef7eb2e8f9f7 1286 */
<> 144:ef7eb2e8f9f7 1287 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1288 {
<> 144:ef7eb2e8f9f7 1289 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Disable Rx and Tx DMA Request */
AnnaBridge 165:e614a9f1c9e2 1292 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
AnnaBridge 165:e614a9f1c9e2 1293 hi2s->TxXferCount = 0U;
AnnaBridge 165:e614a9f1c9e2 1294 hi2s->RxXferCount = 0U;
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1297
AnnaBridge 165:e614a9f1c9e2 1298 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
<> 144:ef7eb2e8f9f7 1299 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /**
<> 144:ef7eb2e8f9f7 1303 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1304 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1305 * the configuration information for I2S module
AnnaBridge 165:e614a9f1c9e2 1306 * @retval HAL status
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1309 {
<> 144:ef7eb2e8f9f7 1310 /* Transmit data */
<> 144:ef7eb2e8f9f7 1311 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1312 hi2s->TxXferCount--;
AnnaBridge 165:e614a9f1c9e2 1313
AnnaBridge 165:e614a9f1c9e2 1314 if(hi2s->TxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1317 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1320 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1321 }
<> 144:ef7eb2e8f9f7 1322 }
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /**
<> 144:ef7eb2e8f9f7 1325 * @brief Receive an amount of data in non-blocking mode with Interrupt
AnnaBridge 165:e614a9f1c9e2 1326 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 1327 * the configuration information for I2S module
AnnaBridge 165:e614a9f1c9e2 1328 * @retval HAL status
<> 144:ef7eb2e8f9f7 1329 */
<> 144:ef7eb2e8f9f7 1330 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1331 {
AnnaBridge 165:e614a9f1c9e2 1332 /* Receive data */
<> 144:ef7eb2e8f9f7 1333 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 1334 hi2s->RxXferCount--;
AnnaBridge 165:e614a9f1c9e2 1335
AnnaBridge 165:e614a9f1c9e2 1336 if(hi2s->RxXferCount == 0U)
<> 144:ef7eb2e8f9f7 1337 {
<> 144:ef7eb2e8f9f7 1338 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1339 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1340
AnnaBridge 165:e614a9f1c9e2 1341 hi2s->State = HAL_I2S_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 1342 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1343 }
<> 144:ef7eb2e8f9f7 1344 }
<> 144:ef7eb2e8f9f7 1345
AnnaBridge 165:e614a9f1c9e2 1346 /**
AnnaBridge 165:e614a9f1c9e2 1347 * @brief This function handles I2S interrupt request.
AnnaBridge 165:e614a9f1c9e2 1348 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 1349 * the configuration information for I2S module
AnnaBridge 165:e614a9f1c9e2 1350 * @retval None
AnnaBridge 165:e614a9f1c9e2 1351 */
AnnaBridge 165:e614a9f1c9e2 1352 static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
AnnaBridge 165:e614a9f1c9e2 1353 {
AnnaBridge 165:e614a9f1c9e2 1354 __IO uint32_t i2ssr = hi2s->Instance->SR;
AnnaBridge 165:e614a9f1c9e2 1355
AnnaBridge 165:e614a9f1c9e2 1356 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
AnnaBridge 165:e614a9f1c9e2 1357 {
AnnaBridge 165:e614a9f1c9e2 1358 /* I2S in mode Receiver ------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 1359 if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
AnnaBridge 165:e614a9f1c9e2 1360 {
AnnaBridge 165:e614a9f1c9e2 1361 I2S_Receive_IT(hi2s);
AnnaBridge 165:e614a9f1c9e2 1362 }
AnnaBridge 165:e614a9f1c9e2 1363
AnnaBridge 165:e614a9f1c9e2 1364 /* I2S Overrun error interrupt occured -------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 1365 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
AnnaBridge 165:e614a9f1c9e2 1366 {
AnnaBridge 165:e614a9f1c9e2 1367 /* Disable RXNE and ERR interrupt */
AnnaBridge 165:e614a9f1c9e2 1368 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
AnnaBridge 165:e614a9f1c9e2 1369
AnnaBridge 165:e614a9f1c9e2 1370 /* Clear Overrun flag */
AnnaBridge 165:e614a9f1c9e2 1371 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
AnnaBridge 165:e614a9f1c9e2 1372
AnnaBridge 165:e614a9f1c9e2 1373 /* Set the I2S State ready */
AnnaBridge 165:e614a9f1c9e2 1374 hi2s->State = HAL_I2S_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 1375
AnnaBridge 165:e614a9f1c9e2 1376
AnnaBridge 165:e614a9f1c9e2 1377 /* Set the error code and execute error callback*/
AnnaBridge 165:e614a9f1c9e2 1378 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
AnnaBridge 165:e614a9f1c9e2 1379 HAL_I2S_ErrorCallback(hi2s);
AnnaBridge 165:e614a9f1c9e2 1380 }
AnnaBridge 165:e614a9f1c9e2 1381 }
AnnaBridge 165:e614a9f1c9e2 1382
AnnaBridge 165:e614a9f1c9e2 1383 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
AnnaBridge 165:e614a9f1c9e2 1384 {
AnnaBridge 165:e614a9f1c9e2 1385 /* I2S in mode Transmitter -----------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 1386 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
AnnaBridge 165:e614a9f1c9e2 1387 {
AnnaBridge 165:e614a9f1c9e2 1388 I2S_Transmit_IT(hi2s);
AnnaBridge 165:e614a9f1c9e2 1389 }
AnnaBridge 165:e614a9f1c9e2 1390
AnnaBridge 165:e614a9f1c9e2 1391 /* I2S Underrun error interrupt occurred --------------------------------*/
AnnaBridge 165:e614a9f1c9e2 1392 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
AnnaBridge 165:e614a9f1c9e2 1393 {
AnnaBridge 165:e614a9f1c9e2 1394 /* Disable TXE and ERR interrupt */
AnnaBridge 165:e614a9f1c9e2 1395 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
AnnaBridge 165:e614a9f1c9e2 1396
AnnaBridge 165:e614a9f1c9e2 1397 /* Clear Underrun flag */
AnnaBridge 165:e614a9f1c9e2 1398 __HAL_I2S_CLEAR_UDRFLAG(hi2s);
AnnaBridge 165:e614a9f1c9e2 1399
AnnaBridge 165:e614a9f1c9e2 1400 /* Set the I2S State ready */
AnnaBridge 165:e614a9f1c9e2 1401 hi2s->State = HAL_I2S_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 1402
AnnaBridge 165:e614a9f1c9e2 1403 /* Set the error code and execute error callback*/
AnnaBridge 165:e614a9f1c9e2 1404 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
AnnaBridge 165:e614a9f1c9e2 1405 HAL_I2S_ErrorCallback(hi2s);
AnnaBridge 165:e614a9f1c9e2 1406 }
AnnaBridge 165:e614a9f1c9e2 1407 }
AnnaBridge 165:e614a9f1c9e2 1408 }
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /**
<> 144:ef7eb2e8f9f7 1411 * @brief This function handles I2S Communication Timeout.
<> 144:ef7eb2e8f9f7 1412 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1413 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1414 * @param Flag: Flag checked
AnnaBridge 165:e614a9f1c9e2 1415 * @param State: Value of the flag expected
<> 144:ef7eb2e8f9f7 1416 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 1417 * @retval HAL status
<> 144:ef7eb2e8f9f7 1418 */
AnnaBridge 165:e614a9f1c9e2 1419 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
AnnaBridge 165:e614a9f1c9e2 1420 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1421 {
AnnaBridge 165:e614a9f1c9e2 1422 uint32_t tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1423
AnnaBridge 165:e614a9f1c9e2 1424 /* Wait until flag is set to status*/
AnnaBridge 165:e614a9f1c9e2 1425 while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
<> 144:ef7eb2e8f9f7 1426 {
AnnaBridge 165:e614a9f1c9e2 1427 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1428 {
AnnaBridge 165:e614a9f1c9e2 1429 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1430 {
AnnaBridge 165:e614a9f1c9e2 1431 /* Set the I2S State ready */
AnnaBridge 165:e614a9f1c9e2 1432 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1433
AnnaBridge 165:e614a9f1c9e2 1434 /* Process Unlocked */
AnnaBridge 165:e614a9f1c9e2 1435 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1436
AnnaBridge 165:e614a9f1c9e2 1437 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 }
<> 144:ef7eb2e8f9f7 1440 }
<> 144:ef7eb2e8f9f7 1441 return HAL_OK;
<> 144:ef7eb2e8f9f7 1442 }
<> 144:ef7eb2e8f9f7 1443
<> 144:ef7eb2e8f9f7 1444 /**
<> 144:ef7eb2e8f9f7 1445 * @}
<> 144:ef7eb2e8f9f7 1446 */
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /**
<> 144:ef7eb2e8f9f7 1449 * @}
<> 144:ef7eb2e8f9f7 1450 */
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1453 #endif /* HAL_I2S_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1454 /**
<> 144:ef7eb2e8f9f7 1455 * @}
<> 144:ef7eb2e8f9f7 1456 */
<> 144:ef7eb2e8f9f7 1457
<> 144:ef7eb2e8f9f7 1458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/