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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_dma.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of DMA HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 165:e614a9f1c9e2 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F1xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F1xx_HAL_DMA_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup DMA
<> 144:ef7eb2e8f9f7 52 * @{
AnnaBridge 165:e614a9f1c9e2 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @defgroup DMA_Exported_Types DMA Exported Types
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
AnnaBridge 165:e614a9f1c9e2 60
AnnaBridge 165:e614a9f1c9e2 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct
<> 144:ef7eb2e8f9f7 65 {
<> 144:ef7eb2e8f9f7 66 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
<> 144:ef7eb2e8f9f7 67 from memory to memory or from peripheral to memory.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref DMA_Data_transfer_direction */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 165:e614a9f1c9e2 72
<> 144:ef7eb2e8f9f7 73 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 165:e614a9f1c9e2 75
<> 144:ef7eb2e8f9f7 76 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref DMA_Peripheral_data_size */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 165:e614a9f1c9e2 81
<> 144:ef7eb2e8f9f7 82 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref DMA_mode
<> 144:ef7eb2e8f9f7 84 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 165:e614a9f1c9e2 85 data transfer is configured on the selected Channel */
<> 144:ef7eb2e8f9f7 86
AnnaBridge 165:e614a9f1c9e2 87 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
AnnaBridge 165:e614a9f1c9e2 88 This parameter can be a value of @ref DMA_Priority_level */
<> 144:ef7eb2e8f9f7 89 } DMA_InitTypeDef;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
AnnaBridge 165:e614a9f1c9e2 92 * @brief HAL DMA State structures definition
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94 typedef enum
<> 144:ef7eb2e8f9f7 95 {
AnnaBridge 165:e614a9f1c9e2 96 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
AnnaBridge 165:e614a9f1c9e2 97 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
AnnaBridge 165:e614a9f1c9e2 98 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
AnnaBridge 165:e614a9f1c9e2 99 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
<> 144:ef7eb2e8f9f7 100 }HAL_DMA_StateTypeDef;
<> 144:ef7eb2e8f9f7 101
AnnaBridge 165:e614a9f1c9e2 102 /**
<> 144:ef7eb2e8f9f7 103 * @brief HAL DMA Error Code structure definition
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105 typedef enum
<> 144:ef7eb2e8f9f7 106 {
AnnaBridge 165:e614a9f1c9e2 107 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
AnnaBridge 165:e614a9f1c9e2 108 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
<> 144:ef7eb2e8f9f7 109 }HAL_DMA_LevelCompleteTypeDef;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /**
AnnaBridge 165:e614a9f1c9e2 112 * @brief HAL DMA Callback ID structure definition
AnnaBridge 165:e614a9f1c9e2 113 */
AnnaBridge 165:e614a9f1c9e2 114 typedef enum
AnnaBridge 165:e614a9f1c9e2 115 {
AnnaBridge 165:e614a9f1c9e2 116 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
AnnaBridge 165:e614a9f1c9e2 117 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
AnnaBridge 165:e614a9f1c9e2 118 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
AnnaBridge 165:e614a9f1c9e2 119 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
AnnaBridge 165:e614a9f1c9e2 120 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
AnnaBridge 165:e614a9f1c9e2 121
AnnaBridge 165:e614a9f1c9e2 122 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 165:e614a9f1c9e2 123
AnnaBridge 165:e614a9f1c9e2 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief DMA handle Structure definition
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef struct __DMA_HandleTypeDef
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 DMA_Channel_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 DMA_InitTypeDef Init; /*!< DMA communication parameters */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 HAL_LockTypeDef Lock; /*!< DMA locking object */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 void *Parent; /*!< Parent object state */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
<> 154:37f96f9d4de2 144
<> 154:37f96f9d4de2 145 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 165:e614a9f1c9e2 148
AnnaBridge 165:e614a9f1c9e2 149 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
AnnaBridge 165:e614a9f1c9e2 150
AnnaBridge 165:e614a9f1c9e2 151 uint32_t ChannelIndex; /*!< DMA Channel Index */
AnnaBridge 165:e614a9f1c9e2 152
<> 144:ef7eb2e8f9f7 153 } DMA_HandleTypeDef;
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** @defgroup DMA_Error_Code DMA Error Code
<> 144:ef7eb2e8f9f7 165 * @{
<> 144:ef7eb2e8f9f7 166 */
AnnaBridge 165:e614a9f1c9e2 167 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 165:e614a9f1c9e2 168 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
AnnaBridge 165:e614a9f1c9e2 169 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */
AnnaBridge 165:e614a9f1c9e2 170 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
AnnaBridge 165:e614a9f1c9e2 171 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
<> 144:ef7eb2e8f9f7 177 * @{
AnnaBridge 165:e614a9f1c9e2 178 */
AnnaBridge 165:e614a9f1c9e2 179 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
<> 144:ef7eb2e8f9f7 180 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
<> 144:ef7eb2e8f9f7 181 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @}
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
<> 144:ef7eb2e8f9f7 188 * @{
AnnaBridge 165:e614a9f1c9e2 189 */
AnnaBridge 165:e614a9f1c9e2 190 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
AnnaBridge 165:e614a9f1c9e2 191 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
<> 144:ef7eb2e8f9f7 192 /**
<> 144:ef7eb2e8f9f7 193 * @}
AnnaBridge 165:e614a9f1c9e2 194 */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
<> 144:ef7eb2e8f9f7 197 * @{
AnnaBridge 165:e614a9f1c9e2 198 */
AnnaBridge 165:e614a9f1c9e2 199 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
AnnaBridge 165:e614a9f1c9e2 200 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @}
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
<> 144:ef7eb2e8f9f7 206 * @{
AnnaBridge 165:e614a9f1c9e2 207 */
AnnaBridge 165:e614a9f1c9e2 208 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
AnnaBridge 165:e614a9f1c9e2 209 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
AnnaBridge 165:e614a9f1c9e2 210 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @}
AnnaBridge 165:e614a9f1c9e2 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 165:e614a9f1c9e2 216 * @{
<> 144:ef7eb2e8f9f7 217 */
AnnaBridge 165:e614a9f1c9e2 218 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
AnnaBridge 165:e614a9f1c9e2 219 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
AnnaBridge 165:e614a9f1c9e2 220 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @}
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /** @defgroup DMA_mode DMA mode
<> 144:ef7eb2e8f9f7 226 * @{
AnnaBridge 165:e614a9f1c9e2 227 */
AnnaBridge 165:e614a9f1c9e2 228 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
<> 144:ef7eb2e8f9f7 229 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @}
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /** @defgroup DMA_Priority_level DMA Priority level
<> 144:ef7eb2e8f9f7 235 * @{
<> 144:ef7eb2e8f9f7 236 */
AnnaBridge 165:e614a9f1c9e2 237 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
AnnaBridge 165:e614a9f1c9e2 238 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
AnnaBridge 165:e614a9f1c9e2 239 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
AnnaBridge 165:e614a9f1c9e2 240 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
AnnaBridge 165:e614a9f1c9e2 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
<> 144:ef7eb2e8f9f7 250 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
<> 144:ef7eb2e8f9f7 251 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
<> 144:ef7eb2e8f9f7 252 /**
<> 144:ef7eb2e8f9f7 253 * @}
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /** @defgroup DMA_flag_definitions DMA flag definitions
<> 144:ef7eb2e8f9f7 257 * @{
AnnaBridge 165:e614a9f1c9e2 258 */
AnnaBridge 165:e614a9f1c9e2 259 #define DMA_FLAG_GL1 0x00000001U
AnnaBridge 165:e614a9f1c9e2 260 #define DMA_FLAG_TC1 0x00000002U
AnnaBridge 165:e614a9f1c9e2 261 #define DMA_FLAG_HT1 0x00000004U
AnnaBridge 165:e614a9f1c9e2 262 #define DMA_FLAG_TE1 0x00000008U
AnnaBridge 165:e614a9f1c9e2 263 #define DMA_FLAG_GL2 0x00000010U
AnnaBridge 165:e614a9f1c9e2 264 #define DMA_FLAG_TC2 0x00000020U
AnnaBridge 165:e614a9f1c9e2 265 #define DMA_FLAG_HT2 0x00000040U
AnnaBridge 165:e614a9f1c9e2 266 #define DMA_FLAG_TE2 0x00000080U
AnnaBridge 165:e614a9f1c9e2 267 #define DMA_FLAG_GL3 0x00000100U
AnnaBridge 165:e614a9f1c9e2 268 #define DMA_FLAG_TC3 0x00000200U
AnnaBridge 165:e614a9f1c9e2 269 #define DMA_FLAG_HT3 0x00000400U
AnnaBridge 165:e614a9f1c9e2 270 #define DMA_FLAG_TE3 0x00000800U
AnnaBridge 165:e614a9f1c9e2 271 #define DMA_FLAG_GL4 0x00001000U
AnnaBridge 165:e614a9f1c9e2 272 #define DMA_FLAG_TC4 0x00002000U
AnnaBridge 165:e614a9f1c9e2 273 #define DMA_FLAG_HT4 0x00004000U
AnnaBridge 165:e614a9f1c9e2 274 #define DMA_FLAG_TE4 0x00008000U
AnnaBridge 165:e614a9f1c9e2 275 #define DMA_FLAG_GL5 0x00010000U
AnnaBridge 165:e614a9f1c9e2 276 #define DMA_FLAG_TC5 0x00020000U
AnnaBridge 165:e614a9f1c9e2 277 #define DMA_FLAG_HT5 0x00040000U
AnnaBridge 165:e614a9f1c9e2 278 #define DMA_FLAG_TE5 0x00080000U
AnnaBridge 165:e614a9f1c9e2 279 #define DMA_FLAG_GL6 0x00100000U
AnnaBridge 165:e614a9f1c9e2 280 #define DMA_FLAG_TC6 0x00200000U
AnnaBridge 165:e614a9f1c9e2 281 #define DMA_FLAG_HT6 0x00400000U
AnnaBridge 165:e614a9f1c9e2 282 #define DMA_FLAG_TE6 0x00800000U
AnnaBridge 165:e614a9f1c9e2 283 #define DMA_FLAG_GL7 0x01000000U
AnnaBridge 165:e614a9f1c9e2 284 #define DMA_FLAG_TC7 0x02000000U
AnnaBridge 165:e614a9f1c9e2 285 #define DMA_FLAG_HT7 0x04000000U
AnnaBridge 165:e614a9f1c9e2 286 #define DMA_FLAG_TE7 0x08000000U
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @}
<> 144:ef7eb2e8f9f7 293 */
AnnaBridge 165:e614a9f1c9e2 294
<> 144:ef7eb2e8f9f7 295
AnnaBridge 165:e614a9f1c9e2 296 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 297 /** @defgroup DMA_Exported_Macros DMA Exported Macros
<> 144:ef7eb2e8f9f7 298 * @{
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
AnnaBridge 165:e614a9f1c9e2 301 /** @brief Reset DMA handle state.
AnnaBridge 165:e614a9f1c9e2 302 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 303 * @retval None
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 309 * @param __HANDLE__: DMA handle
AnnaBridge 165:e614a9f1c9e2 310 * @retval None
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 316 * @param __HANDLE__: DMA handle
AnnaBridge 165:e614a9f1c9e2 317 * @retval None
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @brief Enables the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 326 * @param __HANDLE__: DMA handle
AnnaBridge 165:e614a9f1c9e2 327 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 328 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 329 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 330 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 331 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 332 * @retval None
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
AnnaBridge 165:e614a9f1c9e2 337 * @brief Disable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 338 * @param __HANDLE__: DMA handle
AnnaBridge 165:e614a9f1c9e2 339 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 340 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 341 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 342 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 343 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 344 * @retval None
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /**
AnnaBridge 165:e614a9f1c9e2 349 * @brief Check whether the specified DMA Channel interrupt is enabled or not.
<> 144:ef7eb2e8f9f7 350 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 351 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
<> 144:ef7eb2e8f9f7 352 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 353 * @arg DMA_IT_TC: Transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 354 * @arg DMA_IT_HT: Half transfer complete interrupt mask
<> 144:ef7eb2e8f9f7 355 * @arg DMA_IT_TE: Transfer error interrupt mask
<> 144:ef7eb2e8f9f7 356 * @retval The state of DMA_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
AnnaBridge 165:e614a9f1c9e2 361 * @brief Return the number of remaining data units in the current DMA Channel transfer.
<> 144:ef7eb2e8f9f7 362 * @param __HANDLE__: DMA handle
<> 144:ef7eb2e8f9f7 363 * @retval The number of remaining data units in the current DMA Channel transfer.
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @}
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Include DMA HAL Extension module */
<> 144:ef7eb2e8f9f7 372 #include "stm32f1xx_hal_dma_ex.h"
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Exported functions --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 375 /** @addtogroup DMA_Exported_Functions
<> 144:ef7eb2e8f9f7 376 * @{
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378
AnnaBridge 165:e614a9f1c9e2 379 /** @addtogroup DMA_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 380 * @{
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 383 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 384 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
AnnaBridge 165:e614a9f1c9e2 389 /** @addtogroup DMA_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 390 * @{
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 393 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 394 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 395 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
<> 154:37f96f9d4de2 396 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 397 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
AnnaBridge 165:e614a9f1c9e2 398 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 165:e614a9f1c9e2 399 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
AnnaBridge 165:e614a9f1c9e2 400 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 165:e614a9f1c9e2 401
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405
AnnaBridge 165:e614a9f1c9e2 406 /** @addtogroup DMA_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 407 * @{
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 410 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 165:e614a9f1c9e2 411 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 412 /**
<> 144:ef7eb2e8f9f7 413 * @}
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /**
<> 144:ef7eb2e8f9f7 417 * @}
<> 144:ef7eb2e8f9f7 418 */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 421 /** @defgroup DMA_Private_Macros DMA Private Macros
<> 144:ef7eb2e8f9f7 422 * @{
<> 144:ef7eb2e8f9f7 423 */
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
<> 144:ef7eb2e8f9f7 426 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 165:e614a9f1c9e2 427 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 165:e614a9f1c9e2 428
AnnaBridge 165:e614a9f1c9e2 429 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 432 ((STATE) == DMA_PINC_DISABLE))
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
<> 144:ef7eb2e8f9f7 435 ((STATE) == DMA_MINC_DISABLE))
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 438 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 439 ((SIZE) == DMA_PDATAALIGN_WORD))
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
<> 144:ef7eb2e8f9f7 442 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
<> 144:ef7eb2e8f9f7 443 ((SIZE) == DMA_MDATAALIGN_WORD ))
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 165:e614a9f1c9e2 446 ((MODE) == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
<> 144:ef7eb2e8f9f7 449 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
<> 144:ef7eb2e8f9f7 450 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 165:e614a9f1c9e2 451 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Private functions ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @}
<> 144:ef7eb2e8f9f7 461 */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /**
<> 144:ef7eb2e8f9f7 464 * @}
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469 #endif
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #endif /* __STM32F1xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/