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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_dma.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief DMA HAL module driver.
AnnaBridge 165:e614a9f1c9e2 6 * This file provides firmware functions to manage the following
AnnaBridge 165:e614a9f1c9e2 7 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral State and errors functions
AnnaBridge 165:e614a9f1c9e2 11 @verbatim
AnnaBridge 165:e614a9f1c9e2 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
AnnaBridge 165:e614a9f1c9e2 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 [..]
<> 144:ef7eb2e8f9f7 16 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 144:ef7eb2e8f9f7 17 (except for internal SRAM / FLASH memories: no initialization is
AnnaBridge 165:e614a9f1c9e2 18 necessary). Please refer to the Reference manual for connection between peripherals
<> 144:ef7eb2e8f9f7 19 and DMA requests.
<> 144:ef7eb2e8f9f7 20
AnnaBridge 165:e614a9f1c9e2 21 (#) For a given Channel, program the required configuration through the following parameters:
AnnaBridge 165:e614a9f1c9e2 22 Channel request, Transfer Direction, Source and Destination data formats,
AnnaBridge 165:e614a9f1c9e2 23 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
<> 144:ef7eb2e8f9f7 24 using HAL_DMA_Init() function.
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 144:ef7eb2e8f9f7 27 detection.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 144:ef7eb2e8f9f7 32 *** Polling mode IO operation ***
AnnaBridge 165:e614a9f1c9e2 33 =================================
AnnaBridge 165:e614a9f1c9e2 34 [..]
AnnaBridge 165:e614a9f1c9e2 35 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
AnnaBridge 165:e614a9f1c9e2 36 address and destination address and the Length of data to be transferred
AnnaBridge 165:e614a9f1c9e2 37 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
AnnaBridge 165:e614a9f1c9e2 38 case a fixed Timeout can be configured by User depending from his application.
<> 144:ef7eb2e8f9f7 39
AnnaBridge 165:e614a9f1c9e2 40 *** Interrupt mode IO operation ***
AnnaBridge 165:e614a9f1c9e2 41 ===================================
<> 144:ef7eb2e8f9f7 42 [..]
AnnaBridge 165:e614a9f1c9e2 43 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
AnnaBridge 165:e614a9f1c9e2 44 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
AnnaBridge 165:e614a9f1c9e2 45 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
AnnaBridge 165:e614a9f1c9e2 46 Source address and destination address and the Length of data to be transferred.
AnnaBridge 165:e614a9f1c9e2 47 In this case the DMA interrupt is configured
AnnaBridge 165:e614a9f1c9e2 48 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
AnnaBridge 165:e614a9f1c9e2 49 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
AnnaBridge 165:e614a9f1c9e2 50 add his own function by customization of function pointer XferCpltCallback and
AnnaBridge 165:e614a9f1c9e2 51 XferErrorCallback (i.e. a member of DMA handle structure).
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 *** DMA HAL driver macros list ***
<> 144:ef7eb2e8f9f7 54 =============================================
AnnaBridge 165:e614a9f1c9e2 55 [..]
<> 144:ef7eb2e8f9f7 56 Below the list of most used macros in DMA HAL driver.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 59 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 144:ef7eb2e8f9f7 60 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 61 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 144:ef7eb2e8f9f7 62 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 63 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
<> 144:ef7eb2e8f9f7 64 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 [..]
<> 144:ef7eb2e8f9f7 67 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 @endverbatim
<> 144:ef7eb2e8f9f7 70 ******************************************************************************
<> 144:ef7eb2e8f9f7 71 * @attention
<> 144:ef7eb2e8f9f7 72 *
AnnaBridge 165:e614a9f1c9e2 73 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 76 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 77 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 81 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 83 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 84 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 85 *
<> 144:ef7eb2e8f9f7 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** @defgroup DMA DMA
<> 144:ef7eb2e8f9f7 108 * @brief DMA HAL module driver
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #ifdef HAL_DMA_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 134 * @brief Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 135 *
AnnaBridge 165:e614a9f1c9e2 136 @verbatim
<> 144:ef7eb2e8f9f7 137 ===============================================================================
<> 144:ef7eb2e8f9f7 138 ##### Initialization and de-initialization functions #####
AnnaBridge 165:e614a9f1c9e2 139 ===============================================================================
<> 144:ef7eb2e8f9f7 140 [..]
<> 144:ef7eb2e8f9f7 141 This section provides functions allowing to initialize the DMA Channel source
<> 144:ef7eb2e8f9f7 142 and destination addresses, incrementation and data sizes, transfer direction,
<> 144:ef7eb2e8f9f7 143 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 144:ef7eb2e8f9f7 144 [..]
<> 144:ef7eb2e8f9f7 145 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 144:ef7eb2e8f9f7 146 reference manual.
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 @endverbatim
<> 144:ef7eb2e8f9f7 149 * @{
<> 144:ef7eb2e8f9f7 150 */
AnnaBridge 165:e614a9f1c9e2 151
<> 144:ef7eb2e8f9f7 152 /**
AnnaBridge 165:e614a9f1c9e2 153 * @brief Initialize the DMA according to the specified
AnnaBridge 165:e614a9f1c9e2 154 * parameters in the DMA_InitTypeDef and initialize the associated handle.
<> 144:ef7eb2e8f9f7 155 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 156 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 157 * @retval HAL status
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
AnnaBridge 165:e614a9f1c9e2 160 {
AnnaBridge 165:e614a9f1c9e2 161 uint32_t tmp = 0U;
AnnaBridge 165:e614a9f1c9e2 162
<> 144:ef7eb2e8f9f7 163 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 164 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 167 }
AnnaBridge 165:e614a9f1c9e2 168
<> 144:ef7eb2e8f9f7 169 /* Check the parameters */
<> 144:ef7eb2e8f9f7 170 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 144:ef7eb2e8f9f7 175 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 144:ef7eb2e8f9f7 176 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
AnnaBridge 165:e614a9f1c9e2 178
AnnaBridge 165:e614a9f1c9e2 179 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
AnnaBridge 165:e614a9f1c9e2 180 /* calculation of the channel index */
AnnaBridge 165:e614a9f1c9e2 181 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
AnnaBridge 165:e614a9f1c9e2 182 {
AnnaBridge 165:e614a9f1c9e2 183 /* DMA1 */
AnnaBridge 165:e614a9f1c9e2 184 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
AnnaBridge 165:e614a9f1c9e2 185 hdma->DmaBaseAddress = DMA1;
<> 144:ef7eb2e8f9f7 186 }
AnnaBridge 165:e614a9f1c9e2 187 else
AnnaBridge 165:e614a9f1c9e2 188 {
AnnaBridge 165:e614a9f1c9e2 189 /* DMA2 */
AnnaBridge 165:e614a9f1c9e2 190 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
AnnaBridge 165:e614a9f1c9e2 191 hdma->DmaBaseAddress = DMA2;
AnnaBridge 165:e614a9f1c9e2 192 }
AnnaBridge 165:e614a9f1c9e2 193 #else
AnnaBridge 165:e614a9f1c9e2 194 /* DMA1 */
AnnaBridge 165:e614a9f1c9e2 195 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
AnnaBridge 165:e614a9f1c9e2 196 hdma->DmaBaseAddress = DMA1;
AnnaBridge 165:e614a9f1c9e2 197 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
AnnaBridge 165:e614a9f1c9e2 198
<> 144:ef7eb2e8f9f7 199 /* Change DMA peripheral state */
<> 144:ef7eb2e8f9f7 200 hdma->State = HAL_DMA_STATE_BUSY;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Get the CR register value */
<> 144:ef7eb2e8f9f7 203 tmp = hdma->Instance->CCR;
AnnaBridge 165:e614a9f1c9e2 204
AnnaBridge 165:e614a9f1c9e2 205 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
<> 144:ef7eb2e8f9f7 206 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 144:ef7eb2e8f9f7 207 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 144:ef7eb2e8f9f7 208 DMA_CCR_DIR));
AnnaBridge 165:e614a9f1c9e2 209
<> 144:ef7eb2e8f9f7 210 /* Prepare the DMA Channel configuration */
<> 144:ef7eb2e8f9f7 211 tmp |= hdma->Init.Direction |
<> 144:ef7eb2e8f9f7 212 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 144:ef7eb2e8f9f7 213 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 144:ef7eb2e8f9f7 214 hdma->Init.Mode | hdma->Init.Priority;
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Write to DMA Channel CR register */
AnnaBridge 165:e614a9f1c9e2 217 hdma->Instance->CCR = tmp;
AnnaBridge 165:e614a9f1c9e2 218
AnnaBridge 165:e614a9f1c9e2 219
AnnaBridge 165:e614a9f1c9e2 220 /* Clean callbacks */
AnnaBridge 165:e614a9f1c9e2 221 hdma->XferCpltCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 222 hdma->XferHalfCpltCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 223 hdma->XferErrorCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 224 hdma->XferAbortCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 225
<> 144:ef7eb2e8f9f7 226 /* Initialise the error code */
<> 144:ef7eb2e8f9f7 227 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Initialize the DMA state*/
<> 144:ef7eb2e8f9f7 230 hdma->State = HAL_DMA_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 231 /* Allocate lock resource and initialize it */
AnnaBridge 165:e614a9f1c9e2 232 hdma->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 return HAL_OK;
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
AnnaBridge 165:e614a9f1c9e2 238 * @brief DeInitialize the DMA peripheral.
<> 144:ef7eb2e8f9f7 239 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 240 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 241 * @retval HAL status
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* Check the DMA handle allocation */
<> 144:ef7eb2e8f9f7 246 if(hdma == NULL)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 249 }
AnnaBridge 165:e614a9f1c9e2 250
<> 144:ef7eb2e8f9f7 251 /* Check the parameters */
<> 144:ef7eb2e8f9f7 252 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Disable the selected DMA Channelx */
<> 144:ef7eb2e8f9f7 255 __HAL_DMA_DISABLE(hdma);
AnnaBridge 165:e614a9f1c9e2 256
<> 144:ef7eb2e8f9f7 257 /* Reset DMA Channel control register */
AnnaBridge 165:e614a9f1c9e2 258 hdma->Instance->CCR = 0U;
AnnaBridge 165:e614a9f1c9e2 259
<> 144:ef7eb2e8f9f7 260 /* Reset DMA Channel Number of Data to Transfer register */
AnnaBridge 165:e614a9f1c9e2 261 hdma->Instance->CNDTR = 0U;
AnnaBridge 165:e614a9f1c9e2 262
<> 144:ef7eb2e8f9f7 263 /* Reset DMA Channel peripheral address register */
AnnaBridge 165:e614a9f1c9e2 264 hdma->Instance->CPAR = 0U;
AnnaBridge 165:e614a9f1c9e2 265
<> 144:ef7eb2e8f9f7 266 /* Reset DMA Channel memory address register */
AnnaBridge 165:e614a9f1c9e2 267 hdma->Instance->CMAR = 0U;
AnnaBridge 165:e614a9f1c9e2 268
AnnaBridge 165:e614a9f1c9e2 269 #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
AnnaBridge 165:e614a9f1c9e2 270 /* calculation of the channel index */
AnnaBridge 165:e614a9f1c9e2 271 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
AnnaBridge 165:e614a9f1c9e2 272 {
AnnaBridge 165:e614a9f1c9e2 273 /* DMA1 */
AnnaBridge 165:e614a9f1c9e2 274 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
AnnaBridge 165:e614a9f1c9e2 275 hdma->DmaBaseAddress = DMA1;
AnnaBridge 165:e614a9f1c9e2 276 }
AnnaBridge 165:e614a9f1c9e2 277 else
AnnaBridge 165:e614a9f1c9e2 278 {
AnnaBridge 165:e614a9f1c9e2 279 /* DMA2 */
AnnaBridge 165:e614a9f1c9e2 280 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
AnnaBridge 165:e614a9f1c9e2 281 hdma->DmaBaseAddress = DMA2;
AnnaBridge 165:e614a9f1c9e2 282 }
AnnaBridge 165:e614a9f1c9e2 283 #else
AnnaBridge 165:e614a9f1c9e2 284 /* DMA1 */
AnnaBridge 165:e614a9f1c9e2 285 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
AnnaBridge 165:e614a9f1c9e2 286 hdma->DmaBaseAddress = DMA1;
AnnaBridge 165:e614a9f1c9e2 287 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* Clear all flags */
AnnaBridge 165:e614a9f1c9e2 290 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
AnnaBridge 165:e614a9f1c9e2 291
<> 144:ef7eb2e8f9f7 292 /* Initialize the error code */
<> 144:ef7eb2e8f9f7 293 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Initialize the DMA state */
<> 144:ef7eb2e8f9f7 296 hdma->State = HAL_DMA_STATE_RESET;
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /* Release Lock */
<> 144:ef7eb2e8f9f7 299 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 return HAL_OK;
<> 144:ef7eb2e8f9f7 302 }
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /**
<> 144:ef7eb2e8f9f7 305 * @}
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
AnnaBridge 165:e614a9f1c9e2 308 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
AnnaBridge 165:e614a9f1c9e2 309 * @brief Input and Output operation functions
AnnaBridge 165:e614a9f1c9e2 310 *
AnnaBridge 165:e614a9f1c9e2 311 @verbatim
<> 144:ef7eb2e8f9f7 312 ===============================================================================
<> 144:ef7eb2e8f9f7 313 ##### IO operation functions #####
AnnaBridge 165:e614a9f1c9e2 314 ===============================================================================
<> 144:ef7eb2e8f9f7 315 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 316 (+) Configure the source, destination address and data length and Start DMA transfer
AnnaBridge 165:e614a9f1c9e2 317 (+) Configure the source, destination address and data length and
<> 144:ef7eb2e8f9f7 318 Start DMA transfer with interrupt
<> 144:ef7eb2e8f9f7 319 (+) Abort DMA transfer
<> 144:ef7eb2e8f9f7 320 (+) Poll for transfer complete
AnnaBridge 165:e614a9f1c9e2 321 (+) Handle DMA interrupt request
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 @endverbatim
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
AnnaBridge 165:e614a9f1c9e2 328 * @brief Start the DMA Transfer.
AnnaBridge 165:e614a9f1c9e2 329 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 330 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 331 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 332 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 333 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 334 * @retval HAL status
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 337 {
AnnaBridge 165:e614a9f1c9e2 338 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 165:e614a9f1c9e2 339
AnnaBridge 165:e614a9f1c9e2 340 /* Check the parameters */
AnnaBridge 165:e614a9f1c9e2 341 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
AnnaBridge 165:e614a9f1c9e2 342
<> 144:ef7eb2e8f9f7 343 /* Process locked */
<> 144:ef7eb2e8f9f7 344 __HAL_LOCK(hdma);
<> 144:ef7eb2e8f9f7 345
AnnaBridge 165:e614a9f1c9e2 346 if(HAL_DMA_STATE_READY == hdma->State)
AnnaBridge 165:e614a9f1c9e2 347 {
AnnaBridge 165:e614a9f1c9e2 348 /* Change DMA peripheral state */
AnnaBridge 165:e614a9f1c9e2 349 hdma->State = HAL_DMA_STATE_BUSY;
AnnaBridge 165:e614a9f1c9e2 350 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 351
AnnaBridge 165:e614a9f1c9e2 352 /* Disable the peripheral */
AnnaBridge 165:e614a9f1c9e2 353 __HAL_DMA_DISABLE(hdma);
AnnaBridge 165:e614a9f1c9e2 354
AnnaBridge 165:e614a9f1c9e2 355 /* Configure the source, destination address and the data length & clear flags*/
AnnaBridge 165:e614a9f1c9e2 356 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
AnnaBridge 165:e614a9f1c9e2 357
AnnaBridge 165:e614a9f1c9e2 358 /* Enable the Peripheral */
AnnaBridge 165:e614a9f1c9e2 359 __HAL_DMA_ENABLE(hdma);
AnnaBridge 165:e614a9f1c9e2 360 }
AnnaBridge 165:e614a9f1c9e2 361 else
AnnaBridge 165:e614a9f1c9e2 362 {
AnnaBridge 165:e614a9f1c9e2 363 /* Process Unlocked */
AnnaBridge 165:e614a9f1c9e2 364 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 365 status = HAL_BUSY;
AnnaBridge 165:e614a9f1c9e2 366 }
AnnaBridge 165:e614a9f1c9e2 367 return status;
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /**
<> 144:ef7eb2e8f9f7 371 * @brief Start the DMA Transfer with interrupt enabled.
AnnaBridge 165:e614a9f1c9e2 372 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 373 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 374 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 375 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 376 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 377 * @retval HAL status
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 380 {
AnnaBridge 165:e614a9f1c9e2 381 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 165:e614a9f1c9e2 382
AnnaBridge 165:e614a9f1c9e2 383 /* Check the parameters */
AnnaBridge 165:e614a9f1c9e2 384 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
AnnaBridge 165:e614a9f1c9e2 385
<> 144:ef7eb2e8f9f7 386 /* Process locked */
<> 144:ef7eb2e8f9f7 387 __HAL_LOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 388
AnnaBridge 165:e614a9f1c9e2 389 if(HAL_DMA_STATE_READY == hdma->State)
AnnaBridge 165:e614a9f1c9e2 390 {
AnnaBridge 165:e614a9f1c9e2 391 /* Change DMA peripheral state */
AnnaBridge 165:e614a9f1c9e2 392 hdma->State = HAL_DMA_STATE_BUSY;
AnnaBridge 165:e614a9f1c9e2 393 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
AnnaBridge 165:e614a9f1c9e2 394
AnnaBridge 165:e614a9f1c9e2 395 /* Disable the peripheral */
AnnaBridge 165:e614a9f1c9e2 396 __HAL_DMA_DISABLE(hdma);
AnnaBridge 165:e614a9f1c9e2 397
AnnaBridge 165:e614a9f1c9e2 398 /* Configure the source, destination address and the data length & clear flags*/
AnnaBridge 165:e614a9f1c9e2 399 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
AnnaBridge 165:e614a9f1c9e2 400
AnnaBridge 165:e614a9f1c9e2 401 /* Enable the transfer complete interrupt */
AnnaBridge 165:e614a9f1c9e2 402 /* Enable the transfer Error interrupt */
AnnaBridge 165:e614a9f1c9e2 403 if(NULL != hdma->XferHalfCpltCallback)
AnnaBridge 165:e614a9f1c9e2 404 {
AnnaBridge 165:e614a9f1c9e2 405 /* Enable the Half transfer complete interrupt as well */
AnnaBridge 165:e614a9f1c9e2 406 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
AnnaBridge 165:e614a9f1c9e2 407 }
AnnaBridge 165:e614a9f1c9e2 408 else
AnnaBridge 165:e614a9f1c9e2 409 {
AnnaBridge 165:e614a9f1c9e2 410 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
AnnaBridge 165:e614a9f1c9e2 411 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
AnnaBridge 165:e614a9f1c9e2 412 }
AnnaBridge 165:e614a9f1c9e2 413 /* Enable the Peripheral */
AnnaBridge 165:e614a9f1c9e2 414 __HAL_DMA_ENABLE(hdma);
AnnaBridge 165:e614a9f1c9e2 415 }
AnnaBridge 165:e614a9f1c9e2 416 else
AnnaBridge 165:e614a9f1c9e2 417 {
AnnaBridge 165:e614a9f1c9e2 418 /* Process Unlocked */
AnnaBridge 165:e614a9f1c9e2 419 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 420
AnnaBridge 165:e614a9f1c9e2 421 /* Remain BUSY */
AnnaBridge 165:e614a9f1c9e2 422 status = HAL_BUSY;
AnnaBridge 165:e614a9f1c9e2 423 }
AnnaBridge 165:e614a9f1c9e2 424 return status;
AnnaBridge 165:e614a9f1c9e2 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /**
AnnaBridge 165:e614a9f1c9e2 428 * @brief Abort the DMA Transfer.
AnnaBridge 165:e614a9f1c9e2 429 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 430 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 431 * @retval HAL status
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 434 {
AnnaBridge 165:e614a9f1c9e2 435 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 165:e614a9f1c9e2 436
AnnaBridge 165:e614a9f1c9e2 437 /* Disable DMA IT */
AnnaBridge 165:e614a9f1c9e2 438 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
AnnaBridge 165:e614a9f1c9e2 439
<> 144:ef7eb2e8f9f7 440 /* Disable the channel */
<> 144:ef7eb2e8f9f7 441 __HAL_DMA_DISABLE(hdma);
AnnaBridge 165:e614a9f1c9e2 442
AnnaBridge 165:e614a9f1c9e2 443 /* Clear all flags */
AnnaBridge 165:e614a9f1c9e2 444 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Change the DMA state */
<> 144:ef7eb2e8f9f7 447 hdma->State = HAL_DMA_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 448
<> 144:ef7eb2e8f9f7 449 /* Process Unlocked */
AnnaBridge 165:e614a9f1c9e2 450 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 451
AnnaBridge 165:e614a9f1c9e2 452 return status;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 154:37f96f9d4de2 456 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 154:37f96f9d4de2 457 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 458 * the configuration information for the specified DMA Channel.
<> 154:37f96f9d4de2 459 * @retval HAL status
<> 154:37f96f9d4de2 460 */
<> 154:37f96f9d4de2 461 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 154:37f96f9d4de2 462 {
<> 154:37f96f9d4de2 463 HAL_StatusTypeDef status = HAL_OK;
<> 154:37f96f9d4de2 464
<> 154:37f96f9d4de2 465 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 154:37f96f9d4de2 466 {
<> 154:37f96f9d4de2 467 /* no transfer ongoing */
<> 154:37f96f9d4de2 468 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
AnnaBridge 165:e614a9f1c9e2 469
<> 154:37f96f9d4de2 470 status = HAL_ERROR;
<> 154:37f96f9d4de2 471 }
<> 154:37f96f9d4de2 472 else
AnnaBridge 165:e614a9f1c9e2 473 {
<> 154:37f96f9d4de2 474 /* Disable DMA IT */
<> 154:37f96f9d4de2 475 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 154:37f96f9d4de2 476
<> 154:37f96f9d4de2 477 /* Disable the channel */
<> 154:37f96f9d4de2 478 __HAL_DMA_DISABLE(hdma);
<> 154:37f96f9d4de2 479
<> 154:37f96f9d4de2 480 /* Clear all flags */
<> 154:37f96f9d4de2 481 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
<> 154:37f96f9d4de2 482
<> 154:37f96f9d4de2 483 /* Change the DMA state */
<> 154:37f96f9d4de2 484 hdma->State = HAL_DMA_STATE_READY;
<> 154:37f96f9d4de2 485
<> 154:37f96f9d4de2 486 /* Process Unlocked */
<> 154:37f96f9d4de2 487 __HAL_UNLOCK(hdma);
<> 154:37f96f9d4de2 488
<> 154:37f96f9d4de2 489 /* Call User Abort callback */
<> 154:37f96f9d4de2 490 if(hdma->XferAbortCallback != NULL)
<> 154:37f96f9d4de2 491 {
<> 154:37f96f9d4de2 492 hdma->XferAbortCallback(hdma);
<> 154:37f96f9d4de2 493 }
<> 154:37f96f9d4de2 494 }
<> 154:37f96f9d4de2 495 return status;
<> 154:37f96f9d4de2 496 }
<> 154:37f96f9d4de2 497
<> 154:37f96f9d4de2 498 /**
<> 144:ef7eb2e8f9f7 499 * @brief Polling for transfer complete.
<> 144:ef7eb2e8f9f7 500 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 501 * the configuration information for the specified DMA Channel.
AnnaBridge 165:e614a9f1c9e2 502 * @param CompleteLevel: Specifies the DMA level complete.
<> 144:ef7eb2e8f9f7 503 * @param Timeout: Timeout duration.
<> 144:ef7eb2e8f9f7 504 * @retval HAL status
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 uint32_t temp;
AnnaBridge 165:e614a9f1c9e2 509 uint32_t tickstart = 0U;
AnnaBridge 165:e614a9f1c9e2 510
AnnaBridge 165:e614a9f1c9e2 511 if(HAL_DMA_STATE_BUSY != hdma->State)
AnnaBridge 165:e614a9f1c9e2 512 {
AnnaBridge 165:e614a9f1c9e2 513 /* no transfer ongoing */
AnnaBridge 165:e614a9f1c9e2 514 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
AnnaBridge 165:e614a9f1c9e2 515 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 516 return HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 517 }
AnnaBridge 165:e614a9f1c9e2 518
AnnaBridge 165:e614a9f1c9e2 519 /* Polling mode not supported in circular mode */
AnnaBridge 165:e614a9f1c9e2 520 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
AnnaBridge 165:e614a9f1c9e2 521 {
AnnaBridge 165:e614a9f1c9e2 522 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
AnnaBridge 165:e614a9f1c9e2 523 return HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 524 }
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Get the level transfer complete flag */
<> 144:ef7eb2e8f9f7 527 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 /* Transfer Complete flag */
<> 144:ef7eb2e8f9f7 530 temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 531 }
<> 144:ef7eb2e8f9f7 532 else
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 /* Half Transfer Complete flag */
<> 144:ef7eb2e8f9f7 535 temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Get tick */
<> 144:ef7eb2e8f9f7 539 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
AnnaBridge 165:e614a9f1c9e2 544 {
AnnaBridge 165:e614a9f1c9e2 545 /* When a DMA transfer error occurs */
AnnaBridge 165:e614a9f1c9e2 546 /* A hardware clear of its EN bits is performed */
AnnaBridge 165:e614a9f1c9e2 547 /* Clear all flags */
AnnaBridge 165:e614a9f1c9e2 548 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
AnnaBridge 165:e614a9f1c9e2 549
<> 144:ef7eb2e8f9f7 550 /* Update error code */
<> 144:ef7eb2e8f9f7 551 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /* Change the DMA state */
AnnaBridge 165:e614a9f1c9e2 554 hdma->State= HAL_DMA_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 555
<> 144:ef7eb2e8f9f7 556 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 557 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 558
<> 144:ef7eb2e8f9f7 559 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 562 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 563 {
AnnaBridge 165:e614a9f1c9e2 564 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 /* Update error code */
<> 144:ef7eb2e8f9f7 567 SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
AnnaBridge 165:e614a9f1c9e2 568
<> 144:ef7eb2e8f9f7 569 /* Change the DMA state */
AnnaBridge 165:e614a9f1c9e2 570 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 573 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 574
AnnaBridge 165:e614a9f1c9e2 575 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 583 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 584
AnnaBridge 165:e614a9f1c9e2 585 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 144:ef7eb2e8f9f7 586 all transfers are complete) */
<> 144:ef7eb2e8f9f7 587 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 else
AnnaBridge 165:e614a9f1c9e2 590 {
<> 144:ef7eb2e8f9f7 591 /* Clear the half transfer complete flag */
<> 144:ef7eb2e8f9f7 592 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Process unlocked */
<> 144:ef7eb2e8f9f7 596 __HAL_UNLOCK(hdma);
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 return HAL_OK;
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @brief Handles DMA interrupt request.
<> 144:ef7eb2e8f9f7 603 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 604 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 605 * @retval None
<> 144:ef7eb2e8f9f7 606 */
<> 144:ef7eb2e8f9f7 607 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 608 {
AnnaBridge 165:e614a9f1c9e2 609 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
AnnaBridge 165:e614a9f1c9e2 610 uint32_t source_it = hdma->Instance->CCR;
AnnaBridge 165:e614a9f1c9e2 611
AnnaBridge 165:e614a9f1c9e2 612 /* Half Transfer Complete Interrupt management ******************************/
AnnaBridge 165:e614a9f1c9e2 613 if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
<> 144:ef7eb2e8f9f7 614 {
AnnaBridge 165:e614a9f1c9e2 615 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
AnnaBridge 165:e614a9f1c9e2 616 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
AnnaBridge 165:e614a9f1c9e2 617 {
AnnaBridge 165:e614a9f1c9e2 618 /* Disable the half transfer interrupt */
AnnaBridge 165:e614a9f1c9e2 619 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
AnnaBridge 165:e614a9f1c9e2 620 }
AnnaBridge 165:e614a9f1c9e2 621 /* Clear the half transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 622 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
AnnaBridge 165:e614a9f1c9e2 623
AnnaBridge 165:e614a9f1c9e2 624 /* DMA peripheral state is not updated in Half Transfer */
AnnaBridge 165:e614a9f1c9e2 625 /* but in Transfer Complete case */
AnnaBridge 165:e614a9f1c9e2 626
AnnaBridge 165:e614a9f1c9e2 627 if(hdma->XferHalfCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 628 {
AnnaBridge 165:e614a9f1c9e2 629 /* Half transfer callback */
AnnaBridge 165:e614a9f1c9e2 630 hdma->XferHalfCpltCallback(hdma);
AnnaBridge 165:e614a9f1c9e2 631 }
AnnaBridge 165:e614a9f1c9e2 632 }
AnnaBridge 165:e614a9f1c9e2 633
AnnaBridge 165:e614a9f1c9e2 634 /* Transfer Complete Interrupt management ***********************************/
AnnaBridge 165:e614a9f1c9e2 635 else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
AnnaBridge 165:e614a9f1c9e2 636 {
AnnaBridge 165:e614a9f1c9e2 637 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
AnnaBridge 165:e614a9f1c9e2 638 {
AnnaBridge 165:e614a9f1c9e2 639 /* Disable the transfer complete and error interrupt */
AnnaBridge 165:e614a9f1c9e2 640 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
AnnaBridge 165:e614a9f1c9e2 641
<> 144:ef7eb2e8f9f7 642 /* Change the DMA state */
AnnaBridge 165:e614a9f1c9e2 643 hdma->State = HAL_DMA_STATE_READY;
AnnaBridge 165:e614a9f1c9e2 644 }
AnnaBridge 165:e614a9f1c9e2 645 /* Clear the transfer complete flag */
AnnaBridge 165:e614a9f1c9e2 646 __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
AnnaBridge 165:e614a9f1c9e2 647
AnnaBridge 165:e614a9f1c9e2 648 /* Process Unlocked */
AnnaBridge 165:e614a9f1c9e2 649 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 650
AnnaBridge 165:e614a9f1c9e2 651 if(hdma->XferCpltCallback != NULL)
AnnaBridge 165:e614a9f1c9e2 652 {
AnnaBridge 165:e614a9f1c9e2 653 /* Transfer complete callback */
AnnaBridge 165:e614a9f1c9e2 654 hdma->XferCpltCallback(hdma);
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
AnnaBridge 165:e614a9f1c9e2 658 /* Transfer Error Interrupt management **************************************/
AnnaBridge 165:e614a9f1c9e2 659 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 144:ef7eb2e8f9f7 660 {
AnnaBridge 165:e614a9f1c9e2 661 /* When a DMA transfer error occurs */
AnnaBridge 165:e614a9f1c9e2 662 /* A hardware clear of its EN bits is performed */
AnnaBridge 165:e614a9f1c9e2 663 /* Disable ALL DMA IT */
AnnaBridge 165:e614a9f1c9e2 664 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
AnnaBridge 165:e614a9f1c9e2 665
AnnaBridge 165:e614a9f1c9e2 666 /* Clear all flags */
AnnaBridge 165:e614a9f1c9e2 667 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
AnnaBridge 165:e614a9f1c9e2 668
AnnaBridge 165:e614a9f1c9e2 669 /* Update error code */
AnnaBridge 165:e614a9f1c9e2 670 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 144:ef7eb2e8f9f7 671
AnnaBridge 165:e614a9f1c9e2 672 /* Change the DMA state */
AnnaBridge 165:e614a9f1c9e2 673 hdma->State = HAL_DMA_STATE_READY;
<> 144:ef7eb2e8f9f7 674
AnnaBridge 165:e614a9f1c9e2 675 /* Process Unlocked */
AnnaBridge 165:e614a9f1c9e2 676 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 677
AnnaBridge 165:e614a9f1c9e2 678 if (hdma->XferErrorCallback != NULL)
AnnaBridge 165:e614a9f1c9e2 679 {
AnnaBridge 165:e614a9f1c9e2 680 /* Transfer error callback */
AnnaBridge 165:e614a9f1c9e2 681 hdma->XferErrorCallback(hdma);
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683 }
AnnaBridge 165:e614a9f1c9e2 684 return;
AnnaBridge 165:e614a9f1c9e2 685 }
AnnaBridge 165:e614a9f1c9e2 686
AnnaBridge 165:e614a9f1c9e2 687 /**
AnnaBridge 165:e614a9f1c9e2 688 * @brief Register callbacks
AnnaBridge 165:e614a9f1c9e2 689 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 690 * the configuration information for the specified DMA Channel.
AnnaBridge 165:e614a9f1c9e2 691 * @param CallbackID: User Callback identifer
AnnaBridge 165:e614a9f1c9e2 692 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
AnnaBridge 165:e614a9f1c9e2 693 * @param pCallback: pointer to private callbacsk function which has pointer to
AnnaBridge 165:e614a9f1c9e2 694 * a DMA_HandleTypeDef structure as parameter.
AnnaBridge 165:e614a9f1c9e2 695 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 696 */
AnnaBridge 165:e614a9f1c9e2 697 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
AnnaBridge 165:e614a9f1c9e2 698 {
AnnaBridge 165:e614a9f1c9e2 699 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 700
AnnaBridge 165:e614a9f1c9e2 701 /* Process locked */
AnnaBridge 165:e614a9f1c9e2 702 __HAL_LOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 703
AnnaBridge 165:e614a9f1c9e2 704 if(HAL_DMA_STATE_READY == hdma->State)
<> 144:ef7eb2e8f9f7 705 {
AnnaBridge 165:e614a9f1c9e2 706 switch (CallbackID)
<> 144:ef7eb2e8f9f7 707 {
AnnaBridge 165:e614a9f1c9e2 708 case HAL_DMA_XFER_CPLT_CB_ID:
AnnaBridge 165:e614a9f1c9e2 709 hdma->XferCpltCallback = pCallback;
AnnaBridge 165:e614a9f1c9e2 710 break;
AnnaBridge 165:e614a9f1c9e2 711
AnnaBridge 165:e614a9f1c9e2 712 case HAL_DMA_XFER_HALFCPLT_CB_ID:
AnnaBridge 165:e614a9f1c9e2 713 hdma->XferHalfCpltCallback = pCallback;
AnnaBridge 165:e614a9f1c9e2 714 break;
<> 144:ef7eb2e8f9f7 715
AnnaBridge 165:e614a9f1c9e2 716 case HAL_DMA_XFER_ERROR_CB_ID:
AnnaBridge 165:e614a9f1c9e2 717 hdma->XferErrorCallback = pCallback;
AnnaBridge 165:e614a9f1c9e2 718 break;
AnnaBridge 165:e614a9f1c9e2 719
AnnaBridge 165:e614a9f1c9e2 720 case HAL_DMA_XFER_ABORT_CB_ID:
AnnaBridge 165:e614a9f1c9e2 721 hdma->XferAbortCallback = pCallback;
AnnaBridge 165:e614a9f1c9e2 722 break;
AnnaBridge 165:e614a9f1c9e2 723
AnnaBridge 165:e614a9f1c9e2 724 default:
AnnaBridge 165:e614a9f1c9e2 725 status = HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 726 break;
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 }
AnnaBridge 165:e614a9f1c9e2 729 else
AnnaBridge 165:e614a9f1c9e2 730 {
AnnaBridge 165:e614a9f1c9e2 731 status = HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 732 }
AnnaBridge 165:e614a9f1c9e2 733
AnnaBridge 165:e614a9f1c9e2 734 /* Release Lock */
AnnaBridge 165:e614a9f1c9e2 735 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 736
AnnaBridge 165:e614a9f1c9e2 737 return status;
<> 144:ef7eb2e8f9f7 738 }
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /**
AnnaBridge 165:e614a9f1c9e2 741 * @brief UnRegister callbacks
AnnaBridge 165:e614a9f1c9e2 742 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 743 * the configuration information for the specified DMA Channel.
AnnaBridge 165:e614a9f1c9e2 744 * @param CallbackID: User Callback identifer
AnnaBridge 165:e614a9f1c9e2 745 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
AnnaBridge 165:e614a9f1c9e2 746 * @retval HAL status
AnnaBridge 165:e614a9f1c9e2 747 */
AnnaBridge 165:e614a9f1c9e2 748 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
AnnaBridge 165:e614a9f1c9e2 749 {
AnnaBridge 165:e614a9f1c9e2 750 HAL_StatusTypeDef status = HAL_OK;
AnnaBridge 165:e614a9f1c9e2 751
AnnaBridge 165:e614a9f1c9e2 752 /* Process locked */
AnnaBridge 165:e614a9f1c9e2 753 __HAL_LOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 754
AnnaBridge 165:e614a9f1c9e2 755 if(HAL_DMA_STATE_READY == hdma->State)
AnnaBridge 165:e614a9f1c9e2 756 {
AnnaBridge 165:e614a9f1c9e2 757 switch (CallbackID)
AnnaBridge 165:e614a9f1c9e2 758 {
AnnaBridge 165:e614a9f1c9e2 759 case HAL_DMA_XFER_CPLT_CB_ID:
AnnaBridge 165:e614a9f1c9e2 760 hdma->XferCpltCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 761 break;
AnnaBridge 165:e614a9f1c9e2 762
AnnaBridge 165:e614a9f1c9e2 763 case HAL_DMA_XFER_HALFCPLT_CB_ID:
AnnaBridge 165:e614a9f1c9e2 764 hdma->XferHalfCpltCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 765 break;
AnnaBridge 165:e614a9f1c9e2 766
AnnaBridge 165:e614a9f1c9e2 767 case HAL_DMA_XFER_ERROR_CB_ID:
AnnaBridge 165:e614a9f1c9e2 768 hdma->XferErrorCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 769 break;
AnnaBridge 165:e614a9f1c9e2 770
AnnaBridge 165:e614a9f1c9e2 771 case HAL_DMA_XFER_ABORT_CB_ID:
AnnaBridge 165:e614a9f1c9e2 772 hdma->XferAbortCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 773 break;
AnnaBridge 165:e614a9f1c9e2 774
AnnaBridge 165:e614a9f1c9e2 775 case HAL_DMA_XFER_ALL_CB_ID:
AnnaBridge 165:e614a9f1c9e2 776 hdma->XferCpltCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 777 hdma->XferHalfCpltCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 778 hdma->XferErrorCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 779 hdma->XferAbortCallback = NULL;
AnnaBridge 165:e614a9f1c9e2 780 break;
AnnaBridge 165:e614a9f1c9e2 781
AnnaBridge 165:e614a9f1c9e2 782 default:
AnnaBridge 165:e614a9f1c9e2 783 status = HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 784 break;
AnnaBridge 165:e614a9f1c9e2 785 }
AnnaBridge 165:e614a9f1c9e2 786 }
AnnaBridge 165:e614a9f1c9e2 787 else
AnnaBridge 165:e614a9f1c9e2 788 {
AnnaBridge 165:e614a9f1c9e2 789 status = HAL_ERROR;
AnnaBridge 165:e614a9f1c9e2 790 }
AnnaBridge 165:e614a9f1c9e2 791
AnnaBridge 165:e614a9f1c9e2 792 /* Release Lock */
AnnaBridge 165:e614a9f1c9e2 793 __HAL_UNLOCK(hdma);
AnnaBridge 165:e614a9f1c9e2 794
AnnaBridge 165:e614a9f1c9e2 795 return status;
AnnaBridge 165:e614a9f1c9e2 796 }
AnnaBridge 165:e614a9f1c9e2 797
AnnaBridge 165:e614a9f1c9e2 798 /**
<> 144:ef7eb2e8f9f7 799 * @}
<> 144:ef7eb2e8f9f7 800 */
<> 144:ef7eb2e8f9f7 801
AnnaBridge 165:e614a9f1c9e2 802 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
AnnaBridge 165:e614a9f1c9e2 803 * @brief Peripheral State and Errors functions
AnnaBridge 165:e614a9f1c9e2 804 *
AnnaBridge 165:e614a9f1c9e2 805 @verbatim
<> 144:ef7eb2e8f9f7 806 ===============================================================================
AnnaBridge 165:e614a9f1c9e2 807 ##### Peripheral State and Errors functions #####
AnnaBridge 165:e614a9f1c9e2 808 ===============================================================================
<> 144:ef7eb2e8f9f7 809 [..]
<> 144:ef7eb2e8f9f7 810 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 811 (+) Check the DMA state
<> 144:ef7eb2e8f9f7 812 (+) Get error code
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 @endverbatim
<> 144:ef7eb2e8f9f7 815 * @{
<> 144:ef7eb2e8f9f7 816 */
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /**
AnnaBridge 165:e614a9f1c9e2 819 * @brief Return the DMA hande state.
<> 144:ef7eb2e8f9f7 820 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 821 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 822 * @retval HAL state
<> 144:ef7eb2e8f9f7 823 */
<> 144:ef7eb2e8f9f7 824 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 825 {
AnnaBridge 165:e614a9f1c9e2 826 /* Return DMA handle state */
<> 144:ef7eb2e8f9f7 827 return hdma->State;
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /**
AnnaBridge 165:e614a9f1c9e2 831 * @brief Return the DMA error code.
<> 144:ef7eb2e8f9f7 832 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 833 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 834 * @retval DMA Error Code
<> 144:ef7eb2e8f9f7 835 */
<> 144:ef7eb2e8f9f7 836 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 return hdma->ErrorCode;
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /**
<> 144:ef7eb2e8f9f7 842 * @}
<> 144:ef7eb2e8f9f7 843 */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @}
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848
AnnaBridge 165:e614a9f1c9e2 849 /** @addtogroup DMA_Private_Functions
<> 144:ef7eb2e8f9f7 850 * @{
<> 144:ef7eb2e8f9f7 851 */
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /**
<> 144:ef7eb2e8f9f7 854 * @brief Sets the DMA Transfer parameter.
<> 144:ef7eb2e8f9f7 855 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
AnnaBridge 165:e614a9f1c9e2 856 * the configuration information for the specified DMA Channel.
<> 144:ef7eb2e8f9f7 857 * @param SrcAddress: The source memory Buffer address
<> 144:ef7eb2e8f9f7 858 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 859 * @param DataLength: The length of data to be transferred from source to destination
<> 144:ef7eb2e8f9f7 860 * @retval HAL status
<> 144:ef7eb2e8f9f7 861 */
<> 144:ef7eb2e8f9f7 862 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 144:ef7eb2e8f9f7 863 {
AnnaBridge 165:e614a9f1c9e2 864 /* Clear all flags */
AnnaBridge 165:e614a9f1c9e2 865 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
AnnaBridge 165:e614a9f1c9e2 866
<> 144:ef7eb2e8f9f7 867 /* Configure DMA Channel data length */
<> 144:ef7eb2e8f9f7 868 hdma->Instance->CNDTR = DataLength;
AnnaBridge 165:e614a9f1c9e2 869
AnnaBridge 187:0387e8f68319 870 /* Memory to Peripheral */
<> 144:ef7eb2e8f9f7 871 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 874 hdma->Instance->CPAR = DstAddress;
AnnaBridge 165:e614a9f1c9e2 875
<> 144:ef7eb2e8f9f7 876 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 877 hdma->Instance->CMAR = SrcAddress;
<> 144:ef7eb2e8f9f7 878 }
AnnaBridge 187:0387e8f68319 879 /* Peripheral to Memory */
<> 144:ef7eb2e8f9f7 880 else
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 /* Configure DMA Channel source address */
<> 144:ef7eb2e8f9f7 883 hdma->Instance->CPAR = SrcAddress;
AnnaBridge 165:e614a9f1c9e2 884
<> 144:ef7eb2e8f9f7 885 /* Configure DMA Channel destination address */
<> 144:ef7eb2e8f9f7 886 hdma->Instance->CMAR = DstAddress;
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /**
<> 144:ef7eb2e8f9f7 891 * @}
<> 144:ef7eb2e8f9f7 892 */
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 #endif /* HAL_DMA_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 895 /**
<> 144:ef7eb2e8f9f7 896 * @}
<> 144:ef7eb2e8f9f7 897 */
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /**
<> 144:ef7eb2e8f9f7 900 * @}
<> 144:ef7eb2e8f9f7 901 */
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/