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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_dac.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the Digital to Analog Converter (DAC) peripheral:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 9 * + IO operation functions
<> 144:ef7eb2e8f9f7 10 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### DAC Peripheral features #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 *** DAC Channels ***
<> 144:ef7eb2e8f9f7 20 ====================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 The device integrates two 12-bit Digital Analog Converters that can
<> 144:ef7eb2e8f9f7 23 be used independently or simultaneously (dual mode):
<> 144:ef7eb2e8f9f7 24 (#) DAC channel1 with DAC_OUT1 (PA4) as output
<> 144:ef7eb2e8f9f7 25 (#) DAC channel2 with DAC_OUT2 (PA5) as output
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 *** DAC Triggers ***
<> 144:ef7eb2e8f9f7 28 ====================
<> 144:ef7eb2e8f9f7 29 [..]
<> 144:ef7eb2e8f9f7 30 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
<> 144:ef7eb2e8f9f7 31 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
<> 144:ef7eb2e8f9f7 32 [..]
<> 144:ef7eb2e8f9f7 33 Digital to Analog conversion can be triggered by:
<> 144:ef7eb2e8f9f7 34 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
<> 144:ef7eb2e8f9f7 35 The used pin (GPIOx_PIN_9) must be configured in input mode.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7
<> 144:ef7eb2e8f9f7 38 For STM32F10x connectivity line devices and STM32F100x devices: TIM3
<> 144:ef7eb2e8f9f7 39 For STM32F10x high-density and XL-density devices: TIM8
<> 144:ef7eb2e8f9f7 40 For STM32F100x high-density value line devices: TIM15 as
<> 144:ef7eb2e8f9f7 41 replacement of TIM5.
<> 144:ef7eb2e8f9f7 42 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Software using DAC_TRIGGER_SOFTWARE
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 *** DAC Buffer mode feature ***
<> 144:ef7eb2e8f9f7 47 ===============================
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 Each DAC channel integrates an output buffer that can be used to
<> 144:ef7eb2e8f9f7 50 reduce the output impedance, and to drive external loads directly
<> 144:ef7eb2e8f9f7 51 without having to add an external operational amplifier.
<> 144:ef7eb2e8f9f7 52 To enable, the output buffer use
<> 144:ef7eb2e8f9f7 53 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
<> 144:ef7eb2e8f9f7 54 [..]
<> 144:ef7eb2e8f9f7 55 (@) Refer to the device datasheet for more details about output
<> 144:ef7eb2e8f9f7 56 impedance value with and without output buffer.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 *** DAC connect feature ***
<> 144:ef7eb2e8f9f7 59 ===============================
<> 144:ef7eb2e8f9f7 60 [..]
<> 144:ef7eb2e8f9f7 61 Each DAC channel can be connected internally.
<> 144:ef7eb2e8f9f7 62 To connect, use
<> 144:ef7eb2e8f9f7 63 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 *** GPIO configurations guidelines ***
<> 144:ef7eb2e8f9f7 66 =====================
<> 144:ef7eb2e8f9f7 67 [..]
<> 144:ef7eb2e8f9f7 68 When a DAC channel is used (ex channel1 on PA4) and the other is not
<> 144:ef7eb2e8f9f7 69 (ex channel1 on PA5 is configured in Analog and disabled).
<> 144:ef7eb2e8f9f7 70 Channel1 may disturb channel2 as coupling effect.
<> 144:ef7eb2e8f9f7 71 Note that there is no coupling on channel2 as soon as channel2 is turned on.
<> 144:ef7eb2e8f9f7 72 Coupling on adjacent channel could be avoided as follows:
<> 144:ef7eb2e8f9f7 73 when unused PA5 is configured as INPUT PULL-UP or DOWN.
<> 144:ef7eb2e8f9f7 74 PA5 is configured in ANALOG just before it is turned on.
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 *** DAC wave generation feature ***
<> 144:ef7eb2e8f9f7 77 ===================================
<> 144:ef7eb2e8f9f7 78 [..]
<> 144:ef7eb2e8f9f7 79 Both DAC channels can be used to generate
<> 144:ef7eb2e8f9f7 80 (#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
<> 144:ef7eb2e8f9f7 81 (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 *** DAC data format ***
<> 144:ef7eb2e8f9f7 84 =======================
<> 144:ef7eb2e8f9f7 85 [..]
<> 144:ef7eb2e8f9f7 86 The DAC data format can be:
<> 144:ef7eb2e8f9f7 87 (#) 8-bit right alignment using DAC_ALIGN_8B_R
<> 144:ef7eb2e8f9f7 88 (#) 12-bit left alignment using DAC_ALIGN_12B_L
<> 144:ef7eb2e8f9f7 89 (#) 12-bit right alignment using DAC_ALIGN_12B_R
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 *** DAC data value to voltage correspondance ***
<> 144:ef7eb2e8f9f7 92 ================================================
<> 144:ef7eb2e8f9f7 93 [..]
<> 144:ef7eb2e8f9f7 94 The analog output voltage on each DAC channel pin is determined
<> 144:ef7eb2e8f9f7 95 by the following equation:
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 DAC_OUTx = VREF+ * DOR / 4095
<> 144:ef7eb2e8f9f7 98 (+) with DOR is the Data Output Register
<> 144:ef7eb2e8f9f7 99 [..]
<> 144:ef7eb2e8f9f7 100 VEF+ is the input voltage reference (refer to the device datasheet)
<> 144:ef7eb2e8f9f7 101 [..]
<> 144:ef7eb2e8f9f7 102 e.g. To set DAC_OUT1 to 0.7V, use
<> 144:ef7eb2e8f9f7 103 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 *** DMA requests ***
<> 144:ef7eb2e8f9f7 106 =====================
<> 144:ef7eb2e8f9f7 107 [..]
<> 144:ef7eb2e8f9f7 108 A DMA1 request can be generated when an external trigger (but not
<> 144:ef7eb2e8f9f7 109 a software trigger) occurs if DMA1 requests are enabled using
<> 144:ef7eb2e8f9f7 110 HAL_DAC_Start_DMA()
<> 144:ef7eb2e8f9f7 111 [..]
<> 144:ef7eb2e8f9f7 112 DMA requests are mapped as following:
<> 144:ef7eb2e8f9f7 113 (#) DAC channel1 :
<> 144:ef7eb2e8f9f7 114 For STM32F100x low-density, medium-density, high-density with DAC
<> 144:ef7eb2e8f9f7 115 DMA remap:
<> 144:ef7eb2e8f9f7 116 mapped on DMA1 channel3 which must be
<> 144:ef7eb2e8f9f7 117 already configured
<> 144:ef7eb2e8f9f7 118 For STM32F100x high-density without DAC DMA remap and other
<> 144:ef7eb2e8f9f7 119 STM32F1 devices:
<> 144:ef7eb2e8f9f7 120 mapped on DMA2 channel3 which must be
<> 144:ef7eb2e8f9f7 121 already configured
<> 144:ef7eb2e8f9f7 122 (#) DAC channel2 :
<> 144:ef7eb2e8f9f7 123 For STM32F100x low-density, medium-density, high-density with DAC
<> 144:ef7eb2e8f9f7 124 DMA remap:
<> 144:ef7eb2e8f9f7 125 mapped on DMA1 channel4 which must be
<> 144:ef7eb2e8f9f7 126 already configured
<> 144:ef7eb2e8f9f7 127 For STM32F100x high-density without DAC DMA remap and other
<> 144:ef7eb2e8f9f7 128 STM32F1 devices:
<> 144:ef7eb2e8f9f7 129 mapped on DMA2 channel4 which must be
<> 144:ef7eb2e8f9f7 130 already configured
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 133 ==============================================================================
<> 144:ef7eb2e8f9f7 134 [..]
<> 144:ef7eb2e8f9f7 135 (+) DAC APB clock must be enabled to get write access to DAC
<> 144:ef7eb2e8f9f7 136 registers using HAL_DAC_Init()
<> 144:ef7eb2e8f9f7 137 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
<> 144:ef7eb2e8f9f7 138 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
<> 144:ef7eb2e8f9f7 139 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 142 =================================
<> 144:ef7eb2e8f9f7 143 [..]
<> 144:ef7eb2e8f9f7 144 (+) Start the DAC peripheral using HAL_DAC_Start()
<> 144:ef7eb2e8f9f7 145 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
<> 144:ef7eb2e8f9f7 146 (+) Stop the DAC peripheral using HAL_DAC_Stop()
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 149 ==============================
<> 144:ef7eb2e8f9f7 150 [..]
<> 144:ef7eb2e8f9f7 151 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
<> 144:ef7eb2e8f9f7 152 of data to be transferred at each end of conversion
<> 144:ef7eb2e8f9f7 153 (+) At the middle of data transfer HAL_DACEx_ConvHalfCpltCallbackCh1()or HAL_DACEx_ConvHalfCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 154 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 155 HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
<> 144:ef7eb2e8f9f7 156 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
<> 144:ef7eb2e8f9f7 157 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 158 HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
<> 144:ef7eb2e8f9f7 159 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() or HAL_DACEx_ErrorCallbackCh2() function is executed and user can
<> 144:ef7eb2e8f9f7 160 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 or HAL_DACEx_ErrorCallbackCh2
<> 144:ef7eb2e8f9f7 161 (+) For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 162 In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
<> 144:ef7eb2e8f9f7 163 HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DACEx_DMAUnderrunCallbackCh2()
<> 144:ef7eb2e8f9f7 164 function is executed and user can add his own code by customization of function pointer
<> 144:ef7eb2e8f9f7 165 HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DACEx_DMAUnderrunCallbackCh2
<> 144:ef7eb2e8f9f7 166 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
<> 144:ef7eb2e8f9f7 167 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 *** DAC HAL driver macros list ***
<> 144:ef7eb2e8f9f7 170 =============================================
<> 144:ef7eb2e8f9f7 171 [..]
<> 144:ef7eb2e8f9f7 172 Below the list of most used macros in DAC HAL driver.
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 175 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 176 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 177 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status (For STM32F100x devices with specific feature: DMA underrun)
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 [..]
<> 144:ef7eb2e8f9f7 180 (@) You can refer to the DAC HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 @endverbatim
<> 144:ef7eb2e8f9f7 183 ******************************************************************************
<> 144:ef7eb2e8f9f7 184 * @attention
<> 144:ef7eb2e8f9f7 185 *
<> 144:ef7eb2e8f9f7 186 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 187 *
<> 144:ef7eb2e8f9f7 188 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 189 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 190 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 191 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 192 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 193 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 194 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 195 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 196 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 197 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 198 *
<> 144:ef7eb2e8f9f7 199 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 200 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 201 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 202 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 203 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 204 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 205 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 206 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 207 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 208 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 209 *
<> 144:ef7eb2e8f9f7 210 ******************************************************************************
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 215 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 218 * @{
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup DAC DAC
<> 144:ef7eb2e8f9f7 222 * @brief DAC driver modules
<> 144:ef7eb2e8f9f7 223 * @{
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 227 #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 230 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 231 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 232 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 233 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 234 /* Exported functions -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /** @defgroup DAC_Exported_Functions DAC Exported Functions
<> 144:ef7eb2e8f9f7 237 * @{
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 241 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 242 *
<> 144:ef7eb2e8f9f7 243 @verbatim
<> 144:ef7eb2e8f9f7 244 ==============================================================================
<> 144:ef7eb2e8f9f7 245 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 246 ==============================================================================
<> 144:ef7eb2e8f9f7 247 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 248 (+) Initialize and configure the DAC.
<> 144:ef7eb2e8f9f7 249 (+) De-initialize the DAC.
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 @endverbatim
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @brief Initializes the DAC peripheral according to the specified parameters
<> 144:ef7eb2e8f9f7 257 * in the DAC_InitStruct.
<> 144:ef7eb2e8f9f7 258 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 259 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 260 * @retval HAL status
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 265 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269 /* Check the parameters */
<> 144:ef7eb2e8f9f7 270 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 if(hdac->State == HAL_DAC_STATE_RESET)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 275 hdac->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 278 HAL_DAC_MspInit(hdac);
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 282 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 285 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Initialize the DAC state*/
<> 144:ef7eb2e8f9f7 288 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Return function status */
<> 144:ef7eb2e8f9f7 291 return HAL_OK;
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Deinitializes the DAC peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 296 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 297 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 298 * @retval HAL status
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 /* Check DAC handle */
<> 144:ef7eb2e8f9f7 303 if(hdac == NULL)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 306 }
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Check the parameters */
<> 144:ef7eb2e8f9f7 309 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Change DAC state */
<> 144:ef7eb2e8f9f7 312 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 315 HAL_DAC_MspDeInit(hdac);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Set DAC error code to none */
<> 144:ef7eb2e8f9f7 318 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Change DAC state */
<> 144:ef7eb2e8f9f7 321 hdac->State = HAL_DAC_STATE_RESET;
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Release Lock */
<> 144:ef7eb2e8f9f7 324 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Return function status */
<> 144:ef7eb2e8f9f7 327 return HAL_OK;
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /**
<> 144:ef7eb2e8f9f7 331 * @brief Initializes the DAC MSP.
<> 144:ef7eb2e8f9f7 332 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 333 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 334 * @retval None
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 339 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 340 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 341 the HAL_DAC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 342 */
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @brief DeInitializes the DAC MSP.
<> 144:ef7eb2e8f9f7 347 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 348 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 349 * @retval None
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 354 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 355 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 356 the HAL_DAC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @}
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 365 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 366 *
<> 144:ef7eb2e8f9f7 367 @verbatim
<> 144:ef7eb2e8f9f7 368 ==============================================================================
<> 144:ef7eb2e8f9f7 369 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 370 ==============================================================================
<> 144:ef7eb2e8f9f7 371 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 372 (+) Start conversion.
<> 144:ef7eb2e8f9f7 373 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 374 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 375 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 376 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 @endverbatim
<> 144:ef7eb2e8f9f7 379 * @{
<> 144:ef7eb2e8f9f7 380 */
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 384 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 385 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 386 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 387 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 388 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 389 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 390 * @retval HAL status
<> 144:ef7eb2e8f9f7 391 */
<> 144:ef7eb2e8f9f7 392 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 /* Check the parameters */
<> 144:ef7eb2e8f9f7 395 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Process locked */
<> 144:ef7eb2e8f9f7 398 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Change DAC state */
<> 144:ef7eb2e8f9f7 401 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 404 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 407 {
<> 144:ef7eb2e8f9f7 408 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 409 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 412 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 else
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 418 if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 421 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Change DAC state */
<> 144:ef7eb2e8f9f7 426 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Process unlocked */
<> 144:ef7eb2e8f9f7 429 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Return function status */
<> 144:ef7eb2e8f9f7 432 return HAL_OK;
<> 144:ef7eb2e8f9f7 433 }
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 437 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 438 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 439 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 440 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 441 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 442 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 443 * @retval HAL status
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 /* Check the parameters */
<> 144:ef7eb2e8f9f7 448 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 451 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* Change DAC state */
<> 144:ef7eb2e8f9f7 454 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Return function status */
<> 144:ef7eb2e8f9f7 457 return HAL_OK;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 462 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 463 * On these devices, this function enables the interruption of DMA
<> 144:ef7eb2e8f9f7 464 * underrun.
<> 144:ef7eb2e8f9f7 465 * (refer to redefinition of this function in DAC extended file)
<> 144:ef7eb2e8f9f7 466 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 467 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 468 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 469 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 470 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 471 * @arg DAC_CHANNEL_2: DAC Channel2 selected
AnnaBridge 165:e614a9f1c9e2 472 * @param pData: The Source memory Buffer address.
<> 144:ef7eb2e8f9f7 473 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 474 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 475 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 476 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 477 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 478 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 479 * @retval HAL status
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 482 {
AnnaBridge 165:e614a9f1c9e2 483 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /* Check the parameters */
<> 144:ef7eb2e8f9f7 486 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 487 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Process locked */
<> 144:ef7eb2e8f9f7 490 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Change DAC state */
<> 144:ef7eb2e8f9f7 493 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 498 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 501 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 504 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 507 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 510 switch(Alignment)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 513 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 514 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 515 break;
<> 144:ef7eb2e8f9f7 516 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 517 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 518 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 519 break;
<> 144:ef7eb2e8f9f7 520 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 521 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 522 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 523 break;
<> 144:ef7eb2e8f9f7 524 default:
<> 144:ef7eb2e8f9f7 525 break;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527 }
<> 144:ef7eb2e8f9f7 528 else
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 531 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 534 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 537 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 540 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 543 switch(Alignment)
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 546 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 547 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 548 break;
<> 144:ef7eb2e8f9f7 549 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 550 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 551 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 552 break;
<> 144:ef7eb2e8f9f7 553 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 554 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 555 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 556 break;
<> 144:ef7eb2e8f9f7 557 default:
<> 144:ef7eb2e8f9f7 558 break;
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 563 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 566 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 else
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 571 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 575 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 578 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Return function status */
<> 144:ef7eb2e8f9f7 581 return HAL_OK;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /**
<> 144:ef7eb2e8f9f7 585 * @brief Disables DAC and stop conversion of channel.
<> 144:ef7eb2e8f9f7 586 * Note: For STM32F100x devices with specific feature: DMA underrun.
<> 144:ef7eb2e8f9f7 587 * On these devices, this function disables the interruption of DMA
<> 144:ef7eb2e8f9f7 588 * underrun.
<> 144:ef7eb2e8f9f7 589 * (refer to redefinition of this function in DAC extended file)
<> 144:ef7eb2e8f9f7 590 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 591 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 592 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 593 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 594 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 595 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 596 * @retval HAL status
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 __weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Check the parameters */
<> 144:ef7eb2e8f9f7 603 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Disable the selected DAC channel DMA request */
<> 144:ef7eb2e8f9f7 606 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1 << Channel);
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Disable the Peripharal */
<> 144:ef7eb2e8f9f7 609 __HAL_DAC_DISABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Disable the DMA Channel */
<> 144:ef7eb2e8f9f7 612 /* Channel1 is used */
<> 144:ef7eb2e8f9f7 613 if (Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 614 {
<> 144:ef7eb2e8f9f7 615 status = HAL_DMA_Abort(hdac->DMA_Handle1);
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617 else /* Channel2 is used for */
<> 144:ef7eb2e8f9f7 618 {
<> 144:ef7eb2e8f9f7 619 status = HAL_DMA_Abort(hdac->DMA_Handle2);
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Check if DMA Channel effectively disabled */
<> 144:ef7eb2e8f9f7 623 if (status != HAL_OK)
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 626 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 627 }
<> 144:ef7eb2e8f9f7 628 else
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 /* Change DAC state */
<> 144:ef7eb2e8f9f7 631 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /* Return function status */
<> 144:ef7eb2e8f9f7 635 return status;
<> 144:ef7eb2e8f9f7 636 }
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 640 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 641 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 642 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 643 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 644 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 645 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 646 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 647 */
<> 144:ef7eb2e8f9f7 648 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Check the parameters */
<> 144:ef7eb2e8f9f7 651 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 654 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658 else
<> 144:ef7eb2e8f9f7 659 {
<> 144:ef7eb2e8f9f7 660 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /**
<> 144:ef7eb2e8f9f7 665 * @brief Conversion complete callback in non blocking mode for Channel1
<> 144:ef7eb2e8f9f7 666 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 667 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 668 * @retval None
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 673 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 674 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 675 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 676 */
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
<> 144:ef7eb2e8f9f7 681 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 682 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 683 * @retval None
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 688 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 689 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 690 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 691 */
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @brief Error DAC callback for Channel1.
<> 144:ef7eb2e8f9f7 696 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 697 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 698 * @retval None
<> 144:ef7eb2e8f9f7 699 */
<> 144:ef7eb2e8f9f7 700 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 703 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 704 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 705 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
<> 144:ef7eb2e8f9f7 706 */
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /**
<> 144:ef7eb2e8f9f7 710 * @}
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 714 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 715 *
<> 144:ef7eb2e8f9f7 716 @verbatim
<> 144:ef7eb2e8f9f7 717 ==============================================================================
<> 144:ef7eb2e8f9f7 718 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 719 ==============================================================================
<> 144:ef7eb2e8f9f7 720 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 721 (+) Configure channels.
<> 144:ef7eb2e8f9f7 722 (+) Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 @endverbatim
<> 144:ef7eb2e8f9f7 725 * @{
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @brief Configures the selected DAC channel.
<> 144:ef7eb2e8f9f7 730 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 731 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 732 * @param sConfig: DAC configuration structure.
<> 144:ef7eb2e8f9f7 733 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 734 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 735 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 736 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 737 * @retval HAL status
<> 144:ef7eb2e8f9f7 738 */
<> 144:ef7eb2e8f9f7 739 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 740 {
AnnaBridge 165:e614a9f1c9e2 741 uint32_t tmpreg1 = 0U;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Check the DAC parameters */
<> 144:ef7eb2e8f9f7 744 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 745 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 746 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Process locked */
<> 144:ef7eb2e8f9f7 749 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Change DAC state */
<> 144:ef7eb2e8f9f7 752 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Configure for the selected DAC channel: buffer output, trigger */
<> 144:ef7eb2e8f9f7 755 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 756 /* Set BOFFx bit according to DAC_OutputBuffer value */
<> 144:ef7eb2e8f9f7 757 SET_BIT(tmpreg1, (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 760 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 761 MODIFY_REG(hdac->Instance->CR,
<> 144:ef7eb2e8f9f7 762 ((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel,
<> 144:ef7eb2e8f9f7 763 tmpreg1 << Channel);
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Disable wave generation */
<> 144:ef7eb2e8f9f7 766 hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Change DAC state */
<> 144:ef7eb2e8f9f7 769 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Process unlocked */
<> 144:ef7eb2e8f9f7 772 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Return function status */
<> 144:ef7eb2e8f9f7 775 return HAL_OK;
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /**
<> 144:ef7eb2e8f9f7 779 * @brief Set the specified data holding register value for DAC channel.
<> 144:ef7eb2e8f9f7 780 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 781 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 782 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 783 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 784 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 785 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 786 * @param Alignment: Specifies the data alignment.
<> 144:ef7eb2e8f9f7 787 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 788 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 789 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 790 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 791 * @param Data: Data to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 792 * @retval HAL status
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
<> 144:ef7eb2e8f9f7 795 {
AnnaBridge 165:e614a9f1c9e2 796 __IO uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Check the parameters */
<> 144:ef7eb2e8f9f7 799 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 800 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 801 assert_param(IS_DAC_DATA(Data));
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 804 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 805 {
<> 144:ef7eb2e8f9f7 806 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808 else
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Set the DAC channel selected data holding register */
<> 144:ef7eb2e8f9f7 814 *(__IO uint32_t *) tmp = Data;
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Return function status */
<> 144:ef7eb2e8f9f7 817 return HAL_OK;
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /**
<> 144:ef7eb2e8f9f7 821 * @}
<> 144:ef7eb2e8f9f7 822 */
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 825 * @brief Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 826 *
<> 144:ef7eb2e8f9f7 827 @verbatim
<> 144:ef7eb2e8f9f7 828 ==============================================================================
<> 144:ef7eb2e8f9f7 829 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 830 ==============================================================================
<> 144:ef7eb2e8f9f7 831 [..]
<> 144:ef7eb2e8f9f7 832 This subsection provides functions allowing to
<> 144:ef7eb2e8f9f7 833 (+) Check the DAC state.
<> 144:ef7eb2e8f9f7 834 (+) Check the DAC Errors.
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 @endverbatim
<> 144:ef7eb2e8f9f7 837 * @{
<> 144:ef7eb2e8f9f7 838 */
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /**
<> 144:ef7eb2e8f9f7 841 * @brief return the DAC state
<> 144:ef7eb2e8f9f7 842 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 843 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 844 * @retval HAL state
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 /* Return DAC state */
<> 144:ef7eb2e8f9f7 849 return hdac->State;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /**
<> 144:ef7eb2e8f9f7 854 * @brief Return the DAC error code
<> 144:ef7eb2e8f9f7 855 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 856 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 857 * @retval DAC Error Code
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 return hdac->ErrorCode;
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /**
<> 144:ef7eb2e8f9f7 865 * @}
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /**
<> 144:ef7eb2e8f9f7 869 * @}
<> 144:ef7eb2e8f9f7 870 */
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 873 * @{
<> 144:ef7eb2e8f9f7 874 */
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /**
<> 144:ef7eb2e8f9f7 877 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 878 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 879 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 880 * @retval None
<> 144:ef7eb2e8f9f7 881 */
<> 144:ef7eb2e8f9f7 882 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 889 }
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /**
<> 144:ef7eb2e8f9f7 892 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 893 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 894 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 895 * @retval None
<> 144:ef7eb2e8f9f7 896 */
<> 144:ef7eb2e8f9f7 897 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 900 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 901 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /**
<> 144:ef7eb2e8f9f7 905 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 906 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 907 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 908 * @retval None
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 911 {
<> 144:ef7eb2e8f9f7 912 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 915 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /**
<> 144:ef7eb2e8f9f7 923 * @}
<> 144:ef7eb2e8f9f7 924 */
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 #endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 927 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /**
<> 144:ef7eb2e8f9f7 930 * @}
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /**
<> 144:ef7eb2e8f9f7 934 * @}
<> 144:ef7eb2e8f9f7 935 */
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/