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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief CORTEX HAL module driver.
AnnaBridge 165:e614a9f1c9e2 6 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 7 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 8 * + Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 9 * + Peripheral Control functions
AnnaBridge 165:e614a9f1c9e2 10 *
AnnaBridge 165:e614a9f1c9e2 11 @verbatim
<> 144:ef7eb2e8f9f7 12 ==============================================================================
<> 144:ef7eb2e8f9f7 13 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15
<> 144:ef7eb2e8f9f7 16 [..]
AnnaBridge 165:e614a9f1c9e2 17 *** How to configure Interrupts using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 18 ===========================================================
<> 144:ef7eb2e8f9f7 19 [..]
AnnaBridge 165:e614a9f1c9e2 20 This section provides functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 21 The Cortex-M3 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
<> 144:ef7eb2e8f9f7 24 function according to the following table.
AnnaBridge 165:e614a9f1c9e2 25 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
AnnaBridge 165:e614a9f1c9e2 26 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
AnnaBridge 165:e614a9f1c9e2 27 (#) please refer to programming manual for details in how to configure priority.
<> 144:ef7eb2e8f9f7 28
AnnaBridge 165:e614a9f1c9e2 29 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
<> 144:ef7eb2e8f9f7 30 The pending IRQ priority will be managed only by the sub priority.
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 -@- IRQ priority order (sorted by highest to lowest priority):
AnnaBridge 165:e614a9f1c9e2 33 (+@) Lowest preemption priority
<> 144:ef7eb2e8f9f7 34 (+@) Lowest sub priority
<> 144:ef7eb2e8f9f7 35 (+@) Lowest hardware priority (IRQ number)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 [..]
AnnaBridge 165:e614a9f1c9e2 38 *** How to configure Systick using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 39 ========================================================
<> 144:ef7eb2e8f9f7 40 [..]
AnnaBridge 165:e614a9f1c9e2 41 Setup SysTick Timer for time base.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 44 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 45 (++) Configures the SysTick Reload register with value passed as function parameter.
AnnaBridge 165:e614a9f1c9e2 46 (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
<> 144:ef7eb2e8f9f7 47 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 48 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 49 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 50 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 51
AnnaBridge 165:e614a9f1c9e2 52 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
AnnaBridge 165:e614a9f1c9e2 53 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
AnnaBridge 165:e614a9f1c9e2 54 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
AnnaBridge 165:e614a9f1c9e2 55 inside the stm32f1xx_hal_cortex.h file.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 58 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 59 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 64 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 65 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69 * @attention
<> 144:ef7eb2e8f9f7 70 *
AnnaBridge 165:e614a9f1c9e2 71 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 74 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 75 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 76 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 79 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 81 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 82 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup CORTEX CORTEX
<> 144:ef7eb2e8f9f7 106 * @brief CORTEX HAL module driver
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 111
AnnaBridge 165:e614a9f1c9e2 112 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 113 /* Private variables ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 114 /* Private constants ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 115 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private functions ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 117 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 125 * @brief Initialization and Configuration functions
AnnaBridge 165:e614a9f1c9e2 126 *
<> 144:ef7eb2e8f9f7 127 @verbatim
<> 144:ef7eb2e8f9f7 128 ==============================================================================
<> 144:ef7eb2e8f9f7 129 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 [..]
AnnaBridge 165:e614a9f1c9e2 132 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 133 Systick functionalities
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 @endverbatim
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /**
AnnaBridge 165:e614a9f1c9e2 141 * @brief Sets the priority grouping field (preemption priority and subpriority)
<> 144:ef7eb2e8f9f7 142 * using the required unlock sequence.
<> 144:ef7eb2e8f9f7 143 * @param PriorityGroup: The priority grouping bits length.
<> 144:ef7eb2e8f9f7 144 * This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 145 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
<> 144:ef7eb2e8f9f7 146 * 4 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 147 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
<> 144:ef7eb2e8f9f7 148 * 3 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 149 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
<> 144:ef7eb2e8f9f7 150 * 2 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 151 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
<> 144:ef7eb2e8f9f7 152 * 1 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 153 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
<> 144:ef7eb2e8f9f7 154 * 0 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 155 * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
<> 144:ef7eb2e8f9f7 156 * The pending IRQ priority will be managed only by the subpriority.
<> 144:ef7eb2e8f9f7 157 * @retval None
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 /* Check the parameters */
<> 144:ef7eb2e8f9f7 162 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
<> 144:ef7eb2e8f9f7 165 NVIC_SetPriorityGrouping(PriorityGroup);
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Sets the priority of an interrupt.
AnnaBridge 165:e614a9f1c9e2 170 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 171 * This parameter can be an enumerator of IRQn_Type enumeration
AnnaBridge 165:e614a9f1c9e2 172 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
AnnaBridge 165:e614a9f1c9e2 173 * @param PreemptPriority: The preemption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 174 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 175 * A lower priority value indicates a higher priority
<> 144:ef7eb2e8f9f7 176 * @param SubPriority: the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 177 * This parameter can be a value between 0 and 15
<> 144:ef7eb2e8f9f7 178 * A lower priority value indicates a higher priority.
<> 144:ef7eb2e8f9f7 179 * @retval None
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 165:e614a9f1c9e2 182 {
AnnaBridge 165:e614a9f1c9e2 183 uint32_t prioritygroup = 0x00U;
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Check the parameters */
<> 144:ef7eb2e8f9f7 186 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
<> 144:ef7eb2e8f9f7 187 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 prioritygroup = NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 196 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 197 * function should be called before.
AnnaBridge 165:e614a9f1c9e2 198 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 199 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 200 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 201 * @retval None
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 /* Check the parameters */
<> 144:ef7eb2e8f9f7 206 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 209 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 165:e614a9f1c9e2 214 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 215 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 216 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 217 * @retval None
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Check the parameters */
<> 144:ef7eb2e8f9f7 222 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 225 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /**
<> 144:ef7eb2e8f9f7 229 * @brief Initiates a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 230 * @retval None
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 /* System Reset */
<> 144:ef7eb2e8f9f7 235 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 144:ef7eb2e8f9f7 240 * Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 241 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 242 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 243 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
AnnaBridge 165:e614a9f1c9e2 254 * @brief Cortex control functions
AnnaBridge 165:e614a9f1c9e2 255 *
<> 144:ef7eb2e8f9f7 256 @verbatim
<> 144:ef7eb2e8f9f7 257 ==============================================================================
<> 144:ef7eb2e8f9f7 258 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 259 ==============================================================================
<> 144:ef7eb2e8f9f7 260 [..]
<> 144:ef7eb2e8f9f7 261 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 262 (NVIC, SYSTICK, MPU) functionalities.
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 @endverbatim
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
AnnaBridge 165:e614a9f1c9e2 269 #if (__MPU_PRESENT == 1U)
AnnaBridge 165:e614a9f1c9e2 270 /**
AnnaBridge 165:e614a9f1c9e2 271 * @brief Disables the MPU
AnnaBridge 165:e614a9f1c9e2 272 * @retval None
AnnaBridge 165:e614a9f1c9e2 273 */
AnnaBridge 165:e614a9f1c9e2 274 void HAL_MPU_Disable(void)
AnnaBridge 165:e614a9f1c9e2 275 {
AnnaBridge 165:e614a9f1c9e2 276 /* Make sure outstanding transfers are done */
AnnaBridge 165:e614a9f1c9e2 277 __DMB();
AnnaBridge 165:e614a9f1c9e2 278
AnnaBridge 165:e614a9f1c9e2 279 /* Disable fault exceptions */
AnnaBridge 165:e614a9f1c9e2 280 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:e614a9f1c9e2 281
AnnaBridge 165:e614a9f1c9e2 282 /* Disable the MPU and clear the control register*/
AnnaBridge 165:e614a9f1c9e2 283 MPU->CTRL = 0U;
AnnaBridge 165:e614a9f1c9e2 284 }
AnnaBridge 165:e614a9f1c9e2 285
AnnaBridge 165:e614a9f1c9e2 286 /**
AnnaBridge 165:e614a9f1c9e2 287 * @brief Enable the MPU.
AnnaBridge 165:e614a9f1c9e2 288 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
AnnaBridge 165:e614a9f1c9e2 289 * NMI, FAULTMASK and privileged access to the default memory
AnnaBridge 165:e614a9f1c9e2 290 * This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 291 * @arg MPU_HFNMI_PRIVDEF_NONE
AnnaBridge 165:e614a9f1c9e2 292 * @arg MPU_HARDFAULT_NMI
AnnaBridge 165:e614a9f1c9e2 293 * @arg MPU_PRIVILEGED_DEFAULT
AnnaBridge 165:e614a9f1c9e2 294 * @arg MPU_HFNMI_PRIVDEF
AnnaBridge 165:e614a9f1c9e2 295 * @retval None
AnnaBridge 165:e614a9f1c9e2 296 */
AnnaBridge 165:e614a9f1c9e2 297 void HAL_MPU_Enable(uint32_t MPU_Control)
AnnaBridge 165:e614a9f1c9e2 298 {
AnnaBridge 165:e614a9f1c9e2 299 /* Enable the MPU */
AnnaBridge 165:e614a9f1c9e2 300 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
AnnaBridge 165:e614a9f1c9e2 301
AnnaBridge 165:e614a9f1c9e2 302 /* Enable fault exceptions */
AnnaBridge 165:e614a9f1c9e2 303 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
AnnaBridge 165:e614a9f1c9e2 304
AnnaBridge 165:e614a9f1c9e2 305 /* Ensure MPU setting take effects */
AnnaBridge 165:e614a9f1c9e2 306 __DSB();
AnnaBridge 165:e614a9f1c9e2 307 __ISB();
AnnaBridge 165:e614a9f1c9e2 308 }
AnnaBridge 165:e614a9f1c9e2 309
<> 144:ef7eb2e8f9f7 310 /**
<> 144:ef7eb2e8f9f7 311 * @brief Initializes and configures the Region and the memory to be protected.
<> 144:ef7eb2e8f9f7 312 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 313 * the initialization and configuration information.
<> 144:ef7eb2e8f9f7 314 * @retval None
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 /* Check the parameters */
<> 144:ef7eb2e8f9f7 319 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
<> 144:ef7eb2e8f9f7 320 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Set the Region number */
<> 144:ef7eb2e8f9f7 323 MPU->RNR = MPU_Init->Number;
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 if ((MPU_Init->Enable) != RESET)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 /* Check the parameters */
<> 144:ef7eb2e8f9f7 328 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
<> 144:ef7eb2e8f9f7 329 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
<> 144:ef7eb2e8f9f7 330 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
<> 144:ef7eb2e8f9f7 331 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
<> 144:ef7eb2e8f9f7 332 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
<> 144:ef7eb2e8f9f7 333 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
<> 144:ef7eb2e8f9f7 334 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
<> 144:ef7eb2e8f9f7 335 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 MPU->RBAR = MPU_Init->BaseAddress;
<> 144:ef7eb2e8f9f7 338 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
<> 144:ef7eb2e8f9f7 339 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
<> 144:ef7eb2e8f9f7 340 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
<> 144:ef7eb2e8f9f7 341 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
<> 144:ef7eb2e8f9f7 342 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
<> 144:ef7eb2e8f9f7 343 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
<> 144:ef7eb2e8f9f7 344 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
<> 144:ef7eb2e8f9f7 345 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
<> 144:ef7eb2e8f9f7 346 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
<> 144:ef7eb2e8f9f7 347 }
<> 144:ef7eb2e8f9f7 348 else
<> 144:ef7eb2e8f9f7 349 {
AnnaBridge 165:e614a9f1c9e2 350 MPU->RBAR = 0x00U;
AnnaBridge 165:e614a9f1c9e2 351 MPU->RASR = 0x00U;
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
<> 144:ef7eb2e8f9f7 358 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 uint32_t HAL_NVIC_GetPriorityGrouping(void)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Get the PRIGROUP[10:8] field value */
<> 144:ef7eb2e8f9f7 363 return NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @brief Gets the priority of an interrupt.
AnnaBridge 165:e614a9f1c9e2 368 * @param IRQn: External interrupt number.
<> 144:ef7eb2e8f9f7 369 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 370 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 371 * @param PriorityGroup: the priority grouping bits length.
<> 144:ef7eb2e8f9f7 372 * This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 373 * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
<> 144:ef7eb2e8f9f7 374 * 4 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 375 * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
<> 144:ef7eb2e8f9f7 376 * 3 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 377 * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
<> 144:ef7eb2e8f9f7 378 * 2 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 379 * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
<> 144:ef7eb2e8f9f7 380 * 1 bits for subpriority
AnnaBridge 165:e614a9f1c9e2 381 * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
<> 144:ef7eb2e8f9f7 382 * 0 bits for subpriority
<> 144:ef7eb2e8f9f7 383 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
<> 144:ef7eb2e8f9f7 384 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
<> 144:ef7eb2e8f9f7 385 * @retval None
<> 144:ef7eb2e8f9f7 386 */
AnnaBridge 165:e614a9f1c9e2 387 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Check the parameters */
<> 144:ef7eb2e8f9f7 390 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 391 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 392 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @brief Sets Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 397 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 398 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 399 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 400 * @retval None
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:e614a9f1c9e2 403 {
AnnaBridge 165:e614a9f1c9e2 404 /* Check the parameters */
AnnaBridge 165:e614a9f1c9e2 405 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
AnnaBridge 165:e614a9f1c9e2 406
<> 144:ef7eb2e8f9f7 407 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 408 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /**
AnnaBridge 165:e614a9f1c9e2 412 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
<> 144:ef7eb2e8f9f7 413 * and returns the pending bit for the specified interrupt).
AnnaBridge 165:e614a9f1c9e2 414 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 415 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 416 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 417 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 418 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:e614a9f1c9e2 421 {
AnnaBridge 165:e614a9f1c9e2 422 /* Check the parameters */
AnnaBridge 165:e614a9f1c9e2 423 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
AnnaBridge 165:e614a9f1c9e2 424
<> 144:ef7eb2e8f9f7 425 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 426 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
AnnaBridge 165:e614a9f1c9e2 430 * @brief Clears the pending bit of an external interrupt.
AnnaBridge 165:e614a9f1c9e2 431 * @param IRQn External interrupt number.
<> 144:ef7eb2e8f9f7 432 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 433 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 434 * @retval None
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 165:e614a9f1c9e2 437 {
AnnaBridge 165:e614a9f1c9e2 438 /* Check the parameters */
AnnaBridge 165:e614a9f1c9e2 439 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
AnnaBridge 165:e614a9f1c9e2 440
<> 144:ef7eb2e8f9f7 441 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 442 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /**
<> 144:ef7eb2e8f9f7 446 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
<> 144:ef7eb2e8f9f7 447 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 448 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 449 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
<> 144:ef7eb2e8f9f7 450 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 451 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 165:e614a9f1c9e2 454 {
AnnaBridge 165:e614a9f1c9e2 455 /* Check the parameters */
AnnaBridge 165:e614a9f1c9e2 456 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
AnnaBridge 165:e614a9f1c9e2 457
<> 144:ef7eb2e8f9f7 458 /* Return 1 if active else 0 */
<> 144:ef7eb2e8f9f7 459 return NVIC_GetActive(IRQn);
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @brief Configures the SysTick clock source.
<> 144:ef7eb2e8f9f7 464 * @param CLKSource: specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 465 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 466 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 467 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 468 * @retval None
<> 144:ef7eb2e8f9f7 469 */
<> 144:ef7eb2e8f9f7 470 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 471 {
<> 144:ef7eb2e8f9f7 472 /* Check the parameters */
<> 144:ef7eb2e8f9f7 473 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 474 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478 else
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @brief This function handles SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 486 * @retval None
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 495 * @retval None
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 500 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @}
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @}
<> 144:ef7eb2e8f9f7 510 */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @}
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @}
<> 144:ef7eb2e8f9f7 519 */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/