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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_adc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file containing functions prototypes of ADC HAL library.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F1xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F1xx_HAL_ADC_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup ADC
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 55 /** @defgroup ADC_Exported_Types ADC Exported Types
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /**
<> 144:ef7eb2e8f9f7 60 * @brief Structure definition of ADC and regular group initialization
<> 144:ef7eb2e8f9f7 61 * @note Parameters of this structure are shared within 2 scopes:
<> 144:ef7eb2e8f9f7 62 * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
<> 144:ef7eb2e8f9f7 63 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<> 144:ef7eb2e8f9f7 64 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 65 * ADC can be either disabled or enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 typedef struct
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<> 144:ef7eb2e8f9f7 70 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref ADC_Data_align */
<> 144:ef7eb2e8f9f7 72 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<> 144:ef7eb2e8f9f7 73 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<> 144:ef7eb2e8f9f7 74 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<> 144:ef7eb2e8f9f7 75 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<> 144:ef7eb2e8f9f7 76 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<> 144:ef7eb2e8f9f7 77 Scan direction is upward: from rank1 to rank 'n'.
<> 144:ef7eb2e8f9f7 78 This parameter can be a value of @ref ADC_Scan_mode
<> 144:ef7eb2e8f9f7 79 Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
<> 144:ef7eb2e8f9f7 80 or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
<> 144:ef7eb2e8f9f7 81 the last conversion of the sequence. All previous conversions would be overwritten by the last one.
<> 144:ef7eb2e8f9f7 82 Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
<> 144:ef7eb2e8f9f7 83 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<> 144:ef7eb2e8f9f7 84 after the selected trigger occurred (software start or external trigger).
<> 144:ef7eb2e8f9f7 85 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 86 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<> 144:ef7eb2e8f9f7 87 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<> 144:ef7eb2e8f9f7 88 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
<> 144:ef7eb2e8f9f7 89 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<> 144:ef7eb2e8f9f7 90 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 91 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<> 144:ef7eb2e8f9f7 92 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 93 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<> 144:ef7eb2e8f9f7 94 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<> 144:ef7eb2e8f9f7 95 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 96 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<> 144:ef7eb2e8f9f7 97 If set to ADC_SOFTWARE_START, external triggers are disabled.
<> 144:ef7eb2e8f9f7 98 If set to external trigger source, triggering is on event rising edge.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref ADC_External_trigger_source_Regular */
<> 144:ef7eb2e8f9f7 100 }ADC_InitTypeDef;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /**
<> 144:ef7eb2e8f9f7 103 * @brief Structure definition of ADC channel for regular group
<> 144:ef7eb2e8f9f7 104 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 105 * ADC can be either disabled or enabled without conversion on going on regular group.
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 typedef struct
<> 144:ef7eb2e8f9f7 108 {
<> 144:ef7eb2e8f9f7 109 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<> 144:ef7eb2e8f9f7 110 This parameter can be a value of @ref ADC_channels
<> 144:ef7eb2e8f9f7 111 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
<> 144:ef7eb2e8f9f7 112 Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
<> 144:ef7eb2e8f9f7 113 Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
<> 144:ef7eb2e8f9f7 114 It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
<> 144:ef7eb2e8f9f7 115 Refer to errata sheet of these devices for more details. */
<> 144:ef7eb2e8f9f7 116 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
<> 144:ef7eb2e8f9f7 117 This parameter can be a value of @ref ADC_regular_rank
<> 144:ef7eb2e8f9f7 118 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<> 144:ef7eb2e8f9f7 119 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<> 144:ef7eb2e8f9f7 120 Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 121 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
<> 144:ef7eb2e8f9f7 122 This parameter can be a value of @ref ADC_sampling_times
<> 144:ef7eb2e8f9f7 123 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<> 144:ef7eb2e8f9f7 124 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<> 144:ef7eb2e8f9f7 125 Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
<> 144:ef7eb2e8f9f7 126 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<> 144:ef7eb2e8f9f7 127 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
<> 144:ef7eb2e8f9f7 128 }ADC_ChannelConfTypeDef;
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /**
<> 144:ef7eb2e8f9f7 131 * @brief ADC Configuration analog watchdog definition
<> 144:ef7eb2e8f9f7 132 * @note The setting of these parameters with function is conditioned to ADC state.
<> 144:ef7eb2e8f9f7 133 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
<> 144:ef7eb2e8f9f7 134 */
<> 144:ef7eb2e8f9f7 135 typedef struct
<> 144:ef7eb2e8f9f7 136 {
<> 144:ef7eb2e8f9f7 137 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
<> 144:ef7eb2e8f9f7 138 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
<> 144:ef7eb2e8f9f7 139 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<> 144:ef7eb2e8f9f7 140 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
<> 144:ef7eb2e8f9f7 141 This parameter can be a value of @ref ADC_channels. */
<> 144:ef7eb2e8f9f7 142 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<> 144:ef7eb2e8f9f7 143 This parameter can be set to ENABLE or DISABLE */
<> 144:ef7eb2e8f9f7 144 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 145 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<> 144:ef7eb2e8f9f7 146 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<> 144:ef7eb2e8f9f7 147 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<> 144:ef7eb2e8f9f7 148 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
<> 144:ef7eb2e8f9f7 149 }ADC_AnalogWDGConfTypeDef;
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @brief HAL ADC state machine: ADC states definition (bitfields)
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 /* States of ADC global scope */
AnnaBridge 165:e614a9f1c9e2 155 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
AnnaBridge 165:e614a9f1c9e2 156 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
AnnaBridge 165:e614a9f1c9e2 157 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
AnnaBridge 165:e614a9f1c9e2 158 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* States of ADC errors */
AnnaBridge 165:e614a9f1c9e2 161 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
AnnaBridge 165:e614a9f1c9e2 162 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
AnnaBridge 165:e614a9f1c9e2 163 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* States of ADC group regular */
AnnaBridge 165:e614a9f1c9e2 166 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
AnnaBridge 165:e614a9f1c9e2 167 external trigger, low power auto power-on, multimode ADC master control) */
AnnaBridge 165:e614a9f1c9e2 168 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
AnnaBridge 165:e614a9f1c9e2 169 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
AnnaBridge 165:e614a9f1c9e2 170 #define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* States of ADC group injected */
AnnaBridge 165:e614a9f1c9e2 173 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
AnnaBridge 165:e614a9f1c9e2 174 external trigger, low power auto power-on, multimode ADC master control) */
AnnaBridge 165:e614a9f1c9e2 175 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
AnnaBridge 165:e614a9f1c9e2 176 #define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* States of ADC analog watchdogs */
AnnaBridge 165:e614a9f1c9e2 179 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
AnnaBridge 165:e614a9f1c9e2 180 #define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
AnnaBridge 165:e614a9f1c9e2 181 #define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* States of ADC multi-mode */
AnnaBridge 165:e614a9f1c9e2 184 #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @brief ADC handle Structure definition
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190 typedef struct
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 ADC_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 ADC_InitTypeDef Init; /*!< ADC required parameters */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 HAL_LockTypeDef Lock; /*!< ADC locking object */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 __IO uint32_t ErrorCode; /*!< ADC Error code */
<> 144:ef7eb2e8f9f7 203 }ADC_HandleTypeDef;
<> 144:ef7eb2e8f9f7 204 /**
<> 144:ef7eb2e8f9f7 205 * @}
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @defgroup ADC_Exported_Constants ADC Exported Constants
<> 144:ef7eb2e8f9f7 213 * @{
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup ADC_Error_Code ADC Error Code
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
AnnaBridge 165:e614a9f1c9e2 219 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
AnnaBridge 165:e614a9f1c9e2 220 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
AnnaBridge 165:e614a9f1c9e2 221 enable/disable, erroneous state */
AnnaBridge 165:e614a9f1c9e2 222 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
AnnaBridge 165:e614a9f1c9e2 223 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @}
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** @defgroup ADC_Data_align ADC data alignment
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
AnnaBridge 165:e614a9f1c9e2 233 #define ADC_DATAALIGN_RIGHT 0x00000000U
<> 144:ef7eb2e8f9f7 234 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup ADC_Scan_mode ADC scan mode
<> 144:ef7eb2e8f9f7 240 * @{
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
<> 144:ef7eb2e8f9f7 243 /* compatibility with other STM32 devices having a sequencer with */
<> 144:ef7eb2e8f9f7 244 /* additional options. */
AnnaBridge 165:e614a9f1c9e2 245 #define ADC_SCAN_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 246 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
AnnaBridge 165:e614a9f1c9e2 254 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
<> 144:ef7eb2e8f9f7 255 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /** @defgroup ADC_channels ADC channels
<> 144:ef7eb2e8f9f7 261 * @{
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 /* Note: Depending on devices, some channels may not be available on package */
<> 144:ef7eb2e8f9f7 264 /* pins. Refer to device datasheet for channels availability. */
AnnaBridge 165:e614a9f1c9e2 265 #define ADC_CHANNEL_0 0x00000000U
<> 144:ef7eb2e8f9f7 266 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 267 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 268 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 269 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
<> 144:ef7eb2e8f9f7 270 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 271 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 272 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 273 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
<> 144:ef7eb2e8f9f7 274 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 275 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 276 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 277 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
<> 144:ef7eb2e8f9f7 278 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 279 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
<> 144:ef7eb2e8f9f7 280 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 281 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
<> 144:ef7eb2e8f9f7 282 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
<> 144:ef7eb2e8f9f7 285 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /** @defgroup ADC_sampling_times ADC sampling times
<> 144:ef7eb2e8f9f7 291 * @{
<> 144:ef7eb2e8f9f7 292 */
AnnaBridge 165:e614a9f1c9e2 293 #define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
<> 144:ef7eb2e8f9f7 294 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 295 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 296 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 297 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 298 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 299 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 300 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @}
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /** @defgroup ADC_regular_rank ADC rank into regular group
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
AnnaBridge 165:e614a9f1c9e2 308 #define ADC_REGULAR_RANK_1 0x00000001U
AnnaBridge 165:e614a9f1c9e2 309 #define ADC_REGULAR_RANK_2 0x00000002U
AnnaBridge 165:e614a9f1c9e2 310 #define ADC_REGULAR_RANK_3 0x00000003U
AnnaBridge 165:e614a9f1c9e2 311 #define ADC_REGULAR_RANK_4 0x00000004U
AnnaBridge 165:e614a9f1c9e2 312 #define ADC_REGULAR_RANK_5 0x00000005U
AnnaBridge 165:e614a9f1c9e2 313 #define ADC_REGULAR_RANK_6 0x00000006U
AnnaBridge 165:e614a9f1c9e2 314 #define ADC_REGULAR_RANK_7 0x00000007U
AnnaBridge 165:e614a9f1c9e2 315 #define ADC_REGULAR_RANK_8 0x00000008U
AnnaBridge 165:e614a9f1c9e2 316 #define ADC_REGULAR_RANK_9 0x00000009U
AnnaBridge 165:e614a9f1c9e2 317 #define ADC_REGULAR_RANK_10 0x0000000AU
AnnaBridge 165:e614a9f1c9e2 318 #define ADC_REGULAR_RANK_11 0x0000000BU
AnnaBridge 165:e614a9f1c9e2 319 #define ADC_REGULAR_RANK_12 0x0000000CU
AnnaBridge 165:e614a9f1c9e2 320 #define ADC_REGULAR_RANK_13 0x0000000DU
AnnaBridge 165:e614a9f1c9e2 321 #define ADC_REGULAR_RANK_14 0x0000000EU
AnnaBridge 165:e614a9f1c9e2 322 #define ADC_REGULAR_RANK_15 0x0000000FU
AnnaBridge 165:e614a9f1c9e2 323 #define ADC_REGULAR_RANK_16 0x00000010U
<> 144:ef7eb2e8f9f7 324 /**
<> 144:ef7eb2e8f9f7 325 * @}
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
<> 144:ef7eb2e8f9f7 329 * @{
<> 144:ef7eb2e8f9f7 330 */
AnnaBridge 165:e614a9f1c9e2 331 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U
<> 144:ef7eb2e8f9f7 332 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
<> 144:ef7eb2e8f9f7 333 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 334 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
AnnaBridge 165:e614a9f1c9e2 335 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
AnnaBridge 165:e614a9f1c9e2 336 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
<> 144:ef7eb2e8f9f7 337 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /** @defgroup ADC_conversion_group ADC conversion group
<> 144:ef7eb2e8f9f7 343 * @{
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
<> 144:ef7eb2e8f9f7 346 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 347 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @}
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /** @defgroup ADC_Event_type ADC Event type
<> 144:ef7eb2e8f9f7 353 * @{
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @}
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /** @defgroup ADC_interrupts_definition ADC interrupts definition
<> 144:ef7eb2e8f9f7 363 * @{
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
<> 144:ef7eb2e8f9f7 366 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
<> 144:ef7eb2e8f9f7 367 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @}
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /** @defgroup ADC_flags_definition ADC flags definition
<> 144:ef7eb2e8f9f7 373 * @{
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
<> 144:ef7eb2e8f9f7 376 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
<> 144:ef7eb2e8f9f7 377 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
<> 144:ef7eb2e8f9f7 378 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
<> 144:ef7eb2e8f9f7 379 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
<> 144:ef7eb2e8f9f7 380 /**
<> 144:ef7eb2e8f9f7 381 * @}
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /** @addtogroup ADC_Private_Constants ADC Private Constants
<> 144:ef7eb2e8f9f7 392 * @{
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /** @defgroup ADC_conversion_cycles ADC conversion cycles
<> 144:ef7eb2e8f9f7 396 * @{
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398 /* ADC conversion cycles (unit: ADC clock cycles) */
<> 144:ef7eb2e8f9f7 399 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
<> 144:ef7eb2e8f9f7 400 /* resolution 12 bits) */
AnnaBridge 165:e614a9f1c9e2 401 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
AnnaBridge 165:e614a9f1c9e2 402 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
AnnaBridge 165:e614a9f1c9e2 403 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
AnnaBridge 165:e614a9f1c9e2 404 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
AnnaBridge 165:e614a9f1c9e2 405 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
AnnaBridge 165:e614a9f1c9e2 406 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
AnnaBridge 165:e614a9f1c9e2 407 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
AnnaBridge 165:e614a9f1c9e2 408 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
<> 144:ef7eb2e8f9f7 409 /**
<> 144:ef7eb2e8f9f7 410 * @}
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
<> 144:ef7eb2e8f9f7 414 * @{
<> 144:ef7eb2e8f9f7 415 */
<> 144:ef7eb2e8f9f7 416 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
<> 144:ef7eb2e8f9f7 417 (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
<> 144:ef7eb2e8f9f7 418 ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
<> 144:ef7eb2e8f9f7 419 ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
<> 144:ef7eb2e8f9f7 420 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<> 144:ef7eb2e8f9f7 421 (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
<> 144:ef7eb2e8f9f7 422 ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
<> 144:ef7eb2e8f9f7 425 (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
<> 144:ef7eb2e8f9f7 426 ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
<> 144:ef7eb2e8f9f7 427 ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
<> 144:ef7eb2e8f9f7 428 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<> 144:ef7eb2e8f9f7 429 (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
<> 144:ef7eb2e8f9f7 430 ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
<> 144:ef7eb2e8f9f7 433 (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
<> 144:ef7eb2e8f9f7 434 ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
<> 144:ef7eb2e8f9f7 435 ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
<> 144:ef7eb2e8f9f7 436 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<> 144:ef7eb2e8f9f7 437 (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
<> 144:ef7eb2e8f9f7 438 ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
<> 144:ef7eb2e8f9f7 439
AnnaBridge 165:e614a9f1c9e2 440 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
<> 144:ef7eb2e8f9f7 441 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 442 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
<> 144:ef7eb2e8f9f7 443 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 444 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
<> 144:ef7eb2e8f9f7 445 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 446 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
<> 144:ef7eb2e8f9f7 447 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<> 144:ef7eb2e8f9f7 448
AnnaBridge 165:e614a9f1c9e2 449 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
<> 144:ef7eb2e8f9f7 450 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 451 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
<> 144:ef7eb2e8f9f7 452 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 453 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
<> 144:ef7eb2e8f9f7 454 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 455 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
<> 144:ef7eb2e8f9f7 456 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<> 144:ef7eb2e8f9f7 457 /**
<> 144:ef7eb2e8f9f7 458 * @}
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
<> 144:ef7eb2e8f9f7 462 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @}
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /** @defgroup ADC_Exported_Macros ADC Exported Macros
<> 144:ef7eb2e8f9f7 472 * @{
<> 144:ef7eb2e8f9f7 473 */
<> 144:ef7eb2e8f9f7 474 /* Macro for internal HAL driver usage, and possibly can be used into code of */
<> 144:ef7eb2e8f9f7 475 /* final user. */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Enable the ADC peripheral
<> 144:ef7eb2e8f9f7 479 * @note ADC enable requires a delay for ADC stabilization time
<> 144:ef7eb2e8f9f7 480 * (refer to device datasheet, parameter tSTAB)
<> 144:ef7eb2e8f9f7 481 * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
<> 144:ef7eb2e8f9f7 482 * SW start on regular group.
<> 144:ef7eb2e8f9f7 483 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 484 * @retval None
<> 144:ef7eb2e8f9f7 485 */
<> 144:ef7eb2e8f9f7 486 #define __HAL_ADC_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 487 (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @brief Disable the ADC peripheral
<> 144:ef7eb2e8f9f7 491 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 492 * @retval None
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 #define __HAL_ADC_DISABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 495 (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /** @brief Enable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 498 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 499 * @param __INTERRUPT__: ADC Interrupt
<> 144:ef7eb2e8f9f7 500 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 501 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 502 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 503 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 504 * @retval None
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 507 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /** @brief Disable the ADC end of conversion interrupt.
<> 144:ef7eb2e8f9f7 510 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 511 * @param __INTERRUPT__: ADC Interrupt
<> 144:ef7eb2e8f9f7 512 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 513 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 514 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 515 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 516 * @retval None
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 519 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 522 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 523 * @param __INTERRUPT__: ADC interrupt source to check
<> 144:ef7eb2e8f9f7 524 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 525 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<> 144:ef7eb2e8f9f7 526 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<> 144:ef7eb2e8f9f7 527 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<> 144:ef7eb2e8f9f7 528 * @retval None
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<> 144:ef7eb2e8f9f7 531 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /** @brief Get the selected ADC's flag status.
<> 144:ef7eb2e8f9f7 534 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 535 * @param __FLAG__: ADC flag
<> 144:ef7eb2e8f9f7 536 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 537 * @arg ADC_FLAG_STRT: ADC Regular group start flag
<> 144:ef7eb2e8f9f7 538 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<> 144:ef7eb2e8f9f7 539 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 540 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<> 144:ef7eb2e8f9f7 541 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 542 * @retval None
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 545 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /** @brief Clear the ADC's pending flags
<> 144:ef7eb2e8f9f7 548 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 549 * @param __FLAG__: ADC flag
<> 144:ef7eb2e8f9f7 550 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 551 * @arg ADC_FLAG_STRT: ADC Regular group start flag
<> 144:ef7eb2e8f9f7 552 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<> 144:ef7eb2e8f9f7 553 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<> 144:ef7eb2e8f9f7 554 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<> 144:ef7eb2e8f9f7 555 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<> 144:ef7eb2e8f9f7 556 * @retval None
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 144:ef7eb2e8f9f7 559 (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /** @brief Reset ADC handle state
<> 144:ef7eb2e8f9f7 562 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 563 * @retval None
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 566 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @}
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Private macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /** @defgroup ADC_Private_Macros ADC Private Macros
<> 144:ef7eb2e8f9f7 575 * @{
<> 144:ef7eb2e8f9f7 576 */
<> 144:ef7eb2e8f9f7 577 /* Macro reserved for internal HAL driver usage, not intended to be used in */
<> 144:ef7eb2e8f9f7 578 /* code of final user. */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @brief Verification of ADC state: enabled or disabled
<> 144:ef7eb2e8f9f7 582 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 583 * @retval SET (ADC enabled) or RESET (ADC disabled)
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585 #define ADC_IS_ENABLE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 586 ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
<> 144:ef7eb2e8f9f7 587 ) ? SET : RESET)
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /**
<> 144:ef7eb2e8f9f7 590 * @brief Test if conversion trigger of regular group is software start
<> 144:ef7eb2e8f9f7 591 * or external trigger.
<> 144:ef7eb2e8f9f7 592 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 593 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<> 144:ef7eb2e8f9f7 596 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @brief Test if conversion trigger of injected group is software start
<> 144:ef7eb2e8f9f7 600 * or external trigger.
<> 144:ef7eb2e8f9f7 601 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 602 * @retval SET (software start) or RESET (external trigger)
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<> 144:ef7eb2e8f9f7 605 (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @brief Simultaneously clears and sets specific bits of the handle State
<> 144:ef7eb2e8f9f7 609 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<> 144:ef7eb2e8f9f7 610 * the first parameter is the ADC handle State, the second parameter is the
<> 144:ef7eb2e8f9f7 611 * bit field to clear, the third and last parameter is the bit field to set.
<> 144:ef7eb2e8f9f7 612 * @retval None
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 #define ADC_STATE_CLR_SET MODIFY_REG
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @brief Clear ADC error code (set it to error code: "no error")
<> 144:ef7eb2e8f9f7 618 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 619 * @retval None
<> 144:ef7eb2e8f9f7 620 */
<> 144:ef7eb2e8f9f7 621 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 622 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /**
<> 144:ef7eb2e8f9f7 625 * @brief Set ADC number of conversions into regular channel sequence length.
<> 144:ef7eb2e8f9f7 626 * @param _NbrOfConversion_: Regular channel sequence length
<> 144:ef7eb2e8f9f7 627 * @retval None
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
AnnaBridge 165:e614a9f1c9e2 630 (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /**
<> 144:ef7eb2e8f9f7 633 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
<> 144:ef7eb2e8f9f7 634 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 635 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 636 * @retval None
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
AnnaBridge 165:e614a9f1c9e2 639 ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /**
<> 144:ef7eb2e8f9f7 642 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
<> 144:ef7eb2e8f9f7 643 * @param _SAMPLETIME_: Sample time parameter.
<> 144:ef7eb2e8f9f7 644 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 645 * @retval None
<> 144:ef7eb2e8f9f7 646 */
<> 144:ef7eb2e8f9f7 647 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
AnnaBridge 165:e614a9f1c9e2 648 ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /**
<> 144:ef7eb2e8f9f7 651 * @brief Set the selected regular channel rank for rank between 1 and 6.
<> 144:ef7eb2e8f9f7 652 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 653 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 654 * @retval None
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 165:e614a9f1c9e2 657 ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /**
<> 144:ef7eb2e8f9f7 660 * @brief Set the selected regular channel rank for rank between 7 and 12.
<> 144:ef7eb2e8f9f7 661 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 662 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 663 * @retval None
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 165:e614a9f1c9e2 666 ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /**
<> 144:ef7eb2e8f9f7 669 * @brief Set the selected regular channel rank for rank between 13 and 16.
<> 144:ef7eb2e8f9f7 670 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 671 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 672 * @retval None
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 165:e614a9f1c9e2 675 ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @brief Set the injected sequence length.
<> 144:ef7eb2e8f9f7 679 * @param _JSQR_JL_: Sequence length.
<> 144:ef7eb2e8f9f7 680 * @retval None
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
AnnaBridge 165:e614a9f1c9e2 683 (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /**
<> 144:ef7eb2e8f9f7 686 * @brief Set the selected injected channel rank
<> 144:ef7eb2e8f9f7 687 * Note: on STM32F1 devices, channel rank position in JSQR register
<> 144:ef7eb2e8f9f7 688 * is depending on total number of ranks selected into
<> 144:ef7eb2e8f9f7 689 * injected sequencer (ranks sequence starting from 4-JL)
<> 144:ef7eb2e8f9f7 690 * @param _CHANNELNB_: Channel number.
<> 144:ef7eb2e8f9f7 691 * @param _RANKNB_: Rank number.
<> 144:ef7eb2e8f9f7 692 * @param _JSQR_JL_: Sequence length.
<> 144:ef7eb2e8f9f7 693 * @retval None
<> 144:ef7eb2e8f9f7 694 */
<> 144:ef7eb2e8f9f7 695 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
AnnaBridge 165:e614a9f1c9e2 696 ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief Enable ADC continuous conversion mode.
<> 144:ef7eb2e8f9f7 700 * @param _CONTINUOUS_MODE_: Continuous mode.
<> 144:ef7eb2e8f9f7 701 * @retval None
<> 144:ef7eb2e8f9f7 702 */
<> 144:ef7eb2e8f9f7 703 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
AnnaBridge 165:e614a9f1c9e2 704 ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @brief Configures the number of discontinuous conversions for the regular group channels.
<> 144:ef7eb2e8f9f7 708 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<> 144:ef7eb2e8f9f7 709 * @retval None
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
AnnaBridge 165:e614a9f1c9e2 712 (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /**
<> 144:ef7eb2e8f9f7 715 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<> 144:ef7eb2e8f9f7 716 * @param _SCAN_MODE_: Scan conversion mode.
<> 144:ef7eb2e8f9f7 717 * @retval None
<> 144:ef7eb2e8f9f7 718 */
<> 144:ef7eb2e8f9f7 719 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
<> 144:ef7eb2e8f9f7 720 /* is equivalent to ADC_SCAN_ENABLE. */
<> 144:ef7eb2e8f9f7 721 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
<> 144:ef7eb2e8f9f7 722 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
<> 144:ef7eb2e8f9f7 723 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
<> 144:ef7eb2e8f9f7 724 )
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /**
<> 144:ef7eb2e8f9f7 727 * @brief Get the maximum ADC conversion cycles on all channels.
<> 144:ef7eb2e8f9f7 728 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
<> 144:ef7eb2e8f9f7 729 * Approximation of sampling time within 4 ranges, returns the highest value:
<> 144:ef7eb2e8f9f7 730 * below 7.5 cycles {1.5 cycle; 7.5 cycles},
<> 144:ef7eb2e8f9f7 731 * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
<> 144:ef7eb2e8f9f7 732 * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
<> 144:ef7eb2e8f9f7 733 * equal to 239.5 cycles
<> 144:ef7eb2e8f9f7 734 * Unit: ADC clock cycles
<> 144:ef7eb2e8f9f7 735 * @param __HANDLE__: ADC handle
<> 144:ef7eb2e8f9f7 736 * @retval ADC conversion cycles on all channels
<> 144:ef7eb2e8f9f7 737 */
<> 144:ef7eb2e8f9f7 738 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
<> 144:ef7eb2e8f9f7 739 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
<> 144:ef7eb2e8f9f7 740 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
<> 144:ef7eb2e8f9f7 741 \
<> 144:ef7eb2e8f9f7 742 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
<> 144:ef7eb2e8f9f7 743 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
<> 144:ef7eb2e8f9f7 744 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
<> 144:ef7eb2e8f9f7 745 : \
<> 144:ef7eb2e8f9f7 746 ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
<> 144:ef7eb2e8f9f7 747 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
<> 144:ef7eb2e8f9f7 748 ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
<> 144:ef7eb2e8f9f7 749 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
<> 144:ef7eb2e8f9f7 750 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
<> 144:ef7eb2e8f9f7 751 )
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
<> 144:ef7eb2e8f9f7 754 ((ALIGN) == ADC_DATAALIGN_LEFT) )
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
<> 144:ef7eb2e8f9f7 757 ((SCAN_MODE) == ADC_SCAN_ENABLE) )
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
<> 144:ef7eb2e8f9f7 760 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 763 ((CHANNEL) == ADC_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 764 ((CHANNEL) == ADC_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 765 ((CHANNEL) == ADC_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 766 ((CHANNEL) == ADC_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 767 ((CHANNEL) == ADC_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 768 ((CHANNEL) == ADC_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 769 ((CHANNEL) == ADC_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 770 ((CHANNEL) == ADC_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 771 ((CHANNEL) == ADC_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 772 ((CHANNEL) == ADC_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 773 ((CHANNEL) == ADC_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 774 ((CHANNEL) == ADC_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 775 ((CHANNEL) == ADC_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 776 ((CHANNEL) == ADC_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 777 ((CHANNEL) == ADC_CHANNEL_15) || \
<> 144:ef7eb2e8f9f7 778 ((CHANNEL) == ADC_CHANNEL_16) || \
<> 144:ef7eb2e8f9f7 779 ((CHANNEL) == ADC_CHANNEL_17) )
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
<> 144:ef7eb2e8f9f7 782 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
<> 144:ef7eb2e8f9f7 783 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
<> 144:ef7eb2e8f9f7 784 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
<> 144:ef7eb2e8f9f7 785 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
<> 144:ef7eb2e8f9f7 786 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
<> 144:ef7eb2e8f9f7 787 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
<> 144:ef7eb2e8f9f7 788 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
<> 144:ef7eb2e8f9f7 791 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
<> 144:ef7eb2e8f9f7 792 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
<> 144:ef7eb2e8f9f7 793 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
<> 144:ef7eb2e8f9f7 794 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
<> 144:ef7eb2e8f9f7 795 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
<> 144:ef7eb2e8f9f7 796 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
<> 144:ef7eb2e8f9f7 797 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
<> 144:ef7eb2e8f9f7 798 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
<> 144:ef7eb2e8f9f7 799 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
<> 144:ef7eb2e8f9f7 800 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
<> 144:ef7eb2e8f9f7 801 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
<> 144:ef7eb2e8f9f7 802 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
<> 144:ef7eb2e8f9f7 803 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
<> 144:ef7eb2e8f9f7 804 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
<> 144:ef7eb2e8f9f7 805 ((CHANNEL) == ADC_REGULAR_RANK_16) )
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
<> 144:ef7eb2e8f9f7 808 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
<> 144:ef7eb2e8f9f7 809 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
<> 144:ef7eb2e8f9f7 810 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
<> 144:ef7eb2e8f9f7 811 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
<> 144:ef7eb2e8f9f7 812 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
<> 144:ef7eb2e8f9f7 813 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
<> 144:ef7eb2e8f9f7 816 ((CONVERSION) == ADC_INJECTED_GROUP) || \
<> 144:ef7eb2e8f9f7 817 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /** @defgroup ADC_range_verification ADC range verification
<> 144:ef7eb2e8f9f7 823 * For a unique ADC resolution: 12 bits
<> 144:ef7eb2e8f9f7 824 * @{
<> 144:ef7eb2e8f9f7 825 */
AnnaBridge 165:e614a9f1c9e2 826 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
<> 144:ef7eb2e8f9f7 827 /**
<> 144:ef7eb2e8f9f7 828 * @}
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
<> 144:ef7eb2e8f9f7 832 * @{
<> 144:ef7eb2e8f9f7 833 */
AnnaBridge 165:e614a9f1c9e2 834 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
<> 144:ef7eb2e8f9f7 835 /**
<> 144:ef7eb2e8f9f7 836 * @}
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
<> 144:ef7eb2e8f9f7 840 * @{
<> 144:ef7eb2e8f9f7 841 */
AnnaBridge 165:e614a9f1c9e2 842 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
<> 144:ef7eb2e8f9f7 843 /**
<> 144:ef7eb2e8f9f7 844 * @}
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /**
<> 144:ef7eb2e8f9f7 848 * @}
<> 144:ef7eb2e8f9f7 849 */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Include ADC HAL Extension module */
<> 144:ef7eb2e8f9f7 852 #include "stm32f1xx_hal_adc_ex.h"
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 855 /** @addtogroup ADC_Exported_Functions
<> 144:ef7eb2e8f9f7 856 * @{
<> 144:ef7eb2e8f9f7 857 */
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /** @addtogroup ADC_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 860 * @{
<> 144:ef7eb2e8f9f7 861 */
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Initialization and de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 865 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 866 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 867 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 868 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @}
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 /** @addtogroup ADC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 876 * @{
<> 144:ef7eb2e8f9f7 877 */
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 881 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 882 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 883 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 884 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Non-blocking mode: Interruption */
<> 144:ef7eb2e8f9f7 887 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 888 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Non-blocking mode: DMA */
<> 144:ef7eb2e8f9f7 891 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 892 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /* ADC retrieve conversion value intended to be used with polling or interruption */
<> 144:ef7eb2e8f9f7 895 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<> 144:ef7eb2e8f9f7 898 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 899 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 900 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 901 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 902 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 903 /**
<> 144:ef7eb2e8f9f7 904 * @}
<> 144:ef7eb2e8f9f7 905 */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 909 /** @addtogroup ADC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 910 * @{
<> 144:ef7eb2e8f9f7 911 */
<> 144:ef7eb2e8f9f7 912 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 913 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<> 144:ef7eb2e8f9f7 914 /**
<> 144:ef7eb2e8f9f7 915 * @}
<> 144:ef7eb2e8f9f7 916 */
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Peripheral State functions *************************************************/
<> 144:ef7eb2e8f9f7 920 /** @addtogroup ADC_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 921 * @{
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 924 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<> 144:ef7eb2e8f9f7 925 /**
<> 144:ef7eb2e8f9f7 926 * @}
<> 144:ef7eb2e8f9f7 927 */
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /**
<> 144:ef7eb2e8f9f7 931 * @}
<> 144:ef7eb2e8f9f7 932 */
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Internal HAL driver functions **********************************************/
<> 144:ef7eb2e8f9f7 936 /** @addtogroup ADC_Private_Functions
<> 144:ef7eb2e8f9f7 937 * @{
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 940 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
<> 144:ef7eb2e8f9f7 941 void ADC_StabilizationTime(uint32_t DelayUs);
<> 144:ef7eb2e8f9f7 942 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 943 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 944 void ADC_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 945 /**
<> 144:ef7eb2e8f9f7 946 * @}
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /**
<> 144:ef7eb2e8f9f7 951 * @}
<> 144:ef7eb2e8f9f7 952 */
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
<> 144:ef7eb2e8f9f7 955 * @}
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 959 }
<> 144:ef7eb2e8f9f7 960 #endif
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 #endif /* __STM32F1xx_HAL_ADC_H */
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/