mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 187:0387e8f68319
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f1xx_hal_adc.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 6 | * functionalities of the Analog to Digital Convertor (ADC) |
<> | 144:ef7eb2e8f9f7 | 7 | * peripheral: |
<> | 144:ef7eb2e8f9f7 | 8 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 9 | * ++ Initialization and Configuration of ADC |
<> | 144:ef7eb2e8f9f7 | 10 | * + Operation functions |
<> | 144:ef7eb2e8f9f7 | 11 | * ++ Start, stop, get result of conversions of regular |
<> | 144:ef7eb2e8f9f7 | 12 | * group, using 3 possible modes: polling, interruption or DMA. |
<> | 144:ef7eb2e8f9f7 | 13 | * + Control functions |
<> | 144:ef7eb2e8f9f7 | 14 | * ++ Channels configuration on regular group |
<> | 144:ef7eb2e8f9f7 | 15 | * ++ Channels configuration on injected group |
<> | 144:ef7eb2e8f9f7 | 16 | * ++ Analog Watchdog configuration |
<> | 144:ef7eb2e8f9f7 | 17 | * + State functions |
<> | 144:ef7eb2e8f9f7 | 18 | * ++ ADC state machine management |
<> | 144:ef7eb2e8f9f7 | 19 | * ++ Interrupts and flags management |
<> | 144:ef7eb2e8f9f7 | 20 | * Other functions (extended functions) are available in file |
<> | 144:ef7eb2e8f9f7 | 21 | * "stm32f1xx_hal_adc_ex.c". |
<> | 144:ef7eb2e8f9f7 | 22 | * |
<> | 144:ef7eb2e8f9f7 | 23 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 24 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 25 | ##### ADC peripheral features ##### |
<> | 144:ef7eb2e8f9f7 | 26 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 27 | [..] |
<> | 144:ef7eb2e8f9f7 | 28 | (+) 12-bit resolution |
<> | 144:ef7eb2e8f9f7 | 29 | |
<> | 144:ef7eb2e8f9f7 | 30 | (+) Interrupt generation at the end of regular conversion, end of injected |
<> | 144:ef7eb2e8f9f7 | 31 | conversion, and in case of analog watchdog or overrun events. |
<> | 144:ef7eb2e8f9f7 | 32 | |
<> | 144:ef7eb2e8f9f7 | 33 | (+) Single and continuous conversion modes. |
<> | 144:ef7eb2e8f9f7 | 34 | |
<> | 144:ef7eb2e8f9f7 | 35 | (+) Scan mode for conversion of several channels sequentially. |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | (+) Data alignment with in-built data coherency. |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | (+) Programmable sampling time (channel wise) |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | (+) ADC conversion of regular group and injected group. |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | (+) External trigger (timer or EXTI) |
<> | 144:ef7eb2e8f9f7 | 44 | for both regular and injected groups. |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | (+) DMA request generation for transfer of conversions data of regular group. |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | (+) Multimode Dual mode (available on devices with 2 ADCs or more). |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | (+) Configurable DMA data storage in Multimode Dual mode (available on devices |
<> | 144:ef7eb2e8f9f7 | 51 | with 2 DCs or more). |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | (+) Configurable delay between conversions in Dual interleaved mode (available |
<> | 144:ef7eb2e8f9f7 | 54 | on devices with 2 DCs or more). |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | (+) ADC calibration |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | (+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at |
<> | 144:ef7eb2e8f9f7 | 59 | slower speed. |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to |
<> | 144:ef7eb2e8f9f7 | 62 | Vdda or to an external voltage reference). |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 66 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 67 | [..] |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | *** Configuration of top level parameters related to ADC *** |
<> | 144:ef7eb2e8f9f7 | 70 | ============================================================ |
<> | 144:ef7eb2e8f9f7 | 71 | [..] |
<> | 144:ef7eb2e8f9f7 | 72 | |
<> | 144:ef7eb2e8f9f7 | 73 | (#) Enable the ADC interface |
<> | 144:ef7eb2e8f9f7 | 74 | (++) As prerequisite, ADC clock must be configured at RCC top level. |
<> | 144:ef7eb2e8f9f7 | 75 | Caution: On STM32F1, ADC clock frequency max is 14MHz (refer |
<> | 144:ef7eb2e8f9f7 | 76 | to device datasheet). |
<> | 144:ef7eb2e8f9f7 | 77 | Therefore, ADC clock prescaler must be configured in |
<> | 144:ef7eb2e8f9f7 | 78 | function of ADC clock source frequency to remain below |
<> | 144:ef7eb2e8f9f7 | 79 | this maximum frequency. |
<> | 144:ef7eb2e8f9f7 | 80 | (++) One clock setting is mandatory: |
<> | 144:ef7eb2e8f9f7 | 81 | ADC clock (core clock, also possibly conversion clock). |
<> | 144:ef7eb2e8f9f7 | 82 | (+++) Example: |
<> | 144:ef7eb2e8f9f7 | 83 | Into HAL_ADC_MspInit() (recommended code location) or with |
<> | 144:ef7eb2e8f9f7 | 84 | other device clock parameters configuration: |
<> | 144:ef7eb2e8f9f7 | 85 | (+++) RCC_PeriphCLKInitTypeDef PeriphClkInit; |
<> | 144:ef7eb2e8f9f7 | 86 | (+++) __ADC1_CLK_ENABLE(); |
<> | 144:ef7eb2e8f9f7 | 87 | (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; |
<> | 144:ef7eb2e8f9f7 | 88 | (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2; |
<> | 144:ef7eb2e8f9f7 | 89 | (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | (#) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 92 | (++) Enable the clock for the ADC GPIOs |
<> | 144:ef7eb2e8f9f7 | 93 | using macro __HAL_RCC_GPIOx_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 94 | (++) Configure these ADC pins in analog mode |
<> | 144:ef7eb2e8f9f7 | 95 | using function HAL_GPIO_Init() |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | (#) Optionally, in case of usage of ADC with interruptions: |
<> | 144:ef7eb2e8f9f7 | 98 | (++) Configure the NVIC for ADC |
<> | 144:ef7eb2e8f9f7 | 99 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 100 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 101 | into the function of corresponding ADC interruption vector |
<> | 144:ef7eb2e8f9f7 | 102 | ADCx_IRQHandler(). |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | (#) Optionally, in case of usage of DMA: |
<> | 144:ef7eb2e8f9f7 | 105 | (++) Configure the DMA (DMA channel, mode normal or circular, ...) |
<> | 144:ef7eb2e8f9f7 | 106 | using function HAL_DMA_Init(). |
<> | 144:ef7eb2e8f9f7 | 107 | (++) Configure the NVIC for DMA |
<> | 144:ef7eb2e8f9f7 | 108 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 109 | (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() |
<> | 144:ef7eb2e8f9f7 | 110 | into the function of corresponding DMA interruption vector |
<> | 144:ef7eb2e8f9f7 | 111 | DMAx_Channelx_IRQHandler(). |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | *** Configuration of ADC, groups regular/injected, channels parameters *** |
<> | 144:ef7eb2e8f9f7 | 114 | ========================================================================== |
<> | 144:ef7eb2e8f9f7 | 115 | [..] |
<> | 144:ef7eb2e8f9f7 | 116 | |
<> | 144:ef7eb2e8f9f7 | 117 | (#) Configure the ADC parameters (resolution, data alignment, ...) |
<> | 144:ef7eb2e8f9f7 | 118 | and regular group parameters (conversion trigger, sequencer, ...) |
<> | 144:ef7eb2e8f9f7 | 119 | using function HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | (#) Configure the channels for regular group parameters (channel number, |
<> | 144:ef7eb2e8f9f7 | 122 | channel rank into sequencer, ..., into regular group) |
<> | 144:ef7eb2e8f9f7 | 123 | using function HAL_ADC_ConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 124 | |
<> | 144:ef7eb2e8f9f7 | 125 | (#) Optionally, configure the injected group parameters (conversion trigger, |
<> | 144:ef7eb2e8f9f7 | 126 | sequencer, ..., of injected group) |
<> | 144:ef7eb2e8f9f7 | 127 | and the channels for injected group parameters (channel number, |
<> | 144:ef7eb2e8f9f7 | 128 | channel rank into sequencer, ..., into injected group) |
<> | 144:ef7eb2e8f9f7 | 129 | using function HAL_ADCEx_InjectedConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | (#) Optionally, configure the analog watchdog parameters (channels |
<> | 144:ef7eb2e8f9f7 | 132 | monitored, thresholds, ...) |
<> | 144:ef7eb2e8f9f7 | 133 | using function HAL_ADC_AnalogWDGConfig(). |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | (#) Optionally, for devices with several ADC instances: configure the |
<> | 144:ef7eb2e8f9f7 | 136 | multimode parameters |
<> | 144:ef7eb2e8f9f7 | 137 | using function HAL_ADCEx_MultiModeConfigChannel(). |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | *** Execution of ADC conversions *** |
<> | 144:ef7eb2e8f9f7 | 140 | ==================================== |
<> | 144:ef7eb2e8f9f7 | 141 | [..] |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | (#) Optionally, perform an automatic ADC calibration to improve the |
<> | 144:ef7eb2e8f9f7 | 144 | conversion accuracy |
<> | 144:ef7eb2e8f9f7 | 145 | using function HAL_ADCEx_Calibration_Start(). |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | (#) ADC driver can be used among three modes: polling, interruption, |
<> | 144:ef7eb2e8f9f7 | 148 | transfer by DMA. |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | (++) ADC conversion by polling: |
<> | 144:ef7eb2e8f9f7 | 151 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 152 | using function HAL_ADC_Start() |
<> | 144:ef7eb2e8f9f7 | 153 | (+++) Wait for ADC conversion completion |
<> | 144:ef7eb2e8f9f7 | 154 | using function HAL_ADC_PollForConversion() |
<> | 144:ef7eb2e8f9f7 | 155 | (or for injected group: HAL_ADCEx_InjectedPollForConversion() ) |
<> | 144:ef7eb2e8f9f7 | 156 | (+++) Retrieve conversion results |
<> | 144:ef7eb2e8f9f7 | 157 | using function HAL_ADC_GetValue() |
<> | 144:ef7eb2e8f9f7 | 158 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
<> | 144:ef7eb2e8f9f7 | 159 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 160 | using function HAL_ADC_Stop() |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | (++) ADC conversion by interruption: |
<> | 144:ef7eb2e8f9f7 | 163 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 164 | using function HAL_ADC_Start_IT() |
<> | 144:ef7eb2e8f9f7 | 165 | (+++) Wait for ADC conversion completion by call of function |
<> | 144:ef7eb2e8f9f7 | 166 | HAL_ADC_ConvCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 167 | (this function must be implemented in user program) |
<> | 144:ef7eb2e8f9f7 | 168 | (or for injected group: HAL_ADCEx_InjectedConvCpltCallback() ) |
<> | 144:ef7eb2e8f9f7 | 169 | (+++) Retrieve conversion results |
<> | 144:ef7eb2e8f9f7 | 170 | using function HAL_ADC_GetValue() |
<> | 144:ef7eb2e8f9f7 | 171 | (or for injected group: HAL_ADCEx_InjectedGetValue() ) |
<> | 144:ef7eb2e8f9f7 | 172 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 173 | using function HAL_ADC_Stop_IT() |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | (++) ADC conversion with transfer by DMA: |
<> | 144:ef7eb2e8f9f7 | 176 | (+++) Activate the ADC peripheral and start conversions |
<> | 144:ef7eb2e8f9f7 | 177 | using function HAL_ADC_Start_DMA() |
<> | 144:ef7eb2e8f9f7 | 178 | (+++) Wait for ADC conversion completion by call of function |
<> | 144:ef7eb2e8f9f7 | 179 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 180 | (these functions must be implemented in user program) |
<> | 144:ef7eb2e8f9f7 | 181 | (+++) Conversion results are automatically transferred by DMA into |
<> | 144:ef7eb2e8f9f7 | 182 | destination variable address. |
<> | 144:ef7eb2e8f9f7 | 183 | (+++) Stop conversion and disable the ADC peripheral |
<> | 144:ef7eb2e8f9f7 | 184 | using function HAL_ADC_Stop_DMA() |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | (++) For devices with several ADCs: ADC multimode conversion |
<> | 144:ef7eb2e8f9f7 | 187 | with transfer by DMA: |
<> | 144:ef7eb2e8f9f7 | 188 | (+++) Activate the ADC peripheral (slave) and start conversions |
<> | 144:ef7eb2e8f9f7 | 189 | using function HAL_ADC_Start() |
<> | 144:ef7eb2e8f9f7 | 190 | (+++) Activate the ADC peripheral (master) and start conversions |
<> | 144:ef7eb2e8f9f7 | 191 | using function HAL_ADCEx_MultiModeStart_DMA() |
<> | 144:ef7eb2e8f9f7 | 192 | (+++) Wait for ADC conversion completion by call of function |
<> | 144:ef7eb2e8f9f7 | 193 | HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 194 | (these functions must be implemented in user program) |
<> | 144:ef7eb2e8f9f7 | 195 | (+++) Conversion results are automatically transferred by DMA into |
<> | 144:ef7eb2e8f9f7 | 196 | destination variable address. |
<> | 144:ef7eb2e8f9f7 | 197 | (+++) Stop conversion and disable the ADC peripheral (master) |
<> | 144:ef7eb2e8f9f7 | 198 | using function HAL_ADCEx_MultiModeStop_DMA() |
<> | 144:ef7eb2e8f9f7 | 199 | (+++) Stop conversion and disable the ADC peripheral (slave) |
<> | 144:ef7eb2e8f9f7 | 200 | using function HAL_ADC_Stop_IT() |
<> | 144:ef7eb2e8f9f7 | 201 | |
<> | 144:ef7eb2e8f9f7 | 202 | [..] |
<> | 144:ef7eb2e8f9f7 | 203 | |
<> | 144:ef7eb2e8f9f7 | 204 | (@) Callback functions must be implemented in user program: |
<> | 144:ef7eb2e8f9f7 | 205 | (+@) HAL_ADC_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 206 | (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) |
<> | 144:ef7eb2e8f9f7 | 207 | (+@) HAL_ADC_ConvCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 208 | (+@) HAL_ADC_ConvHalfCpltCallback |
<> | 144:ef7eb2e8f9f7 | 209 | (+@) HAL_ADCEx_InjectedConvCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | *** Deinitialization of ADC *** |
<> | 144:ef7eb2e8f9f7 | 212 | ============================================================ |
<> | 144:ef7eb2e8f9f7 | 213 | [..] |
<> | 144:ef7eb2e8f9f7 | 214 | |
<> | 144:ef7eb2e8f9f7 | 215 | (#) Disable the ADC interface |
<> | 144:ef7eb2e8f9f7 | 216 | (++) ADC clock can be hard reset and disabled at RCC top level. |
<> | 144:ef7eb2e8f9f7 | 217 | (++) Hard reset of ADC peripherals |
<> | 144:ef7eb2e8f9f7 | 218 | using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). |
<> | 144:ef7eb2e8f9f7 | 219 | (++) ADC clock disable |
<> | 144:ef7eb2e8f9f7 | 220 | using the equivalent macro/functions as configuration step. |
<> | 144:ef7eb2e8f9f7 | 221 | (+++) Example: |
<> | 144:ef7eb2e8f9f7 | 222 | Into HAL_ADC_MspDeInit() (recommended code location) or with |
<> | 144:ef7eb2e8f9f7 | 223 | other device clock parameters configuration: |
<> | 144:ef7eb2e8f9f7 | 224 | (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC |
<> | 144:ef7eb2e8f9f7 | 225 | (+++) PeriphClkInit.AdcClockSelection = RCC_ADCPLLCLK2_OFF |
<> | 144:ef7eb2e8f9f7 | 226 | (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) |
<> | 144:ef7eb2e8f9f7 | 227 | |
<> | 144:ef7eb2e8f9f7 | 228 | (#) ADC pins configuration |
<> | 144:ef7eb2e8f9f7 | 229 | (++) Disable the clock for the ADC GPIOs |
<> | 144:ef7eb2e8f9f7 | 230 | using macro __HAL_RCC_GPIOx_CLK_DISABLE() |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | (#) Optionally, in case of usage of ADC with interruptions: |
<> | 144:ef7eb2e8f9f7 | 233 | (++) Disable the NVIC for ADC |
<> | 144:ef7eb2e8f9f7 | 234 | using function HAL_NVIC_EnableIRQ(ADCx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 235 | |
<> | 144:ef7eb2e8f9f7 | 236 | (#) Optionally, in case of usage of DMA: |
<> | 144:ef7eb2e8f9f7 | 237 | (++) Deinitialize the DMA |
<> | 144:ef7eb2e8f9f7 | 238 | using function HAL_DMA_Init(). |
<> | 144:ef7eb2e8f9f7 | 239 | (++) Disable the NVIC for DMA |
<> | 144:ef7eb2e8f9f7 | 240 | using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | [..] |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 245 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 246 | * @attention |
<> | 144:ef7eb2e8f9f7 | 247 | * |
<> | 144:ef7eb2e8f9f7 | 248 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 249 | * |
<> | 144:ef7eb2e8f9f7 | 250 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 251 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 252 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 253 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 254 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 255 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 256 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 257 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 258 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 259 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 260 | * |
<> | 144:ef7eb2e8f9f7 | 261 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 262 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 263 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 264 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 265 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 266 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 267 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 268 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 269 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 270 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 271 | * |
<> | 144:ef7eb2e8f9f7 | 272 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 273 | */ |
<> | 144:ef7eb2e8f9f7 | 274 | |
<> | 144:ef7eb2e8f9f7 | 275 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 276 | #include "stm32f1xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 277 | |
<> | 144:ef7eb2e8f9f7 | 278 | /** @addtogroup STM32F1xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 279 | * @{ |
<> | 144:ef7eb2e8f9f7 | 280 | */ |
<> | 144:ef7eb2e8f9f7 | 281 | |
<> | 144:ef7eb2e8f9f7 | 282 | /** @defgroup ADC ADC |
<> | 144:ef7eb2e8f9f7 | 283 | * @brief ADC HAL module driver |
<> | 144:ef7eb2e8f9f7 | 284 | * @{ |
<> | 144:ef7eb2e8f9f7 | 285 | */ |
<> | 144:ef7eb2e8f9f7 | 286 | |
<> | 144:ef7eb2e8f9f7 | 287 | #ifdef HAL_ADC_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 288 | |
<> | 144:ef7eb2e8f9f7 | 289 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 290 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 291 | /** @defgroup ADC_Private_Constants ADC Private Constants |
<> | 144:ef7eb2e8f9f7 | 292 | * @{ |
<> | 144:ef7eb2e8f9f7 | 293 | */ |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | /* Timeout values for ADC enable and disable settling time. */ |
<> | 144:ef7eb2e8f9f7 | 296 | /* Values defined to be higher than worst cases: low clocks freq, */ |
<> | 144:ef7eb2e8f9f7 | 297 | /* maximum prescaler. */ |
<> | 144:ef7eb2e8f9f7 | 298 | /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ |
<> | 144:ef7eb2e8f9f7 | 299 | /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ |
<> | 144:ef7eb2e8f9f7 | 300 | /* Unit: ms */ |
AnnaBridge | 165:e614a9f1c9e2 | 301 | #define ADC_ENABLE_TIMEOUT 2U |
AnnaBridge | 165:e614a9f1c9e2 | 302 | #define ADC_DISABLE_TIMEOUT 2U |
<> | 144:ef7eb2e8f9f7 | 303 | |
<> | 144:ef7eb2e8f9f7 | 304 | /* Delay for ADC stabilization time. */ |
<> | 144:ef7eb2e8f9f7 | 305 | /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ |
<> | 144:ef7eb2e8f9f7 | 306 | /* Unit: us */ |
AnnaBridge | 165:e614a9f1c9e2 | 307 | #define ADC_STAB_DELAY_US 1U |
<> | 144:ef7eb2e8f9f7 | 308 | |
<> | 144:ef7eb2e8f9f7 | 309 | /* Delay for temperature sensor stabilization time. */ |
<> | 144:ef7eb2e8f9f7 | 310 | /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ |
<> | 144:ef7eb2e8f9f7 | 311 | /* Unit: us */ |
AnnaBridge | 165:e614a9f1c9e2 | 312 | #define ADC_TEMPSENSOR_DELAY_US 10U |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | /** |
<> | 144:ef7eb2e8f9f7 | 315 | * @} |
<> | 144:ef7eb2e8f9f7 | 316 | */ |
<> | 144:ef7eb2e8f9f7 | 317 | |
<> | 144:ef7eb2e8f9f7 | 318 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 319 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 320 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 321 | /** @defgroup ADC_Private_Functions ADC Private Functions |
<> | 144:ef7eb2e8f9f7 | 322 | * @{ |
<> | 144:ef7eb2e8f9f7 | 323 | */ |
<> | 144:ef7eb2e8f9f7 | 324 | /** |
<> | 144:ef7eb2e8f9f7 | 325 | * @} |
<> | 144:ef7eb2e8f9f7 | 326 | */ |
<> | 144:ef7eb2e8f9f7 | 327 | |
<> | 144:ef7eb2e8f9f7 | 328 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | /** @defgroup ADC_Exported_Functions ADC Exported Functions |
<> | 144:ef7eb2e8f9f7 | 331 | * @{ |
<> | 144:ef7eb2e8f9f7 | 332 | */ |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 335 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 336 | * |
<> | 144:ef7eb2e8f9f7 | 337 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 338 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 339 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 340 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 341 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 342 | (+) Initialize and configure the ADC. |
<> | 144:ef7eb2e8f9f7 | 343 | (+) De-initialize the ADC. |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 346 | * @{ |
<> | 144:ef7eb2e8f9f7 | 347 | */ |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | /** |
<> | 144:ef7eb2e8f9f7 | 350 | * @brief Initializes the ADC peripheral and regular group according to |
<> | 144:ef7eb2e8f9f7 | 351 | * parameters specified in structure "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 352 | * @note As prerequisite, ADC clock must be configured at RCC top level |
<> | 144:ef7eb2e8f9f7 | 353 | * (clock source APB2). |
<> | 144:ef7eb2e8f9f7 | 354 | * See commented example code below that can be copied and uncommented |
<> | 144:ef7eb2e8f9f7 | 355 | * into HAL_ADC_MspInit(). |
<> | 144:ef7eb2e8f9f7 | 356 | * @note Possibility to update parameters on the fly: |
<> | 144:ef7eb2e8f9f7 | 357 | * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when |
<> | 144:ef7eb2e8f9f7 | 358 | * coming from ADC state reset. Following calls to this function can |
<> | 144:ef7eb2e8f9f7 | 359 | * be used to reconfigure some parameters of ADC_InitTypeDef |
<> | 144:ef7eb2e8f9f7 | 360 | * structure on the fly, without modifying MSP configuration. If ADC |
<> | 144:ef7eb2e8f9f7 | 361 | * MSP has to be modified again, HAL_ADC_DeInit() must be called |
<> | 144:ef7eb2e8f9f7 | 362 | * before HAL_ADC_Init(). |
<> | 144:ef7eb2e8f9f7 | 363 | * The setting of these parameters is conditioned to ADC state. |
<> | 144:ef7eb2e8f9f7 | 364 | * For parameters constraints, see comments of structure |
<> | 144:ef7eb2e8f9f7 | 365 | * "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 366 | * @note This function configures the ADC within 2 scopes: scope of entire |
<> | 144:ef7eb2e8f9f7 | 367 | * ADC and scope of regular group. For parameters details, see comments |
<> | 144:ef7eb2e8f9f7 | 368 | * of structure "ADC_InitTypeDef". |
<> | 144:ef7eb2e8f9f7 | 369 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 370 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 371 | */ |
<> | 144:ef7eb2e8f9f7 | 372 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 373 | { |
<> | 144:ef7eb2e8f9f7 | 374 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
AnnaBridge | 165:e614a9f1c9e2 | 375 | uint32_t tmp_cr1 = 0U; |
AnnaBridge | 165:e614a9f1c9e2 | 376 | uint32_t tmp_cr2 = 0U; |
AnnaBridge | 165:e614a9f1c9e2 | 377 | uint32_t tmp_sqr1 = 0U; |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 144:ef7eb2e8f9f7 | 379 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 380 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 381 | { |
<> | 144:ef7eb2e8f9f7 | 382 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 383 | } |
<> | 144:ef7eb2e8f9f7 | 384 | |
<> | 144:ef7eb2e8f9f7 | 385 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 386 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 387 | assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); |
<> | 144:ef7eb2e8f9f7 | 388 | assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); |
<> | 144:ef7eb2e8f9f7 | 389 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 390 | assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); |
<> | 144:ef7eb2e8f9f7 | 391 | |
<> | 144:ef7eb2e8f9f7 | 392 | if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) |
<> | 144:ef7eb2e8f9f7 | 393 | { |
<> | 144:ef7eb2e8f9f7 | 394 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
<> | 144:ef7eb2e8f9f7 | 395 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 396 | if(hadc->Init.DiscontinuousConvMode != DISABLE) |
<> | 144:ef7eb2e8f9f7 | 397 | { |
<> | 144:ef7eb2e8f9f7 | 398 | assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); |
<> | 144:ef7eb2e8f9f7 | 399 | } |
<> | 144:ef7eb2e8f9f7 | 400 | } |
<> | 144:ef7eb2e8f9f7 | 401 | |
<> | 144:ef7eb2e8f9f7 | 402 | /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */ |
<> | 144:ef7eb2e8f9f7 | 403 | /* at RCC top level. */ |
<> | 144:ef7eb2e8f9f7 | 404 | /* Refer to header of this file for more details on clock enabling */ |
<> | 144:ef7eb2e8f9f7 | 405 | /* procedure. */ |
<> | 144:ef7eb2e8f9f7 | 406 | |
<> | 144:ef7eb2e8f9f7 | 407 | /* Actions performed only if ADC is coming from state reset: */ |
<> | 144:ef7eb2e8f9f7 | 408 | /* - Initialization of ADC MSP */ |
<> | 144:ef7eb2e8f9f7 | 409 | if (hadc->State == HAL_ADC_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 410 | { |
<> | 144:ef7eb2e8f9f7 | 411 | /* Initialize ADC error code */ |
<> | 144:ef7eb2e8f9f7 | 412 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 413 | |
<> | 144:ef7eb2e8f9f7 | 414 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 415 | hadc->Lock = HAL_UNLOCKED; |
<> | 144:ef7eb2e8f9f7 | 416 | |
<> | 144:ef7eb2e8f9f7 | 417 | /* Init the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 418 | HAL_ADC_MspInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 419 | } |
<> | 144:ef7eb2e8f9f7 | 420 | |
<> | 144:ef7eb2e8f9f7 | 421 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 422 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 423 | /* Note: In case of ADC already enabled, precaution to not launch an */ |
<> | 144:ef7eb2e8f9f7 | 424 | /* unwanted conversion while modifying register CR2 by writing 1 to */ |
<> | 144:ef7eb2e8f9f7 | 425 | /* bit ADON. */ |
<> | 144:ef7eb2e8f9f7 | 426 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 427 | |
<> | 144:ef7eb2e8f9f7 | 428 | |
<> | 144:ef7eb2e8f9f7 | 429 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 430 | /* correctly completed. */ |
<> | 144:ef7eb2e8f9f7 | 431 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) && |
<> | 144:ef7eb2e8f9f7 | 432 | (tmp_hal_status == HAL_OK) ) |
<> | 144:ef7eb2e8f9f7 | 433 | { |
<> | 144:ef7eb2e8f9f7 | 434 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 435 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 436 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 437 | HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 438 | |
<> | 144:ef7eb2e8f9f7 | 439 | /* Set ADC parameters */ |
<> | 144:ef7eb2e8f9f7 | 440 | |
<> | 144:ef7eb2e8f9f7 | 441 | /* Configuration of ADC: */ |
<> | 144:ef7eb2e8f9f7 | 442 | /* - data alignment */ |
<> | 144:ef7eb2e8f9f7 | 443 | /* - external trigger to start conversion */ |
<> | 144:ef7eb2e8f9f7 | 444 | /* - external trigger polarity (always set to 1, because needed for all */ |
<> | 144:ef7eb2e8f9f7 | 445 | /* triggers: external trigger of SW start) */ |
<> | 144:ef7eb2e8f9f7 | 446 | /* - continuous conversion mode */ |
<> | 144:ef7eb2e8f9f7 | 447 | /* Note: External trigger polarity (ADC_CR2_EXTTRIG) is set into */ |
<> | 144:ef7eb2e8f9f7 | 448 | /* HAL_ADC_Start_xxx functions because if set in this function, */ |
<> | 144:ef7eb2e8f9f7 | 449 | /* a conversion on injected group would start a conversion also on */ |
<> | 144:ef7eb2e8f9f7 | 450 | /* regular group after ADC enabling. */ |
<> | 144:ef7eb2e8f9f7 | 451 | tmp_cr2 |= (hadc->Init.DataAlign | |
<> | 144:ef7eb2e8f9f7 | 452 | ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) | |
<> | 144:ef7eb2e8f9f7 | 453 | ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) ); |
<> | 144:ef7eb2e8f9f7 | 454 | |
<> | 144:ef7eb2e8f9f7 | 455 | /* Configuration of ADC: */ |
<> | 144:ef7eb2e8f9f7 | 456 | /* - scan mode */ |
<> | 144:ef7eb2e8f9f7 | 457 | /* - discontinuous mode disable/enable */ |
<> | 144:ef7eb2e8f9f7 | 458 | /* - discontinuous mode number of conversions */ |
<> | 144:ef7eb2e8f9f7 | 459 | tmp_cr1 |= (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode)); |
<> | 144:ef7eb2e8f9f7 | 460 | |
<> | 144:ef7eb2e8f9f7 | 461 | /* Enable discontinuous mode only if continuous mode is disabled */ |
<> | 144:ef7eb2e8f9f7 | 462 | /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */ |
<> | 144:ef7eb2e8f9f7 | 463 | /* discontinuous is set anyway, but will have no effect on ADC HW. */ |
<> | 144:ef7eb2e8f9f7 | 464 | if (hadc->Init.DiscontinuousConvMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 465 | { |
<> | 144:ef7eb2e8f9f7 | 466 | if (hadc->Init.ContinuousConvMode == DISABLE) |
<> | 144:ef7eb2e8f9f7 | 467 | { |
<> | 144:ef7eb2e8f9f7 | 468 | /* Enable the selected ADC regular discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 469 | /* Set the number of channels to be converted in discontinuous mode */ |
<> | 144:ef7eb2e8f9f7 | 470 | SET_BIT(tmp_cr1, ADC_CR1_DISCEN | |
<> | 144:ef7eb2e8f9f7 | 471 | ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) ); |
<> | 144:ef7eb2e8f9f7 | 472 | } |
<> | 144:ef7eb2e8f9f7 | 473 | else |
<> | 144:ef7eb2e8f9f7 | 474 | { |
<> | 144:ef7eb2e8f9f7 | 475 | /* ADC regular group settings continuous and sequencer discontinuous*/ |
<> | 144:ef7eb2e8f9f7 | 476 | /* cannot be enabled simultaneously. */ |
<> | 144:ef7eb2e8f9f7 | 477 | |
<> | 144:ef7eb2e8f9f7 | 478 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 479 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 480 | |
<> | 144:ef7eb2e8f9f7 | 481 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 482 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 483 | } |
<> | 144:ef7eb2e8f9f7 | 484 | } |
<> | 144:ef7eb2e8f9f7 | 485 | |
<> | 144:ef7eb2e8f9f7 | 486 | /* Update ADC configuration register CR1 with previous settings */ |
<> | 144:ef7eb2e8f9f7 | 487 | MODIFY_REG(hadc->Instance->CR1, |
<> | 144:ef7eb2e8f9f7 | 488 | ADC_CR1_SCAN | |
<> | 144:ef7eb2e8f9f7 | 489 | ADC_CR1_DISCEN | |
<> | 144:ef7eb2e8f9f7 | 490 | ADC_CR1_DISCNUM , |
<> | 144:ef7eb2e8f9f7 | 491 | tmp_cr1 ); |
<> | 144:ef7eb2e8f9f7 | 492 | |
<> | 144:ef7eb2e8f9f7 | 493 | /* Update ADC configuration register CR2 with previous settings */ |
<> | 144:ef7eb2e8f9f7 | 494 | MODIFY_REG(hadc->Instance->CR2, |
<> | 144:ef7eb2e8f9f7 | 495 | ADC_CR2_ALIGN | |
<> | 144:ef7eb2e8f9f7 | 496 | ADC_CR2_EXTSEL | |
<> | 144:ef7eb2e8f9f7 | 497 | ADC_CR2_EXTTRIG | |
<> | 144:ef7eb2e8f9f7 | 498 | ADC_CR2_CONT , |
<> | 144:ef7eb2e8f9f7 | 499 | tmp_cr2 ); |
<> | 144:ef7eb2e8f9f7 | 500 | |
<> | 144:ef7eb2e8f9f7 | 501 | /* Configuration of regular group sequencer: */ |
<> | 144:ef7eb2e8f9f7 | 502 | /* - if scan mode is disabled, regular channels sequence length is set to */ |
<> | 144:ef7eb2e8f9f7 | 503 | /* 0x00: 1 channel converted (channel on regular rank 1) */ |
<> | 144:ef7eb2e8f9f7 | 504 | /* Parameter "NbrOfConversion" is discarded. */ |
<> | 144:ef7eb2e8f9f7 | 505 | /* Note: Scan mode is present by hardware on this device and, if */ |
<> | 144:ef7eb2e8f9f7 | 506 | /* disabled, discards automatically nb of conversions. Anyway, nb of */ |
<> | 144:ef7eb2e8f9f7 | 507 | /* conversions is forced to 0x00 for alignment over all STM32 devices. */ |
<> | 144:ef7eb2e8f9f7 | 508 | /* - if scan mode is enabled, regular channels sequence length is set to */ |
<> | 144:ef7eb2e8f9f7 | 509 | /* parameter "NbrOfConversion" */ |
<> | 144:ef7eb2e8f9f7 | 510 | if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 511 | { |
<> | 144:ef7eb2e8f9f7 | 512 | tmp_sqr1 = ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion); |
<> | 144:ef7eb2e8f9f7 | 513 | } |
<> | 144:ef7eb2e8f9f7 | 514 | |
<> | 144:ef7eb2e8f9f7 | 515 | MODIFY_REG(hadc->Instance->SQR1, |
<> | 144:ef7eb2e8f9f7 | 516 | ADC_SQR1_L , |
<> | 144:ef7eb2e8f9f7 | 517 | tmp_sqr1 ); |
<> | 144:ef7eb2e8f9f7 | 518 | |
<> | 144:ef7eb2e8f9f7 | 519 | /* Check back that ADC registers have effectively been configured to */ |
<> | 144:ef7eb2e8f9f7 | 520 | /* ensure of no potential problem of ADC core IP clocking. */ |
<> | 144:ef7eb2e8f9f7 | 521 | /* Check through register CR2 (excluding bits set in other functions: */ |
<> | 144:ef7eb2e8f9f7 | 522 | /* execution control bits (ADON, JSWSTART, SWSTART), regular group bits */ |
<> | 144:ef7eb2e8f9f7 | 523 | /* (DMA), injected group bits (JEXTTRIG and JEXTSEL), channel internal */ |
<> | 144:ef7eb2e8f9f7 | 524 | /* measurement path bit (TSVREFE). */ |
<> | 144:ef7eb2e8f9f7 | 525 | if (READ_BIT(hadc->Instance->CR2, ~(ADC_CR2_ADON | ADC_CR2_DMA | |
<> | 144:ef7eb2e8f9f7 | 526 | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
<> | 144:ef7eb2e8f9f7 | 527 | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL | |
<> | 144:ef7eb2e8f9f7 | 528 | ADC_CR2_TSVREFE )) |
<> | 144:ef7eb2e8f9f7 | 529 | == tmp_cr2) |
<> | 144:ef7eb2e8f9f7 | 530 | { |
<> | 144:ef7eb2e8f9f7 | 531 | /* Set ADC error code to none */ |
<> | 144:ef7eb2e8f9f7 | 532 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | /* Set the ADC state */ |
<> | 144:ef7eb2e8f9f7 | 535 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 536 | HAL_ADC_STATE_BUSY_INTERNAL, |
<> | 144:ef7eb2e8f9f7 | 537 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 538 | } |
<> | 144:ef7eb2e8f9f7 | 539 | else |
<> | 144:ef7eb2e8f9f7 | 540 | { |
<> | 144:ef7eb2e8f9f7 | 541 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 542 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 543 | HAL_ADC_STATE_BUSY_INTERNAL, |
<> | 144:ef7eb2e8f9f7 | 544 | HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 545 | |
<> | 144:ef7eb2e8f9f7 | 546 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 547 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 548 | |
<> | 144:ef7eb2e8f9f7 | 549 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 550 | } |
<> | 144:ef7eb2e8f9f7 | 551 | |
<> | 144:ef7eb2e8f9f7 | 552 | } |
<> | 144:ef7eb2e8f9f7 | 553 | else |
<> | 144:ef7eb2e8f9f7 | 554 | { |
<> | 144:ef7eb2e8f9f7 | 555 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 556 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 557 | |
<> | 144:ef7eb2e8f9f7 | 558 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 559 | } |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 562 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 563 | } |
<> | 144:ef7eb2e8f9f7 | 564 | |
<> | 144:ef7eb2e8f9f7 | 565 | /** |
<> | 144:ef7eb2e8f9f7 | 566 | * @brief Deinitialize the ADC peripheral registers to their default reset |
<> | 144:ef7eb2e8f9f7 | 567 | * values, with deinitialization of the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 568 | * If needed, the example code can be copied and uncommented into |
<> | 144:ef7eb2e8f9f7 | 569 | * function HAL_ADC_MspDeInit(). |
<> | 144:ef7eb2e8f9f7 | 570 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 571 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 572 | */ |
<> | 144:ef7eb2e8f9f7 | 573 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 574 | { |
<> | 144:ef7eb2e8f9f7 | 575 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 576 | |
<> | 144:ef7eb2e8f9f7 | 577 | /* Check ADC handle */ |
<> | 144:ef7eb2e8f9f7 | 578 | if(hadc == NULL) |
<> | 144:ef7eb2e8f9f7 | 579 | { |
<> | 144:ef7eb2e8f9f7 | 580 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 581 | } |
<> | 144:ef7eb2e8f9f7 | 582 | |
<> | 144:ef7eb2e8f9f7 | 583 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 584 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 585 | |
<> | 144:ef7eb2e8f9f7 | 586 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 587 | SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 588 | |
<> | 144:ef7eb2e8f9f7 | 589 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 590 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 591 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 592 | |
<> | 144:ef7eb2e8f9f7 | 593 | |
<> | 144:ef7eb2e8f9f7 | 594 | /* Configuration of ADC parameters if previous preliminary actions are */ |
<> | 144:ef7eb2e8f9f7 | 595 | /* correctly completed. */ |
<> | 144:ef7eb2e8f9f7 | 596 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 597 | { |
<> | 144:ef7eb2e8f9f7 | 598 | /* ========== Reset ADC registers ========== */ |
<> | 144:ef7eb2e8f9f7 | 599 | |
<> | 144:ef7eb2e8f9f7 | 600 | |
<> | 144:ef7eb2e8f9f7 | 601 | |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | /* Reset register SR */ |
<> | 144:ef7eb2e8f9f7 | 604 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC | |
<> | 144:ef7eb2e8f9f7 | 605 | ADC_FLAG_JSTRT | ADC_FLAG_STRT)); |
<> | 144:ef7eb2e8f9f7 | 606 | |
<> | 144:ef7eb2e8f9f7 | 607 | /* Reset register CR1 */ |
<> | 144:ef7eb2e8f9f7 | 608 | CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | |
<> | 144:ef7eb2e8f9f7 | 609 | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | |
<> | 144:ef7eb2e8f9f7 | 610 | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | |
<> | 144:ef7eb2e8f9f7 | 611 | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )); |
<> | 144:ef7eb2e8f9f7 | 612 | |
<> | 144:ef7eb2e8f9f7 | 613 | /* Reset register CR2 */ |
<> | 144:ef7eb2e8f9f7 | 614 | CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART | |
<> | 144:ef7eb2e8f9f7 | 615 | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG | |
<> | 144:ef7eb2e8f9f7 | 616 | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA | |
<> | 144:ef7eb2e8f9f7 | 617 | ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT | |
<> | 144:ef7eb2e8f9f7 | 618 | ADC_CR2_ADON )); |
<> | 144:ef7eb2e8f9f7 | 619 | |
<> | 144:ef7eb2e8f9f7 | 620 | /* Reset register SMPR1 */ |
<> | 144:ef7eb2e8f9f7 | 621 | CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | |
<> | 144:ef7eb2e8f9f7 | 622 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | |
<> | 144:ef7eb2e8f9f7 | 623 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10 )); |
<> | 144:ef7eb2e8f9f7 | 624 | |
<> | 144:ef7eb2e8f9f7 | 625 | /* Reset register SMPR2 */ |
<> | 144:ef7eb2e8f9f7 | 626 | CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | |
<> | 144:ef7eb2e8f9f7 | 627 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | |
<> | 144:ef7eb2e8f9f7 | 628 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | |
<> | 144:ef7eb2e8f9f7 | 629 | ADC_SMPR2_SMP0 )); |
<> | 144:ef7eb2e8f9f7 | 630 | |
<> | 144:ef7eb2e8f9f7 | 631 | /* Reset register JOFR1 */ |
<> | 144:ef7eb2e8f9f7 | 632 | CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1); |
<> | 144:ef7eb2e8f9f7 | 633 | /* Reset register JOFR2 */ |
<> | 144:ef7eb2e8f9f7 | 634 | CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2); |
<> | 144:ef7eb2e8f9f7 | 635 | /* Reset register JOFR3 */ |
<> | 144:ef7eb2e8f9f7 | 636 | CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3); |
<> | 144:ef7eb2e8f9f7 | 637 | /* Reset register JOFR4 */ |
<> | 144:ef7eb2e8f9f7 | 638 | CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4); |
<> | 144:ef7eb2e8f9f7 | 639 | |
<> | 144:ef7eb2e8f9f7 | 640 | /* Reset register HTR */ |
<> | 144:ef7eb2e8f9f7 | 641 | CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT); |
<> | 144:ef7eb2e8f9f7 | 642 | /* Reset register LTR */ |
<> | 144:ef7eb2e8f9f7 | 643 | CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT); |
<> | 144:ef7eb2e8f9f7 | 644 | |
<> | 144:ef7eb2e8f9f7 | 645 | /* Reset register SQR1 */ |
<> | 144:ef7eb2e8f9f7 | 646 | CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | |
<> | 144:ef7eb2e8f9f7 | 647 | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | |
<> | 144:ef7eb2e8f9f7 | 648 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); |
<> | 144:ef7eb2e8f9f7 | 649 | |
<> | 144:ef7eb2e8f9f7 | 650 | /* Reset register SQR1 */ |
<> | 144:ef7eb2e8f9f7 | 651 | CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L | |
<> | 144:ef7eb2e8f9f7 | 652 | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | |
<> | 144:ef7eb2e8f9f7 | 653 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13 ); |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | /* Reset register SQR2 */ |
<> | 144:ef7eb2e8f9f7 | 656 | CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | |
<> | 144:ef7eb2e8f9f7 | 657 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 ); |
<> | 144:ef7eb2e8f9f7 | 658 | |
<> | 144:ef7eb2e8f9f7 | 659 | /* Reset register SQR3 */ |
<> | 144:ef7eb2e8f9f7 | 660 | CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 | |
<> | 144:ef7eb2e8f9f7 | 661 | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 ); |
<> | 144:ef7eb2e8f9f7 | 662 | |
<> | 144:ef7eb2e8f9f7 | 663 | /* Reset register JSQR */ |
<> | 144:ef7eb2e8f9f7 | 664 | CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | |
<> | 144:ef7eb2e8f9f7 | 665 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
<> | 144:ef7eb2e8f9f7 | 666 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); |
<> | 144:ef7eb2e8f9f7 | 667 | |
<> | 144:ef7eb2e8f9f7 | 668 | /* Reset register JSQR */ |
<> | 144:ef7eb2e8f9f7 | 669 | CLEAR_BIT(hadc->Instance->JSQR, ADC_JSQR_JL | |
<> | 144:ef7eb2e8f9f7 | 670 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | |
<> | 144:ef7eb2e8f9f7 | 671 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ); |
<> | 144:ef7eb2e8f9f7 | 672 | |
<> | 144:ef7eb2e8f9f7 | 673 | /* Reset register DR */ |
<> | 144:ef7eb2e8f9f7 | 674 | /* bits in access mode read only, no direct reset applicable*/ |
<> | 144:ef7eb2e8f9f7 | 675 | |
<> | 144:ef7eb2e8f9f7 | 676 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
<> | 144:ef7eb2e8f9f7 | 677 | /* bits in access mode read only, no direct reset applicable*/ |
<> | 144:ef7eb2e8f9f7 | 678 | |
<> | 144:ef7eb2e8f9f7 | 679 | /* ========== Hard reset ADC peripheral ========== */ |
<> | 144:ef7eb2e8f9f7 | 680 | /* Performs a global reset of the entire ADC peripheral: ADC state is */ |
<> | 144:ef7eb2e8f9f7 | 681 | /* forced to a similar state after device power-on. */ |
<> | 144:ef7eb2e8f9f7 | 682 | /* If needed, copy-paste and uncomment the following reset code into */ |
<> | 144:ef7eb2e8f9f7 | 683 | /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */ |
<> | 144:ef7eb2e8f9f7 | 684 | /* */ |
<> | 144:ef7eb2e8f9f7 | 685 | /* __HAL_RCC_ADC1_FORCE_RESET() */ |
<> | 144:ef7eb2e8f9f7 | 686 | /* __HAL_RCC_ADC1_RELEASE_RESET() */ |
<> | 144:ef7eb2e8f9f7 | 687 | |
<> | 144:ef7eb2e8f9f7 | 688 | /* DeInit the low level hardware */ |
<> | 144:ef7eb2e8f9f7 | 689 | HAL_ADC_MspDeInit(hadc); |
<> | 144:ef7eb2e8f9f7 | 690 | |
<> | 144:ef7eb2e8f9f7 | 691 | /* Set ADC error code to none */ |
<> | 144:ef7eb2e8f9f7 | 692 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 693 | |
<> | 144:ef7eb2e8f9f7 | 694 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 695 | hadc->State = HAL_ADC_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 696 | |
<> | 144:ef7eb2e8f9f7 | 697 | } |
<> | 144:ef7eb2e8f9f7 | 698 | |
<> | 144:ef7eb2e8f9f7 | 699 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 700 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 701 | |
<> | 144:ef7eb2e8f9f7 | 702 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 703 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 704 | } |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | /** |
<> | 144:ef7eb2e8f9f7 | 707 | * @brief Initializes the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 708 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 709 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 710 | */ |
<> | 144:ef7eb2e8f9f7 | 711 | __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 712 | { |
<> | 144:ef7eb2e8f9f7 | 713 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 714 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 715 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 716 | function HAL_ADC_MspInit must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 717 | */ |
<> | 144:ef7eb2e8f9f7 | 718 | } |
<> | 144:ef7eb2e8f9f7 | 719 | |
<> | 144:ef7eb2e8f9f7 | 720 | /** |
<> | 144:ef7eb2e8f9f7 | 721 | * @brief DeInitializes the ADC MSP. |
<> | 144:ef7eb2e8f9f7 | 722 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 723 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 724 | */ |
<> | 144:ef7eb2e8f9f7 | 725 | __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 726 | { |
<> | 144:ef7eb2e8f9f7 | 727 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 728 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 729 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 730 | function HAL_ADC_MspDeInit must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 731 | */ |
<> | 144:ef7eb2e8f9f7 | 732 | } |
<> | 144:ef7eb2e8f9f7 | 733 | |
<> | 144:ef7eb2e8f9f7 | 734 | /** |
<> | 144:ef7eb2e8f9f7 | 735 | * @} |
<> | 144:ef7eb2e8f9f7 | 736 | */ |
<> | 144:ef7eb2e8f9f7 | 737 | |
<> | 144:ef7eb2e8f9f7 | 738 | /** @defgroup ADC_Exported_Functions_Group2 IO operation functions |
<> | 144:ef7eb2e8f9f7 | 739 | * @brief Input and Output operation functions |
<> | 144:ef7eb2e8f9f7 | 740 | * |
<> | 144:ef7eb2e8f9f7 | 741 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 742 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 743 | ##### IO operation functions ##### |
<> | 144:ef7eb2e8f9f7 | 744 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 745 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 746 | (+) Start conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 747 | (+) Stop conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 748 | (+) Poll for conversion complete on regular group. |
<> | 144:ef7eb2e8f9f7 | 749 | (+) Poll for conversion event. |
<> | 144:ef7eb2e8f9f7 | 750 | (+) Get result of regular channel conversion. |
<> | 144:ef7eb2e8f9f7 | 751 | (+) Start conversion of regular group and enable interruptions. |
<> | 144:ef7eb2e8f9f7 | 752 | (+) Stop conversion of regular group and disable interruptions. |
<> | 144:ef7eb2e8f9f7 | 753 | (+) Handle ADC interrupt request |
<> | 144:ef7eb2e8f9f7 | 754 | (+) Start conversion of regular group and enable DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 755 | (+) Stop conversion of regular group and disable ADC DMA transfer. |
<> | 144:ef7eb2e8f9f7 | 756 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 757 | * @{ |
<> | 144:ef7eb2e8f9f7 | 758 | */ |
<> | 144:ef7eb2e8f9f7 | 759 | |
<> | 144:ef7eb2e8f9f7 | 760 | /** |
<> | 144:ef7eb2e8f9f7 | 761 | * @brief Enables ADC, starts conversion of regular group. |
<> | 144:ef7eb2e8f9f7 | 762 | * Interruptions enabled in this function: None. |
<> | 144:ef7eb2e8f9f7 | 763 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 764 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 765 | */ |
<> | 144:ef7eb2e8f9f7 | 766 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 767 | { |
<> | 144:ef7eb2e8f9f7 | 768 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 769 | |
<> | 144:ef7eb2e8f9f7 | 770 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 771 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 772 | |
<> | 144:ef7eb2e8f9f7 | 773 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 774 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 775 | |
<> | 144:ef7eb2e8f9f7 | 776 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 777 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 778 | |
<> | 144:ef7eb2e8f9f7 | 779 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 780 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 781 | { |
<> | 144:ef7eb2e8f9f7 | 782 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 783 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 784 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 785 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 786 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC, |
<> | 144:ef7eb2e8f9f7 | 787 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 788 | |
<> | 144:ef7eb2e8f9f7 | 789 | /* Set group injected state (from auto-injection) and multimode state */ |
<> | 144:ef7eb2e8f9f7 | 790 | /* for all cases of multimode: independent mode, multimode ADC master */ |
<> | 144:ef7eb2e8f9f7 | 791 | /* or multimode ADC slave (for devices with several ADCs): */ |
<> | 144:ef7eb2e8f9f7 | 792 | if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) |
<> | 144:ef7eb2e8f9f7 | 793 | { |
<> | 144:ef7eb2e8f9f7 | 794 | /* Set ADC state (ADC independent or master) */ |
<> | 144:ef7eb2e8f9f7 | 795 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
<> | 144:ef7eb2e8f9f7 | 796 | |
<> | 144:ef7eb2e8f9f7 | 797 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 798 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 799 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
<> | 144:ef7eb2e8f9f7 | 800 | { |
<> | 144:ef7eb2e8f9f7 | 801 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 802 | } |
<> | 144:ef7eb2e8f9f7 | 803 | } |
<> | 144:ef7eb2e8f9f7 | 804 | else |
<> | 144:ef7eb2e8f9f7 | 805 | { |
<> | 144:ef7eb2e8f9f7 | 806 | /* Set ADC state (ADC slave) */ |
<> | 144:ef7eb2e8f9f7 | 807 | SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
<> | 144:ef7eb2e8f9f7 | 808 | |
<> | 144:ef7eb2e8f9f7 | 809 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 810 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 811 | if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) |
<> | 144:ef7eb2e8f9f7 | 812 | { |
<> | 144:ef7eb2e8f9f7 | 813 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 814 | } |
<> | 144:ef7eb2e8f9f7 | 815 | } |
<> | 144:ef7eb2e8f9f7 | 816 | |
<> | 144:ef7eb2e8f9f7 | 817 | /* State machine update: Check if an injected conversion is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 818 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 819 | { |
<> | 144:ef7eb2e8f9f7 | 820 | /* Reset ADC error code fields related to conversions on group regular */ |
<> | 144:ef7eb2e8f9f7 | 821 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
<> | 144:ef7eb2e8f9f7 | 822 | } |
<> | 144:ef7eb2e8f9f7 | 823 | else |
<> | 144:ef7eb2e8f9f7 | 824 | { |
<> | 144:ef7eb2e8f9f7 | 825 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 826 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 827 | } |
<> | 144:ef7eb2e8f9f7 | 828 | |
<> | 144:ef7eb2e8f9f7 | 829 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 830 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 831 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 832 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 833 | |
<> | 144:ef7eb2e8f9f7 | 834 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 835 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
<> | 144:ef7eb2e8f9f7 | 836 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 837 | |
<> | 144:ef7eb2e8f9f7 | 838 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 839 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 840 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 841 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 842 | /* Case of multimode enabled: */ |
<> | 144:ef7eb2e8f9f7 | 843 | /* - if ADC is slave, ADC is enabled only (conversion is not started). */ |
<> | 144:ef7eb2e8f9f7 | 844 | /* - if ADC is master, ADC is enabled and conversion is started. */ |
<> | 144:ef7eb2e8f9f7 | 845 | /* If ADC is master, ADC is enabled and conversion is started. */ |
<> | 144:ef7eb2e8f9f7 | 846 | /* Note: Alternate trigger for single conversion could be to force an */ |
<> | 144:ef7eb2e8f9f7 | 847 | /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ |
<> | 144:ef7eb2e8f9f7 | 848 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 849 | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
<> | 144:ef7eb2e8f9f7 | 850 | { |
<> | 144:ef7eb2e8f9f7 | 851 | /* Start ADC conversion on regular group with SW start */ |
<> | 144:ef7eb2e8f9f7 | 852 | SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); |
<> | 144:ef7eb2e8f9f7 | 853 | } |
<> | 144:ef7eb2e8f9f7 | 854 | else |
<> | 144:ef7eb2e8f9f7 | 855 | { |
<> | 144:ef7eb2e8f9f7 | 856 | /* Start ADC conversion on regular group with external trigger */ |
<> | 144:ef7eb2e8f9f7 | 857 | SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); |
<> | 144:ef7eb2e8f9f7 | 858 | } |
<> | 144:ef7eb2e8f9f7 | 859 | } |
<> | 144:ef7eb2e8f9f7 | 860 | else |
<> | 144:ef7eb2e8f9f7 | 861 | { |
<> | 144:ef7eb2e8f9f7 | 862 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 863 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 864 | } |
<> | 144:ef7eb2e8f9f7 | 865 | |
<> | 144:ef7eb2e8f9f7 | 866 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 867 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 868 | } |
<> | 144:ef7eb2e8f9f7 | 869 | |
<> | 144:ef7eb2e8f9f7 | 870 | /** |
<> | 144:ef7eb2e8f9f7 | 871 | * @brief Stop ADC conversion of regular group (and injected channels in |
<> | 144:ef7eb2e8f9f7 | 872 | * case of auto_injection mode), disable ADC peripheral. |
<> | 144:ef7eb2e8f9f7 | 873 | * @note: ADC peripheral disable is forcing stop of potential |
<> | 144:ef7eb2e8f9f7 | 874 | * conversion on injected group. If injected group is under use, it |
<> | 144:ef7eb2e8f9f7 | 875 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
<> | 144:ef7eb2e8f9f7 | 876 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 877 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 878 | */ |
<> | 144:ef7eb2e8f9f7 | 879 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 880 | { |
<> | 144:ef7eb2e8f9f7 | 881 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 882 | |
<> | 144:ef7eb2e8f9f7 | 883 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 884 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 885 | |
<> | 144:ef7eb2e8f9f7 | 886 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 887 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 888 | |
<> | 144:ef7eb2e8f9f7 | 889 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 890 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 891 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 892 | |
<> | 144:ef7eb2e8f9f7 | 893 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 894 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 895 | { |
<> | 144:ef7eb2e8f9f7 | 896 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 897 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 898 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 899 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 900 | } |
<> | 144:ef7eb2e8f9f7 | 901 | |
<> | 144:ef7eb2e8f9f7 | 902 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 903 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 904 | |
<> | 144:ef7eb2e8f9f7 | 905 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 906 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 907 | } |
<> | 144:ef7eb2e8f9f7 | 908 | |
<> | 144:ef7eb2e8f9f7 | 909 | /** |
<> | 144:ef7eb2e8f9f7 | 910 | * @brief Wait for regular group conversion to be completed. |
<> | 144:ef7eb2e8f9f7 | 911 | * @note This function cannot be used in a particular setup: ADC configured |
<> | 144:ef7eb2e8f9f7 | 912 | * in DMA mode. |
<> | 144:ef7eb2e8f9f7 | 913 | * In this case, DMA resets the flag EOC and polling cannot be |
<> | 144:ef7eb2e8f9f7 | 914 | * performed on each conversion. |
<> | 144:ef7eb2e8f9f7 | 915 | * @note On STM32F1 devices, limitation in case of sequencer enabled |
<> | 144:ef7eb2e8f9f7 | 916 | * (several ranks selected): polling cannot be done on each |
<> | 144:ef7eb2e8f9f7 | 917 | * conversion inside the sequence. In this case, polling is replaced by |
<> | 144:ef7eb2e8f9f7 | 918 | * wait for maximum conversion time. |
<> | 144:ef7eb2e8f9f7 | 919 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 920 | * @param Timeout: Timeout value in millisecond. |
<> | 144:ef7eb2e8f9f7 | 921 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 922 | */ |
<> | 144:ef7eb2e8f9f7 | 923 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 924 | { |
AnnaBridge | 165:e614a9f1c9e2 | 925 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 926 | |
<> | 144:ef7eb2e8f9f7 | 927 | /* Variables for polling in case of scan mode enabled and polling for each */ |
<> | 144:ef7eb2e8f9f7 | 928 | /* conversion. */ |
AnnaBridge | 165:e614a9f1c9e2 | 929 | __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; |
AnnaBridge | 165:e614a9f1c9e2 | 930 | uint32_t Conversion_Timeout_CPU_cycles_max = 0U; |
<> | 144:ef7eb2e8f9f7 | 931 | |
<> | 144:ef7eb2e8f9f7 | 932 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 933 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 934 | |
<> | 144:ef7eb2e8f9f7 | 935 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 936 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 937 | |
<> | 144:ef7eb2e8f9f7 | 938 | /* Verification that ADC configuration is compliant with polling for */ |
<> | 144:ef7eb2e8f9f7 | 939 | /* each conversion: */ |
<> | 144:ef7eb2e8f9f7 | 940 | /* Particular case is ADC configured in DMA mode */ |
<> | 144:ef7eb2e8f9f7 | 941 | if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) |
<> | 144:ef7eb2e8f9f7 | 942 | { |
<> | 144:ef7eb2e8f9f7 | 943 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 944 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 945 | |
<> | 144:ef7eb2e8f9f7 | 946 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 947 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 948 | |
<> | 144:ef7eb2e8f9f7 | 949 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 950 | } |
<> | 144:ef7eb2e8f9f7 | 951 | |
<> | 144:ef7eb2e8f9f7 | 952 | /* Polling for end of conversion: differentiation if single/sequence */ |
<> | 144:ef7eb2e8f9f7 | 953 | /* conversion. */ |
<> | 144:ef7eb2e8f9f7 | 954 | /* - If single conversion for regular group (Scan mode disabled or enabled */ |
<> | 144:ef7eb2e8f9f7 | 955 | /* with NbrOfConversion =1), flag EOC is used to determine the */ |
<> | 144:ef7eb2e8f9f7 | 956 | /* conversion completion. */ |
<> | 144:ef7eb2e8f9f7 | 957 | /* - If sequence conversion for regular group (scan mode enabled and */ |
<> | 144:ef7eb2e8f9f7 | 958 | /* NbrOfConversion >=2), flag EOC is set only at the end of the */ |
<> | 144:ef7eb2e8f9f7 | 959 | /* sequence. */ |
<> | 144:ef7eb2e8f9f7 | 960 | /* To poll for each conversion, the maximum conversion time is computed */ |
<> | 144:ef7eb2e8f9f7 | 961 | /* from ADC conversion time (selected sampling time + conversion time of */ |
<> | 144:ef7eb2e8f9f7 | 962 | /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ |
<> | 144:ef7eb2e8f9f7 | 963 | /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ |
<> | 144:ef7eb2e8f9f7 | 964 | /* As flag EOC is not set after each conversion, no timeout status can */ |
<> | 144:ef7eb2e8f9f7 | 965 | /* be set. */ |
<> | 144:ef7eb2e8f9f7 | 966 | if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN) && |
<> | 144:ef7eb2e8f9f7 | 967 | HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ) |
<> | 144:ef7eb2e8f9f7 | 968 | { |
<> | 144:ef7eb2e8f9f7 | 969 | /* Wait until End of Conversion flag is raised */ |
<> | 144:ef7eb2e8f9f7 | 970 | while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC)) |
<> | 144:ef7eb2e8f9f7 | 971 | { |
<> | 144:ef7eb2e8f9f7 | 972 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 973 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 974 | { |
AnnaBridge | 165:e614a9f1c9e2 | 975 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 976 | { |
<> | 144:ef7eb2e8f9f7 | 977 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 978 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 979 | |
<> | 144:ef7eb2e8f9f7 | 980 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 981 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 982 | |
<> | 144:ef7eb2e8f9f7 | 983 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 984 | } |
<> | 144:ef7eb2e8f9f7 | 985 | } |
<> | 144:ef7eb2e8f9f7 | 986 | } |
<> | 144:ef7eb2e8f9f7 | 987 | } |
<> | 144:ef7eb2e8f9f7 | 988 | else |
<> | 144:ef7eb2e8f9f7 | 989 | { |
<> | 144:ef7eb2e8f9f7 | 990 | /* Replace polling by wait for maximum conversion time */ |
<> | 144:ef7eb2e8f9f7 | 991 | /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ |
<> | 144:ef7eb2e8f9f7 | 992 | /* and ADC maximum conversion cycles on all channels. */ |
<> | 144:ef7eb2e8f9f7 | 993 | /* - Wait for the expected ADC clock cycles delay */ |
<> | 144:ef7eb2e8f9f7 | 994 | Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock |
<> | 144:ef7eb2e8f9f7 | 995 | / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) |
<> | 144:ef7eb2e8f9f7 | 996 | * ADC_CONVCYCLES_MAX_RANGE(hadc) ); |
<> | 144:ef7eb2e8f9f7 | 997 | |
<> | 144:ef7eb2e8f9f7 | 998 | while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) |
<> | 144:ef7eb2e8f9f7 | 999 | { |
<> | 144:ef7eb2e8f9f7 | 1000 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 1001 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1002 | { |
AnnaBridge | 165:e614a9f1c9e2 | 1003 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1004 | { |
<> | 144:ef7eb2e8f9f7 | 1005 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 1006 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 1007 | |
<> | 144:ef7eb2e8f9f7 | 1008 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1009 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1010 | |
<> | 144:ef7eb2e8f9f7 | 1011 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1012 | } |
<> | 144:ef7eb2e8f9f7 | 1013 | } |
<> | 144:ef7eb2e8f9f7 | 1014 | Conversion_Timeout_CPU_cycles ++; |
<> | 144:ef7eb2e8f9f7 | 1015 | } |
<> | 144:ef7eb2e8f9f7 | 1016 | } |
<> | 144:ef7eb2e8f9f7 | 1017 | |
<> | 144:ef7eb2e8f9f7 | 1018 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 1019 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1020 | |
<> | 144:ef7eb2e8f9f7 | 1021 | /* Update ADC state machine */ |
<> | 144:ef7eb2e8f9f7 | 1022 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1023 | |
<> | 144:ef7eb2e8f9f7 | 1024 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1025 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 1026 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
<> | 144:ef7eb2e8f9f7 | 1027 | /* (several ranks selected), end of conversion flag is raised */ |
<> | 144:ef7eb2e8f9f7 | 1028 | /* at the end of the sequence. */ |
<> | 144:ef7eb2e8f9f7 | 1029 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 1030 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 1031 | { |
<> | 144:ef7eb2e8f9f7 | 1032 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1033 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1034 | |
<> | 144:ef7eb2e8f9f7 | 1035 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 1036 | { |
<> | 144:ef7eb2e8f9f7 | 1037 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1038 | } |
<> | 144:ef7eb2e8f9f7 | 1039 | } |
<> | 144:ef7eb2e8f9f7 | 1040 | |
<> | 144:ef7eb2e8f9f7 | 1041 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1042 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1043 | } |
<> | 144:ef7eb2e8f9f7 | 1044 | |
<> | 144:ef7eb2e8f9f7 | 1045 | /** |
<> | 144:ef7eb2e8f9f7 | 1046 | * @brief Poll for conversion event. |
<> | 144:ef7eb2e8f9f7 | 1047 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1048 | * @param EventType: the ADC event type. |
<> | 144:ef7eb2e8f9f7 | 1049 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 1050 | * @arg ADC_AWD_EVENT: ADC Analog watchdog event. |
<> | 144:ef7eb2e8f9f7 | 1051 | * @param Timeout: Timeout value in millisecond. |
<> | 144:ef7eb2e8f9f7 | 1052 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1053 | */ |
<> | 144:ef7eb2e8f9f7 | 1054 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1055 | { |
AnnaBridge | 165:e614a9f1c9e2 | 1056 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1057 | |
<> | 144:ef7eb2e8f9f7 | 1058 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1059 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1060 | assert_param(IS_ADC_EVENT_TYPE(EventType)); |
<> | 144:ef7eb2e8f9f7 | 1061 | |
<> | 144:ef7eb2e8f9f7 | 1062 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 1063 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1064 | |
<> | 144:ef7eb2e8f9f7 | 1065 | /* Check selected event flag */ |
<> | 144:ef7eb2e8f9f7 | 1066 | while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1067 | { |
<> | 144:ef7eb2e8f9f7 | 1068 | /* Check if timeout is disabled (set to infinite wait) */ |
<> | 144:ef7eb2e8f9f7 | 1069 | if(Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 1070 | { |
AnnaBridge | 165:e614a9f1c9e2 | 1071 | if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 1072 | { |
<> | 144:ef7eb2e8f9f7 | 1073 | /* Update ADC state machine to timeout */ |
<> | 144:ef7eb2e8f9f7 | 1074 | SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); |
<> | 144:ef7eb2e8f9f7 | 1075 | |
<> | 144:ef7eb2e8f9f7 | 1076 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1077 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1078 | |
<> | 144:ef7eb2e8f9f7 | 1079 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1080 | } |
<> | 144:ef7eb2e8f9f7 | 1081 | } |
<> | 144:ef7eb2e8f9f7 | 1082 | } |
<> | 144:ef7eb2e8f9f7 | 1083 | |
<> | 144:ef7eb2e8f9f7 | 1084 | /* Analog watchdog (level out of window) event */ |
<> | 144:ef7eb2e8f9f7 | 1085 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1086 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 1087 | |
<> | 144:ef7eb2e8f9f7 | 1088 | /* Clear ADC analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 1089 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 1090 | |
<> | 144:ef7eb2e8f9f7 | 1091 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1092 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1093 | } |
<> | 144:ef7eb2e8f9f7 | 1094 | |
<> | 144:ef7eb2e8f9f7 | 1095 | /** |
<> | 144:ef7eb2e8f9f7 | 1096 | * @brief Enables ADC, starts conversion of regular group with interruption. |
<> | 144:ef7eb2e8f9f7 | 1097 | * Interruptions enabled in this function: |
<> | 144:ef7eb2e8f9f7 | 1098 | * - EOC (end of conversion of regular group) |
<> | 144:ef7eb2e8f9f7 | 1099 | * Each of these interruptions has its dedicated callback function. |
<> | 144:ef7eb2e8f9f7 | 1100 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1101 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1102 | */ |
<> | 144:ef7eb2e8f9f7 | 1103 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1104 | { |
<> | 144:ef7eb2e8f9f7 | 1105 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1106 | |
<> | 144:ef7eb2e8f9f7 | 1107 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1108 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1109 | |
<> | 144:ef7eb2e8f9f7 | 1110 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1111 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1112 | |
<> | 144:ef7eb2e8f9f7 | 1113 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1114 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1115 | |
<> | 144:ef7eb2e8f9f7 | 1116 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1117 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1118 | { |
<> | 144:ef7eb2e8f9f7 | 1119 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1120 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 1121 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 1122 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1123 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 1124 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1125 | |
<> | 144:ef7eb2e8f9f7 | 1126 | /* Set group injected state (from auto-injection) and multimode state */ |
<> | 144:ef7eb2e8f9f7 | 1127 | /* for all cases of multimode: independent mode, multimode ADC master */ |
<> | 144:ef7eb2e8f9f7 | 1128 | /* or multimode ADC slave (for devices with several ADCs): */ |
<> | 144:ef7eb2e8f9f7 | 1129 | if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) |
<> | 144:ef7eb2e8f9f7 | 1130 | { |
<> | 144:ef7eb2e8f9f7 | 1131 | /* Set ADC state (ADC independent or master) */ |
<> | 144:ef7eb2e8f9f7 | 1132 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
<> | 144:ef7eb2e8f9f7 | 1133 | |
<> | 144:ef7eb2e8f9f7 | 1134 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 1135 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 1136 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1137 | { |
<> | 144:ef7eb2e8f9f7 | 1138 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1139 | } |
<> | 144:ef7eb2e8f9f7 | 1140 | } |
<> | 144:ef7eb2e8f9f7 | 1141 | else |
<> | 144:ef7eb2e8f9f7 | 1142 | { |
<> | 144:ef7eb2e8f9f7 | 1143 | /* Set ADC state (ADC slave) */ |
<> | 144:ef7eb2e8f9f7 | 1144 | SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
<> | 144:ef7eb2e8f9f7 | 1145 | |
<> | 144:ef7eb2e8f9f7 | 1146 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 1147 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 1148 | if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) |
<> | 144:ef7eb2e8f9f7 | 1149 | { |
<> | 144:ef7eb2e8f9f7 | 1150 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1151 | } |
<> | 144:ef7eb2e8f9f7 | 1152 | } |
<> | 144:ef7eb2e8f9f7 | 1153 | |
<> | 144:ef7eb2e8f9f7 | 1154 | /* State machine update: Check if an injected conversion is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 1155 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 1156 | { |
<> | 144:ef7eb2e8f9f7 | 1157 | /* Reset ADC error code fields related to conversions on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1158 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
<> | 144:ef7eb2e8f9f7 | 1159 | } |
<> | 144:ef7eb2e8f9f7 | 1160 | else |
<> | 144:ef7eb2e8f9f7 | 1161 | { |
<> | 144:ef7eb2e8f9f7 | 1162 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 1163 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1164 | } |
<> | 144:ef7eb2e8f9f7 | 1165 | |
<> | 144:ef7eb2e8f9f7 | 1166 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1167 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 1168 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 1169 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1170 | |
<> | 144:ef7eb2e8f9f7 | 1171 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1172 | /* (To ensure of no unknown state from potential previous ADC operations) */ |
<> | 144:ef7eb2e8f9f7 | 1173 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1174 | |
<> | 144:ef7eb2e8f9f7 | 1175 | /* Enable end of conversion interrupt for regular group */ |
<> | 144:ef7eb2e8f9f7 | 1176 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 1177 | |
<> | 144:ef7eb2e8f9f7 | 1178 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 1179 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 1180 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 1181 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 1182 | /* Case of multimode enabled: */ |
<> | 144:ef7eb2e8f9f7 | 1183 | /* - if ADC is slave, ADC is enabled only (conversion is not started). */ |
<> | 144:ef7eb2e8f9f7 | 1184 | /* - if ADC is master, ADC is enabled and conversion is started. */ |
<> | 144:ef7eb2e8f9f7 | 1185 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 1186 | ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) |
<> | 144:ef7eb2e8f9f7 | 1187 | { |
<> | 144:ef7eb2e8f9f7 | 1188 | /* Start ADC conversion on regular group with SW start */ |
<> | 144:ef7eb2e8f9f7 | 1189 | SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); |
<> | 144:ef7eb2e8f9f7 | 1190 | } |
<> | 144:ef7eb2e8f9f7 | 1191 | else |
<> | 144:ef7eb2e8f9f7 | 1192 | { |
<> | 144:ef7eb2e8f9f7 | 1193 | /* Start ADC conversion on regular group with external trigger */ |
<> | 144:ef7eb2e8f9f7 | 1194 | SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); |
<> | 144:ef7eb2e8f9f7 | 1195 | } |
<> | 144:ef7eb2e8f9f7 | 1196 | } |
<> | 144:ef7eb2e8f9f7 | 1197 | else |
<> | 144:ef7eb2e8f9f7 | 1198 | { |
<> | 144:ef7eb2e8f9f7 | 1199 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1200 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1201 | } |
<> | 144:ef7eb2e8f9f7 | 1202 | |
<> | 144:ef7eb2e8f9f7 | 1203 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1204 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1205 | } |
<> | 144:ef7eb2e8f9f7 | 1206 | |
<> | 144:ef7eb2e8f9f7 | 1207 | /** |
<> | 144:ef7eb2e8f9f7 | 1208 | * @brief Stop ADC conversion of regular group (and injected group in |
<> | 144:ef7eb2e8f9f7 | 1209 | * case of auto_injection mode), disable interrution of |
<> | 144:ef7eb2e8f9f7 | 1210 | * end-of-conversion, disable ADC peripheral. |
<> | 144:ef7eb2e8f9f7 | 1211 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1212 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1213 | */ |
<> | 144:ef7eb2e8f9f7 | 1214 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1215 | { |
<> | 144:ef7eb2e8f9f7 | 1216 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1217 | |
<> | 144:ef7eb2e8f9f7 | 1218 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1219 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1220 | |
<> | 144:ef7eb2e8f9f7 | 1221 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1222 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1223 | |
<> | 144:ef7eb2e8f9f7 | 1224 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 1225 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1226 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1227 | |
<> | 144:ef7eb2e8f9f7 | 1228 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1229 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1230 | { |
<> | 144:ef7eb2e8f9f7 | 1231 | /* Disable ADC end of conversion interrupt for regular group */ |
<> | 144:ef7eb2e8f9f7 | 1232 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 1233 | |
<> | 144:ef7eb2e8f9f7 | 1234 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1235 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1236 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1237 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1238 | } |
<> | 144:ef7eb2e8f9f7 | 1239 | |
<> | 144:ef7eb2e8f9f7 | 1240 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1241 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1242 | |
<> | 144:ef7eb2e8f9f7 | 1243 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1244 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1245 | } |
<> | 144:ef7eb2e8f9f7 | 1246 | |
<> | 144:ef7eb2e8f9f7 | 1247 | /** |
<> | 144:ef7eb2e8f9f7 | 1248 | * @brief Enables ADC, starts conversion of regular group and transfers result |
<> | 144:ef7eb2e8f9f7 | 1249 | * through DMA. |
<> | 144:ef7eb2e8f9f7 | 1250 | * Interruptions enabled in this function: |
<> | 144:ef7eb2e8f9f7 | 1251 | * - DMA transfer complete |
<> | 144:ef7eb2e8f9f7 | 1252 | * - DMA half transfer |
<> | 144:ef7eb2e8f9f7 | 1253 | * Each of these interruptions has its dedicated callback function. |
<> | 144:ef7eb2e8f9f7 | 1254 | * @note For devices with several ADCs: This function is for single-ADC mode |
<> | 144:ef7eb2e8f9f7 | 1255 | * only. For multimode, use the dedicated MultimodeStart function. |
<> | 144:ef7eb2e8f9f7 | 1256 | * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending |
<> | 144:ef7eb2e8f9f7 | 1257 | * on devices) have DMA capability. |
<> | 144:ef7eb2e8f9f7 | 1258 | * ADC2 converted data can be transferred in dual ADC mode using DMA |
<> | 144:ef7eb2e8f9f7 | 1259 | * of ADC1 (ADC master in multimode). |
<> | 144:ef7eb2e8f9f7 | 1260 | * In case of using ADC1 with DMA on a device featuring 2 ADC |
<> | 144:ef7eb2e8f9f7 | 1261 | * instances: ADC1 conversion register DR contains ADC1 conversion |
<> | 144:ef7eb2e8f9f7 | 1262 | * result (ADC1 register DR bits 0 to 11) and, additionally, ADC2 last |
<> | 144:ef7eb2e8f9f7 | 1263 | * conversion result (ADC1 register DR bits 16 to 27). Therefore, to |
<> | 144:ef7eb2e8f9f7 | 1264 | * have DMA transferring the conversion results of ADC1 only, DMA must |
<> | 144:ef7eb2e8f9f7 | 1265 | * be configured to transfer size: half word. |
<> | 144:ef7eb2e8f9f7 | 1266 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1267 | * @param pData: The destination Buffer address. |
<> | 144:ef7eb2e8f9f7 | 1268 | * @param Length: The length of data to be transferred from ADC peripheral to memory. |
<> | 144:ef7eb2e8f9f7 | 1269 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1270 | */ |
<> | 144:ef7eb2e8f9f7 | 1271 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) |
<> | 144:ef7eb2e8f9f7 | 1272 | { |
<> | 144:ef7eb2e8f9f7 | 1273 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1274 | |
<> | 144:ef7eb2e8f9f7 | 1275 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1276 | assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1277 | |
<> | 144:ef7eb2e8f9f7 | 1278 | /* Verification if multimode is disabled (for devices with several ADC) */ |
<> | 144:ef7eb2e8f9f7 | 1279 | /* If multimode is enabled, dedicated function multimode conversion */ |
<> | 144:ef7eb2e8f9f7 | 1280 | /* start DMA must be used. */ |
<> | 144:ef7eb2e8f9f7 | 1281 | if(ADC_MULTIMODE_IS_ENABLE(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1282 | { |
<> | 144:ef7eb2e8f9f7 | 1283 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1284 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1285 | |
<> | 144:ef7eb2e8f9f7 | 1286 | /* Enable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1287 | tmp_hal_status = ADC_Enable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1288 | |
<> | 144:ef7eb2e8f9f7 | 1289 | /* Start conversion if ADC is effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1290 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1291 | { |
<> | 144:ef7eb2e8f9f7 | 1292 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1293 | /* - Clear state bitfield related to regular group conversion results */ |
<> | 144:ef7eb2e8f9f7 | 1294 | /* - Set state bitfield related to regular operation */ |
<> | 144:ef7eb2e8f9f7 | 1295 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1296 | HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, |
<> | 144:ef7eb2e8f9f7 | 1297 | HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1298 | |
<> | 144:ef7eb2e8f9f7 | 1299 | /* Set group injected state (from auto-injection) and multimode state */ |
<> | 144:ef7eb2e8f9f7 | 1300 | /* for all cases of multimode: independent mode, multimode ADC master */ |
<> | 144:ef7eb2e8f9f7 | 1301 | /* or multimode ADC slave (for devices with several ADCs): */ |
<> | 144:ef7eb2e8f9f7 | 1302 | if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) |
<> | 144:ef7eb2e8f9f7 | 1303 | { |
<> | 144:ef7eb2e8f9f7 | 1304 | /* Set ADC state (ADC independent or master) */ |
<> | 144:ef7eb2e8f9f7 | 1305 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
<> | 144:ef7eb2e8f9f7 | 1306 | |
<> | 144:ef7eb2e8f9f7 | 1307 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 1308 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 1309 | if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1310 | { |
<> | 144:ef7eb2e8f9f7 | 1311 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1312 | } |
<> | 144:ef7eb2e8f9f7 | 1313 | } |
<> | 144:ef7eb2e8f9f7 | 1314 | else |
<> | 144:ef7eb2e8f9f7 | 1315 | { |
<> | 144:ef7eb2e8f9f7 | 1316 | /* Set ADC state (ADC slave) */ |
<> | 144:ef7eb2e8f9f7 | 1317 | SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); |
<> | 144:ef7eb2e8f9f7 | 1318 | |
<> | 144:ef7eb2e8f9f7 | 1319 | /* If conversions on group regular are also triggering group injected, */ |
<> | 144:ef7eb2e8f9f7 | 1320 | /* update ADC state. */ |
<> | 144:ef7eb2e8f9f7 | 1321 | if (ADC_MULTIMODE_AUTO_INJECTED(hadc)) |
<> | 144:ef7eb2e8f9f7 | 1322 | { |
<> | 144:ef7eb2e8f9f7 | 1323 | ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1324 | } |
<> | 144:ef7eb2e8f9f7 | 1325 | } |
<> | 144:ef7eb2e8f9f7 | 1326 | |
<> | 144:ef7eb2e8f9f7 | 1327 | /* State machine update: Check if an injected conversion is ongoing */ |
<> | 144:ef7eb2e8f9f7 | 1328 | if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 1329 | { |
<> | 144:ef7eb2e8f9f7 | 1330 | /* Reset ADC error code fields related to conversions on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1331 | CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); |
<> | 144:ef7eb2e8f9f7 | 1332 | } |
<> | 144:ef7eb2e8f9f7 | 1333 | else |
<> | 144:ef7eb2e8f9f7 | 1334 | { |
<> | 144:ef7eb2e8f9f7 | 1335 | /* Reset ADC all error code fields */ |
<> | 144:ef7eb2e8f9f7 | 1336 | ADC_CLEAR_ERRORCODE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1337 | } |
<> | 144:ef7eb2e8f9f7 | 1338 | |
<> | 144:ef7eb2e8f9f7 | 1339 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1340 | /* Unlock before starting ADC conversions: in case of potential */ |
<> | 144:ef7eb2e8f9f7 | 1341 | /* interruption, to let the process to ADC IRQ Handler. */ |
<> | 144:ef7eb2e8f9f7 | 1342 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1343 | |
<> | 144:ef7eb2e8f9f7 | 1344 | /* Set the DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1345 | hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; |
<> | 144:ef7eb2e8f9f7 | 1346 | |
<> | 144:ef7eb2e8f9f7 | 1347 | /* Set the DMA half transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1348 | hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; |
<> | 144:ef7eb2e8f9f7 | 1349 | |
<> | 144:ef7eb2e8f9f7 | 1350 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1351 | hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1352 | |
<> | 144:ef7eb2e8f9f7 | 1353 | |
<> | 144:ef7eb2e8f9f7 | 1354 | /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ |
<> | 144:ef7eb2e8f9f7 | 1355 | /* start (in case of SW start): */ |
<> | 144:ef7eb2e8f9f7 | 1356 | |
<> | 144:ef7eb2e8f9f7 | 1357 | /* Clear regular group conversion flag and overrun flag */ |
<> | 144:ef7eb2e8f9f7 | 1358 | /* (To ensure of no unknown state from potential previous ADC */ |
<> | 144:ef7eb2e8f9f7 | 1359 | /* operations) */ |
<> | 144:ef7eb2e8f9f7 | 1360 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1361 | |
<> | 144:ef7eb2e8f9f7 | 1362 | /* Enable ADC DMA mode */ |
<> | 144:ef7eb2e8f9f7 | 1363 | SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); |
<> | 144:ef7eb2e8f9f7 | 1364 | |
<> | 144:ef7eb2e8f9f7 | 1365 | /* Start the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1366 | HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); |
<> | 144:ef7eb2e8f9f7 | 1367 | |
<> | 144:ef7eb2e8f9f7 | 1368 | /* Enable conversion of regular group. */ |
<> | 144:ef7eb2e8f9f7 | 1369 | /* If software start has been selected, conversion starts immediately. */ |
<> | 144:ef7eb2e8f9f7 | 1370 | /* If external trigger has been selected, conversion will start at next */ |
<> | 144:ef7eb2e8f9f7 | 1371 | /* trigger event. */ |
<> | 144:ef7eb2e8f9f7 | 1372 | if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) |
<> | 144:ef7eb2e8f9f7 | 1373 | { |
<> | 144:ef7eb2e8f9f7 | 1374 | /* Start ADC conversion on regular group with SW start */ |
<> | 144:ef7eb2e8f9f7 | 1375 | SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); |
<> | 144:ef7eb2e8f9f7 | 1376 | } |
<> | 144:ef7eb2e8f9f7 | 1377 | else |
<> | 144:ef7eb2e8f9f7 | 1378 | { |
<> | 144:ef7eb2e8f9f7 | 1379 | /* Start ADC conversion on regular group with external trigger */ |
<> | 144:ef7eb2e8f9f7 | 1380 | SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); |
<> | 144:ef7eb2e8f9f7 | 1381 | } |
<> | 144:ef7eb2e8f9f7 | 1382 | } |
<> | 144:ef7eb2e8f9f7 | 1383 | else |
<> | 144:ef7eb2e8f9f7 | 1384 | { |
<> | 144:ef7eb2e8f9f7 | 1385 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1386 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1387 | } |
<> | 144:ef7eb2e8f9f7 | 1388 | } |
<> | 144:ef7eb2e8f9f7 | 1389 | else |
<> | 144:ef7eb2e8f9f7 | 1390 | { |
<> | 144:ef7eb2e8f9f7 | 1391 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1392 | } |
<> | 144:ef7eb2e8f9f7 | 1393 | |
<> | 144:ef7eb2e8f9f7 | 1394 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1395 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1396 | } |
<> | 144:ef7eb2e8f9f7 | 1397 | |
<> | 144:ef7eb2e8f9f7 | 1398 | /** |
<> | 144:ef7eb2e8f9f7 | 1399 | * @brief Stop ADC conversion of regular group (and injected group in |
<> | 144:ef7eb2e8f9f7 | 1400 | * case of auto_injection mode), disable ADC DMA transfer, disable |
<> | 144:ef7eb2e8f9f7 | 1401 | * ADC peripheral. |
<> | 144:ef7eb2e8f9f7 | 1402 | * @note: ADC peripheral disable is forcing stop of potential |
<> | 144:ef7eb2e8f9f7 | 1403 | * conversion on injected group. If injected group is under use, it |
<> | 144:ef7eb2e8f9f7 | 1404 | * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. |
<> | 144:ef7eb2e8f9f7 | 1405 | * @note For devices with several ADCs: This function is for single-ADC mode |
<> | 144:ef7eb2e8f9f7 | 1406 | * only. For multimode, use the dedicated MultimodeStop function. |
<> | 144:ef7eb2e8f9f7 | 1407 | * @note On STM32F1 devices, only ADC1 and ADC3 (ADC availability depending |
<> | 144:ef7eb2e8f9f7 | 1408 | * on devices) have DMA capability. |
<> | 144:ef7eb2e8f9f7 | 1409 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1410 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1411 | */ |
<> | 144:ef7eb2e8f9f7 | 1412 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1413 | { |
<> | 144:ef7eb2e8f9f7 | 1414 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1415 | |
<> | 144:ef7eb2e8f9f7 | 1416 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1417 | assert_param(IS_ADC_DMA_CAPABILITY_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1418 | |
<> | 144:ef7eb2e8f9f7 | 1419 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1420 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1421 | |
<> | 144:ef7eb2e8f9f7 | 1422 | /* Stop potential conversion on going, on regular and injected groups */ |
<> | 144:ef7eb2e8f9f7 | 1423 | /* Disable ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1424 | tmp_hal_status = ADC_ConversionStop_Disable(hadc); |
<> | 144:ef7eb2e8f9f7 | 1425 | |
<> | 144:ef7eb2e8f9f7 | 1426 | /* Check if ADC is effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1427 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1428 | { |
<> | 144:ef7eb2e8f9f7 | 1429 | /* Disable ADC DMA mode */ |
<> | 144:ef7eb2e8f9f7 | 1430 | CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); |
<> | 144:ef7eb2e8f9f7 | 1431 | |
<> | 144:ef7eb2e8f9f7 | 1432 | /* Disable the DMA channel (in case of DMA in circular mode or stop while */ |
<> | 144:ef7eb2e8f9f7 | 1433 | /* DMA transfer is on going) */ |
<> | 144:ef7eb2e8f9f7 | 1434 | tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); |
<> | 144:ef7eb2e8f9f7 | 1435 | |
<> | 144:ef7eb2e8f9f7 | 1436 | /* Check if DMA channel effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 1437 | if (tmp_hal_status == HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1438 | { |
<> | 144:ef7eb2e8f9f7 | 1439 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1440 | ADC_STATE_CLR_SET(hadc->State, |
<> | 144:ef7eb2e8f9f7 | 1441 | HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, |
<> | 144:ef7eb2e8f9f7 | 1442 | HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1443 | } |
<> | 144:ef7eb2e8f9f7 | 1444 | else |
<> | 144:ef7eb2e8f9f7 | 1445 | { |
<> | 144:ef7eb2e8f9f7 | 1446 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1447 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 1448 | } |
<> | 144:ef7eb2e8f9f7 | 1449 | } |
<> | 144:ef7eb2e8f9f7 | 1450 | |
<> | 144:ef7eb2e8f9f7 | 1451 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1452 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1453 | |
<> | 144:ef7eb2e8f9f7 | 1454 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1455 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1456 | } |
<> | 144:ef7eb2e8f9f7 | 1457 | |
<> | 144:ef7eb2e8f9f7 | 1458 | /** |
<> | 144:ef7eb2e8f9f7 | 1459 | * @brief Get ADC regular group conversion result. |
<> | 144:ef7eb2e8f9f7 | 1460 | * @note Reading register DR automatically clears ADC flag EOC |
<> | 144:ef7eb2e8f9f7 | 1461 | * (ADC group regular end of unitary conversion). |
<> | 144:ef7eb2e8f9f7 | 1462 | * @note This function does not clear ADC flag EOS |
<> | 144:ef7eb2e8f9f7 | 1463 | * (ADC group regular end of sequence conversion). |
<> | 144:ef7eb2e8f9f7 | 1464 | * Occurrence of flag EOS rising: |
<> | 144:ef7eb2e8f9f7 | 1465 | * - If sequencer is composed of 1 rank, flag EOS is equivalent |
<> | 144:ef7eb2e8f9f7 | 1466 | * to flag EOC. |
<> | 144:ef7eb2e8f9f7 | 1467 | * - If sequencer is composed of several ranks, during the scan |
<> | 144:ef7eb2e8f9f7 | 1468 | * sequence flag EOC only is raised, at the end of the scan sequence |
<> | 144:ef7eb2e8f9f7 | 1469 | * both flags EOC and EOS are raised. |
<> | 144:ef7eb2e8f9f7 | 1470 | * To clear this flag, either use function: |
<> | 144:ef7eb2e8f9f7 | 1471 | * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming |
<> | 144:ef7eb2e8f9f7 | 1472 | * model polling: @ref HAL_ADC_PollForConversion() |
<> | 144:ef7eb2e8f9f7 | 1473 | * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). |
<> | 144:ef7eb2e8f9f7 | 1474 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1475 | * @retval ADC group regular conversion data |
<> | 144:ef7eb2e8f9f7 | 1476 | */ |
<> | 144:ef7eb2e8f9f7 | 1477 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1478 | { |
<> | 144:ef7eb2e8f9f7 | 1479 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1480 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1481 | |
<> | 144:ef7eb2e8f9f7 | 1482 | /* Note: EOC flag is not cleared here by software because automatically */ |
<> | 144:ef7eb2e8f9f7 | 1483 | /* cleared by hardware when reading register DR. */ |
<> | 144:ef7eb2e8f9f7 | 1484 | |
<> | 144:ef7eb2e8f9f7 | 1485 | /* Return ADC converted value */ |
<> | 144:ef7eb2e8f9f7 | 1486 | return hadc->Instance->DR; |
<> | 144:ef7eb2e8f9f7 | 1487 | } |
<> | 144:ef7eb2e8f9f7 | 1488 | |
<> | 144:ef7eb2e8f9f7 | 1489 | /** |
<> | 144:ef7eb2e8f9f7 | 1490 | * @brief Handles ADC interrupt request |
<> | 144:ef7eb2e8f9f7 | 1491 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1492 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1493 | */ |
<> | 144:ef7eb2e8f9f7 | 1494 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1495 | { |
<> | 144:ef7eb2e8f9f7 | 1496 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1497 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1498 | assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); |
<> | 144:ef7eb2e8f9f7 | 1499 | assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); |
<> | 144:ef7eb2e8f9f7 | 1500 | |
<> | 144:ef7eb2e8f9f7 | 1501 | |
<> | 144:ef7eb2e8f9f7 | 1502 | /* ========== Check End of Conversion flag for regular group ========== */ |
<> | 144:ef7eb2e8f9f7 | 1503 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) |
<> | 144:ef7eb2e8f9f7 | 1504 | { |
<> | 144:ef7eb2e8f9f7 | 1505 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) ) |
<> | 144:ef7eb2e8f9f7 | 1506 | { |
<> | 144:ef7eb2e8f9f7 | 1507 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 1508 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
<> | 144:ef7eb2e8f9f7 | 1509 | { |
<> | 144:ef7eb2e8f9f7 | 1510 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1511 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1512 | } |
<> | 144:ef7eb2e8f9f7 | 1513 | |
<> | 144:ef7eb2e8f9f7 | 1514 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1515 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 1516 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
<> | 144:ef7eb2e8f9f7 | 1517 | /* (several ranks selected), end of conversion flag is raised */ |
<> | 144:ef7eb2e8f9f7 | 1518 | /* at the end of the sequence. */ |
<> | 144:ef7eb2e8f9f7 | 1519 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 1520 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 1521 | { |
<> | 144:ef7eb2e8f9f7 | 1522 | /* Disable ADC end of conversion interrupt on group regular */ |
<> | 144:ef7eb2e8f9f7 | 1523 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); |
<> | 144:ef7eb2e8f9f7 | 1524 | |
<> | 144:ef7eb2e8f9f7 | 1525 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1526 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1527 | |
<> | 144:ef7eb2e8f9f7 | 1528 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 1529 | { |
<> | 144:ef7eb2e8f9f7 | 1530 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1531 | } |
<> | 144:ef7eb2e8f9f7 | 1532 | } |
<> | 144:ef7eb2e8f9f7 | 1533 | |
<> | 144:ef7eb2e8f9f7 | 1534 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1535 | HAL_ADC_ConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1536 | |
<> | 144:ef7eb2e8f9f7 | 1537 | /* Clear regular group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 1538 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); |
<> | 144:ef7eb2e8f9f7 | 1539 | } |
<> | 144:ef7eb2e8f9f7 | 1540 | } |
<> | 144:ef7eb2e8f9f7 | 1541 | |
<> | 144:ef7eb2e8f9f7 | 1542 | /* ========== Check End of Conversion flag for injected group ========== */ |
<> | 144:ef7eb2e8f9f7 | 1543 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) |
<> | 144:ef7eb2e8f9f7 | 1544 | { |
<> | 144:ef7eb2e8f9f7 | 1545 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)) |
<> | 144:ef7eb2e8f9f7 | 1546 | { |
<> | 144:ef7eb2e8f9f7 | 1547 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 1548 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) |
<> | 144:ef7eb2e8f9f7 | 1549 | { |
<> | 144:ef7eb2e8f9f7 | 1550 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1551 | SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); |
<> | 144:ef7eb2e8f9f7 | 1552 | } |
<> | 144:ef7eb2e8f9f7 | 1553 | |
<> | 144:ef7eb2e8f9f7 | 1554 | /* Determine whether any further conversion upcoming on group injected */ |
<> | 144:ef7eb2e8f9f7 | 1555 | /* by external trigger, scan sequence on going or by automatic injected */ |
<> | 144:ef7eb2e8f9f7 | 1556 | /* conversion from group regular (same conditions as group regular */ |
<> | 144:ef7eb2e8f9f7 | 1557 | /* interruption disabling above). */ |
<> | 144:ef7eb2e8f9f7 | 1558 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
<> | 144:ef7eb2e8f9f7 | 1559 | /* (several ranks selected), end of conversion flag is raised */ |
<> | 144:ef7eb2e8f9f7 | 1560 | /* at the end of the sequence. */ |
<> | 144:ef7eb2e8f9f7 | 1561 | if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || |
<> | 144:ef7eb2e8f9f7 | 1562 | (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && |
<> | 144:ef7eb2e8f9f7 | 1563 | (ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 1564 | (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) |
<> | 144:ef7eb2e8f9f7 | 1565 | { |
<> | 144:ef7eb2e8f9f7 | 1566 | /* Disable ADC end of conversion interrupt on group injected */ |
<> | 144:ef7eb2e8f9f7 | 1567 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); |
<> | 144:ef7eb2e8f9f7 | 1568 | |
<> | 144:ef7eb2e8f9f7 | 1569 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1570 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 1571 | |
<> | 144:ef7eb2e8f9f7 | 1572 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 1573 | { |
<> | 144:ef7eb2e8f9f7 | 1574 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 1575 | } |
<> | 144:ef7eb2e8f9f7 | 1576 | } |
<> | 144:ef7eb2e8f9f7 | 1577 | |
<> | 144:ef7eb2e8f9f7 | 1578 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1579 | HAL_ADCEx_InjectedConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1580 | |
<> | 144:ef7eb2e8f9f7 | 1581 | /* Clear injected group conversion flag */ |
<> | 144:ef7eb2e8f9f7 | 1582 | __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); |
<> | 144:ef7eb2e8f9f7 | 1583 | } |
<> | 144:ef7eb2e8f9f7 | 1584 | } |
<> | 144:ef7eb2e8f9f7 | 1585 | |
<> | 144:ef7eb2e8f9f7 | 1586 | /* ========== Check Analog watchdog flags ========== */ |
<> | 144:ef7eb2e8f9f7 | 1587 | if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD)) |
<> | 144:ef7eb2e8f9f7 | 1588 | { |
<> | 144:ef7eb2e8f9f7 | 1589 | if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) |
<> | 144:ef7eb2e8f9f7 | 1590 | { |
<> | 144:ef7eb2e8f9f7 | 1591 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1592 | SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); |
<> | 144:ef7eb2e8f9f7 | 1593 | |
<> | 144:ef7eb2e8f9f7 | 1594 | /* Level out of window callback */ |
<> | 144:ef7eb2e8f9f7 | 1595 | HAL_ADC_LevelOutOfWindowCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 1596 | |
<> | 144:ef7eb2e8f9f7 | 1597 | /* Clear the ADC analog watchdog flag */ |
<> | 144:ef7eb2e8f9f7 | 1598 | __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); |
<> | 144:ef7eb2e8f9f7 | 1599 | } |
<> | 144:ef7eb2e8f9f7 | 1600 | } |
<> | 144:ef7eb2e8f9f7 | 1601 | |
<> | 144:ef7eb2e8f9f7 | 1602 | } |
<> | 144:ef7eb2e8f9f7 | 1603 | |
<> | 144:ef7eb2e8f9f7 | 1604 | /** |
<> | 144:ef7eb2e8f9f7 | 1605 | * @brief Conversion complete callback in non blocking mode |
<> | 144:ef7eb2e8f9f7 | 1606 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1607 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1608 | */ |
<> | 144:ef7eb2e8f9f7 | 1609 | __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1610 | { |
<> | 144:ef7eb2e8f9f7 | 1611 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1612 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1613 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1614 | function HAL_ADC_ConvCpltCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1615 | */ |
<> | 144:ef7eb2e8f9f7 | 1616 | } |
<> | 144:ef7eb2e8f9f7 | 1617 | |
<> | 144:ef7eb2e8f9f7 | 1618 | /** |
<> | 144:ef7eb2e8f9f7 | 1619 | * @brief Conversion DMA half-transfer callback in non blocking mode |
<> | 144:ef7eb2e8f9f7 | 1620 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1621 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1622 | */ |
<> | 144:ef7eb2e8f9f7 | 1623 | __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1624 | { |
<> | 144:ef7eb2e8f9f7 | 1625 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1626 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1627 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1628 | function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1629 | */ |
<> | 144:ef7eb2e8f9f7 | 1630 | } |
<> | 144:ef7eb2e8f9f7 | 1631 | |
<> | 144:ef7eb2e8f9f7 | 1632 | /** |
<> | 144:ef7eb2e8f9f7 | 1633 | * @brief Analog watchdog callback in non blocking mode. |
<> | 144:ef7eb2e8f9f7 | 1634 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1635 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1636 | */ |
<> | 144:ef7eb2e8f9f7 | 1637 | __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1638 | { |
<> | 144:ef7eb2e8f9f7 | 1639 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1640 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1641 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1642 | function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1643 | */ |
<> | 144:ef7eb2e8f9f7 | 1644 | } |
<> | 144:ef7eb2e8f9f7 | 1645 | |
<> | 144:ef7eb2e8f9f7 | 1646 | /** |
<> | 144:ef7eb2e8f9f7 | 1647 | * @brief ADC error callback in non blocking mode |
<> | 144:ef7eb2e8f9f7 | 1648 | * (ADC conversion with interruption or transfer by DMA) |
<> | 144:ef7eb2e8f9f7 | 1649 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1650 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1651 | */ |
<> | 144:ef7eb2e8f9f7 | 1652 | __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1653 | { |
<> | 144:ef7eb2e8f9f7 | 1654 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 1655 | UNUSED(hadc); |
<> | 144:ef7eb2e8f9f7 | 1656 | /* NOTE : This function should not be modified. When the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1657 | function HAL_ADC_ErrorCallback must be implemented in the user file. |
<> | 144:ef7eb2e8f9f7 | 1658 | */ |
<> | 144:ef7eb2e8f9f7 | 1659 | } |
<> | 144:ef7eb2e8f9f7 | 1660 | |
<> | 144:ef7eb2e8f9f7 | 1661 | |
<> | 144:ef7eb2e8f9f7 | 1662 | /** |
<> | 144:ef7eb2e8f9f7 | 1663 | * @} |
<> | 144:ef7eb2e8f9f7 | 1664 | */ |
<> | 144:ef7eb2e8f9f7 | 1665 | |
<> | 144:ef7eb2e8f9f7 | 1666 | /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 1667 | * @brief Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 1668 | * |
<> | 144:ef7eb2e8f9f7 | 1669 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1670 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1671 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 1672 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1673 | [..] This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 1674 | (+) Configure channels on regular group |
<> | 144:ef7eb2e8f9f7 | 1675 | (+) Configure the analog watchdog |
<> | 144:ef7eb2e8f9f7 | 1676 | |
<> | 144:ef7eb2e8f9f7 | 1677 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1678 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1679 | */ |
<> | 144:ef7eb2e8f9f7 | 1680 | |
<> | 144:ef7eb2e8f9f7 | 1681 | /** |
<> | 144:ef7eb2e8f9f7 | 1682 | * @brief Configures the the selected channel to be linked to the regular |
<> | 144:ef7eb2e8f9f7 | 1683 | * group. |
<> | 144:ef7eb2e8f9f7 | 1684 | * @note In case of usage of internal measurement channels: |
<> | 144:ef7eb2e8f9f7 | 1685 | * Vbat/VrefInt/TempSensor. |
<> | 144:ef7eb2e8f9f7 | 1686 | * These internal paths can be be disabled using function |
<> | 144:ef7eb2e8f9f7 | 1687 | * HAL_ADC_DeInit(). |
<> | 144:ef7eb2e8f9f7 | 1688 | * @note Possibility to update parameters on the fly: |
<> | 144:ef7eb2e8f9f7 | 1689 | * This function initializes channel into regular group, following |
<> | 144:ef7eb2e8f9f7 | 1690 | * calls to this function can be used to reconfigure some parameters |
<> | 144:ef7eb2e8f9f7 | 1691 | * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting |
<> | 144:ef7eb2e8f9f7 | 1692 | * the ADC. |
<> | 144:ef7eb2e8f9f7 | 1693 | * The setting of these parameters is conditioned to ADC state. |
<> | 144:ef7eb2e8f9f7 | 1694 | * For parameters constraints, see comments of structure |
<> | 144:ef7eb2e8f9f7 | 1695 | * "ADC_ChannelConfTypeDef". |
<> | 144:ef7eb2e8f9f7 | 1696 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1697 | * @param sConfig: Structure of ADC channel for regular group. |
<> | 144:ef7eb2e8f9f7 | 1698 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1699 | */ |
<> | 144:ef7eb2e8f9f7 | 1700 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) |
<> | 144:ef7eb2e8f9f7 | 1701 | { |
<> | 144:ef7eb2e8f9f7 | 1702 | HAL_StatusTypeDef tmp_hal_status = HAL_OK; |
AnnaBridge | 165:e614a9f1c9e2 | 1703 | __IO uint32_t wait_loop_index = 0U; |
<> | 144:ef7eb2e8f9f7 | 1704 | |
<> | 144:ef7eb2e8f9f7 | 1705 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1706 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1707 | assert_param(IS_ADC_CHANNEL(sConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1708 | assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); |
<> | 144:ef7eb2e8f9f7 | 1709 | assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); |
<> | 144:ef7eb2e8f9f7 | 1710 | |
<> | 144:ef7eb2e8f9f7 | 1711 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1712 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1713 | |
<> | 144:ef7eb2e8f9f7 | 1714 | |
<> | 144:ef7eb2e8f9f7 | 1715 | /* Regular sequence configuration */ |
<> | 144:ef7eb2e8f9f7 | 1716 | /* For Rank 1 to 6 */ |
AnnaBridge | 165:e614a9f1c9e2 | 1717 | if (sConfig->Rank < 7U) |
<> | 144:ef7eb2e8f9f7 | 1718 | { |
<> | 144:ef7eb2e8f9f7 | 1719 | MODIFY_REG(hadc->Instance->SQR3 , |
<> | 144:ef7eb2e8f9f7 | 1720 | ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , |
<> | 144:ef7eb2e8f9f7 | 1721 | ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); |
<> | 144:ef7eb2e8f9f7 | 1722 | } |
<> | 144:ef7eb2e8f9f7 | 1723 | /* For Rank 7 to 12 */ |
AnnaBridge | 165:e614a9f1c9e2 | 1724 | else if (sConfig->Rank < 13U) |
<> | 144:ef7eb2e8f9f7 | 1725 | { |
<> | 144:ef7eb2e8f9f7 | 1726 | MODIFY_REG(hadc->Instance->SQR2 , |
<> | 144:ef7eb2e8f9f7 | 1727 | ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , |
<> | 144:ef7eb2e8f9f7 | 1728 | ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) ); |
<> | 144:ef7eb2e8f9f7 | 1729 | } |
<> | 144:ef7eb2e8f9f7 | 1730 | /* For Rank 13 to 16 */ |
<> | 144:ef7eb2e8f9f7 | 1731 | else |
<> | 144:ef7eb2e8f9f7 | 1732 | { |
<> | 144:ef7eb2e8f9f7 | 1733 | MODIFY_REG(hadc->Instance->SQR1 , |
<> | 144:ef7eb2e8f9f7 | 1734 | ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank) , |
<> | 144:ef7eb2e8f9f7 | 1735 | ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) ); |
<> | 144:ef7eb2e8f9f7 | 1736 | } |
<> | 144:ef7eb2e8f9f7 | 1737 | |
<> | 144:ef7eb2e8f9f7 | 1738 | |
<> | 144:ef7eb2e8f9f7 | 1739 | /* Channel sampling time configuration */ |
<> | 144:ef7eb2e8f9f7 | 1740 | /* For channels 10 to 17 */ |
<> | 144:ef7eb2e8f9f7 | 1741 | if (sConfig->Channel >= ADC_CHANNEL_10) |
<> | 144:ef7eb2e8f9f7 | 1742 | { |
<> | 144:ef7eb2e8f9f7 | 1743 | MODIFY_REG(hadc->Instance->SMPR1 , |
<> | 144:ef7eb2e8f9f7 | 1744 | ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel) , |
<> | 144:ef7eb2e8f9f7 | 1745 | ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) ); |
<> | 144:ef7eb2e8f9f7 | 1746 | } |
<> | 144:ef7eb2e8f9f7 | 1747 | else /* For channels 0 to 9 */ |
<> | 144:ef7eb2e8f9f7 | 1748 | { |
<> | 144:ef7eb2e8f9f7 | 1749 | MODIFY_REG(hadc->Instance->SMPR2 , |
<> | 144:ef7eb2e8f9f7 | 1750 | ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel) , |
<> | 144:ef7eb2e8f9f7 | 1751 | ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) ); |
<> | 144:ef7eb2e8f9f7 | 1752 | } |
<> | 144:ef7eb2e8f9f7 | 1753 | |
<> | 144:ef7eb2e8f9f7 | 1754 | /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ |
<> | 144:ef7eb2e8f9f7 | 1755 | /* and VREFINT measurement path. */ |
<> | 144:ef7eb2e8f9f7 | 1756 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || |
<> | 144:ef7eb2e8f9f7 | 1757 | (sConfig->Channel == ADC_CHANNEL_VREFINT) ) |
<> | 144:ef7eb2e8f9f7 | 1758 | { |
<> | 144:ef7eb2e8f9f7 | 1759 | /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ |
<> | 144:ef7eb2e8f9f7 | 1760 | /* measurement channels (VrefInt/TempSensor). If these channels are */ |
<> | 144:ef7eb2e8f9f7 | 1761 | /* intended to be set on other ADC instances, an error is reported. */ |
<> | 144:ef7eb2e8f9f7 | 1762 | if (hadc->Instance == ADC1) |
<> | 144:ef7eb2e8f9f7 | 1763 | { |
<> | 144:ef7eb2e8f9f7 | 1764 | if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1765 | { |
<> | 144:ef7eb2e8f9f7 | 1766 | SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); |
<> | 144:ef7eb2e8f9f7 | 1767 | |
<> | 144:ef7eb2e8f9f7 | 1768 | if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) |
<> | 144:ef7eb2e8f9f7 | 1769 | { |
<> | 144:ef7eb2e8f9f7 | 1770 | /* Delay for temperature sensor stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 1771 | /* Compute number of CPU cycles to wait for */ |
AnnaBridge | 165:e614a9f1c9e2 | 1772 | wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); |
AnnaBridge | 165:e614a9f1c9e2 | 1773 | while(wait_loop_index != 0U) |
<> | 144:ef7eb2e8f9f7 | 1774 | { |
<> | 144:ef7eb2e8f9f7 | 1775 | wait_loop_index--; |
<> | 144:ef7eb2e8f9f7 | 1776 | } |
<> | 144:ef7eb2e8f9f7 | 1777 | } |
<> | 144:ef7eb2e8f9f7 | 1778 | } |
<> | 144:ef7eb2e8f9f7 | 1779 | } |
<> | 144:ef7eb2e8f9f7 | 1780 | else |
<> | 144:ef7eb2e8f9f7 | 1781 | { |
<> | 144:ef7eb2e8f9f7 | 1782 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1783 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); |
<> | 144:ef7eb2e8f9f7 | 1784 | |
<> | 144:ef7eb2e8f9f7 | 1785 | tmp_hal_status = HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1786 | } |
<> | 144:ef7eb2e8f9f7 | 1787 | } |
<> | 144:ef7eb2e8f9f7 | 1788 | |
<> | 144:ef7eb2e8f9f7 | 1789 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1790 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1791 | |
<> | 144:ef7eb2e8f9f7 | 1792 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1793 | return tmp_hal_status; |
<> | 144:ef7eb2e8f9f7 | 1794 | } |
<> | 144:ef7eb2e8f9f7 | 1795 | |
<> | 144:ef7eb2e8f9f7 | 1796 | /** |
<> | 144:ef7eb2e8f9f7 | 1797 | * @brief Configures the analog watchdog. |
<> | 144:ef7eb2e8f9f7 | 1798 | * @note Analog watchdog thresholds can be modified while ADC conversion |
<> | 144:ef7eb2e8f9f7 | 1799 | * is on going. |
<> | 144:ef7eb2e8f9f7 | 1800 | * In this case, some constraints must be taken into account: |
<> | 144:ef7eb2e8f9f7 | 1801 | * the programmed threshold values are effective from the next |
<> | 144:ef7eb2e8f9f7 | 1802 | * ADC EOC (end of unitary conversion). |
<> | 144:ef7eb2e8f9f7 | 1803 | * Considering that registers write delay may happen due to |
<> | 144:ef7eb2e8f9f7 | 1804 | * bus activity, this might cause an uncertainty on the |
<> | 144:ef7eb2e8f9f7 | 1805 | * effective timing of the new programmed threshold values. |
<> | 144:ef7eb2e8f9f7 | 1806 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1807 | * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration |
<> | 144:ef7eb2e8f9f7 | 1808 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1809 | */ |
<> | 144:ef7eb2e8f9f7 | 1810 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) |
<> | 144:ef7eb2e8f9f7 | 1811 | { |
<> | 144:ef7eb2e8f9f7 | 1812 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1813 | assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); |
<> | 144:ef7eb2e8f9f7 | 1814 | assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); |
<> | 144:ef7eb2e8f9f7 | 1815 | assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); |
<> | 144:ef7eb2e8f9f7 | 1816 | assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold)); |
<> | 144:ef7eb2e8f9f7 | 1817 | assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold)); |
<> | 144:ef7eb2e8f9f7 | 1818 | |
<> | 144:ef7eb2e8f9f7 | 1819 | if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || |
<> | 144:ef7eb2e8f9f7 | 1820 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || |
<> | 144:ef7eb2e8f9f7 | 1821 | (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) |
<> | 144:ef7eb2e8f9f7 | 1822 | { |
<> | 144:ef7eb2e8f9f7 | 1823 | assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); |
<> | 144:ef7eb2e8f9f7 | 1824 | } |
<> | 144:ef7eb2e8f9f7 | 1825 | |
<> | 144:ef7eb2e8f9f7 | 1826 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 1827 | __HAL_LOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1828 | |
<> | 144:ef7eb2e8f9f7 | 1829 | /* Analog watchdog configuration */ |
<> | 144:ef7eb2e8f9f7 | 1830 | |
<> | 144:ef7eb2e8f9f7 | 1831 | /* Configure ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1832 | if(AnalogWDGConfig->ITMode == ENABLE) |
<> | 144:ef7eb2e8f9f7 | 1833 | { |
<> | 144:ef7eb2e8f9f7 | 1834 | /* Enable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1835 | __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1836 | } |
<> | 144:ef7eb2e8f9f7 | 1837 | else |
<> | 144:ef7eb2e8f9f7 | 1838 | { |
<> | 144:ef7eb2e8f9f7 | 1839 | /* Disable the ADC Analog watchdog interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1840 | __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); |
<> | 144:ef7eb2e8f9f7 | 1841 | } |
<> | 144:ef7eb2e8f9f7 | 1842 | |
<> | 144:ef7eb2e8f9f7 | 1843 | /* Configuration of analog watchdog: */ |
<> | 144:ef7eb2e8f9f7 | 1844 | /* - Set the analog watchdog enable mode: regular and/or injected groups, */ |
<> | 144:ef7eb2e8f9f7 | 1845 | /* one or all channels. */ |
<> | 144:ef7eb2e8f9f7 | 1846 | /* - Set the Analog watchdog channel (is not used if watchdog */ |
<> | 144:ef7eb2e8f9f7 | 1847 | /* mode "all channels": ADC_CFGR_AWD1SGL=0). */ |
<> | 144:ef7eb2e8f9f7 | 1848 | MODIFY_REG(hadc->Instance->CR1 , |
<> | 144:ef7eb2e8f9f7 | 1849 | ADC_CR1_AWDSGL | |
<> | 144:ef7eb2e8f9f7 | 1850 | ADC_CR1_JAWDEN | |
<> | 144:ef7eb2e8f9f7 | 1851 | ADC_CR1_AWDEN | |
<> | 144:ef7eb2e8f9f7 | 1852 | ADC_CR1_AWDCH , |
<> | 144:ef7eb2e8f9f7 | 1853 | AnalogWDGConfig->WatchdogMode | |
<> | 144:ef7eb2e8f9f7 | 1854 | AnalogWDGConfig->Channel ); |
<> | 144:ef7eb2e8f9f7 | 1855 | |
<> | 144:ef7eb2e8f9f7 | 1856 | /* Set the high threshold */ |
<> | 144:ef7eb2e8f9f7 | 1857 | WRITE_REG(hadc->Instance->HTR, AnalogWDGConfig->HighThreshold); |
<> | 144:ef7eb2e8f9f7 | 1858 | |
<> | 144:ef7eb2e8f9f7 | 1859 | /* Set the low threshold */ |
<> | 144:ef7eb2e8f9f7 | 1860 | WRITE_REG(hadc->Instance->LTR, AnalogWDGConfig->LowThreshold); |
<> | 144:ef7eb2e8f9f7 | 1861 | |
<> | 144:ef7eb2e8f9f7 | 1862 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1863 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1864 | |
<> | 144:ef7eb2e8f9f7 | 1865 | /* Return function status */ |
<> | 144:ef7eb2e8f9f7 | 1866 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1867 | } |
<> | 144:ef7eb2e8f9f7 | 1868 | |
<> | 144:ef7eb2e8f9f7 | 1869 | |
<> | 144:ef7eb2e8f9f7 | 1870 | /** |
<> | 144:ef7eb2e8f9f7 | 1871 | * @} |
<> | 144:ef7eb2e8f9f7 | 1872 | */ |
<> | 144:ef7eb2e8f9f7 | 1873 | |
<> | 144:ef7eb2e8f9f7 | 1874 | |
<> | 144:ef7eb2e8f9f7 | 1875 | /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1876 | * @brief Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 1877 | * |
<> | 144:ef7eb2e8f9f7 | 1878 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 1879 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1880 | ##### Peripheral State and Errors functions ##### |
<> | 144:ef7eb2e8f9f7 | 1881 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 1882 | [..] |
<> | 144:ef7eb2e8f9f7 | 1883 | This subsection provides functions to get in run-time the status of the |
<> | 144:ef7eb2e8f9f7 | 1884 | peripheral. |
<> | 144:ef7eb2e8f9f7 | 1885 | (+) Check the ADC state |
<> | 144:ef7eb2e8f9f7 | 1886 | (+) Check the ADC error code |
<> | 144:ef7eb2e8f9f7 | 1887 | |
<> | 144:ef7eb2e8f9f7 | 1888 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 1889 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1890 | */ |
<> | 144:ef7eb2e8f9f7 | 1891 | |
<> | 144:ef7eb2e8f9f7 | 1892 | /** |
<> | 144:ef7eb2e8f9f7 | 1893 | * @brief return the ADC state |
<> | 144:ef7eb2e8f9f7 | 1894 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1895 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 1896 | */ |
<> | 144:ef7eb2e8f9f7 | 1897 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1898 | { |
<> | 144:ef7eb2e8f9f7 | 1899 | /* Return ADC state */ |
<> | 144:ef7eb2e8f9f7 | 1900 | return hadc->State; |
<> | 144:ef7eb2e8f9f7 | 1901 | } |
<> | 144:ef7eb2e8f9f7 | 1902 | |
<> | 144:ef7eb2e8f9f7 | 1903 | /** |
<> | 144:ef7eb2e8f9f7 | 1904 | * @brief Return the ADC error code |
<> | 144:ef7eb2e8f9f7 | 1905 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1906 | * @retval ADC Error Code |
<> | 144:ef7eb2e8f9f7 | 1907 | */ |
<> | 144:ef7eb2e8f9f7 | 1908 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) |
<> | 144:ef7eb2e8f9f7 | 1909 | { |
<> | 144:ef7eb2e8f9f7 | 1910 | return hadc->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 1911 | } |
<> | 144:ef7eb2e8f9f7 | 1912 | |
<> | 144:ef7eb2e8f9f7 | 1913 | /** |
<> | 144:ef7eb2e8f9f7 | 1914 | * @} |
<> | 144:ef7eb2e8f9f7 | 1915 | */ |
<> | 144:ef7eb2e8f9f7 | 1916 | |
<> | 144:ef7eb2e8f9f7 | 1917 | /** |
<> | 144:ef7eb2e8f9f7 | 1918 | * @} |
<> | 144:ef7eb2e8f9f7 | 1919 | */ |
<> | 144:ef7eb2e8f9f7 | 1920 | |
<> | 144:ef7eb2e8f9f7 | 1921 | /** @defgroup ADC_Private_Functions ADC Private Functions |
<> | 144:ef7eb2e8f9f7 | 1922 | * @{ |
<> | 144:ef7eb2e8f9f7 | 1923 | */ |
<> | 144:ef7eb2e8f9f7 | 1924 | |
<> | 144:ef7eb2e8f9f7 | 1925 | /** |
<> | 144:ef7eb2e8f9f7 | 1926 | * @brief Enable the selected ADC. |
<> | 144:ef7eb2e8f9f7 | 1927 | * @note Prerequisite condition to use this function: ADC must be disabled |
<> | 144:ef7eb2e8f9f7 | 1928 | * and voltage regulator must be enabled (done into HAL_ADC_Init()). |
<> | 144:ef7eb2e8f9f7 | 1929 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1930 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1931 | */ |
<> | 144:ef7eb2e8f9f7 | 1932 | HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1933 | { |
AnnaBridge | 165:e614a9f1c9e2 | 1934 | uint32_t tickstart = 0U; |
AnnaBridge | 165:e614a9f1c9e2 | 1935 | __IO uint32_t wait_loop_index = 0U; |
<> | 144:ef7eb2e8f9f7 | 1936 | |
<> | 144:ef7eb2e8f9f7 | 1937 | /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ |
<> | 144:ef7eb2e8f9f7 | 1938 | /* enabling phase not yet completed: flag ADC ready not yet set). */ |
<> | 144:ef7eb2e8f9f7 | 1939 | /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ |
<> | 144:ef7eb2e8f9f7 | 1940 | /* causes: ADC clock not running, ...). */ |
<> | 144:ef7eb2e8f9f7 | 1941 | if (ADC_IS_ENABLE(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1942 | { |
<> | 144:ef7eb2e8f9f7 | 1943 | /* Enable the Peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1944 | __HAL_ADC_ENABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1945 | |
<> | 144:ef7eb2e8f9f7 | 1946 | /* Delay for ADC stabilization time */ |
<> | 144:ef7eb2e8f9f7 | 1947 | /* Compute number of CPU cycles to wait for */ |
AnnaBridge | 165:e614a9f1c9e2 | 1948 | wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); |
AnnaBridge | 165:e614a9f1c9e2 | 1949 | while(wait_loop_index != 0U) |
<> | 144:ef7eb2e8f9f7 | 1950 | { |
<> | 144:ef7eb2e8f9f7 | 1951 | wait_loop_index--; |
<> | 144:ef7eb2e8f9f7 | 1952 | } |
<> | 144:ef7eb2e8f9f7 | 1953 | |
<> | 144:ef7eb2e8f9f7 | 1954 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 1955 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1956 | |
<> | 144:ef7eb2e8f9f7 | 1957 | /* Wait for ADC effectively enabled */ |
<> | 144:ef7eb2e8f9f7 | 1958 | while(ADC_IS_ENABLE(hadc) == RESET) |
<> | 144:ef7eb2e8f9f7 | 1959 | { |
<> | 144:ef7eb2e8f9f7 | 1960 | if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 1961 | { |
<> | 144:ef7eb2e8f9f7 | 1962 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 1963 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1964 | |
<> | 144:ef7eb2e8f9f7 | 1965 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 1966 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 1967 | |
<> | 144:ef7eb2e8f9f7 | 1968 | /* Process unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1969 | __HAL_UNLOCK(hadc); |
<> | 144:ef7eb2e8f9f7 | 1970 | |
<> | 144:ef7eb2e8f9f7 | 1971 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1972 | } |
<> | 144:ef7eb2e8f9f7 | 1973 | } |
<> | 144:ef7eb2e8f9f7 | 1974 | } |
<> | 144:ef7eb2e8f9f7 | 1975 | |
<> | 144:ef7eb2e8f9f7 | 1976 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 1977 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1978 | } |
<> | 144:ef7eb2e8f9f7 | 1979 | |
<> | 144:ef7eb2e8f9f7 | 1980 | /** |
<> | 144:ef7eb2e8f9f7 | 1981 | * @brief Stop ADC conversion and disable the selected ADC |
<> | 144:ef7eb2e8f9f7 | 1982 | * @note Prerequisite condition to use this function: ADC conversions must be |
<> | 144:ef7eb2e8f9f7 | 1983 | * stopped to disable the ADC. |
<> | 144:ef7eb2e8f9f7 | 1984 | * @param hadc: ADC handle |
<> | 144:ef7eb2e8f9f7 | 1985 | * @retval HAL status. |
<> | 144:ef7eb2e8f9f7 | 1986 | */ |
<> | 144:ef7eb2e8f9f7 | 1987 | HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) |
<> | 144:ef7eb2e8f9f7 | 1988 | { |
AnnaBridge | 165:e614a9f1c9e2 | 1989 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1990 | |
<> | 144:ef7eb2e8f9f7 | 1991 | /* Verification if ADC is not already disabled */ |
<> | 144:ef7eb2e8f9f7 | 1992 | if (ADC_IS_ENABLE(hadc) != RESET) |
<> | 144:ef7eb2e8f9f7 | 1993 | { |
<> | 144:ef7eb2e8f9f7 | 1994 | /* Disable the ADC peripheral */ |
<> | 144:ef7eb2e8f9f7 | 1995 | __HAL_ADC_DISABLE(hadc); |
<> | 144:ef7eb2e8f9f7 | 1996 | |
<> | 144:ef7eb2e8f9f7 | 1997 | /* Get tick count */ |
<> | 144:ef7eb2e8f9f7 | 1998 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1999 | |
<> | 144:ef7eb2e8f9f7 | 2000 | /* Wait for ADC effectively disabled */ |
<> | 144:ef7eb2e8f9f7 | 2001 | while(ADC_IS_ENABLE(hadc) != RESET) |
<> | 144:ef7eb2e8f9f7 | 2002 | { |
<> | 144:ef7eb2e8f9f7 | 2003 | if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 2004 | { |
<> | 144:ef7eb2e8f9f7 | 2005 | /* Update ADC state machine to error */ |
<> | 144:ef7eb2e8f9f7 | 2006 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2007 | |
<> | 144:ef7eb2e8f9f7 | 2008 | /* Set ADC error code to ADC IP internal error */ |
<> | 144:ef7eb2e8f9f7 | 2009 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); |
<> | 144:ef7eb2e8f9f7 | 2010 | |
<> | 144:ef7eb2e8f9f7 | 2011 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2012 | } |
<> | 144:ef7eb2e8f9f7 | 2013 | } |
<> | 144:ef7eb2e8f9f7 | 2014 | } |
<> | 144:ef7eb2e8f9f7 | 2015 | |
<> | 144:ef7eb2e8f9f7 | 2016 | /* Return HAL status */ |
<> | 144:ef7eb2e8f9f7 | 2017 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2018 | } |
<> | 144:ef7eb2e8f9f7 | 2019 | |
<> | 144:ef7eb2e8f9f7 | 2020 | /** |
<> | 144:ef7eb2e8f9f7 | 2021 | * @brief DMA transfer complete callback. |
<> | 144:ef7eb2e8f9f7 | 2022 | * @param hdma: pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2023 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2024 | */ |
<> | 144:ef7eb2e8f9f7 | 2025 | void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2026 | { |
<> | 144:ef7eb2e8f9f7 | 2027 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 2028 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2029 | |
<> | 144:ef7eb2e8f9f7 | 2030 | /* Update state machine on conversion status if not in error state */ |
<> | 144:ef7eb2e8f9f7 | 2031 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) |
<> | 144:ef7eb2e8f9f7 | 2032 | { |
<> | 144:ef7eb2e8f9f7 | 2033 | /* Update ADC state machine */ |
<> | 144:ef7eb2e8f9f7 | 2034 | SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); |
<> | 144:ef7eb2e8f9f7 | 2035 | |
<> | 144:ef7eb2e8f9f7 | 2036 | /* Determine whether any further conversion upcoming on group regular */ |
<> | 144:ef7eb2e8f9f7 | 2037 | /* by external trigger, continuous mode or scan sequence on going. */ |
<> | 144:ef7eb2e8f9f7 | 2038 | /* Note: On STM32F1 devices, in case of sequencer enabled */ |
<> | 144:ef7eb2e8f9f7 | 2039 | /* (several ranks selected), end of conversion flag is raised */ |
<> | 144:ef7eb2e8f9f7 | 2040 | /* at the end of the sequence. */ |
<> | 144:ef7eb2e8f9f7 | 2041 | if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && |
<> | 144:ef7eb2e8f9f7 | 2042 | (hadc->Init.ContinuousConvMode == DISABLE) ) |
<> | 144:ef7eb2e8f9f7 | 2043 | { |
<> | 144:ef7eb2e8f9f7 | 2044 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 2045 | CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); |
<> | 144:ef7eb2e8f9f7 | 2046 | |
<> | 144:ef7eb2e8f9f7 | 2047 | if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) |
<> | 144:ef7eb2e8f9f7 | 2048 | { |
<> | 144:ef7eb2e8f9f7 | 2049 | SET_BIT(hadc->State, HAL_ADC_STATE_READY); |
<> | 144:ef7eb2e8f9f7 | 2050 | } |
<> | 144:ef7eb2e8f9f7 | 2051 | } |
<> | 144:ef7eb2e8f9f7 | 2052 | |
<> | 144:ef7eb2e8f9f7 | 2053 | /* Conversion complete callback */ |
<> | 144:ef7eb2e8f9f7 | 2054 | HAL_ADC_ConvCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2055 | } |
<> | 144:ef7eb2e8f9f7 | 2056 | else |
<> | 144:ef7eb2e8f9f7 | 2057 | { |
<> | 144:ef7eb2e8f9f7 | 2058 | /* Call DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 2059 | hadc->DMA_Handle->XferErrorCallback(hdma); |
<> | 144:ef7eb2e8f9f7 | 2060 | } |
<> | 144:ef7eb2e8f9f7 | 2061 | } |
<> | 144:ef7eb2e8f9f7 | 2062 | |
<> | 144:ef7eb2e8f9f7 | 2063 | /** |
<> | 144:ef7eb2e8f9f7 | 2064 | * @brief DMA half transfer complete callback. |
<> | 144:ef7eb2e8f9f7 | 2065 | * @param hdma: pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2066 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2067 | */ |
<> | 144:ef7eb2e8f9f7 | 2068 | void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2069 | { |
<> | 144:ef7eb2e8f9f7 | 2070 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 2071 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2072 | |
<> | 144:ef7eb2e8f9f7 | 2073 | /* Half conversion callback */ |
<> | 144:ef7eb2e8f9f7 | 2074 | HAL_ADC_ConvHalfCpltCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2075 | } |
<> | 144:ef7eb2e8f9f7 | 2076 | |
<> | 144:ef7eb2e8f9f7 | 2077 | /** |
<> | 144:ef7eb2e8f9f7 | 2078 | * @brief DMA error callback |
<> | 144:ef7eb2e8f9f7 | 2079 | * @param hdma: pointer to DMA handle. |
<> | 144:ef7eb2e8f9f7 | 2080 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2081 | */ |
<> | 144:ef7eb2e8f9f7 | 2082 | void ADC_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 2083 | { |
<> | 144:ef7eb2e8f9f7 | 2084 | /* Retrieve ADC handle corresponding to current DMA handle */ |
<> | 144:ef7eb2e8f9f7 | 2085 | ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 2086 | |
<> | 144:ef7eb2e8f9f7 | 2087 | /* Set ADC state */ |
<> | 144:ef7eb2e8f9f7 | 2088 | SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 2089 | |
<> | 144:ef7eb2e8f9f7 | 2090 | /* Set ADC error code to DMA error */ |
<> | 144:ef7eb2e8f9f7 | 2091 | SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 2092 | |
<> | 144:ef7eb2e8f9f7 | 2093 | /* Error callback */ |
<> | 144:ef7eb2e8f9f7 | 2094 | HAL_ADC_ErrorCallback(hadc); |
<> | 144:ef7eb2e8f9f7 | 2095 | } |
<> | 144:ef7eb2e8f9f7 | 2096 | |
<> | 144:ef7eb2e8f9f7 | 2097 | /** |
<> | 144:ef7eb2e8f9f7 | 2098 | * @} |
<> | 144:ef7eb2e8f9f7 | 2099 | */ |
<> | 144:ef7eb2e8f9f7 | 2100 | |
<> | 144:ef7eb2e8f9f7 | 2101 | #endif /* HAL_ADC_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 2102 | /** |
<> | 144:ef7eb2e8f9f7 | 2103 | * @} |
<> | 144:ef7eb2e8f9f7 | 2104 | */ |
<> | 144:ef7eb2e8f9f7 | 2105 | |
<> | 144:ef7eb2e8f9f7 | 2106 | /** |
<> | 144:ef7eb2e8f9f7 | 2107 | * @} |
<> | 144:ef7eb2e8f9f7 | 2108 | */ |
<> | 144:ef7eb2e8f9f7 | 2109 | |
<> | 144:ef7eb2e8f9f7 | 2110 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |