mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
187:0387e8f68319 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 187:0387e8f68319 5 * @brief This file contains all the functions prototypes for the HAL
<> 144:ef7eb2e8f9f7 6 * module driver.
<> 144:ef7eb2e8f9f7 7 ******************************************************************************
<> 144:ef7eb2e8f9f7 8 * @attention
<> 144:ef7eb2e8f9f7 9 *
AnnaBridge 165:e614a9f1c9e2 10 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 13 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 14 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 15 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 17 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 18 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 20 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 21 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 33 *
<> 144:ef7eb2e8f9f7 34 ******************************************************************************
AnnaBridge 187:0387e8f68319 35 */
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 38 #ifndef __STM32F1xx_HAL_H
<> 144:ef7eb2e8f9f7 39 #define __STM32F1xx_HAL_H
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #ifdef __cplusplus
AnnaBridge 187:0387e8f68319 42 extern "C" {
<> 144:ef7eb2e8f9f7 43 #endif
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 46 #include "stm32f1xx_hal_conf.h"
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /** @addtogroup HAL
<> 144:ef7eb2e8f9f7 53 * @{
AnnaBridge 187:0387e8f68319 54 */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58
AnnaBridge 187:0387e8f68319 59 /** @defgroup HAL_Exported_Constants HAL Exported Constants
AnnaBridge 187:0387e8f68319 60 * @{
AnnaBridge 187:0387e8f68319 61 */
AnnaBridge 187:0387e8f68319 62
AnnaBridge 187:0387e8f68319 63 /** @defgroup HAL_TICK_FREQ Tick Frequency
AnnaBridge 187:0387e8f68319 64 * @{
AnnaBridge 187:0387e8f68319 65 */
AnnaBridge 187:0387e8f68319 66 typedef enum
AnnaBridge 187:0387e8f68319 67 {
AnnaBridge 187:0387e8f68319 68 HAL_TICK_FREQ_10HZ = 100U,
AnnaBridge 187:0387e8f68319 69 HAL_TICK_FREQ_100HZ = 10U,
AnnaBridge 187:0387e8f68319 70 HAL_TICK_FREQ_1KHZ = 1U,
AnnaBridge 187:0387e8f68319 71 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
AnnaBridge 187:0387e8f68319 72 } HAL_TickFreqTypeDef;
AnnaBridge 187:0387e8f68319 73 /**
AnnaBridge 187:0387e8f68319 74 * @}
AnnaBridge 187:0387e8f68319 75 */
AnnaBridge 187:0387e8f68319 76
AnnaBridge 187:0387e8f68319 77 /**
AnnaBridge 187:0387e8f68319 78 * @}
AnnaBridge 187:0387e8f68319 79 */
<> 144:ef7eb2e8f9f7 80 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 /** @defgroup HAL_Exported_Macros HAL Exported Macros
<> 144:ef7eb2e8f9f7 82 * @{
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
AnnaBridge 187:0387e8f68319 86 * @brief Freeze/Unfreeze Peripherals in Debug mode
<> 144:ef7eb2e8f9f7 87 * Note: On devices STM32F10xx8 and STM32F10xxB,
<> 144:ef7eb2e8f9f7 88 * STM32F101xC/D/E and STM32F103xC/D/E,
<> 144:ef7eb2e8f9f7 89 * STM32F101xF/G and STM32F103xF/G
<> 144:ef7eb2e8f9f7 90 * STM32F10xx4 and STM32F10xx6
AnnaBridge 187:0387e8f68319 91 * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
<> 144:ef7eb2e8f9f7 92 * debug mode (not accessible by the user software in normal mode).
<> 144:ef7eb2e8f9f7 93 * Refer to errata sheet of these devices for more details.
<> 144:ef7eb2e8f9f7 94 * @{
<> 144:ef7eb2e8f9f7 95 */
AnnaBridge 187:0387e8f68319 96
<> 144:ef7eb2e8f9f7 97 /* Peripherals on APB1 */
<> 144:ef7eb2e8f9f7 98 /**
AnnaBridge 187:0387e8f68319 99 * @brief TIM2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 102 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /**
AnnaBridge 187:0387e8f68319 105 * @brief TIM3 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 108 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #if defined (DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 111 /**
AnnaBridge 187:0387e8f68319 112 * @brief TIM4 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 115 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
<> 144:ef7eb2e8f9f7 116 #endif
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #if defined (DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 119 /**
AnnaBridge 187:0387e8f68319 120 * @brief TIM5 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 123 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
<> 144:ef7eb2e8f9f7 124 #endif
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #if defined (DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 127 /**
AnnaBridge 187:0387e8f68319 128 * @brief TIM6 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 131 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
<> 144:ef7eb2e8f9f7 132 #endif
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #if defined (DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 135 /**
AnnaBridge 187:0387e8f68319 136 * @brief TIM7 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 139 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
<> 144:ef7eb2e8f9f7 140 #endif
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #if defined (DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 143 /**
AnnaBridge 187:0387e8f68319 144 * @brief TIM12 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 147 #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
<> 144:ef7eb2e8f9f7 148 #endif
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #if defined (DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 151 /**
AnnaBridge 187:0387e8f68319 152 * @brief TIM13 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 155 #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
<> 144:ef7eb2e8f9f7 156 #endif
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 #if defined (DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 159 /**
AnnaBridge 187:0387e8f68319 160 * @brief TIM14 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162 #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 163 #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
<> 144:ef7eb2e8f9f7 164 #endif
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
AnnaBridge 187:0387e8f68319 167 * @brief WWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 170 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
AnnaBridge 187:0387e8f68319 173 * @brief IWDG Peripherals Debug mode
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 176 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /**
AnnaBridge 187:0387e8f68319 179 * @brief I2C1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 182 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 185 /**
AnnaBridge 187:0387e8f68319 186 * @brief I2C2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 189 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
<> 144:ef7eb2e8f9f7 190 #endif
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #if defined (DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 193 /**
AnnaBridge 187:0387e8f68319 194 * @brief CAN1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 197 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
<> 144:ef7eb2e8f9f7 198 #endif
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 #if defined (DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 201 /**
AnnaBridge 187:0387e8f68319 202 * @brief CAN2 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
<> 144:ef7eb2e8f9f7 205 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
AnnaBridge 187:0387e8f68319 206 #endif
AnnaBridge 187:0387e8f68319 207
<> 144:ef7eb2e8f9f7 208 /* Peripherals on APB2 */
<> 144:ef7eb2e8f9f7 209 #if defined (DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 210 /**
AnnaBridge 187:0387e8f68319 211 * @brief TIM1 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 214 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
<> 144:ef7eb2e8f9f7 215 #endif
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #if defined (DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 218 /**
AnnaBridge 187:0387e8f68319 219 * @brief TIM8 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 222 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
<> 144:ef7eb2e8f9f7 223 #endif
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #if defined (DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 226 /**
AnnaBridge 187:0387e8f68319 227 * @brief TIM9 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229 #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 230 #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
<> 144:ef7eb2e8f9f7 231 #endif
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 #if defined (DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 234 /**
AnnaBridge 187:0387e8f68319 235 * @brief TIM10 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 238 #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
<> 144:ef7eb2e8f9f7 239 #endif
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #if defined (DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 242 /**
AnnaBridge 187:0387e8f68319 243 * @brief TIM11 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 246 #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
<> 144:ef7eb2e8f9f7 247 #endif
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 #if defined (DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 251 /**
AnnaBridge 187:0387e8f68319 252 * @brief TIM15 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 255 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
<> 144:ef7eb2e8f9f7 256 #endif
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 #if defined (DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 259 /**
AnnaBridge 187:0387e8f68319 260 * @brief TIM16 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 263 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
<> 144:ef7eb2e8f9f7 264 #endif
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 #if defined (DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 267 /**
AnnaBridge 187:0387e8f68319 268 * @brief TIM17 Peripherals Debug mode
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 271 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
<> 144:ef7eb2e8f9f7 272 #endif
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @}
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
AnnaBridge 187:0387e8f68319 278 /** @defgroup HAL_Private_Macros HAL Private Macros
AnnaBridge 187:0387e8f68319 279 * @{
AnnaBridge 187:0387e8f68319 280 */
AnnaBridge 187:0387e8f68319 281 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
AnnaBridge 187:0387e8f68319 282 ((FREQ) == HAL_TICK_FREQ_100HZ) || \
AnnaBridge 187:0387e8f68319 283 ((FREQ) == HAL_TICK_FREQ_1KHZ))
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 289 /** @addtogroup HAL_Exported_Functions
<> 144:ef7eb2e8f9f7 290 * @{
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 /** @addtogroup HAL_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 /* Initialization and de-initialization functions ******************************/
<> 144:ef7eb2e8f9f7 296 HAL_StatusTypeDef HAL_Init(void);
<> 144:ef7eb2e8f9f7 297 HAL_StatusTypeDef HAL_DeInit(void);
AnnaBridge 165:e614a9f1c9e2 298 void HAL_MspInit(void);
AnnaBridge 165:e614a9f1c9e2 299 void HAL_MspDeInit(void);
AnnaBridge 187:0387e8f68319 300 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @}
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /** @addtogroup HAL_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 /* Peripheral Control functions ************************************************/
AnnaBridge 165:e614a9f1c9e2 309 void HAL_IncTick(void);
AnnaBridge 187:0387e8f68319 310 void HAL_Delay(uint32_t Delay);
AnnaBridge 165:e614a9f1c9e2 311 uint32_t HAL_GetTick(void);
AnnaBridge 187:0387e8f68319 312 uint32_t HAL_GetTickPrio(void);
AnnaBridge 187:0387e8f68319 313 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
AnnaBridge 187:0387e8f68319 314 HAL_TickFreqTypeDef HAL_GetTickFreq(void);
AnnaBridge 165:e614a9f1c9e2 315 void HAL_SuspendTick(void);
AnnaBridge 165:e614a9f1c9e2 316 void HAL_ResumeTick(void);
AnnaBridge 165:e614a9f1c9e2 317 uint32_t HAL_GetHalVersion(void);
AnnaBridge 165:e614a9f1c9e2 318 uint32_t HAL_GetREVID(void);
AnnaBridge 165:e614a9f1c9e2 319 uint32_t HAL_GetDEVID(void);
AnnaBridge 165:e614a9f1c9e2 320 void HAL_DBGMCU_EnableDBGSleepMode(void);
AnnaBridge 165:e614a9f1c9e2 321 void HAL_DBGMCU_DisableDBGSleepMode(void);
AnnaBridge 165:e614a9f1c9e2 322 void HAL_DBGMCU_EnableDBGStopMode(void);
AnnaBridge 165:e614a9f1c9e2 323 void HAL_DBGMCU_DisableDBGStopMode(void);
AnnaBridge 165:e614a9f1c9e2 324 void HAL_DBGMCU_EnableDBGStandbyMode(void);
AnnaBridge 165:e614a9f1c9e2 325 void HAL_DBGMCU_DisableDBGStandbyMode(void);
AnnaBridge 165:e614a9f1c9e2 326 void HAL_GetUID(uint32_t *UID);
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @}
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @}
<> 144:ef7eb2e8f9f7 333 */
AnnaBridge 165:e614a9f1c9e2 334 /* Private types -------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 335 /* Private variables ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 336 /** @defgroup HAL_Private_Variables HAL Private Variables
AnnaBridge 165:e614a9f1c9e2 337 * @{
AnnaBridge 165:e614a9f1c9e2 338 */
<> 144:ef7eb2e8f9f7 339 /**
<> 144:ef7eb2e8f9f7 340 * @}
AnnaBridge 165:e614a9f1c9e2 341 */
AnnaBridge 165:e614a9f1c9e2 342 /* Private constants ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 343 /** @defgroup HAL_Private_Constants HAL Private Constants
AnnaBridge 165:e614a9f1c9e2 344 * @{
AnnaBridge 165:e614a9f1c9e2 345 */
AnnaBridge 165:e614a9f1c9e2 346 /**
AnnaBridge 165:e614a9f1c9e2 347 * @}
AnnaBridge 165:e614a9f1c9e2 348 */
AnnaBridge 165:e614a9f1c9e2 349 /* Private macros ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 350 /* Private functions ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 351 /**
AnnaBridge 165:e614a9f1c9e2 352 * @}
AnnaBridge 165:e614a9f1c9e2 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @}
AnnaBridge 187:0387e8f68319 357 */
AnnaBridge 187:0387e8f68319 358
<> 144:ef7eb2e8f9f7 359 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 360 }
<> 144:ef7eb2e8f9f7 361 #endif
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 #endif /* __STM32F1xx_HAL_H */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/