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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 87:444eeba2d452

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f4xx_hal_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.0
<>	144:ef7eb2e8f9f7	6	* @date 06-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of RCC HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F4xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F4xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f4xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/* Include RCC HAL Extended module */
<>	144:ef7eb2e8f9f7	50	/* (include on top of file since RCC structures are defined in extended file) */
<>	144:ef7eb2e8f9f7	51	#include "stm32f4xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup STM32F4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/** @addtogroup RCC
<>	144:ef7eb2e8f9f7	58	* @{
<>	144:ef7eb2e8f9f7	59	*/
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	62	/** @defgroup RCC_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	63	* @{
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	/**
<>	144:ef7eb2e8f9f7	67	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<>	144:ef7eb2e8f9f7	68	*/
<>	144:ef7eb2e8f9f7	69	typedef struct
<>	144:ef7eb2e8f9f7	70	{
<>	144:ef7eb2e8f9f7	71	uint32_t OscillatorType; /*!< The oscillators to be configured.
<>	144:ef7eb2e8f9f7	72	This parameter can be a value of @ref RCC_Oscillator_Type */
<>	144:ef7eb2e8f9f7	73
<>	144:ef7eb2e8f9f7	74	uint32_t HSEState; /*!< The new state of the HSE.
<>	144:ef7eb2e8f9f7	75	This parameter can be a value of @ref RCC_HSE_Config */
<>	144:ef7eb2e8f9f7	76
<>	144:ef7eb2e8f9f7	77	uint32_t LSEState; /*!< The new state of the LSE.
<>	144:ef7eb2e8f9f7	78	This parameter can be a value of @ref RCC_LSE_Config */
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	uint32_t HSIState; /*!< The new state of the HSI.
<>	144:ef7eb2e8f9f7	81	This parameter can be a value of @ref RCC_HSI_Config */
<>	144:ef7eb2e8f9f7	82
<>	144:ef7eb2e8f9f7	83	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	84	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
<>	144:ef7eb2e8f9f7	85
<>	144:ef7eb2e8f9f7	86	uint32_t LSIState; /*!< The new state of the LSI.
<>	144:ef7eb2e8f9f7	87	This parameter can be a value of @ref RCC_LSI_Config */
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
<>	144:ef7eb2e8f9f7	90	}RCC_OscInitTypeDef;
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	/**
<>	144:ef7eb2e8f9f7	93	* @brief RCC System, AHB and APB busses clock configuration structure definition
<>	144:ef7eb2e8f9f7	94	*/
<>	144:ef7eb2e8f9f7	95	typedef struct
<>	144:ef7eb2e8f9f7	96	{
<>	144:ef7eb2e8f9f7	97	uint32_t ClockType; /*!< The clock to be configured.
<>	144:ef7eb2e8f9f7	98	This parameter can be a value of @ref RCC_System_Clock_Type */
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<>	144:ef7eb2e8f9f7	101	This parameter can be a value of @ref RCC_System_Clock_Source */
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	104	This parameter can be a value of @ref RCC_AHB_Clock_Source */
<>	144:ef7eb2e8f9f7	105
<>	144:ef7eb2e8f9f7	106	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	107	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	110	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	}RCC_ClkInitTypeDef;
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	/**
<>	144:ef7eb2e8f9f7	115	* @}
<>	144:ef7eb2e8f9f7	116	*/
<>	144:ef7eb2e8f9f7	117
<>	144:ef7eb2e8f9f7	118	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	119	/** @defgroup RCC_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	120	* @{
<>	144:ef7eb2e8f9f7	121	*/
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	/** @defgroup RCC_Oscillator_Type Oscillator Type
<>	144:ef7eb2e8f9f7	124	* @{
<>	144:ef7eb2e8f9f7	125	*/
<>	144:ef7eb2e8f9f7	126	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	127	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	128	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	129	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	130	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	131	/**
<>	144:ef7eb2e8f9f7	132	* @}
<>	144:ef7eb2e8f9f7	133	*/
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/** @defgroup RCC_HSE_Config HSE Config
<>	144:ef7eb2e8f9f7	136	* @{
<>	144:ef7eb2e8f9f7	137	*/
<>	144:ef7eb2e8f9f7	138	#define RCC_HSE_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	139	#define RCC_HSE_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	140	#define RCC_HSE_BYPASS ((uint8_t)0x05U)
<>	144:ef7eb2e8f9f7	141	/**
<>	144:ef7eb2e8f9f7	142	* @}
<>	144:ef7eb2e8f9f7	143	*/
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	/** @defgroup RCC_LSE_Config LSE Config
<>	144:ef7eb2e8f9f7	146	* @{
<>	144:ef7eb2e8f9f7	147	*/
<>	144:ef7eb2e8f9f7	148	#define RCC_LSE_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	149	#define RCC_LSE_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	150	#define RCC_LSE_BYPASS ((uint8_t)0x05U)
<>	144:ef7eb2e8f9f7	151	/**
<>	144:ef7eb2e8f9f7	152	* @}
<>	144:ef7eb2e8f9f7	153	*/
<>	144:ef7eb2e8f9f7	154
<>	144:ef7eb2e8f9f7	155	/** @defgroup RCC_HSI_Config HSI Config
<>	144:ef7eb2e8f9f7	156	* @{
<>	144:ef7eb2e8f9f7	157	*/
<>	144:ef7eb2e8f9f7	158	#define RCC_HSI_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	159	#define RCC_HSI_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	160
<>	144:ef7eb2e8f9f7	161	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
<>	144:ef7eb2e8f9f7	162	/**
<>	144:ef7eb2e8f9f7	163	* @}
<>	144:ef7eb2e8f9f7	164	*/
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	/** @defgroup RCC_LSI_Config LSI Config
<>	144:ef7eb2e8f9f7	167	* @{
<>	144:ef7eb2e8f9f7	168	*/
<>	144:ef7eb2e8f9f7	169	#define RCC_LSI_OFF ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	170	#define RCC_LSI_ON ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	171	/**
<>	144:ef7eb2e8f9f7	172	* @}
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	/** @defgroup RCC_PLL_Config PLL Config
<>	144:ef7eb2e8f9f7	176	* @{
<>	144:ef7eb2e8f9f7	177	*/
<>	144:ef7eb2e8f9f7	178	#define RCC_PLL_NONE ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	179	#define RCC_PLL_OFF ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	180	#define RCC_PLL_ON ((uint8_t)0x02U)
<>	144:ef7eb2e8f9f7	181	/**
<>	144:ef7eb2e8f9f7	182	* @}
<>	144:ef7eb2e8f9f7	183	*/
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
<>	144:ef7eb2e8f9f7	186	* @{
<>	144:ef7eb2e8f9f7	187	*/
<>	144:ef7eb2e8f9f7	188	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	189	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	190	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
<>	144:ef7eb2e8f9f7	191	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	192	/**
<>	144:ef7eb2e8f9f7	193	* @}
<>	144:ef7eb2e8f9f7	194	*/
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<>	144:ef7eb2e8f9f7	197	* @{
<>	144:ef7eb2e8f9f7	198	*/
<>	144:ef7eb2e8f9f7	199	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
<>	144:ef7eb2e8f9f7	200	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
<>	144:ef7eb2e8f9f7	201	/**
<>	144:ef7eb2e8f9f7	202	* @}
<>	144:ef7eb2e8f9f7	203	*/
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/** @defgroup RCC_System_Clock_Type System Clock Type
<>	144:ef7eb2e8f9f7	206	* @{
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	209	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	210	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	211	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	212	/**
<>	144:ef7eb2e8f9f7	213	* @}
<>	144:ef7eb2e8f9f7	214	*/
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	/** @defgroup RCC_System_Clock_Source System Clock Source
<>	144:ef7eb2e8f9f7	217	* @{
<>	144:ef7eb2e8f9f7	218	*/
<>	144:ef7eb2e8f9f7	219	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
<>	144:ef7eb2e8f9f7	220	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
<>	144:ef7eb2e8f9f7	221	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
<>	144:ef7eb2e8f9f7	222	#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1))
<>	144:ef7eb2e8f9f7	223	/**
<>	144:ef7eb2e8f9f7	224	* @}
<>	144:ef7eb2e8f9f7	225	*/
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
<>	144:ef7eb2e8f9f7	228	* @{
<>	144:ef7eb2e8f9f7	229	*/
<>	144:ef7eb2e8f9f7	230	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	144:ef7eb2e8f9f7	231	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	144:ef7eb2e8f9f7	232	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	233	#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 \| RCC_CFGR_SWS_1)) /!< PLLR used as system clock /
<>	144:ef7eb2e8f9f7	234	/**
<>	144:ef7eb2e8f9f7	235	* @}
<>	144:ef7eb2e8f9f7	236	*/
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
<>	144:ef7eb2e8f9f7	239	* @{
<>	144:ef7eb2e8f9f7	240	*/
<>	144:ef7eb2e8f9f7	241	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
<>	144:ef7eb2e8f9f7	242	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
<>	144:ef7eb2e8f9f7	243	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
<>	144:ef7eb2e8f9f7	244	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
<>	144:ef7eb2e8f9f7	245	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
<>	144:ef7eb2e8f9f7	246	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
<>	144:ef7eb2e8f9f7	247	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
<>	144:ef7eb2e8f9f7	248	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
<>	144:ef7eb2e8f9f7	249	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
<>	144:ef7eb2e8f9f7	250	/**
<>	144:ef7eb2e8f9f7	251	* @}
<>	144:ef7eb2e8f9f7	252	*/
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
<>	144:ef7eb2e8f9f7	255	* @{
<>	144:ef7eb2e8f9f7	256	*/
<>	144:ef7eb2e8f9f7	257	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
<>	144:ef7eb2e8f9f7	258	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
<>	144:ef7eb2e8f9f7	259	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
<>	144:ef7eb2e8f9f7	260	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
<>	144:ef7eb2e8f9f7	261	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
<>	144:ef7eb2e8f9f7	262	/**
<>	144:ef7eb2e8f9f7	263	* @}
<>	144:ef7eb2e8f9f7	264	*/
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
<>	144:ef7eb2e8f9f7	267	* @{
<>	144:ef7eb2e8f9f7	268	*/
<>	144:ef7eb2e8f9f7	269	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	270	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	271	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
<>	144:ef7eb2e8f9f7	272	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
<>	144:ef7eb2e8f9f7	273	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
<>	144:ef7eb2e8f9f7	274	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
<>	144:ef7eb2e8f9f7	275	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
<>	144:ef7eb2e8f9f7	276	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
<>	144:ef7eb2e8f9f7	277	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
<>	144:ef7eb2e8f9f7	278	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
<>	144:ef7eb2e8f9f7	279	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
<>	144:ef7eb2e8f9f7	280	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
<>	144:ef7eb2e8f9f7	281	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
<>	144:ef7eb2e8f9f7	282	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
<>	144:ef7eb2e8f9f7	283	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
<>	144:ef7eb2e8f9f7	284	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
<>	144:ef7eb2e8f9f7	285	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
<>	144:ef7eb2e8f9f7	286	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
<>	144:ef7eb2e8f9f7	287	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
<>	144:ef7eb2e8f9f7	288	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
<>	144:ef7eb2e8f9f7	289	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
<>	144:ef7eb2e8f9f7	290	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
<>	144:ef7eb2e8f9f7	291	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
<>	144:ef7eb2e8f9f7	292	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
<>	144:ef7eb2e8f9f7	293	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
<>	144:ef7eb2e8f9f7	294	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
<>	144:ef7eb2e8f9f7	295	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
<>	144:ef7eb2e8f9f7	296	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
<>	144:ef7eb2e8f9f7	297	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
<>	144:ef7eb2e8f9f7	298	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
<>	144:ef7eb2e8f9f7	299	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
<>	144:ef7eb2e8f9f7	300	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
<>	144:ef7eb2e8f9f7	301	/**
<>	144:ef7eb2e8f9f7	302	* @}
<>	144:ef7eb2e8f9f7	303	*/
<>	144:ef7eb2e8f9f7	304
<>	144:ef7eb2e8f9f7	305	/** @defgroup RCC_MCO_Index MCO Index
<>	144:ef7eb2e8f9f7	306	* @{
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308	#define RCC_MCO1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	309	#define RCC_MCO2 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	310	/**
<>	144:ef7eb2e8f9f7	311	* @}
<>	144:ef7eb2e8f9f7	312	*/
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
<>	144:ef7eb2e8f9f7	315	* @{
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	318	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
<>	144:ef7eb2e8f9f7	319	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
<>	144:ef7eb2e8f9f7	320	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
<>	144:ef7eb2e8f9f7	321	/**
<>	144:ef7eb2e8f9f7	322	* @}
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
<>	144:ef7eb2e8f9f7	326	* @{
<>	144:ef7eb2e8f9f7	327	*/
<>	144:ef7eb2e8f9f7	328	#define RCC_MCODIV_1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	329	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
<>	144:ef7eb2e8f9f7	330	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
<>	144:ef7eb2e8f9f7	331	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
<>	144:ef7eb2e8f9f7	332	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
<>	144:ef7eb2e8f9f7	333	/**
<>	144:ef7eb2e8f9f7	334	* @}
<>	144:ef7eb2e8f9f7	335	*/
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/** @defgroup RCC_Interrupt Interrupts
<>	144:ef7eb2e8f9f7	338	* @{
<>	144:ef7eb2e8f9f7	339	*/
<>	144:ef7eb2e8f9f7	340	#define RCC_IT_LSIRDY ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	341	#define RCC_IT_LSERDY ((uint8_t)0x02U)
<>	144:ef7eb2e8f9f7	342	#define RCC_IT_HSIRDY ((uint8_t)0x04U)
<>	144:ef7eb2e8f9f7	343	#define RCC_IT_HSERDY ((uint8_t)0x08U)
<>	144:ef7eb2e8f9f7	344	#define RCC_IT_PLLRDY ((uint8_t)0x10U)
<>	144:ef7eb2e8f9f7	345	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
<>	144:ef7eb2e8f9f7	346	#define RCC_IT_CSS ((uint8_t)0x80U)
<>	144:ef7eb2e8f9f7	347	/**
<>	144:ef7eb2e8f9f7	348	* @}
<>	144:ef7eb2e8f9f7	349	*/
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/** @defgroup RCC_Flag Flags
<>	144:ef7eb2e8f9f7	352	* Elements values convention: 0XXYYYYYb
<>	144:ef7eb2e8f9f7	353	* - YYYYY : Flag position in the register
<>	144:ef7eb2e8f9f7	354	* - 0XX : Register index
<>	144:ef7eb2e8f9f7	355	* - 01: CR register
<>	144:ef7eb2e8f9f7	356	* - 10: BDCR register
<>	144:ef7eb2e8f9f7	357	* - 11: CSR register
<>	144:ef7eb2e8f9f7	358	* @{
<>	144:ef7eb2e8f9f7	359	*/
<>	144:ef7eb2e8f9f7	360	/* Flags in the CR register */
<>	144:ef7eb2e8f9f7	361	#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
<>	144:ef7eb2e8f9f7	362	#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
<>	144:ef7eb2e8f9f7	363	#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
<>	144:ef7eb2e8f9f7	364	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/* Flags in the BDCR register */
<>	144:ef7eb2e8f9f7	367	#define RCC_FLAG_LSERDY ((uint8_t)0x41U)
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/* Flags in the CSR register */
<>	144:ef7eb2e8f9f7	370	#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
<>	144:ef7eb2e8f9f7	371	#define RCC_FLAG_BORRST ((uint8_t)0x79U)
<>	144:ef7eb2e8f9f7	372	#define RCC_FLAG_PINRST ((uint8_t)0x7AU)
<>	144:ef7eb2e8f9f7	373	#define RCC_FLAG_PORRST ((uint8_t)0x7BU)
<>	144:ef7eb2e8f9f7	374	#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
<>	144:ef7eb2e8f9f7	375	#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
<>	144:ef7eb2e8f9f7	376	#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
<>	144:ef7eb2e8f9f7	377	#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
<>	144:ef7eb2e8f9f7	378	/**
<>	144:ef7eb2e8f9f7	379	* @}
<>	144:ef7eb2e8f9f7	380	*/
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/**
<>	144:ef7eb2e8f9f7	383	* @}
<>	144:ef7eb2e8f9f7	384	*/
<>	144:ef7eb2e8f9f7	385
<>	144:ef7eb2e8f9f7	386	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	387	/** @defgroup RCC_Exported_Macros RCC Exported Macros
<>	144:ef7eb2e8f9f7	388	* @{
<>	144:ef7eb2e8f9f7	389	*/
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	392	* @brief Enable or disable the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	393	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	394	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	395	* using it.
<>	144:ef7eb2e8f9f7	396	* @{
<>	144:ef7eb2e8f9f7	397	*/
<>	144:ef7eb2e8f9f7	398	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	399	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	400	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	401	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	402	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	403	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	404	} while(0)
<>	144:ef7eb2e8f9f7	405	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	406	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	407	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	408	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	409	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	410	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	411	} while(0)
<>	144:ef7eb2e8f9f7	412	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	413	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	414	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	415	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	416	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	417	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	418	} while(0)
<>	144:ef7eb2e8f9f7	419	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	420	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	421	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	422	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	423	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	424	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	425	} while(0)
<>	144:ef7eb2e8f9f7	426	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	427	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	428	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	429	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	430	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	431	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	432	} while(0)
<>	144:ef7eb2e8f9f7	433	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	434	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	435	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<>	144:ef7eb2e8f9f7	436	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	437	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<>	144:ef7eb2e8f9f7	438	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	439	} while(0)
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
<>	144:ef7eb2e8f9f7	442	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
<>	144:ef7eb2e8f9f7	443	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
<>	144:ef7eb2e8f9f7	444	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
<>	144:ef7eb2e8f9f7	445	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
<>	144:ef7eb2e8f9f7	446	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
<>	144:ef7eb2e8f9f7	447	/**
<>	144:ef7eb2e8f9f7	448	* @}
<>	144:ef7eb2e8f9f7	449	*/
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	452	* @brief Get the enable or disable status of the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	453	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	454	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	455	* using it.
<>	144:ef7eb2e8f9f7	456	* @{
<>	144:ef7eb2e8f9f7	457	*/
<>	144:ef7eb2e8f9f7	458	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
<>	144:ef7eb2e8f9f7	459	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
<>	144:ef7eb2e8f9f7	460	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
<>	144:ef7eb2e8f9f7	461	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
<>	144:ef7eb2e8f9f7	462	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
<>	144:ef7eb2e8f9f7	463	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
<>	144:ef7eb2e8f9f7	466	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
<>	144:ef7eb2e8f9f7	467	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
<>	144:ef7eb2e8f9f7	468	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
<>	144:ef7eb2e8f9f7	469	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
<>	144:ef7eb2e8f9f7	470	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
<>	144:ef7eb2e8f9f7	471	/**
<>	144:ef7eb2e8f9f7	472	* @}
<>	144:ef7eb2e8f9f7	473	*/
<>	144:ef7eb2e8f9f7	474
<>	144:ef7eb2e8f9f7	475	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	476	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<>	144:ef7eb2e8f9f7	477	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	478	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	479	* using it.
<>	144:ef7eb2e8f9f7	480	* @{
<>	144:ef7eb2e8f9f7	481	*/
<>	144:ef7eb2e8f9f7	482	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	483	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	484	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<>	144:ef7eb2e8f9f7	485	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	486	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<>	144:ef7eb2e8f9f7	487	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	488	} while(0)
<>	144:ef7eb2e8f9f7	489	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	490	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	491	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	492	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	493	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	494	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	495	} while(0)
<>	144:ef7eb2e8f9f7	496	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	497	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	498	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<>	144:ef7eb2e8f9f7	499	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	500	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<>	144:ef7eb2e8f9f7	501	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	502	} while(0)
<>	144:ef7eb2e8f9f7	503	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	504	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	505	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	506	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	507	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	508	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	509	} while(0)
<>	144:ef7eb2e8f9f7	510	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	511	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	512	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	513	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	514	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	515	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	516	} while(0)
<>	144:ef7eb2e8f9f7	517	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	518	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	519	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<>	144:ef7eb2e8f9f7	520	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	521	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<>	144:ef7eb2e8f9f7	522	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	523	} while(0)
<>	144:ef7eb2e8f9f7	524	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	525	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	526	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	527	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	528	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	529	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	530	} while(0)
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
<>	144:ef7eb2e8f9f7	533	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	534	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<>	144:ef7eb2e8f9f7	535	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<>	144:ef7eb2e8f9f7	536	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
<>	144:ef7eb2e8f9f7	537	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<>	144:ef7eb2e8f9f7	538	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	539	/**
<>	144:ef7eb2e8f9f7	540	* @}
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	544	* @brief Get the enable or disable status of the APB1 peripheral clock.
<>	144:ef7eb2e8f9f7	545	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	546	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	547	* using it.
<>	144:ef7eb2e8f9f7	548	* @{
<>	144:ef7eb2e8f9f7	549	*/
<>	144:ef7eb2e8f9f7	550	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
<>	144:ef7eb2e8f9f7	551	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
<>	144:ef7eb2e8f9f7	552	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
<>	144:ef7eb2e8f9f7	553	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
<>	144:ef7eb2e8f9f7	554	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
<>	144:ef7eb2e8f9f7	555	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
<>	144:ef7eb2e8f9f7	556	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
<>	144:ef7eb2e8f9f7	559	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
<>	144:ef7eb2e8f9f7	560	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
<>	144:ef7eb2e8f9f7	561	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
<>	144:ef7eb2e8f9f7	562	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
<>	144:ef7eb2e8f9f7	563	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
<>	144:ef7eb2e8f9f7	564	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
<>	144:ef7eb2e8f9f7	565	/**
<>	144:ef7eb2e8f9f7	566	* @}
<>	144:ef7eb2e8f9f7	567	*/
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	570	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<>	144:ef7eb2e8f9f7	571	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	572	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	573	* using it.
<>	144:ef7eb2e8f9f7	574	* @{
<>	144:ef7eb2e8f9f7	575	*/
<>	144:ef7eb2e8f9f7	576	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	577	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	578	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	579	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	580	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	581	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	582	} while(0)
<>	144:ef7eb2e8f9f7	583	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	584	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	585	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	586	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	587	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	588	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	589	} while(0)
<>	144:ef7eb2e8f9f7	590	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	591	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	592	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<>	144:ef7eb2e8f9f7	593	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	594	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<>	144:ef7eb2e8f9f7	595	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	596	} while(0)
<>	144:ef7eb2e8f9f7	597	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	598	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	599	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	600	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	601	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	602	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	603	} while(0)
<>	144:ef7eb2e8f9f7	604	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	605	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	606	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	607	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	608	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	609	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	610	} while(0)
<>	144:ef7eb2e8f9f7	611	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	612	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	613	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<>	144:ef7eb2e8f9f7	614	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	615	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<>	144:ef7eb2e8f9f7	616	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	617	} while(0)
<>	144:ef7eb2e8f9f7	618	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	619	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	620	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<>	144:ef7eb2e8f9f7	621	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	622	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<>	144:ef7eb2e8f9f7	623	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	624	} while(0)
<>	144:ef7eb2e8f9f7	625	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	626	__IO uint32_t tmpreg = 0x00U; \
<>	144:ef7eb2e8f9f7	627	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<>	144:ef7eb2e8f9f7	628	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	629	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<>	144:ef7eb2e8f9f7	630	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	631	} while(0)
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
<>	144:ef7eb2e8f9f7	634	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
<>	144:ef7eb2e8f9f7	635	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
<>	144:ef7eb2e8f9f7	636	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
<>	144:ef7eb2e8f9f7	637	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
<>	144:ef7eb2e8f9f7	638	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
<>	144:ef7eb2e8f9f7	639	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
<>	144:ef7eb2e8f9f7	640	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
<>	144:ef7eb2e8f9f7	641	/**
<>	144:ef7eb2e8f9f7	642	* @}
<>	144:ef7eb2e8f9f7	643	*/
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	646	* @brief Get the enable or disable status of the APB2 peripheral clock.
<>	144:ef7eb2e8f9f7	647	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	648	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	649	* using it.
<>	144:ef7eb2e8f9f7	650	* @{
<>	144:ef7eb2e8f9f7	651	*/
<>	144:ef7eb2e8f9f7	652	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
<>	144:ef7eb2e8f9f7	653	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
<>	144:ef7eb2e8f9f7	654	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
<>	144:ef7eb2e8f9f7	655	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
<>	144:ef7eb2e8f9f7	656	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
<>	144:ef7eb2e8f9f7	657	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
<>	144:ef7eb2e8f9f7	658	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
<>	144:ef7eb2e8f9f7	659	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
<>	144:ef7eb2e8f9f7	662	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
<>	144:ef7eb2e8f9f7	663	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
<>	144:ef7eb2e8f9f7	664	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
<>	144:ef7eb2e8f9f7	665	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
<>	144:ef7eb2e8f9f7	666	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
<>	144:ef7eb2e8f9f7	667	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
<>	144:ef7eb2e8f9f7	668	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
<>	144:ef7eb2e8f9f7	669	/**
<>	144:ef7eb2e8f9f7	670	* @}
<>	144:ef7eb2e8f9f7	671	*/
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
<>	144:ef7eb2e8f9f7	674	* @brief Force or release AHB1 peripheral reset.
<>	144:ef7eb2e8f9f7	675	* @{
<>	144:ef7eb2e8f9f7	676	*/
<>	144:ef7eb2e8f9f7	677	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	678	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	679	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	680	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	681	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	682	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	683	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	686	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	687	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	688	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	689	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	690	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	691	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
<>	144:ef7eb2e8f9f7	692	/**
<>	144:ef7eb2e8f9f7	693	* @}
<>	144:ef7eb2e8f9f7	694	*/
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
<>	144:ef7eb2e8f9f7	697	* @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	698	* @{
<>	144:ef7eb2e8f9f7	699	*/
<>	144:ef7eb2e8f9f7	700	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	701	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
<>	144:ef7eb2e8f9f7	702	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	703	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
<>	144:ef7eb2e8f9f7	704	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	705	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	706	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
<>	144:ef7eb2e8f9f7	707	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	708
<>	144:ef7eb2e8f9f7	709	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	710	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<>	144:ef7eb2e8f9f7	711	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	712	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<>	144:ef7eb2e8f9f7	713	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	714	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	715	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<>	144:ef7eb2e8f9f7	716	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	717	/**
<>	144:ef7eb2e8f9f7	718	* @}
<>	144:ef7eb2e8f9f7	719	*/
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
<>	144:ef7eb2e8f9f7	722	* @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	723	* @{
<>	144:ef7eb2e8f9f7	724	*/
<>	144:ef7eb2e8f9f7	725	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	726	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	727	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	728	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
<>	144:ef7eb2e8f9f7	729	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
<>	144:ef7eb2e8f9f7	730	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	731	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	732	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
<>	144:ef7eb2e8f9f7	733	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	736	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	737	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	738	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
<>	144:ef7eb2e8f9f7	739	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
<>	144:ef7eb2e8f9f7	740	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	741	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	742	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
<>	144:ef7eb2e8f9f7	743	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
<>	144:ef7eb2e8f9f7	744	/**
<>	144:ef7eb2e8f9f7	745	* @}
<>	144:ef7eb2e8f9f7	746	*/
<>	144:ef7eb2e8f9f7	747
<>	144:ef7eb2e8f9f7	748	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	749	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	750	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	751	* power consumption.
<>	144:ef7eb2e8f9f7	752	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	753	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	754	* @{
<>	144:ef7eb2e8f9f7	755	*/
<>	144:ef7eb2e8f9f7	756	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
<>	144:ef7eb2e8f9f7	757	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
<>	144:ef7eb2e8f9f7	758	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
<>	144:ef7eb2e8f9f7	759	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
<>	144:ef7eb2e8f9f7	760	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
<>	144:ef7eb2e8f9f7	761	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
<>	144:ef7eb2e8f9f7	764	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
<>	144:ef7eb2e8f9f7	765	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
<>	144:ef7eb2e8f9f7	766	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
<>	144:ef7eb2e8f9f7	767	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
<>	144:ef7eb2e8f9f7	768	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
<>	144:ef7eb2e8f9f7	769	/**
<>	144:ef7eb2e8f9f7	770	* @}
<>	144:ef7eb2e8f9f7	771	*/
<>	144:ef7eb2e8f9f7	772
<>	144:ef7eb2e8f9f7	773	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	774	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	775	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	776	* power consumption.
<>	144:ef7eb2e8f9f7	777	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	778	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	779	* @{
<>	144:ef7eb2e8f9f7	780	*/
<>	144:ef7eb2e8f9f7	781	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
<>	144:ef7eb2e8f9f7	782	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
<>	144:ef7eb2e8f9f7	783	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
<>	144:ef7eb2e8f9f7	784	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
<>	144:ef7eb2e8f9f7	785	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
<>	144:ef7eb2e8f9f7	786	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
<>	144:ef7eb2e8f9f7	787	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
<>	144:ef7eb2e8f9f7	788
<>	144:ef7eb2e8f9f7	789	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
<>	144:ef7eb2e8f9f7	790	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
<>	144:ef7eb2e8f9f7	791	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
<>	144:ef7eb2e8f9f7	792	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
<>	144:ef7eb2e8f9f7	793	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
<>	144:ef7eb2e8f9f7	794	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
<>	144:ef7eb2e8f9f7	795	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
<>	144:ef7eb2e8f9f7	796	/**
<>	144:ef7eb2e8f9f7	797	* @}
<>	144:ef7eb2e8f9f7	798	*/
<>	144:ef7eb2e8f9f7	799
<>	144:ef7eb2e8f9f7	800	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
<>	144:ef7eb2e8f9f7	801	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	802	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	803	* power consumption.
<>	144:ef7eb2e8f9f7	804	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	805	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	806	* @{
<>	144:ef7eb2e8f9f7	807	*/
<>	144:ef7eb2e8f9f7	808	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
<>	144:ef7eb2e8f9f7	809	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
<>	144:ef7eb2e8f9f7	810	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
<>	144:ef7eb2e8f9f7	811	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
<>	144:ef7eb2e8f9f7	812	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
<>	144:ef7eb2e8f9f7	813	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
<>	144:ef7eb2e8f9f7	814	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
<>	144:ef7eb2e8f9f7	815	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
<>	144:ef7eb2e8f9f7	818	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
<>	144:ef7eb2e8f9f7	819	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
<>	144:ef7eb2e8f9f7	820	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
<>	144:ef7eb2e8f9f7	821	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
<>	144:ef7eb2e8f9f7	822	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
<>	144:ef7eb2e8f9f7	823	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
<>	144:ef7eb2e8f9f7	824	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
<>	144:ef7eb2e8f9f7	825	/**
<>	144:ef7eb2e8f9f7	826	* @}
<>	144:ef7eb2e8f9f7	827	*/
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/** @defgroup RCC_HSI_Configuration HSI Configuration
<>	144:ef7eb2e8f9f7	830	* @{
<>	144:ef7eb2e8f9f7	831	*/
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<>	144:ef7eb2e8f9f7	834	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	835	* It is used (enabled by hardware) as system clock source after startup
<>	144:ef7eb2e8f9f7	836	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
<>	144:ef7eb2e8f9f7	837	* of the HSE used directly or indirectly as system clock (if the Clock
<>	144:ef7eb2e8f9f7	838	* Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	839	* @note HSI can not be stopped if it is used as system clock source. In this case,
<>	144:ef7eb2e8f9f7	840	* you have to select another source of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	841	* @note After enabling the HSI, the application software should wait on HSIRDY
<>	144:ef7eb2e8f9f7	842	* flag to be set indicating that HSI clock is stable and can be used as
<>	144:ef7eb2e8f9f7	843	* system clock source.
<>	144:ef7eb2e8f9f7	844	* This parameter can be: ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	845	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	846	* clock cycles.
<>	144:ef7eb2e8f9f7	847	*/
<>	144:ef7eb2e8f9f7	848	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
<>	144:ef7eb2e8f9f7	849	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
<>	144:ef7eb2e8f9f7	850
<>	144:ef7eb2e8f9f7	851	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<>	144:ef7eb2e8f9f7	852	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	853	* and temperature that influence the frequency of the internal HSI RC.
<>	144:ef7eb2e8f9f7	854	* @param __HSICalibrationValue__: specifies the calibration trimming value.
<>	144:ef7eb2e8f9f7	855	* (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	856	* This parameter must be a number between 0 and 0x1F.
<>	144:ef7eb2e8f9f7	857	*/
<>	144:ef7eb2e8f9f7	858	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
<>	144:ef7eb2e8f9f7	859	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
<>	144:ef7eb2e8f9f7	860	/**
<>	144:ef7eb2e8f9f7	861	* @}
<>	144:ef7eb2e8f9f7	862	*/
<>	144:ef7eb2e8f9f7	863
<>	144:ef7eb2e8f9f7	864	/** @defgroup RCC_LSI_Configuration LSI Configuration
<>	144:ef7eb2e8f9f7	865	* @{
<>	144:ef7eb2e8f9f7	866	*/
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	869	* @note After enabling the LSI, the application software should wait on
<>	144:ef7eb2e8f9f7	870	* LSIRDY flag to be set indicating that LSI clock is stable and can
<>	144:ef7eb2e8f9f7	871	* be used to clock the IWDG and/or the RTC.
<>	144:ef7eb2e8f9f7	872	* @note LSI can not be disabled if the IWDG is running.
<>	144:ef7eb2e8f9f7	873	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<>	144:ef7eb2e8f9f7	874	* clock cycles.
<>	144:ef7eb2e8f9f7	875	*/
<>	144:ef7eb2e8f9f7	876	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
<>	144:ef7eb2e8f9f7	877	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
<>	144:ef7eb2e8f9f7	878	/**
<>	144:ef7eb2e8f9f7	879	* @}
<>	144:ef7eb2e8f9f7	880	*/
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	/** @defgroup RCC_HSE_Configuration HSE Configuration
<>	144:ef7eb2e8f9f7	883	* @{
<>	144:ef7eb2e8f9f7	884	*/
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/**
<>	144:ef7eb2e8f9f7	887	* @brief Macro to configure the External High Speed oscillator (HSE).
<>	144:ef7eb2e8f9f7	888	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
<>	144:ef7eb2e8f9f7	889	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	890	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<>	144:ef7eb2e8f9f7	891	* software should wait on HSERDY flag to be set indicating that HSE clock
<>	144:ef7eb2e8f9f7	892	* is stable and can be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	893	* @note HSE state can not be changed if it is used directly or through the
<>	144:ef7eb2e8f9f7	894	* PLL as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	895	* of the system clock then change the HSE state (ex. disable it).
<>	144:ef7eb2e8f9f7	896	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	897	* @note This function reset the CSSON bit, so if the clock security system(CSS)
<>	144:ef7eb2e8f9f7	898	* was previously enabled you have to enable it again after calling this
<>	144:ef7eb2e8f9f7	899	* function.
<>	144:ef7eb2e8f9f7	900	* @param __STATE__: specifies the new state of the HSE.
<>	144:ef7eb2e8f9f7	901	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	902	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
<>	144:ef7eb2e8f9f7	903	* 6 HSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	904	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
<>	144:ef7eb2e8f9f7	905	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	906	*/
<>	144:ef7eb2e8f9f7	907	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__))
<>	144:ef7eb2e8f9f7	908	/**
<>	144:ef7eb2e8f9f7	909	* @}
<>	144:ef7eb2e8f9f7	910	*/
<>	144:ef7eb2e8f9f7	911
<>	144:ef7eb2e8f9f7	912	/** @defgroup RCC_LSE_Configuration LSE Configuration
<>	144:ef7eb2e8f9f7	913	* @{
<>	144:ef7eb2e8f9f7	914	*/
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	/**
<>	144:ef7eb2e8f9f7	917	* @brief Macro to configure the External Low Speed oscillator (LSE).
<>	144:ef7eb2e8f9f7	918	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
<>	144:ef7eb2e8f9f7	919	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
<>	144:ef7eb2e8f9f7	920	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	921	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	922	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	923	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	924	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<>	144:ef7eb2e8f9f7	925	* software should wait on LSERDY flag to be set indicating that LSE clock
<>	144:ef7eb2e8f9f7	926	* is stable and can be used to clock the RTC.
<>	144:ef7eb2e8f9f7	927	* @param __STATE__: specifies the new state of the LSE.
<>	144:ef7eb2e8f9f7	928	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	929	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
<>	144:ef7eb2e8f9f7	930	* 6 LSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	931	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
<>	144:ef7eb2e8f9f7	932	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	933	*/
<>	144:ef7eb2e8f9f7	934	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	/**
<>	144:ef7eb2e8f9f7	937	* @}
<>	144:ef7eb2e8f9f7	938	*/
<>	144:ef7eb2e8f9f7	939
<>	144:ef7eb2e8f9f7	940	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
<>	144:ef7eb2e8f9f7	941	* @{
<>	144:ef7eb2e8f9f7	942	*/
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/** @brief Macros to enable or disable the RTC clock.
<>	144:ef7eb2e8f9f7	945	* @note These macros must be used only after the RTC clock source was selected.
<>	144:ef7eb2e8f9f7	946	*/
<>	144:ef7eb2e8f9f7	947	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
<>	144:ef7eb2e8f9f7	948	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/** @brief Macros to configure the RTC clock (RTCCLK).
<>	144:ef7eb2e8f9f7	951	* @note As the RTC clock configuration bits are in the Backup domain and write
<>	144:ef7eb2e8f9f7	952	* access is denied to this domain after reset, you have to enable write
<>	144:ef7eb2e8f9f7	953	* access using the Power Backup Access macro before to configure
<>	144:ef7eb2e8f9f7	954	* the RTC clock source (to be done once after reset).
<>	144:ef7eb2e8f9f7	955	* @note Once the RTC clock is configured it can't be changed unless the
<>	144:ef7eb2e8f9f7	956	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
<>	144:ef7eb2e8f9f7	957	* a Power On Reset (POR).
<>	144:ef7eb2e8f9f7	958	* @param __RTCCLKSource__: specifies the RTC clock source.
<>	144:ef7eb2e8f9f7	959	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	960	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
<>	144:ef7eb2e8f9f7	961	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
<>	144:ef7eb2e8f9f7	962	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
<>	144:ef7eb2e8f9f7	963	* as RTC clock, where x:[2,31]
<>	144:ef7eb2e8f9f7	964	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<>	144:ef7eb2e8f9f7	965	* work in STOP and STANDBY modes, and can be used as wake-up source.
<>	144:ef7eb2e8f9f7	966	* However, when the HSE clock is used as RTC clock source, the RTC
<>	144:ef7eb2e8f9f7	967	* cannot be used in STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	968	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
<>	144:ef7eb2e8f9f7	969	* RTC clock source).
<>	144:ef7eb2e8f9f7	970	*/
<>	144:ef7eb2e8f9f7	971	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
<>	144:ef7eb2e8f9f7	972	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
<>	144:ef7eb2e8f9f7	975	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFFU); \
<>	144:ef7eb2e8f9f7	976	} while (0)
<>	144:ef7eb2e8f9f7	977
<>	144:ef7eb2e8f9f7	978	/** @brief Macros to force or release the Backup domain reset.
<>	144:ef7eb2e8f9f7	979	* @note This function resets the RTC peripheral (including the backup registers)
<>	144:ef7eb2e8f9f7	980	* and the RTC clock source selection in RCC_CSR register.
<>	144:ef7eb2e8f9f7	981	* @note The BKPSRAM is not affected by this reset.
<>	144:ef7eb2e8f9f7	982	*/
<>	144:ef7eb2e8f9f7	983	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
<>	144:ef7eb2e8f9f7	984	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
<>	144:ef7eb2e8f9f7	985	/**
<>	144:ef7eb2e8f9f7	986	* @}
<>	144:ef7eb2e8f9f7	987	*/
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/** @defgroup RCC_PLL_Configuration PLL Configuration
<>	144:ef7eb2e8f9f7	990	* @{
<>	144:ef7eb2e8f9f7	991	*/
<>	144:ef7eb2e8f9f7	992
<>	144:ef7eb2e8f9f7	993	/** @brief Macros to enable or disable the main PLL.
<>	144:ef7eb2e8f9f7	994	* @note After enabling the main PLL, the application software should wait on
<>	144:ef7eb2e8f9f7	995	* PLLRDY flag to be set indicating that PLL clock is stable and can
<>	144:ef7eb2e8f9f7	996	* be used as system clock source.
<>	144:ef7eb2e8f9f7	997	* @note The main PLL can not be disabled if it is used as system clock source
<>	144:ef7eb2e8f9f7	998	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	999	*/
<>	144:ef7eb2e8f9f7	1000	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
<>	144:ef7eb2e8f9f7	1001	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
<>	144:ef7eb2e8f9f7	1002
<>	144:ef7eb2e8f9f7	1003	/** @brief Macro to configure the PLL clock source.
<>	144:ef7eb2e8f9f7	1004	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	1005	* @param __PLLSOURCE__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	1006	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1007	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1008	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1009	*
<>	144:ef7eb2e8f9f7	1010	*/
<>	144:ef7eb2e8f9f7	1011	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	/** @brief Macro to configure the PLL multiplication factor.
<>	144:ef7eb2e8f9f7	1014	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	1015	* @param __PLLM__: specifies the division factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	1016	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<>	144:ef7eb2e8f9f7	1017	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	1018	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	1019	* of 2 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	1020	*
<>	144:ef7eb2e8f9f7	1021	*/
<>	144:ef7eb2e8f9f7	1022	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
<>	144:ef7eb2e8f9f7	1023	/**
<>	144:ef7eb2e8f9f7	1024	* @}
<>	144:ef7eb2e8f9f7	1025	*/
<>	144:ef7eb2e8f9f7	1026
<>	144:ef7eb2e8f9f7	1027	/** @defgroup RCC_Get_Clock_source Get Clock source
<>	144:ef7eb2e8f9f7	1028	* @{
<>	144:ef7eb2e8f9f7	1029	*/
<>	144:ef7eb2e8f9f7	1030	/**
<>	144:ef7eb2e8f9f7	1031	* @brief Macro to configure the system clock source.
<>	144:ef7eb2e8f9f7	1032	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
<>	144:ef7eb2e8f9f7	1033	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1034	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	1035	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	1036	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
<>	144:ef7eb2e8f9f7	1037	* - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
<>	144:ef7eb2e8f9f7	1038	*/
<>	144:ef7eb2e8f9f7	1039	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	/** @brief Macro to get the clock source used as system clock.
<>	144:ef7eb2e8f9f7	1042	* @retval The clock source used as system clock. The returned value can be one
<>	144:ef7eb2e8f9f7	1043	* of the following:
<>	144:ef7eb2e8f9f7	1044	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
<>	144:ef7eb2e8f9f7	1045	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
<>	144:ef7eb2e8f9f7	1046	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
<>	144:ef7eb2e8f9f7	1047	* - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
<>	144:ef7eb2e8f9f7	1048	*/
<>	144:ef7eb2e8f9f7	1049	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/** @brief Macro to get the oscillator used as PLL clock source.
<>	144:ef7eb2e8f9f7	1052	* @retval The oscillator used as PLL clock source. The returned value can be one
<>	144:ef7eb2e8f9f7	1053	* of the following:
<>	144:ef7eb2e8f9f7	1054	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	1055	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	1056	*/
<>	144:ef7eb2e8f9f7	1057	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
<>	144:ef7eb2e8f9f7	1058	/**
<>	144:ef7eb2e8f9f7	1059	* @}
<>	144:ef7eb2e8f9f7	1060	*/
<>	144:ef7eb2e8f9f7	1061
<>	144:ef7eb2e8f9f7	1062	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
<>	144:ef7eb2e8f9f7	1063	* @{
<>	144:ef7eb2e8f9f7	1064	*/
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	/** @brief Macro to configure the MCO1 clock.
<>	144:ef7eb2e8f9f7	1067	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	1068	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1069	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1070	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1071	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1072	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	1073	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	1074	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1075	* @arg RCC_MCODIV_1: no division applied to MCOx clock
<>	144:ef7eb2e8f9f7	1076	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1077	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1078	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1079	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1080	*/
<>	144:ef7eb2e8f9f7	1081	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1082	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
<>	144:ef7eb2e8f9f7	1083
<>	144:ef7eb2e8f9f7	1084	/** @brief Macro to configure the MCO2 clock.
<>	144:ef7eb2e8f9f7	1085	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	1086	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1087	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
<>	144:ef7eb2e8f9f7	1088	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
<>	144:ef7eb2e8f9f7	1089	* @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
<>	144:ef7eb2e8f9f7	1090	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1091	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1092	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	1093	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1094	* @arg RCC_MCODIV_1: no division applied to MCOx clock
<>	144:ef7eb2e8f9f7	1095	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1096	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1097	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1098	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1099	* @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
<>	144:ef7eb2e8f9f7	1100	* at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
<>	144:ef7eb2e8f9f7	1101	*/
<>	144:ef7eb2e8f9f7	1102	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1103	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 3U)));
<>	144:ef7eb2e8f9f7	1104	/**
<>	144:ef7eb2e8f9f7	1105	* @}
<>	144:ef7eb2e8f9f7	1106	*/
<>	144:ef7eb2e8f9f7	1107
<>	144:ef7eb2e8f9f7	1108	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<>	144:ef7eb2e8f9f7	1109	* @brief macros to manage the specified RCC Flags and interrupts.
<>	144:ef7eb2e8f9f7	1110	* @{
<>	144:ef7eb2e8f9f7	1111	*/
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
<>	144:ef7eb2e8f9f7	1114	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1115	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	1116	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1117	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1118	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1119	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1120	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1121	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1122	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1123	*/
<>	144:ef7eb2e8f9f7	1124	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
<>	144:ef7eb2e8f9f7	1127	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1128	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	1129	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1130	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1131	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1132	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1133	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1134	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1135	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1136	*/
<>	144:ef7eb2e8f9f7	1137	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
<>	144:ef7eb2e8f9f7	1140	* bits to clear the selected interrupt pending bits.
<>	144:ef7eb2e8f9f7	1141	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	1142	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1143	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1144	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1145	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1146	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1147	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1148	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1149	* @arg RCC_IT_CSS: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1150	*/
<>	144:ef7eb2e8f9f7	1151	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1152
<>	144:ef7eb2e8f9f7	1153	/** @brief Check the RCC's interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	1154	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
<>	144:ef7eb2e8f9f7	1155	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1156	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1157	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1158	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1159	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1160	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1161	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1162	* @arg RCC_IT_CSS: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1163	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1164	*/
<>	144:ef7eb2e8f9f7	1165	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
<>	144:ef7eb2e8f9f7	1168	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
<>	144:ef7eb2e8f9f7	1169	*/
<>	144:ef7eb2e8f9f7	1170	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	/** @brief Check RCC flag is set or not.
<>	144:ef7eb2e8f9f7	1173	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	1174	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1175	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1176	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1177	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
<>	144:ef7eb2e8f9f7	1178	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
<>	144:ef7eb2e8f9f7	1179	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1180	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1181	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
<>	144:ef7eb2e8f9f7	1182	* @arg RCC_FLAG_PINRST: Pin reset.
<>	144:ef7eb2e8f9f7	1183	* @arg RCC_FLAG_PORRST: POR/PDR reset.
<>	144:ef7eb2e8f9f7	1184	* @arg RCC_FLAG_SFTRST: Software reset.
<>	144:ef7eb2e8f9f7	1185	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
<>	144:ef7eb2e8f9f7	1186	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
<>	144:ef7eb2e8f9f7	1187	* @arg RCC_FLAG_LPWRRST: Low Power reset.
<>	144:ef7eb2e8f9f7	1188	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1189	*/
<>	144:ef7eb2e8f9f7	1190	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
<>	144:ef7eb2e8f9f7	1191	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193	/**
<>	144:ef7eb2e8f9f7	1194	* @}
<>	144:ef7eb2e8f9f7	1195	*/
<>	144:ef7eb2e8f9f7	1196
<>	144:ef7eb2e8f9f7	1197	/**
<>	144:ef7eb2e8f9f7	1198	* @}
<>	144:ef7eb2e8f9f7	1199	*/
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1202	/** @addtogroup RCC_Exported_Functions
<>	144:ef7eb2e8f9f7	1203	* @{
<>	144:ef7eb2e8f9f7	1204	*/
<>	144:ef7eb2e8f9f7	1205
<>	144:ef7eb2e8f9f7	1206	/** @addtogroup RCC_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1207	* @{
<>	144:ef7eb2e8f9f7	1208	*/
<>	144:ef7eb2e8f9f7	1209	/* Initialization and de-initialization functions ******************************/
<>	144:ef7eb2e8f9f7	1210	void HAL_RCC_DeInit(void);
<>	144:ef7eb2e8f9f7	1211	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1212	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<>	144:ef7eb2e8f9f7	1213	/**
<>	144:ef7eb2e8f9f7	1214	* @}
<>	144:ef7eb2e8f9f7	1215	*/
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/** @addtogroup RCC_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	1218	* @{
<>	144:ef7eb2e8f9f7	1219	*/
<>	144:ef7eb2e8f9f7	1220	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1221	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<>	144:ef7eb2e8f9f7	1222	void HAL_RCC_EnableCSS(void);
<>	144:ef7eb2e8f9f7	1223	void HAL_RCC_DisableCSS(void);
<>	144:ef7eb2e8f9f7	1224	uint32_t HAL_RCC_GetSysClockFreq(void);
<>	144:ef7eb2e8f9f7	1225	uint32_t HAL_RCC_GetHCLKFreq(void);
<>	144:ef7eb2e8f9f7	1226	uint32_t HAL_RCC_GetPCLK1Freq(void);
<>	144:ef7eb2e8f9f7	1227	uint32_t HAL_RCC_GetPCLK2Freq(void);
<>	144:ef7eb2e8f9f7	1228	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1229	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	/* CSS NMI IRQ handler */
<>	144:ef7eb2e8f9f7	1232	void HAL_RCC_NMI_IRQHandler(void);
<>	144:ef7eb2e8f9f7	1233
<>	144:ef7eb2e8f9f7	1234	/* User Callbacks in non blocking mode (IT mode) */
<>	144:ef7eb2e8f9f7	1235	void HAL_RCC_CSSCallback(void);
<>	144:ef7eb2e8f9f7	1236
<>	144:ef7eb2e8f9f7	1237	/**
<>	144:ef7eb2e8f9f7	1238	* @}
<>	144:ef7eb2e8f9f7	1239	*/
<>	144:ef7eb2e8f9f7	1240
<>	144:ef7eb2e8f9f7	1241	/**
<>	144:ef7eb2e8f9f7	1242	* @}
<>	144:ef7eb2e8f9f7	1243	*/
<>	144:ef7eb2e8f9f7	1244
<>	144:ef7eb2e8f9f7	1245	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1246	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1247	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1248	/** @defgroup RCC_Private_Constants RCC Private Constants
<>	144:ef7eb2e8f9f7	1249	* @{
<>	144:ef7eb2e8f9f7	1250	*/
<>	144:ef7eb2e8f9f7	1251
<>	144:ef7eb2e8f9f7	1252	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
<>	144:ef7eb2e8f9f7	1253	* @brief RCC registers bit address in the alias region
<>	144:ef7eb2e8f9f7	1254	* @{
<>	144:ef7eb2e8f9f7	1255	*/
<>	144:ef7eb2e8f9f7	1256	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
<>	144:ef7eb2e8f9f7	1257	/* --- CR Register ---*/
<>	144:ef7eb2e8f9f7	1258	/* Alias word address of HSION bit */
<>	144:ef7eb2e8f9f7	1259	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
<>	144:ef7eb2e8f9f7	1260	#define RCC_HSION_BIT_NUMBER 0x00U
<>	144:ef7eb2e8f9f7	1261	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1262	/* Alias word address of CSSON bit */
<>	144:ef7eb2e8f9f7	1263	#define RCC_CSSON_BIT_NUMBER 0x13U
<>	144:ef7eb2e8f9f7	1264	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1265	/* Alias word address of PLLON bit */
<>	144:ef7eb2e8f9f7	1266	#define RCC_PLLON_BIT_NUMBER 0x18U
<>	144:ef7eb2e8f9f7	1267	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1268
<>	144:ef7eb2e8f9f7	1269	/* --- BDCR Register ---*/
<>	144:ef7eb2e8f9f7	1270	/* Alias word address of RTCEN bit */
<>	144:ef7eb2e8f9f7	1271	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
<>	144:ef7eb2e8f9f7	1272	#define RCC_RTCEN_BIT_NUMBER 0x0FU
<>	144:ef7eb2e8f9f7	1273	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1274	/* Alias word address of BDRST bit */
<>	144:ef7eb2e8f9f7	1275	#define RCC_BDRST_BIT_NUMBER 0x10U
<>	144:ef7eb2e8f9f7	1276	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	/* --- CSR Register ---*/
<>	144:ef7eb2e8f9f7	1279	/* Alias word address of LSION bit */
<>	144:ef7eb2e8f9f7	1280	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
<>	144:ef7eb2e8f9f7	1281	#define RCC_LSION_BIT_NUMBER 0x00U
<>	144:ef7eb2e8f9f7	1282	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/* CR register byte 3 (Bits[23:16]) base address */
<>	144:ef7eb2e8f9f7	1285	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	/* CIR register byte 2 (Bits[15:8]) base address */
<>	144:ef7eb2e8f9f7	1288	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
<>	144:ef7eb2e8f9f7	1289
<>	144:ef7eb2e8f9f7	1290	/* CIR register byte 3 (Bits[23:16]) base address */
<>	144:ef7eb2e8f9f7	1291	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
<>	144:ef7eb2e8f9f7	1292
<>	144:ef7eb2e8f9f7	1293	/* BDCR register base address */
<>	144:ef7eb2e8f9f7	1294	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
<>	144:ef7eb2e8f9f7	1297	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	1298
<>	144:ef7eb2e8f9f7	1299	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	1300	#define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
<>	144:ef7eb2e8f9f7	1301	#define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
<>	144:ef7eb2e8f9f7	1302
<>	144:ef7eb2e8f9f7	1303	/**
<>	144:ef7eb2e8f9f7	1304	* @}
<>	144:ef7eb2e8f9f7	1305	*/
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	/**
<>	144:ef7eb2e8f9f7	1308	* @}
<>	144:ef7eb2e8f9f7	1309	*/
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1312	/** @defgroup RCC_Private_Macros RCC Private Macros
<>	144:ef7eb2e8f9f7	1313	* @{
<>	144:ef7eb2e8f9f7	1314	*/
<>	144:ef7eb2e8f9f7	1315
<>	144:ef7eb2e8f9f7	1316	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
<>	144:ef7eb2e8f9f7	1317	* @{
<>	144:ef7eb2e8f9f7	1318	*/
<>	144:ef7eb2e8f9f7	1319	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1322	((HSE) == RCC_HSE_BYPASS))
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1325	((LSE) == RCC_LSE_BYPASS))
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
<>	144:ef7eb2e8f9f7	1330
<>	144:ef7eb2e8f9f7	1331	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1334	((SOURCE) == RCC_PLLSOURCE_HSE))
<>	144:ef7eb2e8f9f7	1335
<>	144:ef7eb2e8f9f7	1336	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1337	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	1338	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
<>	144:ef7eb2e8f9f7	1339	((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
<>	144:ef7eb2e8f9f7	1340
<>	144:ef7eb2e8f9f7	1341	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	1342	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	1343	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1344	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) \|\| \
<>	144:ef7eb2e8f9f7	1345	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1346	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) \|\| \
<>	144:ef7eb2e8f9f7	1347	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) \|\| \
<>	144:ef7eb2e8f9f7	1348	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) \|\| \
<>	144:ef7eb2e8f9f7	1349	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1350	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) \|\| \
<>	144:ef7eb2e8f9f7	1351	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) \|\| \
<>	144:ef7eb2e8f9f7	1352	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) \|\| \
<>	144:ef7eb2e8f9f7	1353	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) \|\| \
<>	144:ef7eb2e8f9f7	1354	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) \|\| \
<>	144:ef7eb2e8f9f7	1355	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) \|\| \
<>	144:ef7eb2e8f9f7	1356	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) \|\| \
<>	144:ef7eb2e8f9f7	1357	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) \|\| \
<>	144:ef7eb2e8f9f7	1358	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) \|\| \
<>	144:ef7eb2e8f9f7	1359	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) \|\| \
<>	144:ef7eb2e8f9f7	1360	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) \|\| \
<>	144:ef7eb2e8f9f7	1361	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) \|\| \
<>	144:ef7eb2e8f9f7	1362	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) \|\| \
<>	144:ef7eb2e8f9f7	1363	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) \|\| \
<>	144:ef7eb2e8f9f7	1364	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) \|\| \
<>	144:ef7eb2e8f9f7	1365	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) \|\| \
<>	144:ef7eb2e8f9f7	1366	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) \|\| \
<>	144:ef7eb2e8f9f7	1367	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) \|\| \
<>	144:ef7eb2e8f9f7	1368	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) \|\| \
<>	144:ef7eb2e8f9f7	1369	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) \|\| \
<>	144:ef7eb2e8f9f7	1370	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) \|\| \
<>	144:ef7eb2e8f9f7	1371	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) \|\| \
<>	144:ef7eb2e8f9f7	1372	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
<>	144:ef7eb2e8f9f7	1375
<>	144:ef7eb2e8f9f7	1376	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) \|\| ((VALUE) == 4U) \|\| ((VALUE) == 6U) \|\| ((VALUE) == 8U))
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378	#define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1381	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1382	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
<>	144:ef7eb2e8f9f7	1383	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
<>	144:ef7eb2e8f9f7	1384	((HCLK) == RCC_SYSCLK_DIV512))
<>	144:ef7eb2e8f9f7	1385
<>	144:ef7eb2e8f9f7	1386	#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1389	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1390	((PCLK) == RCC_HCLK_DIV16))
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	1395	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	1396
<>	144:ef7eb2e8f9f7	1397	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
<>	144:ef7eb2e8f9f7	1398	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
<>	144:ef7eb2e8f9f7	1399	((DIV) == RCC_MCODIV_5))
<>	144:ef7eb2e8f9f7	1400	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
<>	144:ef7eb2e8f9f7	1401
<>	144:ef7eb2e8f9f7	1402	/**
<>	144:ef7eb2e8f9f7	1403	* @}
<>	144:ef7eb2e8f9f7	1404	*/
<>	144:ef7eb2e8f9f7	1405
<>	144:ef7eb2e8f9f7	1406	/**
<>	144:ef7eb2e8f9f7	1407	* @}
<>	144:ef7eb2e8f9f7	1408	*/
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410	/**
<>	144:ef7eb2e8f9f7	1411	* @}
<>	144:ef7eb2e8f9f7	1412	*/
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	/**
<>	144:ef7eb2e8f9f7	1415	* @}
<>	144:ef7eb2e8f9f7	1416	*/
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1419	}
<>	144:ef7eb2e8f9f7	1420	#endif
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	#endif /* __STM32F4xx_HAL_RCC_H */
<>	144:ef7eb2e8f9f7	1423
<>	144:ef7eb2e8f9f7	1424	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/