mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
161:2cc1468da177
Child:
182:a56a73fd2a6f
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**
<> 161:2cc1468da177 2 ******************************************************************************
<> 161:2cc1468da177 3 * @file stm32f7xx_ll_utils.c
<> 161:2cc1468da177 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 161:2cc1468da177 7 * @brief UTILS LL module driver.
<> 161:2cc1468da177 8 ******************************************************************************
<> 161:2cc1468da177 9 * @attention
<> 161:2cc1468da177 10 *
<> 161:2cc1468da177 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 161:2cc1468da177 12 *
<> 161:2cc1468da177 13 * Redistribution and use in source and binary forms, with or without modification,
<> 161:2cc1468da177 14 * are permitted provided that the following conditions are met:
<> 161:2cc1468da177 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 161:2cc1468da177 16 * this list of conditions and the following disclaimer.
<> 161:2cc1468da177 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 161:2cc1468da177 18 * this list of conditions and the following disclaimer in the documentation
<> 161:2cc1468da177 19 * and/or other materials provided with the distribution.
<> 161:2cc1468da177 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 161:2cc1468da177 21 * may be used to endorse or promote products derived from this software
<> 161:2cc1468da177 22 * without specific prior written permission.
<> 161:2cc1468da177 23 *
<> 161:2cc1468da177 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 161:2cc1468da177 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 161:2cc1468da177 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 161:2cc1468da177 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 161:2cc1468da177 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 161:2cc1468da177 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 161:2cc1468da177 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 161:2cc1468da177 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 34 *
<> 161:2cc1468da177 35 ******************************************************************************
<> 161:2cc1468da177 36 */
<> 161:2cc1468da177 37 /* Includes ------------------------------------------------------------------*/
<> 161:2cc1468da177 38 #include "stm32f7xx_ll_utils.h"
<> 161:2cc1468da177 39 #include "stm32f7xx_ll_rcc.h"
<> 161:2cc1468da177 40 #include "stm32f7xx_ll_system.h"
<> 161:2cc1468da177 41 #include "stm32f7xx_ll_pwr.h"
<> 161:2cc1468da177 42
<> 161:2cc1468da177 43 /** @addtogroup STM32F7xx_LL_Driver
<> 161:2cc1468da177 44 * @{
<> 161:2cc1468da177 45 */
<> 161:2cc1468da177 46
<> 161:2cc1468da177 47 /** @addtogroup UTILS_LL
<> 161:2cc1468da177 48 * @{
<> 161:2cc1468da177 49 */
<> 161:2cc1468da177 50
<> 161:2cc1468da177 51 /* Private types -------------------------------------------------------------*/
<> 161:2cc1468da177 52 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 53 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 54 /** @addtogroup UTILS_LL_Private_Constants
<> 161:2cc1468da177 55 * @{
<> 161:2cc1468da177 56 */
<> 161:2cc1468da177 57 #define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
<> 161:2cc1468da177 58 #define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
<> 161:2cc1468da177 59 #define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
<> 161:2cc1468da177 60
<> 161:2cc1468da177 61 /* Defines used for PLL range */
<> 161:2cc1468da177 62 #define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
<> 161:2cc1468da177 63 #define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
<> 161:2cc1468da177 64 #define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
<> 161:2cc1468da177 65 #define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
<> 161:2cc1468da177 66
<> 161:2cc1468da177 67 /* Defines used for HSE range */
<> 161:2cc1468da177 68 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
<> 161:2cc1468da177 69 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
<> 161:2cc1468da177 70
<> 161:2cc1468da177 71 /* Defines used for FLASH latency according to HCLK Frequency */
<> 161:2cc1468da177 72 #define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
<> 161:2cc1468da177 73 #define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
<> 161:2cc1468da177 74 #define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
<> 161:2cc1468da177 75 #define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
<> 161:2cc1468da177 76 #define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
<> 161:2cc1468da177 77 #define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */
<> 161:2cc1468da177 78 #define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */
<> 161:2cc1468da177 79 #define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
<> 161:2cc1468da177 80 #define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
<> 161:2cc1468da177 81 #define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
<> 161:2cc1468da177 82 #define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
<> 161:2cc1468da177 83 #define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
<> 161:2cc1468da177 84 #define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
<> 161:2cc1468da177 85 #define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
<> 161:2cc1468da177 86 #define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
<> 161:2cc1468da177 87 #define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
<> 161:2cc1468da177 88 /**
<> 161:2cc1468da177 89 * @}
<> 161:2cc1468da177 90 */
<> 161:2cc1468da177 91
<> 161:2cc1468da177 92 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 93 /** @addtogroup UTILS_LL_Private_Macros
<> 161:2cc1468da177 94 * @{
<> 161:2cc1468da177 95 */
<> 161:2cc1468da177 96 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
<> 161:2cc1468da177 97 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
<> 161:2cc1468da177 98 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
<> 161:2cc1468da177 99 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
<> 161:2cc1468da177 100 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
<> 161:2cc1468da177 101 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
<> 161:2cc1468da177 102 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
<> 161:2cc1468da177 103 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
<> 161:2cc1468da177 104 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
<> 161:2cc1468da177 105
<> 161:2cc1468da177 106 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
<> 161:2cc1468da177 107 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
<> 161:2cc1468da177 108 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
<> 161:2cc1468da177 109 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
<> 161:2cc1468da177 110 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
<> 161:2cc1468da177 111
<> 161:2cc1468da177 112 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
<> 161:2cc1468da177 113 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
<> 161:2cc1468da177 114 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
<> 161:2cc1468da177 115 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
<> 161:2cc1468da177 116 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
<> 161:2cc1468da177 117
<> 161:2cc1468da177 118 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
<> 161:2cc1468da177 119 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
<> 161:2cc1468da177 120 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
<> 161:2cc1468da177 121 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
<> 161:2cc1468da177 122 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
<> 161:2cc1468da177 123 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
<> 161:2cc1468da177 124 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
<> 161:2cc1468da177 125 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
<> 161:2cc1468da177 126 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
<> 161:2cc1468da177 127 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
<> 161:2cc1468da177 128 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
<> 161:2cc1468da177 129 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
<> 161:2cc1468da177 130 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
<> 161:2cc1468da177 131 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
<> 161:2cc1468da177 132 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
<> 161:2cc1468da177 133 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
<> 161:2cc1468da177 134 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
<> 161:2cc1468da177 135 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
<> 161:2cc1468da177 136 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
<> 161:2cc1468da177 137 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
<> 161:2cc1468da177 138 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
<> 161:2cc1468da177 139 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
<> 161:2cc1468da177 140 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
<> 161:2cc1468da177 141 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
<> 161:2cc1468da177 142 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
<> 161:2cc1468da177 143 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
<> 161:2cc1468da177 144 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
<> 161:2cc1468da177 145 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
<> 161:2cc1468da177 146 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
<> 161:2cc1468da177 147 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
<> 161:2cc1468da177 148 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
<> 161:2cc1468da177 149 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
<> 161:2cc1468da177 150 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
<> 161:2cc1468da177 151 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
<> 161:2cc1468da177 152 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
<> 161:2cc1468da177 153 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
<> 161:2cc1468da177 154 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
<> 161:2cc1468da177 155 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
<> 161:2cc1468da177 156 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
<> 161:2cc1468da177 157 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
<> 161:2cc1468da177 158 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
<> 161:2cc1468da177 159 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
<> 161:2cc1468da177 160 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
<> 161:2cc1468da177 161 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
<> 161:2cc1468da177 162 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
<> 161:2cc1468da177 163 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
<> 161:2cc1468da177 164 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
<> 161:2cc1468da177 165 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
<> 161:2cc1468da177 166 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
<> 161:2cc1468da177 167 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
<> 161:2cc1468da177 168 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
<> 161:2cc1468da177 169 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
<> 161:2cc1468da177 170 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
<> 161:2cc1468da177 171 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
<> 161:2cc1468da177 172 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
<> 161:2cc1468da177 173 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
<> 161:2cc1468da177 174 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
<> 161:2cc1468da177 175 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
<> 161:2cc1468da177 176 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
<> 161:2cc1468da177 177 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
<> 161:2cc1468da177 178 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
<> 161:2cc1468da177 179 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
<> 161:2cc1468da177 180
<> 161:2cc1468da177 181 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
<> 161:2cc1468da177 182
<> 161:2cc1468da177 183 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
<> 161:2cc1468da177 184 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
<> 161:2cc1468da177 185 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
<> 161:2cc1468da177 186 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
<> 161:2cc1468da177 187
<> 161:2cc1468da177 188 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
<> 161:2cc1468da177 189
<> 161:2cc1468da177 190 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
<> 161:2cc1468da177 191
<> 161:2cc1468da177 192 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
<> 161:2cc1468da177 193 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
<> 161:2cc1468da177 194 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
<> 161:2cc1468da177 195
<> 161:2cc1468da177 196 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
<> 161:2cc1468da177 197 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
<> 161:2cc1468da177 198
<> 161:2cc1468da177 199 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
<> 161:2cc1468da177 200 /**
<> 161:2cc1468da177 201 * @}
<> 161:2cc1468da177 202 */
<> 161:2cc1468da177 203 /* Private function prototypes -----------------------------------------------*/
<> 161:2cc1468da177 204 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
<> 161:2cc1468da177 205 * @{
<> 161:2cc1468da177 206 */
<> 161:2cc1468da177 207 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
<> 161:2cc1468da177 208 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
<> 161:2cc1468da177 209 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
<> 161:2cc1468da177 210 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
<> 161:2cc1468da177 211 static ErrorStatus UTILS_PLL_IsBusy(void);
<> 161:2cc1468da177 212 /**
<> 161:2cc1468da177 213 * @}
<> 161:2cc1468da177 214 */
<> 161:2cc1468da177 215
<> 161:2cc1468da177 216 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 217 /** @addtogroup UTILS_LL_Exported_Functions
<> 161:2cc1468da177 218 * @{
<> 161:2cc1468da177 219 */
<> 161:2cc1468da177 220
<> 161:2cc1468da177 221 /** @addtogroup UTILS_LL_EF_DELAY
<> 161:2cc1468da177 222 * @{
<> 161:2cc1468da177 223 */
<> 161:2cc1468da177 224
<> 161:2cc1468da177 225 /**
<> 161:2cc1468da177 226 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
<> 161:2cc1468da177 227 * @note When a RTOS is used, it is recommended to avoid changing the Systick
<> 161:2cc1468da177 228 * configuration by calling this function, for a delay use rather osDelay RTOS service.
<> 161:2cc1468da177 229 * @param HCLKFrequency HCLK frequency in Hz
<> 161:2cc1468da177 230 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
<> 161:2cc1468da177 231 * @retval None
<> 161:2cc1468da177 232 */
<> 161:2cc1468da177 233 void LL_Init1msTick(uint32_t HCLKFrequency)
<> 161:2cc1468da177 234 {
<> 161:2cc1468da177 235 /* Use frequency provided in argument */
<> 161:2cc1468da177 236 LL_InitTick(HCLKFrequency, 1000U);
<> 161:2cc1468da177 237 }
<> 161:2cc1468da177 238
<> 161:2cc1468da177 239 /**
<> 161:2cc1468da177 240 * @brief This function provides accurate delay (in milliseconds) based
<> 161:2cc1468da177 241 * on SysTick counter flag
<> 161:2cc1468da177 242 * @note When a RTOS is used, it is recommended to avoid using blocking delay
<> 161:2cc1468da177 243 * and use rather osDelay service.
<> 161:2cc1468da177 244 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
<> 161:2cc1468da177 245 * will configure Systick to 1ms
<> 161:2cc1468da177 246 * @param Delay specifies the delay time length, in milliseconds.
<> 161:2cc1468da177 247 * @retval None
<> 161:2cc1468da177 248 */
<> 161:2cc1468da177 249 void LL_mDelay(uint32_t Delay)
<> 161:2cc1468da177 250 {
<> 161:2cc1468da177 251 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
<> 161:2cc1468da177 252 /* Add this code to indicate that local variable is not used */
<> 161:2cc1468da177 253 ((void)tmp);
<> 161:2cc1468da177 254
<> 161:2cc1468da177 255 /* Add a period to guaranty minimum wait */
<> 161:2cc1468da177 256 if(Delay < LL_MAX_DELAY)
<> 161:2cc1468da177 257 {
<> 161:2cc1468da177 258 Delay++;
<> 161:2cc1468da177 259 }
<> 161:2cc1468da177 260
<> 161:2cc1468da177 261 while (Delay)
<> 161:2cc1468da177 262 {
<> 161:2cc1468da177 263 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
<> 161:2cc1468da177 264 {
<> 161:2cc1468da177 265 Delay--;
<> 161:2cc1468da177 266 }
<> 161:2cc1468da177 267 }
<> 161:2cc1468da177 268 }
<> 161:2cc1468da177 269
<> 161:2cc1468da177 270 /**
<> 161:2cc1468da177 271 * @}
<> 161:2cc1468da177 272 */
<> 161:2cc1468da177 273
<> 161:2cc1468da177 274 /** @addtogroup UTILS_EF_SYSTEM
<> 161:2cc1468da177 275 * @brief System Configuration functions
<> 161:2cc1468da177 276 *
<> 161:2cc1468da177 277 @verbatim
<> 161:2cc1468da177 278 ===============================================================================
<> 161:2cc1468da177 279 ##### System Configuration functions #####
<> 161:2cc1468da177 280 ===============================================================================
<> 161:2cc1468da177 281 [..]
<> 161:2cc1468da177 282 System, AHB and APB buses clocks configuration
<> 161:2cc1468da177 283
<> 161:2cc1468da177 284 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
<> 161:2cc1468da177 285 @endverbatim
<> 161:2cc1468da177 286 @internal
<> 161:2cc1468da177 287 Depending on the device voltage range, the maximum frequency should be
<> 161:2cc1468da177 288 adapted accordingly:
<> 161:2cc1468da177 289 (++) +------------------------------------------------------------------------------------------------+
<> 161:2cc1468da177 290 (++) | Wait states | HCLK clock frequency (MHz) |
<> 161:2cc1468da177 291 (++) | |-------------------------------------------------------------------------------|
<> 161:2cc1468da177 292 (++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
<> 161:2cc1468da177 293 (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V |
<> 161:2cc1468da177 294 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 295 (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 |
<> 161:2cc1468da177 296 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 297 (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 |
<> 161:2cc1468da177 298 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 299 (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 |
<> 161:2cc1468da177 300 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 301 (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 |
<> 161:2cc1468da177 302 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 303 (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 |
<> 161:2cc1468da177 304 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 305 (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 |
<> 161:2cc1468da177 306 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 307 (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 |
<> 161:2cc1468da177 308 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 309 (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 |
<> 161:2cc1468da177 310 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 311 (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 |
<> 161:2cc1468da177 312 (++) |----------------|-------------------|-------------------|-------------------|-------------------|
<> 161:2cc1468da177 313 (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- |
<> 161:2cc1468da177 314 (++) +------------------------------------------------------------------------------------------------+
<> 161:2cc1468da177 315
<> 161:2cc1468da177 316 @endinternal
<> 161:2cc1468da177 317 * @{
<> 161:2cc1468da177 318 */
<> 161:2cc1468da177 319
<> 161:2cc1468da177 320 /**
<> 161:2cc1468da177 321 * @brief This function sets directly SystemCoreClock CMSIS variable.
<> 161:2cc1468da177 322 * @note Variable can be calculated also through SystemCoreClockUpdate function.
<> 161:2cc1468da177 323 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
<> 161:2cc1468da177 324 * @retval None
<> 161:2cc1468da177 325 */
<> 161:2cc1468da177 326 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
<> 161:2cc1468da177 327 {
<> 161:2cc1468da177 328 /* HCLK clock frequency */
<> 161:2cc1468da177 329 SystemCoreClock = HCLKFrequency;
<> 161:2cc1468da177 330 }
<> 161:2cc1468da177 331
<> 161:2cc1468da177 332 /**
<> 161:2cc1468da177 333 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
<> 161:2cc1468da177 334 * @note The application need to ensure that PLL is disabled.
<> 161:2cc1468da177 335 * @note Function is based on the following formula:
<> 161:2cc1468da177 336 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
<> 161:2cc1468da177 337 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM)
<> 161:2cc1468da177 338 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
<> 161:2cc1468da177 339 * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
<> 161:2cc1468da177 340 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 161:2cc1468da177 341 * the configuration information for the PLL.
<> 161:2cc1468da177 342 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 161:2cc1468da177 343 * the configuration information for the BUS prescalers.
<> 161:2cc1468da177 344 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 345 * - SUCCESS: Max frequency configuration done
<> 161:2cc1468da177 346 * - ERROR: Max frequency configuration not done
<> 161:2cc1468da177 347 */
<> 161:2cc1468da177 348 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
<> 161:2cc1468da177 349 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 161:2cc1468da177 350 {
<> 161:2cc1468da177 351 ErrorStatus status = SUCCESS;
<> 161:2cc1468da177 352 uint32_t pllfreq = 0U;
<> 161:2cc1468da177 353
<> 161:2cc1468da177 354 /* Check if one of the PLL is enabled */
<> 161:2cc1468da177 355 if(UTILS_PLL_IsBusy() == SUCCESS)
<> 161:2cc1468da177 356 {
<> 161:2cc1468da177 357 /* Calculate the new PLL output frequency */
<> 161:2cc1468da177 358 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
<> 161:2cc1468da177 359
<> 161:2cc1468da177 360 /* Enable HSI if not enabled */
<> 161:2cc1468da177 361 if(LL_RCC_HSI_IsReady() != 1U)
<> 161:2cc1468da177 362 {
<> 161:2cc1468da177 363 LL_RCC_HSI_Enable();
<> 161:2cc1468da177 364 while (LL_RCC_HSI_IsReady() != 1U)
<> 161:2cc1468da177 365 {
<> 161:2cc1468da177 366 /* Wait for HSI ready */
<> 161:2cc1468da177 367 }
<> 161:2cc1468da177 368 }
<> 161:2cc1468da177 369
<> 161:2cc1468da177 370 /* Configure PLL */
<> 161:2cc1468da177 371 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
<> 161:2cc1468da177 372 UTILS_PLLInitStruct->PLLP);
<> 161:2cc1468da177 373
<> 161:2cc1468da177 374 /* Enable PLL and switch system clock to PLL */
<> 161:2cc1468da177 375 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 161:2cc1468da177 376 }
<> 161:2cc1468da177 377 else
<> 161:2cc1468da177 378 {
<> 161:2cc1468da177 379 /* Current PLL configuration cannot be modified */
<> 161:2cc1468da177 380 status = ERROR;
<> 161:2cc1468da177 381 }
<> 161:2cc1468da177 382
<> 161:2cc1468da177 383 return status;
<> 161:2cc1468da177 384 }
<> 161:2cc1468da177 385
<> 161:2cc1468da177 386 /**
<> 161:2cc1468da177 387 * @brief This function configures system clock with HSE as clock source of the PLL
<> 161:2cc1468da177 388 * @note The application need to ensure that PLL is disabled.
<> 161:2cc1468da177 389 * @note Function is based on the following formula:
<> 161:2cc1468da177 390 * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
<> 161:2cc1468da177 391 * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
<> 161:2cc1468da177 392 * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
<> 161:2cc1468da177 393 * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
<> 161:2cc1468da177 394 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
<> 161:2cc1468da177 395 * @param HSEBypass This parameter can be one of the following values:
<> 161:2cc1468da177 396 * @arg @ref LL_UTILS_HSEBYPASS_ON
<> 161:2cc1468da177 397 * @arg @ref LL_UTILS_HSEBYPASS_OFF
<> 161:2cc1468da177 398 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 161:2cc1468da177 399 * the configuration information for the PLL.
<> 161:2cc1468da177 400 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 161:2cc1468da177 401 * the configuration information for the BUS prescalers.
<> 161:2cc1468da177 402 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 403 * - SUCCESS: Max frequency configuration done
<> 161:2cc1468da177 404 * - ERROR: Max frequency configuration not done
<> 161:2cc1468da177 405 */
<> 161:2cc1468da177 406 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
<> 161:2cc1468da177 407 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 161:2cc1468da177 408 {
<> 161:2cc1468da177 409 ErrorStatus status = SUCCESS;
<> 161:2cc1468da177 410 uint32_t pllfreq = 0U;
<> 161:2cc1468da177 411
<> 161:2cc1468da177 412 /* Check the parameters */
<> 161:2cc1468da177 413 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
<> 161:2cc1468da177 414 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
<> 161:2cc1468da177 415
<> 161:2cc1468da177 416 /* Check if one of the PLL is enabled */
<> 161:2cc1468da177 417 if(UTILS_PLL_IsBusy() == SUCCESS)
<> 161:2cc1468da177 418 {
<> 161:2cc1468da177 419 /* Calculate the new PLL output frequency */
<> 161:2cc1468da177 420 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
<> 161:2cc1468da177 421
<> 161:2cc1468da177 422 /* Enable HSE if not enabled */
<> 161:2cc1468da177 423 if(LL_RCC_HSE_IsReady() != 1U)
<> 161:2cc1468da177 424 {
<> 161:2cc1468da177 425 /* Check if need to enable HSE bypass feature or not */
<> 161:2cc1468da177 426 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
<> 161:2cc1468da177 427 {
<> 161:2cc1468da177 428 LL_RCC_HSE_EnableBypass();
<> 161:2cc1468da177 429 }
<> 161:2cc1468da177 430 else
<> 161:2cc1468da177 431 {
<> 161:2cc1468da177 432 LL_RCC_HSE_DisableBypass();
<> 161:2cc1468da177 433 }
<> 161:2cc1468da177 434
<> 161:2cc1468da177 435 /* Enable HSE */
<> 161:2cc1468da177 436 LL_RCC_HSE_Enable();
<> 161:2cc1468da177 437 while (LL_RCC_HSE_IsReady() != 1U)
<> 161:2cc1468da177 438 {
<> 161:2cc1468da177 439 /* Wait for HSE ready */
<> 161:2cc1468da177 440 }
<> 161:2cc1468da177 441 }
<> 161:2cc1468da177 442
<> 161:2cc1468da177 443 /* Configure PLL */
<> 161:2cc1468da177 444 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
<> 161:2cc1468da177 445 UTILS_PLLInitStruct->PLLP);
<> 161:2cc1468da177 446
<> 161:2cc1468da177 447 /* Enable PLL and switch system clock to PLL */
<> 161:2cc1468da177 448 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
<> 161:2cc1468da177 449 }
<> 161:2cc1468da177 450 else
<> 161:2cc1468da177 451 {
<> 161:2cc1468da177 452 /* Current PLL configuration cannot be modified */
<> 161:2cc1468da177 453 status = ERROR;
<> 161:2cc1468da177 454 }
<> 161:2cc1468da177 455
<> 161:2cc1468da177 456 return status;
<> 161:2cc1468da177 457 }
<> 161:2cc1468da177 458
<> 161:2cc1468da177 459 /**
<> 161:2cc1468da177 460 * @}
<> 161:2cc1468da177 461 */
<> 161:2cc1468da177 462
<> 161:2cc1468da177 463 /**
<> 161:2cc1468da177 464 * @}
<> 161:2cc1468da177 465 */
<> 161:2cc1468da177 466
<> 161:2cc1468da177 467 /** @addtogroup UTILS_LL_Private_Functions
<> 161:2cc1468da177 468 * @{
<> 161:2cc1468da177 469 */
<> 161:2cc1468da177 470 /**
<> 161:2cc1468da177 471 * @brief Update number of Flash wait states in line with new frequency and current
<> 161:2cc1468da177 472 voltage range.
<> 161:2cc1468da177 473 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
<> 161:2cc1468da177 474 * @param HCLK_Frequency HCLK frequency
<> 161:2cc1468da177 475 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 476 * - SUCCESS: Latency has been modified
<> 161:2cc1468da177 477 * - ERROR: Latency cannot be modified
<> 161:2cc1468da177 478 */
<> 161:2cc1468da177 479 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
<> 161:2cc1468da177 480 {
<> 161:2cc1468da177 481 ErrorStatus status = SUCCESS;
<> 161:2cc1468da177 482
<> 161:2cc1468da177 483 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
<> 161:2cc1468da177 484
<> 161:2cc1468da177 485 /* Frequency cannot be equal to 0 */
<> 161:2cc1468da177 486 if(HCLK_Frequency == 0U)
<> 161:2cc1468da177 487 {
<> 161:2cc1468da177 488 status = ERROR;
<> 161:2cc1468da177 489 }
<> 161:2cc1468da177 490 else
<> 161:2cc1468da177 491 {
<> 161:2cc1468da177 492 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
<> 161:2cc1468da177 493 {
<> 161:2cc1468da177 494 if(LL_PWR_IsEnabledOverDriveMode() != 0U)
<> 161:2cc1468da177 495 {
<> 161:2cc1468da177 496 if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
<> 161:2cc1468da177 497 {
<> 161:2cc1468da177 498 /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
<> 161:2cc1468da177 499 latency = LL_FLASH_LATENCY_7;
<> 161:2cc1468da177 500 }
<> 161:2cc1468da177 501 else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
<> 161:2cc1468da177 502 {
<> 161:2cc1468da177 503 /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
<> 161:2cc1468da177 504 latency = LL_FLASH_LATENCY_6;
<> 161:2cc1468da177 505 }
<> 161:2cc1468da177 506 }
<> 161:2cc1468da177 507 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
<> 161:2cc1468da177 508 {
<> 161:2cc1468da177 509 /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
<> 161:2cc1468da177 510 latency = LL_FLASH_LATENCY_5;
<> 161:2cc1468da177 511 }
<> 161:2cc1468da177 512 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
<> 161:2cc1468da177 513 {
<> 161:2cc1468da177 514 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
<> 161:2cc1468da177 515 latency = LL_FLASH_LATENCY_4;
<> 161:2cc1468da177 516 }
<> 161:2cc1468da177 517 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
<> 161:2cc1468da177 518 {
<> 161:2cc1468da177 519 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
<> 161:2cc1468da177 520 latency = LL_FLASH_LATENCY_3;
<> 161:2cc1468da177 521 }
<> 161:2cc1468da177 522 else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
<> 161:2cc1468da177 523 {
<> 161:2cc1468da177 524 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
<> 161:2cc1468da177 525 latency = LL_FLASH_LATENCY_2;
<> 161:2cc1468da177 526 }
<> 161:2cc1468da177 527 else
<> 161:2cc1468da177 528 {
<> 161:2cc1468da177 529 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
<> 161:2cc1468da177 530 {
<> 161:2cc1468da177 531 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
<> 161:2cc1468da177 532 latency = LL_FLASH_LATENCY_1;
<> 161:2cc1468da177 533 }
<> 161:2cc1468da177 534 /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
<> 161:2cc1468da177 535 }
<> 161:2cc1468da177 536 }
<> 161:2cc1468da177 537 else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
<> 161:2cc1468da177 538 {
<> 161:2cc1468da177 539 if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
<> 161:2cc1468da177 540 {
<> 161:2cc1468da177 541 /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */
<> 161:2cc1468da177 542 latency = LL_FLASH_LATENCY_5;
<> 161:2cc1468da177 543 }
<> 161:2cc1468da177 544 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
<> 161:2cc1468da177 545 {
<> 161:2cc1468da177 546 /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
<> 161:2cc1468da177 547 latency = LL_FLASH_LATENCY_4;
<> 161:2cc1468da177 548 }
<> 161:2cc1468da177 549 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
<> 161:2cc1468da177 550 {
<> 161:2cc1468da177 551 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
<> 161:2cc1468da177 552 latency = LL_FLASH_LATENCY_3;
<> 161:2cc1468da177 553 }
<> 161:2cc1468da177 554 else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
<> 161:2cc1468da177 555 {
<> 161:2cc1468da177 556 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
<> 161:2cc1468da177 557 latency = LL_FLASH_LATENCY_2;
<> 161:2cc1468da177 558 }
<> 161:2cc1468da177 559 else
<> 161:2cc1468da177 560 {
<> 161:2cc1468da177 561 if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
<> 161:2cc1468da177 562 {
<> 161:2cc1468da177 563 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
<> 161:2cc1468da177 564 latency = LL_FLASH_LATENCY_1;
<> 161:2cc1468da177 565 }
<> 161:2cc1468da177 566 /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
<> 161:2cc1468da177 567 }
<> 161:2cc1468da177 568 }
<> 161:2cc1468da177 569 else /* Scale 3 */
<> 161:2cc1468da177 570 {
<> 161:2cc1468da177 571 if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
<> 161:2cc1468da177 572 {
<> 161:2cc1468da177 573 /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
<> 161:2cc1468da177 574 latency = LL_FLASH_LATENCY_4;
<> 161:2cc1468da177 575 }
<> 161:2cc1468da177 576 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
<> 161:2cc1468da177 577 {
<> 161:2cc1468da177 578 /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
<> 161:2cc1468da177 579 latency = LL_FLASH_LATENCY_3;
<> 161:2cc1468da177 580 }
<> 161:2cc1468da177 581 else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
<> 161:2cc1468da177 582 {
<> 161:2cc1468da177 583 /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
<> 161:2cc1468da177 584 latency = LL_FLASH_LATENCY_2;
<> 161:2cc1468da177 585 }
<> 161:2cc1468da177 586 else
<> 161:2cc1468da177 587 {
<> 161:2cc1468da177 588 if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
<> 161:2cc1468da177 589 {
<> 161:2cc1468da177 590 /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
<> 161:2cc1468da177 591 latency = LL_FLASH_LATENCY_1;
<> 161:2cc1468da177 592 }
<> 161:2cc1468da177 593 /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
<> 161:2cc1468da177 594 }
<> 161:2cc1468da177 595 }
<> 161:2cc1468da177 596
<> 161:2cc1468da177 597 LL_FLASH_SetLatency(latency);
<> 161:2cc1468da177 598
<> 161:2cc1468da177 599 /* Check that the new number of wait states is taken into account to access the Flash
<> 161:2cc1468da177 600 memory by reading the FLASH_ACR register */
<> 161:2cc1468da177 601 if(LL_FLASH_GetLatency() != latency)
<> 161:2cc1468da177 602 {
<> 161:2cc1468da177 603 status = ERROR;
<> 161:2cc1468da177 604 }
<> 161:2cc1468da177 605 }
<> 161:2cc1468da177 606 return status;
<> 161:2cc1468da177 607 }
<> 161:2cc1468da177 608
<> 161:2cc1468da177 609 /**
<> 161:2cc1468da177 610 * @brief Function to check that PLL can be modified
<> 161:2cc1468da177 611 * @param PLL_InputFrequency PLL input frequency (in Hz)
<> 161:2cc1468da177 612 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
<> 161:2cc1468da177 613 * the configuration information for the PLL.
<> 161:2cc1468da177 614 * @retval PLL output frequency (in Hz)
<> 161:2cc1468da177 615 */
<> 161:2cc1468da177 616 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
<> 161:2cc1468da177 617 {
<> 161:2cc1468da177 618 uint32_t pllfreq = 0U;
<> 161:2cc1468da177 619
<> 161:2cc1468da177 620 /* Check the parameters */
<> 161:2cc1468da177 621 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
<> 161:2cc1468da177 622 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
<> 161:2cc1468da177 623 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
<> 161:2cc1468da177 624
<> 161:2cc1468da177 625 /* Check different PLL parameters according to RM */
<> 161:2cc1468da177 626 /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
<> 161:2cc1468da177 627 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
<> 161:2cc1468da177 628 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
<> 161:2cc1468da177 629
<> 161:2cc1468da177 630 /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
<> 161:2cc1468da177 631 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
<> 161:2cc1468da177 632 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
<> 161:2cc1468da177 633
<> 161:2cc1468da177 634 /* - PLLP: ensure that max frequency at 216000000 Hz is reached */
<> 161:2cc1468da177 635 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
<> 161:2cc1468da177 636 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
<> 161:2cc1468da177 637
<> 161:2cc1468da177 638 return pllfreq;
<> 161:2cc1468da177 639 }
<> 161:2cc1468da177 640
<> 161:2cc1468da177 641 /**
<> 161:2cc1468da177 642 * @brief Function to check that PLL can be modified
<> 161:2cc1468da177 643 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 644 * - SUCCESS: PLL modification can be done
<> 161:2cc1468da177 645 * - ERROR: PLL is busy
<> 161:2cc1468da177 646 */
<> 161:2cc1468da177 647 static ErrorStatus UTILS_PLL_IsBusy(void)
<> 161:2cc1468da177 648 {
<> 161:2cc1468da177 649 ErrorStatus status = SUCCESS;
<> 161:2cc1468da177 650
<> 161:2cc1468da177 651 /* Check if PLL is busy*/
<> 161:2cc1468da177 652 if(LL_RCC_PLL_IsReady() != 0U)
<> 161:2cc1468da177 653 {
<> 161:2cc1468da177 654 /* PLL configuration cannot be modified */
<> 161:2cc1468da177 655 status = ERROR;
<> 161:2cc1468da177 656 }
<> 161:2cc1468da177 657
<> 161:2cc1468da177 658 /* Check if PLLSAI is busy*/
<> 161:2cc1468da177 659 if(LL_RCC_PLLSAI_IsReady() != 0U)
<> 161:2cc1468da177 660 {
<> 161:2cc1468da177 661 /* PLLSAI1 configuration cannot be modified */
<> 161:2cc1468da177 662 status = ERROR;
<> 161:2cc1468da177 663 }
<> 161:2cc1468da177 664 /* Check if PLLI2S is busy*/
<> 161:2cc1468da177 665 if(LL_RCC_PLLI2S_IsReady() != 0U)
<> 161:2cc1468da177 666 {
<> 161:2cc1468da177 667 /* PLLI2S configuration cannot be modified */
<> 161:2cc1468da177 668 status = ERROR;
<> 161:2cc1468da177 669 }
<> 161:2cc1468da177 670 return status;
<> 161:2cc1468da177 671 }
<> 161:2cc1468da177 672
<> 161:2cc1468da177 673 /**
<> 161:2cc1468da177 674 * @brief Function to enable PLL and switch system clock to PLL
<> 161:2cc1468da177 675 * @param SYSCLK_Frequency SYSCLK frequency
<> 161:2cc1468da177 676 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
<> 161:2cc1468da177 677 * the configuration information for the BUS prescalers.
<> 161:2cc1468da177 678 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 679 * - SUCCESS: No problem to switch system to PLL
<> 161:2cc1468da177 680 * - ERROR: Problem to switch system to PLL
<> 161:2cc1468da177 681 */
<> 161:2cc1468da177 682 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
<> 161:2cc1468da177 683 {
<> 161:2cc1468da177 684 ErrorStatus status = SUCCESS;
<> 161:2cc1468da177 685 uint32_t hclk_frequency = 0U;
<> 161:2cc1468da177 686
<> 161:2cc1468da177 687 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
<> 161:2cc1468da177 688 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
<> 161:2cc1468da177 689 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
<> 161:2cc1468da177 690
<> 161:2cc1468da177 691 /* Calculate HCLK frequency */
<> 161:2cc1468da177 692 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
<> 161:2cc1468da177 693
<> 161:2cc1468da177 694 /* Increasing the number of wait states because of higher CPU frequency */
<> 161:2cc1468da177 695 if(SystemCoreClock < hclk_frequency)
<> 161:2cc1468da177 696 {
<> 161:2cc1468da177 697 /* Set FLASH latency to highest latency */
<> 161:2cc1468da177 698 status = UTILS_SetFlashLatency(hclk_frequency);
<> 161:2cc1468da177 699 }
<> 161:2cc1468da177 700
<> 161:2cc1468da177 701 /* Update system clock configuration */
<> 161:2cc1468da177 702 if(status == SUCCESS)
<> 161:2cc1468da177 703 {
<> 161:2cc1468da177 704 /* Enable PLL */
<> 161:2cc1468da177 705 LL_RCC_PLL_Enable();
<> 161:2cc1468da177 706 while (LL_RCC_PLL_IsReady() != 1U)
<> 161:2cc1468da177 707 {
<> 161:2cc1468da177 708 /* Wait for PLL ready */
<> 161:2cc1468da177 709 }
<> 161:2cc1468da177 710
<> 161:2cc1468da177 711 /* Sysclk activation on the main PLL */
<> 161:2cc1468da177 712 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
<> 161:2cc1468da177 713 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
<> 161:2cc1468da177 714 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
<> 161:2cc1468da177 715 {
<> 161:2cc1468da177 716 /* Wait for system clock switch to PLL */
<> 161:2cc1468da177 717 }
<> 161:2cc1468da177 718
<> 161:2cc1468da177 719 /* Set APB1 & APB2 prescaler*/
<> 161:2cc1468da177 720 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
<> 161:2cc1468da177 721 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
<> 161:2cc1468da177 722 }
<> 161:2cc1468da177 723
<> 161:2cc1468da177 724 /* Decreasing the number of wait states because of lower CPU frequency */
<> 161:2cc1468da177 725 if(SystemCoreClock > hclk_frequency)
<> 161:2cc1468da177 726 {
<> 161:2cc1468da177 727 /* Set FLASH latency to lowest latency */
<> 161:2cc1468da177 728 status = UTILS_SetFlashLatency(hclk_frequency);
<> 161:2cc1468da177 729 }
<> 161:2cc1468da177 730
<> 161:2cc1468da177 731 /* Update SystemCoreClock variable */
<> 161:2cc1468da177 732 if(status == SUCCESS)
<> 161:2cc1468da177 733 {
<> 161:2cc1468da177 734 LL_SetSystemCoreClock(hclk_frequency);
<> 161:2cc1468da177 735 }
<> 161:2cc1468da177 736
<> 161:2cc1468da177 737 return status;
<> 161:2cc1468da177 738 }
<> 161:2cc1468da177 739
<> 161:2cc1468da177 740 /**
<> 161:2cc1468da177 741 * @}
<> 161:2cc1468da177 742 */
<> 161:2cc1468da177 743
<> 161:2cc1468da177 744 /**
<> 161:2cc1468da177 745 * @}
<> 161:2cc1468da177 746 */
<> 161:2cc1468da177 747
<> 161:2cc1468da177 748 /**
<> 161:2cc1468da177 749 * @}
<> 161:2cc1468da177 750 */
<> 161:2cc1468da177 751
<> 161:2cc1468da177 752 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/