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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_tim.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief Header file of TIM LL module.
<>	161:2cc1468da177	8	******************************************************************************
<>	161:2cc1468da177	9	* @attention
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	12	*
<>	161:2cc1468da177	13	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	14	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	18	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	19	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	21	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	22	* without specific prior written permission.
<>	161:2cc1468da177	23	*
<>	161:2cc1468da177	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	34	*
<>	161:2cc1468da177	35	******************************************************************************
<>	161:2cc1468da177	36	*/
<>	161:2cc1468da177	37
<>	161:2cc1468da177	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	39	#ifndef __STM32F7xx_LL_TIM_H
<>	161:2cc1468da177	40	#define __STM32F7xx_LL_TIM_H
<>	161:2cc1468da177	41
<>	161:2cc1468da177	42	#ifdef __cplusplus
<>	161:2cc1468da177	43	extern "C" {
<>	161:2cc1468da177	44	#endif
<>	161:2cc1468da177	45
<>	161:2cc1468da177	46	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	47	#include "stm32f7xx.h"
<>	161:2cc1468da177	48
<>	161:2cc1468da177	49	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	50	* @{
<>	161:2cc1468da177	51	*/
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	#if defined (TIM1) \|\| defined (TIM8) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM9) \|\| defined (TIM10) \|\| defined (TIM11) \|\| defined (TIM12) \|\| defined (TIM13) \|\| defined (TIM14) \|\| defined (TIM6) \|\| defined (TIM7)
<>	161:2cc1468da177	54
<>	161:2cc1468da177	55	/** @defgroup TIM_LL TIM
<>	161:2cc1468da177	56	* @{
<>	161:2cc1468da177	57	*/
<>	161:2cc1468da177	58
<>	161:2cc1468da177	59	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	60	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
<>	161:2cc1468da177	62	* @{
<>	161:2cc1468da177	63	*/
<>	161:2cc1468da177	64	static const uint8_t OFFSET_TAB_CCMRx[] =
<>	161:2cc1468da177	65	{
<>	161:2cc1468da177	66	0x00U, /* 0: TIMx_CH1 */
<>	161:2cc1468da177	67	0x00U, /* 1: TIMx_CH1N */
<>	161:2cc1468da177	68	0x00U, /* 2: TIMx_CH2 */
<>	161:2cc1468da177	69	0x00U, /* 3: TIMx_CH2N */
<>	161:2cc1468da177	70	0x04U, /* 4: TIMx_CH3 */
<>	161:2cc1468da177	71	0x04U, /* 5: TIMx_CH3N */
<>	161:2cc1468da177	72	0x04U, /* 6: TIMx_CH4 */
<>	161:2cc1468da177	73	0x3CU, /* 7: TIMx_CH5 */
<>	161:2cc1468da177	74	0x3CU /* 8: TIMx_CH6 */
<>	161:2cc1468da177	75	};
<>	161:2cc1468da177	76
<>	161:2cc1468da177	77	static const uint8_t SHIFT_TAB_OCxx[] =
<>	161:2cc1468da177	78	{
<>	161:2cc1468da177	79	0U, /* 0: OC1M, OC1FE, OC1PE */
<>	161:2cc1468da177	80	0U, /* 1: - NA */
<>	161:2cc1468da177	81	8U, /* 2: OC2M, OC2FE, OC2PE */
<>	161:2cc1468da177	82	0U, /* 3: - NA */
<>	161:2cc1468da177	83	0U, /* 4: OC3M, OC3FE, OC3PE */
<>	161:2cc1468da177	84	0U, /* 5: - NA */
<>	161:2cc1468da177	85	8U, /* 6: OC4M, OC4FE, OC4PE */
<>	161:2cc1468da177	86	0U, /* 7: OC5M, OC5FE, OC5PE */
<>	161:2cc1468da177	87	8U /* 8: OC6M, OC6FE, OC6PE */
<>	161:2cc1468da177	88	};
<>	161:2cc1468da177	89
<>	161:2cc1468da177	90	static const uint8_t SHIFT_TAB_ICxx[] =
<>	161:2cc1468da177	91	{
<>	161:2cc1468da177	92	0U, /* 0: CC1S, IC1PSC, IC1F */
<>	161:2cc1468da177	93	0U, /* 1: - NA */
<>	161:2cc1468da177	94	8U, /* 2: CC2S, IC2PSC, IC2F */
<>	161:2cc1468da177	95	0U, /* 3: - NA */
<>	161:2cc1468da177	96	0U, /* 4: CC3S, IC3PSC, IC3F */
<>	161:2cc1468da177	97	0U, /* 5: - NA */
<>	161:2cc1468da177	98	8U, /* 6: CC4S, IC4PSC, IC4F */
<>	161:2cc1468da177	99	0U, /* 7: - NA */
<>	161:2cc1468da177	100	0U /* 8: - NA */
<>	161:2cc1468da177	101	};
<>	161:2cc1468da177	102
<>	161:2cc1468da177	103	static const uint8_t SHIFT_TAB_CCxP[] =
<>	161:2cc1468da177	104	{
<>	161:2cc1468da177	105	0U, /* 0: CC1P */
<>	161:2cc1468da177	106	2U, /* 1: CC1NP */
<>	161:2cc1468da177	107	4U, /* 2: CC2P */
<>	161:2cc1468da177	108	6U, /* 3: CC2NP */
<>	161:2cc1468da177	109	8U, /* 4: CC3P */
<>	161:2cc1468da177	110	10U, /* 5: CC3NP */
<>	161:2cc1468da177	111	12U, /* 6: CC4P */
<>	161:2cc1468da177	112	16U, /* 7: CC5P */
<>	161:2cc1468da177	113	20U /* 8: CC6P */
<>	161:2cc1468da177	114	};
<>	161:2cc1468da177	115
<>	161:2cc1468da177	116	static const uint8_t SHIFT_TAB_OISx[] =
<>	161:2cc1468da177	117	{
<>	161:2cc1468da177	118	0U, /* 0: OIS1 */
<>	161:2cc1468da177	119	1U, /* 1: OIS1N */
<>	161:2cc1468da177	120	2U, /* 2: OIS2 */
<>	161:2cc1468da177	121	3U, /* 3: OIS2N */
<>	161:2cc1468da177	122	4U, /* 4: OIS3 */
<>	161:2cc1468da177	123	5U, /* 5: OIS3N */
<>	161:2cc1468da177	124	6U, /* 6: OIS4 */
<>	161:2cc1468da177	125	8U, /* 7: OIS5 */
<>	161:2cc1468da177	126	10U /* 8: OIS6 */
<>	161:2cc1468da177	127	};
<>	161:2cc1468da177	128	/**
<>	161:2cc1468da177	129	* @}
<>	161:2cc1468da177	130	*/
<>	161:2cc1468da177	131
<>	161:2cc1468da177	132
<>	161:2cc1468da177	133	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	134	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
<>	161:2cc1468da177	135	* @{
<>	161:2cc1468da177	136	*/
<>	161:2cc1468da177	137
<>	161:2cc1468da177	138	#if defined(TIM_BREAK_INPUT_SUPPORT)
<>	161:2cc1468da177	139	/* Defines used for the bit position in the register and perform offsets */
<>	161:2cc1468da177	140	#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source)
<>	161:2cc1468da177	141
<>	161:2cc1468da177	142	/* Generic bit definitions for TIMx_AF1 register */
<>	161:2cc1468da177	143	#define TIMx_AF1_BKINE TIM1_AF1_BKINE /!< BRK BKINE input enable /
<>	161:2cc1468da177	144	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	145	#define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /!< BRK DFSDM1_BREAK[0] enable /
<>	161:2cc1468da177	146	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	147	#define TIMx_AF1_BKINP TIM1_AF1_BKINP /!< BRK BKIN input polarity /
<>	161:2cc1468da177	148	/* Generic bit definitions for TIMx_AF2 register */
<>	161:2cc1468da177	149	#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /!< BRK B2KINE input enable /
<>	161:2cc1468da177	150	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	151	#define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /!< BRK DFSDM_BREAK[0] enable /
<>	161:2cc1468da177	152	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	153	#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /!< BRK BK2IN input polarity /
<>	161:2cc1468da177	154	#endif /* TIM_BREAK_INPUT_SUPPORT */
<>	161:2cc1468da177	155
<>	161:2cc1468da177	156	/* Remap mask definitions */
<>	161:2cc1468da177	157	#define TIMx_OR_RMP_SHIFT 16U
<>	161:2cc1468da177	158	#define TIMx_OR_RMP_MASK 0x0000FFFFU
<>	161:2cc1468da177	159	#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
<>	161:2cc1468da177	160	#define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
<>	161:2cc1468da177	161	#define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
<>	161:2cc1468da177	162
<>	161:2cc1468da177	163	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
<>	161:2cc1468da177	164	#define DT_DELAY_1 ((uint8_t)0x7FU)
<>	161:2cc1468da177	165	#define DT_DELAY_2 ((uint8_t)0x3FU)
<>	161:2cc1468da177	166	#define DT_DELAY_3 ((uint8_t)0x1FU)
<>	161:2cc1468da177	167	#define DT_DELAY_4 ((uint8_t)0x1FU)
<>	161:2cc1468da177	168
<>	161:2cc1468da177	169	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
<>	161:2cc1468da177	170	#define DT_RANGE_1 ((uint8_t)0x00U)
<>	161:2cc1468da177	171	#define DT_RANGE_2 ((uint8_t)0x80U)
<>	161:2cc1468da177	172	#define DT_RANGE_3 ((uint8_t)0xC0U)
<>	161:2cc1468da177	173	#define DT_RANGE_4 ((uint8_t)0xE0U)
<>	161:2cc1468da177	174
<>	161:2cc1468da177	175
<>	161:2cc1468da177	176	/**
<>	161:2cc1468da177	177	* @}
<>	161:2cc1468da177	178	*/
<>	161:2cc1468da177	179
<>	161:2cc1468da177	180	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	181	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
<>	161:2cc1468da177	182	* @{
<>	161:2cc1468da177	183	*/
<>	161:2cc1468da177	184	/** @brief Convert channel id into channel index.
<>	161:2cc1468da177	185	* @param __CHANNEL__ This parameter can be one of the following values:
<>	161:2cc1468da177	186	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	187	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	188	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	189	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	190	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	191	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	192	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	193	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	194	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	195	* @retval none
<>	161:2cc1468da177	196	*/
<>	161:2cc1468da177	197	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
<>	161:2cc1468da177	198	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
<>	161:2cc1468da177	199	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
<>	161:2cc1468da177	200	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
<>	161:2cc1468da177	201	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
<>	161:2cc1468da177	202	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
<>	161:2cc1468da177	203	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
<>	161:2cc1468da177	204	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
<>	161:2cc1468da177	205	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
<>	161:2cc1468da177	206
<>	161:2cc1468da177	207	/** @brief Calculate the deadtime sampling period(in ps).
<>	161:2cc1468da177	208	* @param __TIMCLK__ timer input clock frequency (in Hz).
<>	161:2cc1468da177	209	* @param __CKD__ This parameter can be one of the following values:
<>	161:2cc1468da177	210	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	161:2cc1468da177	211	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	161:2cc1468da177	212	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	161:2cc1468da177	213	* @retval none
<>	161:2cc1468da177	214	*/
<>	161:2cc1468da177	215	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
<>	161:2cc1468da177	216	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
<>	161:2cc1468da177	217	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
<>	161:2cc1468da177	218	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
<>	161:2cc1468da177	219	/**
<>	161:2cc1468da177	220	* @}
<>	161:2cc1468da177	221	*/
<>	161:2cc1468da177	222
<>	161:2cc1468da177	223
<>	161:2cc1468da177	224	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	225	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	226	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
<>	161:2cc1468da177	227	* @{
<>	161:2cc1468da177	228	*/
<>	161:2cc1468da177	229
<>	161:2cc1468da177	230	/**
<>	161:2cc1468da177	231	* @brief TIM Time Base configuration structure definition.
<>	161:2cc1468da177	232	*/
<>	161:2cc1468da177	233	typedef struct
<>	161:2cc1468da177	234	{
<>	161:2cc1468da177	235	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	161:2cc1468da177	236	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	161:2cc1468da177	237
<>	161:2cc1468da177	238	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
<>	161:2cc1468da177	239
<>	161:2cc1468da177	240	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	161:2cc1468da177	241	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
<>	161:2cc1468da177	242
<>	161:2cc1468da177	243	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
<>	161:2cc1468da177	244
<>	161:2cc1468da177	245	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
<>	161:2cc1468da177	246	Auto-Reload Register at the next update event.
<>	161:2cc1468da177	247	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	161:2cc1468da177	248	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
<>	161:2cc1468da177	249
<>	161:2cc1468da177	250	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
<>	161:2cc1468da177	251
<>	161:2cc1468da177	252	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	161:2cc1468da177	253	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
<>	161:2cc1468da177	254
<>	161:2cc1468da177	255	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
<>	161:2cc1468da177	256
<>	161:2cc1468da177	257	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	161:2cc1468da177	258	reaches zero, an update event is generated and counting restarts
<>	161:2cc1468da177	259	from the RCR value (N).
<>	161:2cc1468da177	260	This means in PWM mode that (N+1) corresponds to:
<>	161:2cc1468da177	261	- the number of PWM periods in edge-aligned mode
<>	161:2cc1468da177	262	- the number of half PWM period in center-aligned mode
<>	161:2cc1468da177	263	This parameter must be a number between 0x00 and 0xFF.
<>	161:2cc1468da177	264
<>	161:2cc1468da177	265	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
<>	161:2cc1468da177	266	} LL_TIM_InitTypeDef;
<>	161:2cc1468da177	267
<>	161:2cc1468da177	268	/**
<>	161:2cc1468da177	269	* @brief TIM Output Compare configuration structure definition.
<>	161:2cc1468da177	270	*/
<>	161:2cc1468da177	271	typedef struct
<>	161:2cc1468da177	272	{
<>	161:2cc1468da177	273	uint32_t OCMode; /*!< Specifies the output mode.
<>	161:2cc1468da177	274	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
<>	161:2cc1468da177	275
<>	161:2cc1468da177	276	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
<>	161:2cc1468da177	277
<>	161:2cc1468da177	278	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
<>	161:2cc1468da177	279	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	161:2cc1468da177	280
<>	161:2cc1468da177	281	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	161:2cc1468da177	282
<>	161:2cc1468da177	283	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
<>	161:2cc1468da177	284	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
<>	161:2cc1468da177	285
<>	161:2cc1468da177	286	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
<>	161:2cc1468da177	287
<>	161:2cc1468da177	288	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
<>	161:2cc1468da177	289	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
<>	161:2cc1468da177	290
<>	161:2cc1468da177	291	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
<>	161:2cc1468da177	292
<>	161:2cc1468da177	293	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	161:2cc1468da177	294	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	161:2cc1468da177	295
<>	161:2cc1468da177	296	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	161:2cc1468da177	297
<>	161:2cc1468da177	298	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	161:2cc1468da177	299	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
<>	161:2cc1468da177	300
<>	161:2cc1468da177	301	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
<>	161:2cc1468da177	302
<>	161:2cc1468da177	303
<>	161:2cc1468da177	304	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	161:2cc1468da177	305	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	161:2cc1468da177	306
<>	161:2cc1468da177	307	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	161:2cc1468da177	308
<>	161:2cc1468da177	309	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	161:2cc1468da177	310	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
<>	161:2cc1468da177	311
<>	161:2cc1468da177	312	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
<>	161:2cc1468da177	313	} LL_TIM_OC_InitTypeDef;
<>	161:2cc1468da177	314
<>	161:2cc1468da177	315	/**
<>	161:2cc1468da177	316	* @brief TIM Input Capture configuration structure definition.
<>	161:2cc1468da177	317	*/
<>	161:2cc1468da177	318
<>	161:2cc1468da177	319	typedef struct
<>	161:2cc1468da177	320	{
<>	161:2cc1468da177	321
<>	161:2cc1468da177	322	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	161:2cc1468da177	323	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	161:2cc1468da177	324
<>	161:2cc1468da177	325	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	161:2cc1468da177	326
<>	161:2cc1468da177	327	uint32_t ICActiveInput; /*!< Specifies the input.
<>	161:2cc1468da177	328	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	161:2cc1468da177	329
<>	161:2cc1468da177	330	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	161:2cc1468da177	331
<>	161:2cc1468da177	332	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	161:2cc1468da177	333	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	161:2cc1468da177	334
<>	161:2cc1468da177	335	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	161:2cc1468da177	336
<>	161:2cc1468da177	337	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	161:2cc1468da177	338	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	161:2cc1468da177	339
<>	161:2cc1468da177	340	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	161:2cc1468da177	341	} LL_TIM_IC_InitTypeDef;
<>	161:2cc1468da177	342
<>	161:2cc1468da177	343
<>	161:2cc1468da177	344	/**
<>	161:2cc1468da177	345	* @brief TIM Encoder interface configuration structure definition.
<>	161:2cc1468da177	346	*/
<>	161:2cc1468da177	347	typedef struct
<>	161:2cc1468da177	348	{
<>	161:2cc1468da177	349	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
<>	161:2cc1468da177	350	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
<>	161:2cc1468da177	351
<>	161:2cc1468da177	352	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
<>	161:2cc1468da177	353
<>	161:2cc1468da177	354	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	161:2cc1468da177	355	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	161:2cc1468da177	356
<>	161:2cc1468da177	357	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	161:2cc1468da177	358
<>	161:2cc1468da177	359	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
<>	161:2cc1468da177	360	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	161:2cc1468da177	361
<>	161:2cc1468da177	362	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	161:2cc1468da177	363
<>	161:2cc1468da177	364	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	161:2cc1468da177	365	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	161:2cc1468da177	366
<>	161:2cc1468da177	367	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	161:2cc1468da177	368
<>	161:2cc1468da177	369	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	161:2cc1468da177	370	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	161:2cc1468da177	371
<>	161:2cc1468da177	372	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	161:2cc1468da177	373
<>	161:2cc1468da177	374	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
<>	161:2cc1468da177	375	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	161:2cc1468da177	376
<>	161:2cc1468da177	377	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	161:2cc1468da177	378
<>	161:2cc1468da177	379	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
<>	161:2cc1468da177	380	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
<>	161:2cc1468da177	381
<>	161:2cc1468da177	382	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
<>	161:2cc1468da177	383
<>	161:2cc1468da177	384	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
<>	161:2cc1468da177	385	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	161:2cc1468da177	386
<>	161:2cc1468da177	387	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	161:2cc1468da177	388
<>	161:2cc1468da177	389	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
<>	161:2cc1468da177	390	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	161:2cc1468da177	391
<>	161:2cc1468da177	392	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	161:2cc1468da177	393
<>	161:2cc1468da177	394	} LL_TIM_ENCODER_InitTypeDef;
<>	161:2cc1468da177	395
<>	161:2cc1468da177	396	/**
<>	161:2cc1468da177	397	* @brief TIM Hall sensor interface configuration structure definition.
<>	161:2cc1468da177	398	*/
<>	161:2cc1468da177	399	typedef struct
<>	161:2cc1468da177	400	{
<>	161:2cc1468da177	401
<>	161:2cc1468da177	402	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
<>	161:2cc1468da177	403	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
<>	161:2cc1468da177	404
<>	161:2cc1468da177	405	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
<>	161:2cc1468da177	406
<>	161:2cc1468da177	407	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
<>	161:2cc1468da177	408	Prescaler must be set to get a maximum counter period longer than the
<>	161:2cc1468da177	409	time interval between 2 consecutive changes on the Hall inputs.
<>	161:2cc1468da177	410	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
<>	161:2cc1468da177	411
<>	161:2cc1468da177	412	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
<>	161:2cc1468da177	413
<>	161:2cc1468da177	414	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
<>	161:2cc1468da177	415	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
<>	161:2cc1468da177	416
<>	161:2cc1468da177	417	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
<>	161:2cc1468da177	418
<>	161:2cc1468da177	419	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
<>	161:2cc1468da177	420	A positive pulse (TRGO event) is generated with a programmable delay every time
<>	161:2cc1468da177	421	a change occurs on the Hall inputs.
<>	161:2cc1468da177	422	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
<>	161:2cc1468da177	423
<>	161:2cc1468da177	424	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
<>	161:2cc1468da177	425	} LL_TIM_HALLSENSOR_InitTypeDef;
<>	161:2cc1468da177	426
<>	161:2cc1468da177	427	/**
<>	161:2cc1468da177	428	* @brief BDTR (Break and Dead Time) structure definition
<>	161:2cc1468da177	429	*/
<>	161:2cc1468da177	430	typedef struct
<>	161:2cc1468da177	431	{
<>	161:2cc1468da177	432	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
<>	161:2cc1468da177	433	This parameter can be a value of @ref TIM_LL_EC_OSSR
<>	161:2cc1468da177	434
<>	161:2cc1468da177	435	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
<>	161:2cc1468da177	436
<>	161:2cc1468da177	437	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
<>	161:2cc1468da177	438
<>	161:2cc1468da177	439	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
<>	161:2cc1468da177	440	This parameter can be a value of @ref TIM_LL_EC_OSSI
<>	161:2cc1468da177	441
<>	161:2cc1468da177	442	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
<>	161:2cc1468da177	443
<>	161:2cc1468da177	444	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
<>	161:2cc1468da177	445
<>	161:2cc1468da177	446	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
<>	161:2cc1468da177	447	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
<>	161:2cc1468da177	448
<>	161:2cc1468da177	449	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
<>	161:2cc1468da177	450	has been written, their content is frozen until the next reset.*/
<>	161:2cc1468da177	451
<>	161:2cc1468da177	452	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
<>	161:2cc1468da177	453	switching-on of the outputs.
<>	161:2cc1468da177	454	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	161:2cc1468da177	455
<>	161:2cc1468da177	456	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
<>	161:2cc1468da177	457
<>	161:2cc1468da177	458	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
<>	161:2cc1468da177	459
<>	161:2cc1468da177	460	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
<>	161:2cc1468da177	461	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
<>	161:2cc1468da177	462
<>	161:2cc1468da177	463	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
<>	161:2cc1468da177	464
<>	161:2cc1468da177	465	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	161:2cc1468da177	466
<>	161:2cc1468da177	467	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
<>	161:2cc1468da177	468	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
<>	161:2cc1468da177	469
<>	161:2cc1468da177	470	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
<>	161:2cc1468da177	471
<>	161:2cc1468da177	472	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	161:2cc1468da177	473
<>	161:2cc1468da177	474	uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
<>	161:2cc1468da177	475	This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
<>	161:2cc1468da177	476
<>	161:2cc1468da177	477	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
<>	161:2cc1468da177	478
<>	161:2cc1468da177	479	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	161:2cc1468da177	480
<>	161:2cc1468da177	481	uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
<>	161:2cc1468da177	482	This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
<>	161:2cc1468da177	483
<>	161:2cc1468da177	484	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
<>	161:2cc1468da177	485
<>	161:2cc1468da177	486	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	161:2cc1468da177	487
<>	161:2cc1468da177	488	uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
<>	161:2cc1468da177	489	This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
<>	161:2cc1468da177	490
<>	161:2cc1468da177	491	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
<>	161:2cc1468da177	492
<>	161:2cc1468da177	493	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	161:2cc1468da177	494
<>	161:2cc1468da177	495	uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
<>	161:2cc1468da177	496	This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
<>	161:2cc1468da177	497
<>	161:2cc1468da177	498	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
<>	161:2cc1468da177	499
<>	161:2cc1468da177	500	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	161:2cc1468da177	501
<>	161:2cc1468da177	502	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
<>	161:2cc1468da177	503	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
<>	161:2cc1468da177	504
<>	161:2cc1468da177	505	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
<>	161:2cc1468da177	506
<>	161:2cc1468da177	507	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
<>	161:2cc1468da177	508	} LL_TIM_BDTR_InitTypeDef;
<>	161:2cc1468da177	509
<>	161:2cc1468da177	510	/**
<>	161:2cc1468da177	511	* @}
<>	161:2cc1468da177	512	*/
<>	161:2cc1468da177	513	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	514
<>	161:2cc1468da177	515	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	516	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
<>	161:2cc1468da177	517	* @{
<>	161:2cc1468da177	518	*/
<>	161:2cc1468da177	519
<>	161:2cc1468da177	520	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
<>	161:2cc1468da177	521	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
<>	161:2cc1468da177	522	* @{
<>	161:2cc1468da177	523	*/
<>	161:2cc1468da177	524	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
<>	161:2cc1468da177	525	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
<>	161:2cc1468da177	526	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
<>	161:2cc1468da177	527	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
<>	161:2cc1468da177	528	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
<>	161:2cc1468da177	529	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
<>	161:2cc1468da177	530	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
<>	161:2cc1468da177	531	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
<>	161:2cc1468da177	532	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
<>	161:2cc1468da177	533	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
<>	161:2cc1468da177	534	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
<>	161:2cc1468da177	535	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
<>	161:2cc1468da177	536	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
<>	161:2cc1468da177	537	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
<>	161:2cc1468da177	538	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
<>	161:2cc1468da177	539	#define LL_TIM_SR_SBIF TIM_SR_SBIF /!< System Break interrupt flag /
<>	161:2cc1468da177	540	/**
<>	161:2cc1468da177	541	* @}
<>	161:2cc1468da177	542	*/
<>	161:2cc1468da177	543
<>	161:2cc1468da177	544	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	545	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
<>	161:2cc1468da177	546	* @{
<>	161:2cc1468da177	547	*/
<>	161:2cc1468da177	548	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
<>	161:2cc1468da177	549	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
<>	161:2cc1468da177	550	/**
<>	161:2cc1468da177	551	* @}
<>	161:2cc1468da177	552	*/
<>	161:2cc1468da177	553
<>	161:2cc1468da177	554	/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
<>	161:2cc1468da177	555	* @{
<>	161:2cc1468da177	556	*/
<>	161:2cc1468da177	557	#define LL_TIM_BREAK2_DISABLE 0x00000000U /!< Break2 function disabled /
<>	161:2cc1468da177	558	#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break2 function enabled /
<>	161:2cc1468da177	559	/**
<>	161:2cc1468da177	560	* @}
<>	161:2cc1468da177	561	*/
<>	161:2cc1468da177	562
<>	161:2cc1468da177	563	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
<>	161:2cc1468da177	564	* @{
<>	161:2cc1468da177	565	*/
<>	161:2cc1468da177	566	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
<>	161:2cc1468da177	567	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
<>	161:2cc1468da177	568	/**
<>	161:2cc1468da177	569	* @}
<>	161:2cc1468da177	570	*/
<>	161:2cc1468da177	571	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	572
<>	161:2cc1468da177	573	/** @defgroup TIM_LL_EC_IT IT Defines
<>	161:2cc1468da177	574	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
<>	161:2cc1468da177	575	* @{
<>	161:2cc1468da177	576	*/
<>	161:2cc1468da177	577	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
<>	161:2cc1468da177	578	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
<>	161:2cc1468da177	579	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
<>	161:2cc1468da177	580	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
<>	161:2cc1468da177	581	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
<>	161:2cc1468da177	582	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
<>	161:2cc1468da177	583	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
<>	161:2cc1468da177	584	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
<>	161:2cc1468da177	585	/**
<>	161:2cc1468da177	586	* @}
<>	161:2cc1468da177	587	*/
<>	161:2cc1468da177	588
<>	161:2cc1468da177	589	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
<>	161:2cc1468da177	590	* @{
<>	161:2cc1468da177	591	*/
<>	161:2cc1468da177	592	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
<>	161:2cc1468da177	593	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
<>	161:2cc1468da177	594	/**
<>	161:2cc1468da177	595	* @}
<>	161:2cc1468da177	596	*/
<>	161:2cc1468da177	597
<>	161:2cc1468da177	598	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
<>	161:2cc1468da177	599	* @{
<>	161:2cc1468da177	600	*/
<>	161:2cc1468da177	601	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
<>	161:2cc1468da177	602	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
<>	161:2cc1468da177	603	/**
<>	161:2cc1468da177	604	* @}
<>	161:2cc1468da177	605	*/
<>	161:2cc1468da177	606
<>	161:2cc1468da177	607	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
<>	161:2cc1468da177	608	* @{
<>	161:2cc1468da177	609	*/
<>	161:2cc1468da177	610	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
<>	161:2cc1468da177	611	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
<>	161:2cc1468da177	612	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
<>	161:2cc1468da177	613	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
<>	161:2cc1468da177	614	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
<>	161:2cc1468da177	615	/**
<>	161:2cc1468da177	616	* @}
<>	161:2cc1468da177	617	*/
<>	161:2cc1468da177	618
<>	161:2cc1468da177	619	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
<>	161:2cc1468da177	620	* @{
<>	161:2cc1468da177	621	*/
<>	161:2cc1468da177	622	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
<>	161:2cc1468da177	623	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
<>	161:2cc1468da177	624	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
<>	161:2cc1468da177	625	/**
<>	161:2cc1468da177	626	* @}
<>	161:2cc1468da177	627	*/
<>	161:2cc1468da177	628
<>	161:2cc1468da177	629	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
<>	161:2cc1468da177	630	* @{
<>	161:2cc1468da177	631	*/
<>	161:2cc1468da177	632	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
<>	161:2cc1468da177	633	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
<>	161:2cc1468da177	634	/**
<>	161:2cc1468da177	635	* @}
<>	161:2cc1468da177	636	*/
<>	161:2cc1468da177	637
<>	161:2cc1468da177	638	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
<>	161:2cc1468da177	639	* @{
<>	161:2cc1468da177	640	*/
<>	161:2cc1468da177	641	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
<>	161:2cc1468da177	642	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
<>	161:2cc1468da177	643	/**
<>	161:2cc1468da177	644	* @}
<>	161:2cc1468da177	645	*/
<>	161:2cc1468da177	646
<>	161:2cc1468da177	647	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
<>	161:2cc1468da177	648	* @{
<>	161:2cc1468da177	649	*/
<>	161:2cc1468da177	650	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
<>	161:2cc1468da177	651	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
<>	161:2cc1468da177	652	/**
<>	161:2cc1468da177	653	* @}
<>	161:2cc1468da177	654	*/
<>	161:2cc1468da177	655
<>	161:2cc1468da177	656	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
<>	161:2cc1468da177	657	* @{
<>	161:2cc1468da177	658	*/
<>	161:2cc1468da177	659	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
<>	161:2cc1468da177	660	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
<>	161:2cc1468da177	661	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
<>	161:2cc1468da177	662	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
<>	161:2cc1468da177	663	/**
<>	161:2cc1468da177	664	* @}
<>	161:2cc1468da177	665	*/
<>	161:2cc1468da177	666
<>	161:2cc1468da177	667	/** @defgroup TIM_LL_EC_CHANNEL Channel
<>	161:2cc1468da177	668	* @{
<>	161:2cc1468da177	669	*/
<>	161:2cc1468da177	670	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
<>	161:2cc1468da177	671	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
<>	161:2cc1468da177	672	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
<>	161:2cc1468da177	673	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
<>	161:2cc1468da177	674	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
<>	161:2cc1468da177	675	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
<>	161:2cc1468da177	676	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
<>	161:2cc1468da177	677	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
<>	161:2cc1468da177	678	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
<>	161:2cc1468da177	679	/**
<>	161:2cc1468da177	680	* @}
<>	161:2cc1468da177	681	*/
<>	161:2cc1468da177	682
<>	161:2cc1468da177	683	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	684	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
<>	161:2cc1468da177	685	* @{
<>	161:2cc1468da177	686	*/
<>	161:2cc1468da177	687	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
<>	161:2cc1468da177	688	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
<>	161:2cc1468da177	689	/**
<>	161:2cc1468da177	690	* @}
<>	161:2cc1468da177	691	*/
<>	161:2cc1468da177	692	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	693
<>	161:2cc1468da177	694	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
<>	161:2cc1468da177	695	* @{
<>	161:2cc1468da177	696	*/
<>	161:2cc1468da177	697	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
<>	161:2cc1468da177	698	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
<>	161:2cc1468da177	699	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
<>	161:2cc1468da177	700	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
<>	161:2cc1468da177	701	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
<>	161:2cc1468da177	702	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
<>	161:2cc1468da177	703	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
<>	161:2cc1468da177	704	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
<>	161:2cc1468da177	705	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
<>	161:2cc1468da177	706	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
<>	161:2cc1468da177	707	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
<>	161:2cc1468da177	708	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
<>	161:2cc1468da177	709	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
<>	161:2cc1468da177	710	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
<>	161:2cc1468da177	711	/**
<>	161:2cc1468da177	712	* @}
<>	161:2cc1468da177	713	*/
<>	161:2cc1468da177	714
<>	161:2cc1468da177	715	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
<>	161:2cc1468da177	716	* @{
<>	161:2cc1468da177	717	*/
<>	161:2cc1468da177	718	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
<>	161:2cc1468da177	719	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
<>	161:2cc1468da177	720	/**
<>	161:2cc1468da177	721	* @}
<>	161:2cc1468da177	722	*/
<>	161:2cc1468da177	723
<>	161:2cc1468da177	724	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
<>	161:2cc1468da177	725	* @{
<>	161:2cc1468da177	726	*/
<>	161:2cc1468da177	727	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
<>	161:2cc1468da177	728	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
<>	161:2cc1468da177	729	/**
<>	161:2cc1468da177	730	* @}
<>	161:2cc1468da177	731	*/
<>	161:2cc1468da177	732
<>	161:2cc1468da177	733	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
<>	161:2cc1468da177	734	* @{
<>	161:2cc1468da177	735	*/
<>	161:2cc1468da177	736	#define LL_TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
<>	161:2cc1468da177	737	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
<>	161:2cc1468da177	738	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
<>	161:2cc1468da177	739	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
<>	161:2cc1468da177	740	/**
<>	161:2cc1468da177	741	* @}
<>	161:2cc1468da177	742	*/
<>	161:2cc1468da177	743
<>	161:2cc1468da177	744	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
<>	161:2cc1468da177	745	* @{
<>	161:2cc1468da177	746	*/
<>	161:2cc1468da177	747	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
<>	161:2cc1468da177	748	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
<>	161:2cc1468da177	749	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
<>	161:2cc1468da177	750	/**
<>	161:2cc1468da177	751	* @}
<>	161:2cc1468da177	752	*/
<>	161:2cc1468da177	753
<>	161:2cc1468da177	754	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
<>	161:2cc1468da177	755	* @{
<>	161:2cc1468da177	756	*/
<>	161:2cc1468da177	757	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
<>	161:2cc1468da177	758	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
<>	161:2cc1468da177	759	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
<>	161:2cc1468da177	760	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
<>	161:2cc1468da177	761	/**
<>	161:2cc1468da177	762	* @}
<>	161:2cc1468da177	763	*/
<>	161:2cc1468da177	764
<>	161:2cc1468da177	765	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
<>	161:2cc1468da177	766	* @{
<>	161:2cc1468da177	767	*/
<>	161:2cc1468da177	768	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
<>	161:2cc1468da177	769	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
<>	161:2cc1468da177	770	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
<>	161:2cc1468da177	771	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
<>	161:2cc1468da177	772	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
<>	161:2cc1468da177	773	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
<>	161:2cc1468da177	774	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
<>	161:2cc1468da177	775	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
<>	161:2cc1468da177	776	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
<>	161:2cc1468da177	777	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
<>	161:2cc1468da177	778	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
<>	161:2cc1468da177	779	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
<>	161:2cc1468da177	780	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
<>	161:2cc1468da177	781	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
<>	161:2cc1468da177	782	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
<>	161:2cc1468da177	783	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
<>	161:2cc1468da177	784	/**
<>	161:2cc1468da177	785	* @}
<>	161:2cc1468da177	786	*/
<>	161:2cc1468da177	787
<>	161:2cc1468da177	788	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
<>	161:2cc1468da177	789	* @{
<>	161:2cc1468da177	790	*/
<>	161:2cc1468da177	791	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
<>	161:2cc1468da177	792	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
<>	161:2cc1468da177	793	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
<>	161:2cc1468da177	794	/**
<>	161:2cc1468da177	795	* @}
<>	161:2cc1468da177	796	*/
<>	161:2cc1468da177	797
<>	161:2cc1468da177	798	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
<>	161:2cc1468da177	799	* @{
<>	161:2cc1468da177	800	*/
<>	161:2cc1468da177	801	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
<>	161:2cc1468da177	802	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
<>	161:2cc1468da177	803	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
<>	161:2cc1468da177	804	/**
<>	161:2cc1468da177	805	* @}
<>	161:2cc1468da177	806	*/
<>	161:2cc1468da177	807
<>	161:2cc1468da177	808	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
<>	161:2cc1468da177	809	* @{
<>	161:2cc1468da177	810	*/
<>	161:2cc1468da177	811	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
<>	161:2cc1468da177	812	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
<>	161:2cc1468da177	813	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
<>	161:2cc1468da177	814	/**
<>	161:2cc1468da177	815	* @}
<>	161:2cc1468da177	816	*/
<>	161:2cc1468da177	817
<>	161:2cc1468da177	818	/** @defgroup TIM_LL_EC_TRGO Trigger Output
<>	161:2cc1468da177	819	* @{
<>	161:2cc1468da177	820	*/
<>	161:2cc1468da177	821	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
<>	161:2cc1468da177	822	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
<>	161:2cc1468da177	823	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
<>	161:2cc1468da177	824	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
<>	161:2cc1468da177	825	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
<>	161:2cc1468da177	826	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
<>	161:2cc1468da177	827	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
<>	161:2cc1468da177	828	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
<>	161:2cc1468da177	829	/**
<>	161:2cc1468da177	830	* @}
<>	161:2cc1468da177	831	*/
<>	161:2cc1468da177	832
<>	161:2cc1468da177	833	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
<>	161:2cc1468da177	834	* @{
<>	161:2cc1468da177	835	*/
<>	161:2cc1468da177	836	#define LL_TIM_TRGO2_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
<>	161:2cc1468da177	837	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
<>	161:2cc1468da177	838	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
<>	161:2cc1468da177	839	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
<>	161:2cc1468da177	840	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
<>	161:2cc1468da177	841	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
<>	161:2cc1468da177	842	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
<>	161:2cc1468da177	843	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
<>	161:2cc1468da177	844	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
<>	161:2cc1468da177	845	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
<>	161:2cc1468da177	846	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
<>	161:2cc1468da177	847	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
<>	161:2cc1468da177	848	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
<>	161:2cc1468da177	849	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
<>	161:2cc1468da177	850	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
<>	161:2cc1468da177	851	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
<>	161:2cc1468da177	852	/**
<>	161:2cc1468da177	853	* @}
<>	161:2cc1468da177	854	*/
<>	161:2cc1468da177	855
<>	161:2cc1468da177	856	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
<>	161:2cc1468da177	857	* @{
<>	161:2cc1468da177	858	*/
<>	161:2cc1468da177	859	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
<>	161:2cc1468da177	860	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
<>	161:2cc1468da177	861	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
<>	161:2cc1468da177	862	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
<>	161:2cc1468da177	863	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
<>	161:2cc1468da177	864	/**
<>	161:2cc1468da177	865	* @}
<>	161:2cc1468da177	866	*/
<>	161:2cc1468da177	867
<>	161:2cc1468da177	868	/** @defgroup TIM_LL_EC_TS Trigger Selection
<>	161:2cc1468da177	869	* @{
<>	161:2cc1468da177	870	*/
<>	161:2cc1468da177	871	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
<>	161:2cc1468da177	872	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
<>	161:2cc1468da177	873	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
<>	161:2cc1468da177	874	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
<>	161:2cc1468da177	875	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
<>	161:2cc1468da177	876	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
<>	161:2cc1468da177	877	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
<>	161:2cc1468da177	878	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
<>	161:2cc1468da177	879	/**
<>	161:2cc1468da177	880	* @}
<>	161:2cc1468da177	881	*/
<>	161:2cc1468da177	882
<>	161:2cc1468da177	883	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
<>	161:2cc1468da177	884	* @{
<>	161:2cc1468da177	885	*/
<>	161:2cc1468da177	886	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
<>	161:2cc1468da177	887	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
<>	161:2cc1468da177	888	/**
<>	161:2cc1468da177	889	* @}
<>	161:2cc1468da177	890	*/
<>	161:2cc1468da177	891
<>	161:2cc1468da177	892	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
<>	161:2cc1468da177	893	* @{
<>	161:2cc1468da177	894	*/
<>	161:2cc1468da177	895	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
<>	161:2cc1468da177	896	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
<>	161:2cc1468da177	897	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
<>	161:2cc1468da177	898	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
<>	161:2cc1468da177	899	/**
<>	161:2cc1468da177	900	* @}
<>	161:2cc1468da177	901	*/
<>	161:2cc1468da177	902
<>	161:2cc1468da177	903	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
<>	161:2cc1468da177	904	* @{
<>	161:2cc1468da177	905	*/
<>	161:2cc1468da177	906	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
<>	161:2cc1468da177	907	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
<>	161:2cc1468da177	908	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
<>	161:2cc1468da177	909	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
<>	161:2cc1468da177	910	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
<>	161:2cc1468da177	911	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
<>	161:2cc1468da177	912	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
<>	161:2cc1468da177	913	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
<>	161:2cc1468da177	914	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
<>	161:2cc1468da177	915	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
<>	161:2cc1468da177	916	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
<>	161:2cc1468da177	917	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
<>	161:2cc1468da177	918	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
<>	161:2cc1468da177	919	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
<>	161:2cc1468da177	920	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
<>	161:2cc1468da177	921	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
<>	161:2cc1468da177	922	/**
<>	161:2cc1468da177	923	* @}
<>	161:2cc1468da177	924	*/
<>	161:2cc1468da177	925
<>	161:2cc1468da177	926
<>	161:2cc1468da177	927	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
<>	161:2cc1468da177	928	* @{
<>	161:2cc1468da177	929	*/
<>	161:2cc1468da177	930	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
<>	161:2cc1468da177	931	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
<>	161:2cc1468da177	932	/**
<>	161:2cc1468da177	933	* @}
<>	161:2cc1468da177	934	*/
<>	161:2cc1468da177	935
<>	161:2cc1468da177	936	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
<>	161:2cc1468da177	937	* @{
<>	161:2cc1468da177	938	*/
<>	161:2cc1468da177	939	#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
<>	161:2cc1468da177	940	#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /!< fSAMPLING=fCK_INT, N=2 /
<>	161:2cc1468da177	941	#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /!< fSAMPLING=fCK_INT, N=4 /
<>	161:2cc1468da177	942	#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /!< fSAMPLING=fCK_INT, N=8 /
<>	161:2cc1468da177	943	#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /!< fSAMPLING=fDTS/2, N=6 /
<>	161:2cc1468da177	944	#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /!< fSAMPLING=fDTS/2, N=8 /
<>	161:2cc1468da177	945	#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /!< fSAMPLING=fDTS/4, N=6 /
<>	161:2cc1468da177	946	#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /!< fSAMPLING=fDTS/4, N=8 /
<>	161:2cc1468da177	947	#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /!< fSAMPLING=fDTS/8, N=6 /
<>	161:2cc1468da177	948	#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /!< fSAMPLING=fDTS/8, N=8 /
<>	161:2cc1468da177	949	#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /!< fSAMPLING=fDTS/16, N=5 /
<>	161:2cc1468da177	950	#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /!< fSAMPLING=fDTS/16, N=6 /
<>	161:2cc1468da177	951	#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /!< fSAMPLING=fDTS/16, N=8 /
<>	161:2cc1468da177	952	#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /!< fSAMPLING=fDTS/32, N=5 /
<>	161:2cc1468da177	953	#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /!< fSAMPLING=fDTS/32, N=6 /
<>	161:2cc1468da177	954	#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /!< fSAMPLING=fDTS/32, N=8 /
<>	161:2cc1468da177	955	/**
<>	161:2cc1468da177	956	* @}
<>	161:2cc1468da177	957	*/
<>	161:2cc1468da177	958
<>	161:2cc1468da177	959	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
<>	161:2cc1468da177	960	* @{
<>	161:2cc1468da177	961	*/
<>	161:2cc1468da177	962	#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
<>	161:2cc1468da177	963	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
<>	161:2cc1468da177	964	/**
<>	161:2cc1468da177	965	* @}
<>	161:2cc1468da177	966	*/
<>	161:2cc1468da177	967
<>	161:2cc1468da177	968	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
<>	161:2cc1468da177	969	* @{
<>	161:2cc1468da177	970	*/
<>	161:2cc1468da177	971	#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
<>	161:2cc1468da177	972	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /!< fSAMPLING=fCK_INT, N=2 /
<>	161:2cc1468da177	973	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /!< fSAMPLING=fCK_INT, N=4 /
<>	161:2cc1468da177	974	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /!< fSAMPLING=fCK_INT, N=8 /
<>	161:2cc1468da177	975	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /!< fSAMPLING=fDTS/2, N=6 /
<>	161:2cc1468da177	976	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /!< fSAMPLING=fDTS/2, N=8 /
<>	161:2cc1468da177	977	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /!< fSAMPLING=fDTS/4, N=6 /
<>	161:2cc1468da177	978	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /!< fSAMPLING=fDTS/4, N=8 /
<>	161:2cc1468da177	979	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /!< fSAMPLING=fDTS/8, N=6 /
<>	161:2cc1468da177	980	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /!< fSAMPLING=fDTS/8, N=8 /
<>	161:2cc1468da177	981	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /!< fSAMPLING=fDTS/16, N=5 /
<>	161:2cc1468da177	982	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /!< fSAMPLING=fDTS/16, N=6 /
<>	161:2cc1468da177	983	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /!< fSAMPLING=fDTS/16, N=8 /
<>	161:2cc1468da177	984	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /!< fSAMPLING=fDTS/32, N=5 /
<>	161:2cc1468da177	985	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /!< fSAMPLING=fDTS/32, N=6 /
<>	161:2cc1468da177	986	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /!< fSAMPLING=fDTS/32, N=8 /
<>	161:2cc1468da177	987	/**
<>	161:2cc1468da177	988	* @}
<>	161:2cc1468da177	989	*/
<>	161:2cc1468da177	990
<>	161:2cc1468da177	991	/** @defgroup TIM_LL_EC_OSSI OSSI
<>	161:2cc1468da177	992	* @{
<>	161:2cc1468da177	993	*/
<>	161:2cc1468da177	994	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
<>	161:2cc1468da177	995	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
<>	161:2cc1468da177	996	/**
<>	161:2cc1468da177	997	* @}
<>	161:2cc1468da177	998	*/
<>	161:2cc1468da177	999
<>	161:2cc1468da177	1000	/** @defgroup TIM_LL_EC_OSSR OSSR
<>	161:2cc1468da177	1001	* @{
<>	161:2cc1468da177	1002	*/
<>	161:2cc1468da177	1003	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
<>	161:2cc1468da177	1004	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
<>	161:2cc1468da177	1005	/**
<>	161:2cc1468da177	1006	* @}
<>	161:2cc1468da177	1007	*/
<>	161:2cc1468da177	1008
<>	161:2cc1468da177	1009	#if defined(TIM_BREAK_INPUT_SUPPORT)
<>	161:2cc1468da177	1010	/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
<>	161:2cc1468da177	1011	* @{
<>	161:2cc1468da177	1012	*/
<>	161:2cc1468da177	1013	#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /!< TIMx_BKIN input /
<>	161:2cc1468da177	1014	#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /!< TIMx_BKIN2 input /
<>	161:2cc1468da177	1015	/**
<>	161:2cc1468da177	1016	* @}
<>	161:2cc1468da177	1017	*/
<>	161:2cc1468da177	1018
<>	161:2cc1468da177	1019	/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
<>	161:2cc1468da177	1020	* @{
<>	161:2cc1468da177	1021	*/
<>	161:2cc1468da177	1022	#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /!< BKIN input from AF controller /
<>	161:2cc1468da177	1023	#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BKE /!< internal signal: DFSDM1 break output /
<>	161:2cc1468da177	1024	/**
<>	161:2cc1468da177	1025	* @}
<>	161:2cc1468da177	1026	*/
<>	161:2cc1468da177	1027
<>	161:2cc1468da177	1028	/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
<>	161:2cc1468da177	1029	* @{
<>	161:2cc1468da177	1030	*/
<>	161:2cc1468da177	1031	#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /!< BRK BKIN input is active low /
<>	161:2cc1468da177	1032	#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /!< BRK BKIN input is active high /
<>	161:2cc1468da177	1033	/**
<>	161:2cc1468da177	1034	* @}
<>	161:2cc1468da177	1035	*/
<>	161:2cc1468da177	1036	#endif /* TIM_BREAK_INPUT_SUPPORT */
<>	161:2cc1468da177	1037
<>	161:2cc1468da177	1038	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
<>	161:2cc1468da177	1039	* @{
<>	161:2cc1468da177	1040	*/
<>	161:2cc1468da177	1041	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1042	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1043	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1044	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1045	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1046	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1047	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1048	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1049	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1050	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1051	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1052	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1053	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1054	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1055	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1056	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1057	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1058	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1059	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1060	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1061	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1062	#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1063	#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_AF1 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1064	#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_AF2 register is the DMA base address for DMA burst /
<>	161:2cc1468da177	1065
<>	161:2cc1468da177	1066	/**
<>	161:2cc1468da177	1067	* @}
<>	161:2cc1468da177	1068	*/
<>	161:2cc1468da177	1069
<>	161:2cc1468da177	1070	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
<>	161:2cc1468da177	1071	* @{
<>	161:2cc1468da177	1072	*/
<>	161:2cc1468da177	1073	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
<>	161:2cc1468da177	1074	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1075	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1076	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1077	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1078	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1079	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1080	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1081	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1082	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1083	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1084	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1085	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1086	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1087	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1088	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1089	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1090	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
<>	161:2cc1468da177	1091	/**
<>	161:2cc1468da177	1092	* @}
<>	161:2cc1468da177	1093	*/
<>	161:2cc1468da177	1094
<>	161:2cc1468da177	1095
<>	161:2cc1468da177	1096	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
<>	161:2cc1468da177	1097	* @{
<>	161:2cc1468da177	1098	*/
<>	161:2cc1468da177	1099	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /!< TIM2_ITR1 is connected to TIM8_TRGO /
<>	161:2cc1468da177	1100	#define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM2_OR_ITR1_RMP_0 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to ETH_PTP /
<>	161:2cc1468da177	1101	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR_ITR1_RMP_1 \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
<>	161:2cc1468da177	1102	#define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM2_OR_ITR1_RMP \| TIM2_OR_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_HS SOF /
<>	161:2cc1468da177	1103	/**
<>	161:2cc1468da177	1104	* @}
<>	161:2cc1468da177	1105	*/
<>	161:2cc1468da177	1106
<>	161:2cc1468da177	1107	/** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
<>	161:2cc1468da177	1108	* @{
<>	161:2cc1468da177	1109	*/
<>	161:2cc1468da177	1110	#define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /!< TIM5 channel 4 is connected to GPIO /
<>	161:2cc1468da177	1111	#define LL_TIM_TIM5_TI4_RMP_LSI (TIM5_OR_TI4_RMP_0 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSI internal clock /
<>	161:2cc1468da177	1112	#define LL_TIM_TIM5_TI4_RMP_LSE (TIM5_OR_TI4_RMP_1 \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to LSE /
<>	161:2cc1468da177	1113	#define LL_TIM_TIM5_TI4_RMP_RTC (TIM5_OR_TI4_RMP \| TIM5_OR_RMP_MASK) /!< TIM5 channel 4 is connected to RTC wakeup interrupt /
<>	161:2cc1468da177	1114	/**
<>	161:2cc1468da177	1115	* @}
<>	161:2cc1468da177	1116	*/
<>	161:2cc1468da177	1117
<>	161:2cc1468da177	1118	/** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
<>	161:2cc1468da177	1119	* @{
<>	161:2cc1468da177	1120	*/
<>	161:2cc1468da177	1121	#define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /!< TIM11 channel 1 is connected to GPIO /
<>	161:2cc1468da177	1122	#define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM11_OR_TI1_RMP_0 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to SPDIFRX /
<>	161:2cc1468da177	1123	#define LL_TIM_TIM11_TI1_RMP_HSE (TIM11_OR_TI1_RMP_1 \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to HSE /
<>	161:2cc1468da177	1124	#define LL_TIM_TIM11_TI1_RMP_MCO1 (TIM11_OR_TI1_RMP \| TIM11_OR_RMP_MASK) /!< TIM11 channel 1 is connected to MCO1 /
<>	161:2cc1468da177	1125	/**
<>	161:2cc1468da177	1126	* @}
<>	161:2cc1468da177	1127	*/
<>	161:2cc1468da177	1128
<>	161:2cc1468da177	1129	/**
<>	161:2cc1468da177	1130	* @}
<>	161:2cc1468da177	1131	*/
<>	161:2cc1468da177	1132
<>	161:2cc1468da177	1133
<>	161:2cc1468da177	1134	/**
<>	161:2cc1468da177	1135	* @}
<>	161:2cc1468da177	1136	*/
<>	161:2cc1468da177	1137
<>	161:2cc1468da177	1138	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	1139	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
<>	161:2cc1468da177	1140	* @{
<>	161:2cc1468da177	1141	*/
<>	161:2cc1468da177	1142
<>	161:2cc1468da177	1143	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	161:2cc1468da177	1144	* @{
<>	161:2cc1468da177	1145	*/
<>	161:2cc1468da177	1146	/**
<>	161:2cc1468da177	1147	* @brief Write a value in TIM register.
<>	161:2cc1468da177	1148	* @param __INSTANCE__ TIM Instance
<>	161:2cc1468da177	1149	* @param __REG__ Register to be written
<>	161:2cc1468da177	1150	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	1151	* @retval None
<>	161:2cc1468da177	1152	*/
<>	161:2cc1468da177	1153	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	161:2cc1468da177	1154
<>	161:2cc1468da177	1155	/**
<>	161:2cc1468da177	1156	* @brief Read a value in TIM register.
<>	161:2cc1468da177	1157	* @param __INSTANCE__ TIM Instance
<>	161:2cc1468da177	1158	* @param __REG__ Register to be read
<>	161:2cc1468da177	1159	* @retval Register value
<>	161:2cc1468da177	1160	*/
<>	161:2cc1468da177	1161	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	161:2cc1468da177	1162	/**
<>	161:2cc1468da177	1163	* @}
<>	161:2cc1468da177	1164	*/
<>	161:2cc1468da177	1165
<>	161:2cc1468da177	1166	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
<>	161:2cc1468da177	1167	* @{
<>	161:2cc1468da177	1168	*/
<>	161:2cc1468da177	1169	/**
<>	161:2cc1468da177	1170	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
<>	161:2cc1468da177	1171	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
<>	161:2cc1468da177	1172	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
<>	161:2cc1468da177	1173	* to TIMx_CNT register bit 31)
<>	161:2cc1468da177	1174	* @param __CNT__ Counter value
<>	161:2cc1468da177	1175	* @retval UIF status bit
<>	161:2cc1468da177	1176	*/
<>	161:2cc1468da177	1177	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
<>	161:2cc1468da177	1178	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
<>	161:2cc1468da177	1179
<>	161:2cc1468da177	1180	/**
<>	161:2cc1468da177	1181	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
<>	161:2cc1468da177	1182	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
<>	161:2cc1468da177	1183	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	161:2cc1468da177	1184	* @param __CKD__ This parameter can be one of the following values:
<>	161:2cc1468da177	1185	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	161:2cc1468da177	1186	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	161:2cc1468da177	1187	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	161:2cc1468da177	1188	* @param __DT__ deadtime duration (in ns)
<>	161:2cc1468da177	1189	* @retval DTG[0:7]
<>	161:2cc1468da177	1190	*/
<>	161:2cc1468da177	1191	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
<>	161:2cc1468da177	1192	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
<>	161:2cc1468da177	1193	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
<>	161:2cc1468da177	1194	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
<>	161:2cc1468da177	1195	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
<>	161:2cc1468da177	1196	0U)
<>	161:2cc1468da177	1197
<>	161:2cc1468da177	1198	/**
<>	161:2cc1468da177	1199	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
<>	161:2cc1468da177	1200	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
<>	161:2cc1468da177	1201	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	161:2cc1468da177	1202	* @param __CNTCLK__ counter clock frequency (in Hz)
<>	161:2cc1468da177	1203	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	1204	*/
<>	161:2cc1468da177	1205	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
<>	161:2cc1468da177	1206	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
<>	161:2cc1468da177	1207
<>	161:2cc1468da177	1208	/**
<>	161:2cc1468da177	1209	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
<>	161:2cc1468da177	1210	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
<>	161:2cc1468da177	1211	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	161:2cc1468da177	1212	* @param __PSC__ prescaler
<>	161:2cc1468da177	1213	* @param __FREQ__ output signal frequency (in Hz)
<>	161:2cc1468da177	1214	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	1215	*/
<>	161:2cc1468da177	1216	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
<>	161:2cc1468da177	1217	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
<>	161:2cc1468da177	1218
<>	161:2cc1468da177	1219	/**
<>	161:2cc1468da177	1220	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
<>	161:2cc1468da177	1221	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
<>	161:2cc1468da177	1222	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	161:2cc1468da177	1223	* @param __PSC__ prescaler
<>	161:2cc1468da177	1224	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	161:2cc1468da177	1225	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	1226	*/
<>	161:2cc1468da177	1227	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
<>	161:2cc1468da177	1228	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
<>	161:2cc1468da177	1229	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
<>	161:2cc1468da177	1230
<>	161:2cc1468da177	1231	/**
<>	161:2cc1468da177	1232	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
<>	161:2cc1468da177	1233	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
<>	161:2cc1468da177	1234	* @param __TIMCLK__ timer input clock frequency (in Hz)
<>	161:2cc1468da177	1235	* @param __PSC__ prescaler
<>	161:2cc1468da177	1236	* @param __DELAY__ timer output compare active/inactive delay (in us)
<>	161:2cc1468da177	1237	* @param __PULSE__ pulse duration (in us)
<>	161:2cc1468da177	1238	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	1239	*/
<>	161:2cc1468da177	1240	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
<>	161:2cc1468da177	1241	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
<>	161:2cc1468da177	1242	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
<>	161:2cc1468da177	1243
<>	161:2cc1468da177	1244	/**
<>	161:2cc1468da177	1245	* @brief HELPER macro retrieving the ratio of the input capture prescaler
<>	161:2cc1468da177	1246	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
<>	161:2cc1468da177	1247	* @param __ICPSC__ This parameter can be one of the following values:
<>	161:2cc1468da177	1248	* @arg @ref LL_TIM_ICPSC_DIV1
<>	161:2cc1468da177	1249	* @arg @ref LL_TIM_ICPSC_DIV2
<>	161:2cc1468da177	1250	* @arg @ref LL_TIM_ICPSC_DIV4
<>	161:2cc1468da177	1251	* @arg @ref LL_TIM_ICPSC_DIV8
<>	161:2cc1468da177	1252	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
<>	161:2cc1468da177	1253	*/
<>	161:2cc1468da177	1254	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
<>	161:2cc1468da177	1255	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
<>	161:2cc1468da177	1256
<>	161:2cc1468da177	1257
<>	161:2cc1468da177	1258	/**
<>	161:2cc1468da177	1259	* @}
<>	161:2cc1468da177	1260	*/
<>	161:2cc1468da177	1261
<>	161:2cc1468da177	1262
<>	161:2cc1468da177	1263	/**
<>	161:2cc1468da177	1264	* @}
<>	161:2cc1468da177	1265	*/
<>	161:2cc1468da177	1266
<>	161:2cc1468da177	1267	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	1268	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
<>	161:2cc1468da177	1269	* @{
<>	161:2cc1468da177	1270	*/
<>	161:2cc1468da177	1271
<>	161:2cc1468da177	1272	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
<>	161:2cc1468da177	1273	* @{
<>	161:2cc1468da177	1274	*/
<>	161:2cc1468da177	1275	/**
<>	161:2cc1468da177	1276	* @brief Enable timer counter.
<>	161:2cc1468da177	1277	* @rmtoll CR1 CEN LL_TIM_EnableCounter
<>	161:2cc1468da177	1278	* @param TIMx Timer instance
<>	161:2cc1468da177	1279	* @retval None
<>	161:2cc1468da177	1280	*/
<>	161:2cc1468da177	1281	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1282	{
<>	161:2cc1468da177	1283	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	161:2cc1468da177	1284	}
<>	161:2cc1468da177	1285
<>	161:2cc1468da177	1286	/**
<>	161:2cc1468da177	1287	* @brief Disable timer counter.
<>	161:2cc1468da177	1288	* @rmtoll CR1 CEN LL_TIM_DisableCounter
<>	161:2cc1468da177	1289	* @param TIMx Timer instance
<>	161:2cc1468da177	1290	* @retval None
<>	161:2cc1468da177	1291	*/
<>	161:2cc1468da177	1292	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1293	{
<>	161:2cc1468da177	1294	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
<>	161:2cc1468da177	1295	}
<>	161:2cc1468da177	1296
<>	161:2cc1468da177	1297	/**
<>	161:2cc1468da177	1298	* @brief Indicates whether the timer counter is enabled.
<>	161:2cc1468da177	1299	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
<>	161:2cc1468da177	1300	* @param TIMx Timer instance
<>	161:2cc1468da177	1301	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1302	*/
<>	161:2cc1468da177	1303	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1304	{
<>	161:2cc1468da177	1305	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
<>	161:2cc1468da177	1306	}
<>	161:2cc1468da177	1307
<>	161:2cc1468da177	1308	/**
<>	161:2cc1468da177	1309	* @brief Enable update event generation.
<>	161:2cc1468da177	1310	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
<>	161:2cc1468da177	1311	* @param TIMx Timer instance
<>	161:2cc1468da177	1312	* @retval None
<>	161:2cc1468da177	1313	*/
<>	161:2cc1468da177	1314	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1315	{
<>	161:2cc1468da177	1316	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	161:2cc1468da177	1317	}
<>	161:2cc1468da177	1318
<>	161:2cc1468da177	1319	/**
<>	161:2cc1468da177	1320	* @brief Disable update event generation.
<>	161:2cc1468da177	1321	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
<>	161:2cc1468da177	1322	* @param TIMx Timer instance
<>	161:2cc1468da177	1323	* @retval None
<>	161:2cc1468da177	1324	*/
<>	161:2cc1468da177	1325	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1326	{
<>	161:2cc1468da177	1327	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
<>	161:2cc1468da177	1328	}
<>	161:2cc1468da177	1329
<>	161:2cc1468da177	1330	/**
<>	161:2cc1468da177	1331	* @brief Indicates whether update event generation is enabled.
<>	161:2cc1468da177	1332	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
<>	161:2cc1468da177	1333	* @param TIMx Timer instance
<>	161:2cc1468da177	1334	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1335	*/
<>	161:2cc1468da177	1336	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1337	{
<>	161:2cc1468da177	1338	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
<>	161:2cc1468da177	1339	}
<>	161:2cc1468da177	1340
<>	161:2cc1468da177	1341	/**
<>	161:2cc1468da177	1342	* @brief Set update event source
<>	161:2cc1468da177	1343	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
<>	161:2cc1468da177	1344	* generate an update interrupt or DMA request if enabled:
<>	161:2cc1468da177	1345	* - Counter overflow/underflow
<>	161:2cc1468da177	1346	* - Setting the UG bit
<>	161:2cc1468da177	1347	* - Update generation through the slave mode controller
<>	161:2cc1468da177	1348	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
<>	161:2cc1468da177	1349	* overflow/underflow generates an update interrupt or DMA request if enabled.
<>	161:2cc1468da177	1350	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
<>	161:2cc1468da177	1351	* @param TIMx Timer instance
<>	161:2cc1468da177	1352	* @param UpdateSource This parameter can be one of the following values:
<>	161:2cc1468da177	1353	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	161:2cc1468da177	1354	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	161:2cc1468da177	1355	* @retval None
<>	161:2cc1468da177	1356	*/
<>	161:2cc1468da177	1357	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
<>	161:2cc1468da177	1358	{
<>	161:2cc1468da177	1359	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
<>	161:2cc1468da177	1360	}
<>	161:2cc1468da177	1361
<>	161:2cc1468da177	1362	/**
<>	161:2cc1468da177	1363	* @brief Get actual event update source
<>	161:2cc1468da177	1364	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
<>	161:2cc1468da177	1365	* @param TIMx Timer instance
<>	161:2cc1468da177	1366	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1367	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
<>	161:2cc1468da177	1368	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
<>	161:2cc1468da177	1369	*/
<>	161:2cc1468da177	1370	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1371	{
<>	161:2cc1468da177	1372	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
<>	161:2cc1468da177	1373	}
<>	161:2cc1468da177	1374
<>	161:2cc1468da177	1375	/**
<>	161:2cc1468da177	1376	* @brief Set one pulse mode (one shot v.s. repetitive).
<>	161:2cc1468da177	1377	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
<>	161:2cc1468da177	1378	* @param TIMx Timer instance
<>	161:2cc1468da177	1379	* @param OnePulseMode This parameter can be one of the following values:
<>	161:2cc1468da177	1380	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	161:2cc1468da177	1381	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	161:2cc1468da177	1382	* @retval None
<>	161:2cc1468da177	1383	*/
<>	161:2cc1468da177	1384	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
<>	161:2cc1468da177	1385	{
<>	161:2cc1468da177	1386	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
<>	161:2cc1468da177	1387	}
<>	161:2cc1468da177	1388
<>	161:2cc1468da177	1389	/**
<>	161:2cc1468da177	1390	* @brief Get actual one pulse mode.
<>	161:2cc1468da177	1391	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
<>	161:2cc1468da177	1392	* @param TIMx Timer instance
<>	161:2cc1468da177	1393	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1394	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
<>	161:2cc1468da177	1395	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
<>	161:2cc1468da177	1396	*/
<>	161:2cc1468da177	1397	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1398	{
<>	161:2cc1468da177	1399	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
<>	161:2cc1468da177	1400	}
<>	161:2cc1468da177	1401
<>	161:2cc1468da177	1402	/**
<>	161:2cc1468da177	1403	* @brief Set the timer counter counting mode.
<>	161:2cc1468da177	1404	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	161:2cc1468da177	1405	* check whether or not the counter mode selection feature is supported
<>	161:2cc1468da177	1406	* by a timer instance.
<>	161:2cc1468da177	1407	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
<>	161:2cc1468da177	1408	* CR1 CMS LL_TIM_SetCounterMode
<>	161:2cc1468da177	1409	* @param TIMx Timer instance
<>	161:2cc1468da177	1410	* @param CounterMode This parameter can be one of the following values:
<>	161:2cc1468da177	1411	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	161:2cc1468da177	1412	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	161:2cc1468da177	1413	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	161:2cc1468da177	1414	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	161:2cc1468da177	1415	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	161:2cc1468da177	1416	* @retval None
<>	161:2cc1468da177	1417	*/
<>	161:2cc1468da177	1418	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
<>	161:2cc1468da177	1419	{
<>	161:2cc1468da177	1420	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
<>	161:2cc1468da177	1421	}
<>	161:2cc1468da177	1422
<>	161:2cc1468da177	1423	/**
<>	161:2cc1468da177	1424	* @brief Get actual counter mode.
<>	161:2cc1468da177	1425	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
<>	161:2cc1468da177	1426	* check whether or not the counter mode selection feature is supported
<>	161:2cc1468da177	1427	* by a timer instance.
<>	161:2cc1468da177	1428	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
<>	161:2cc1468da177	1429	* CR1 CMS LL_TIM_GetCounterMode
<>	161:2cc1468da177	1430	* @param TIMx Timer instance
<>	161:2cc1468da177	1431	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1432	* @arg @ref LL_TIM_COUNTERMODE_UP
<>	161:2cc1468da177	1433	* @arg @ref LL_TIM_COUNTERMODE_DOWN
<>	161:2cc1468da177	1434	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
<>	161:2cc1468da177	1435	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
<>	161:2cc1468da177	1436	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
<>	161:2cc1468da177	1437	*/
<>	161:2cc1468da177	1438	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1439	{
<>	161:2cc1468da177	1440	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
<>	161:2cc1468da177	1441	}
<>	161:2cc1468da177	1442
<>	161:2cc1468da177	1443	/**
<>	161:2cc1468da177	1444	* @brief Enable auto-reload (ARR) preload.
<>	161:2cc1468da177	1445	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
<>	161:2cc1468da177	1446	* @param TIMx Timer instance
<>	161:2cc1468da177	1447	* @retval None
<>	161:2cc1468da177	1448	*/
<>	161:2cc1468da177	1449	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1450	{
<>	161:2cc1468da177	1451	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	161:2cc1468da177	1452	}
<>	161:2cc1468da177	1453
<>	161:2cc1468da177	1454	/**
<>	161:2cc1468da177	1455	* @brief Disable auto-reload (ARR) preload.
<>	161:2cc1468da177	1456	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
<>	161:2cc1468da177	1457	* @param TIMx Timer instance
<>	161:2cc1468da177	1458	* @retval None
<>	161:2cc1468da177	1459	*/
<>	161:2cc1468da177	1460	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1461	{
<>	161:2cc1468da177	1462	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
<>	161:2cc1468da177	1463	}
<>	161:2cc1468da177	1464
<>	161:2cc1468da177	1465	/**
<>	161:2cc1468da177	1466	* @brief Indicates whether auto-reload (ARR) preload is enabled.
<>	161:2cc1468da177	1467	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
<>	161:2cc1468da177	1468	* @param TIMx Timer instance
<>	161:2cc1468da177	1469	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1470	*/
<>	161:2cc1468da177	1471	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1472	{
<>	161:2cc1468da177	1473	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
<>	161:2cc1468da177	1474	}
<>	161:2cc1468da177	1475
<>	161:2cc1468da177	1476	/**
<>	161:2cc1468da177	1477	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	161:2cc1468da177	1478	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1479	* whether or not the clock division feature is supported by the timer
<>	161:2cc1468da177	1480	* instance.
<>	161:2cc1468da177	1481	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
<>	161:2cc1468da177	1482	* @param TIMx Timer instance
<>	161:2cc1468da177	1483	* @param ClockDivision This parameter can be one of the following values:
<>	161:2cc1468da177	1484	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	161:2cc1468da177	1485	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	161:2cc1468da177	1486	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	161:2cc1468da177	1487	* @retval None
<>	161:2cc1468da177	1488	*/
<>	161:2cc1468da177	1489	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
<>	161:2cc1468da177	1490	{
<>	161:2cc1468da177	1491	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
<>	161:2cc1468da177	1492	}
<>	161:2cc1468da177	1493
<>	161:2cc1468da177	1494	/**
<>	161:2cc1468da177	1495	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
<>	161:2cc1468da177	1496	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1497	* whether or not the clock division feature is supported by the timer
<>	161:2cc1468da177	1498	* instance.
<>	161:2cc1468da177	1499	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
<>	161:2cc1468da177	1500	* @param TIMx Timer instance
<>	161:2cc1468da177	1501	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1502	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
<>	161:2cc1468da177	1503	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
<>	161:2cc1468da177	1504	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
<>	161:2cc1468da177	1505	*/
<>	161:2cc1468da177	1506	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1507	{
<>	161:2cc1468da177	1508	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
<>	161:2cc1468da177	1509	}
<>	161:2cc1468da177	1510
<>	161:2cc1468da177	1511	/**
<>	161:2cc1468da177	1512	* @brief Set the counter value.
<>	161:2cc1468da177	1513	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1514	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	1515	* @rmtoll CNT CNT LL_TIM_SetCounter
<>	161:2cc1468da177	1516	* @param TIMx Timer instance
<>	161:2cc1468da177	1517	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	161:2cc1468da177	1518	* @retval None
<>	161:2cc1468da177	1519	*/
<>	161:2cc1468da177	1520	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
<>	161:2cc1468da177	1521	{
<>	161:2cc1468da177	1522	WRITE_REG(TIMx->CNT, Counter);
<>	161:2cc1468da177	1523	}
<>	161:2cc1468da177	1524
<>	161:2cc1468da177	1525	/**
<>	161:2cc1468da177	1526	* @brief Get the counter value.
<>	161:2cc1468da177	1527	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1528	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	1529	* @rmtoll CNT CNT LL_TIM_GetCounter
<>	161:2cc1468da177	1530	* @param TIMx Timer instance
<>	161:2cc1468da177	1531	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
<>	161:2cc1468da177	1532	*/
<>	161:2cc1468da177	1533	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1534	{
<>	161:2cc1468da177	1535	return (uint32_t)(READ_REG(TIMx->CNT));
<>	161:2cc1468da177	1536	}
<>	161:2cc1468da177	1537
<>	161:2cc1468da177	1538	/**
<>	161:2cc1468da177	1539	* @brief Get the current direction of the counter
<>	161:2cc1468da177	1540	* @rmtoll CR1 DIR LL_TIM_GetDirection
<>	161:2cc1468da177	1541	* @param TIMx Timer instance
<>	161:2cc1468da177	1542	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1543	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
<>	161:2cc1468da177	1544	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
<>	161:2cc1468da177	1545	*/
<>	161:2cc1468da177	1546	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1547	{
<>	161:2cc1468da177	1548	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
<>	161:2cc1468da177	1549	}
<>	161:2cc1468da177	1550
<>	161:2cc1468da177	1551	/**
<>	161:2cc1468da177	1552	* @brief Set the prescaler value.
<>	161:2cc1468da177	1553	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
<>	161:2cc1468da177	1554	* @note The prescaler can be changed on the fly as this control register is buffered. The new
<>	161:2cc1468da177	1555	* prescaler ratio is taken into account at the next update event.
<>	161:2cc1468da177	1556	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
<>	161:2cc1468da177	1557	* @rmtoll PSC PSC LL_TIM_SetPrescaler
<>	161:2cc1468da177	1558	* @param TIMx Timer instance
<>	161:2cc1468da177	1559	* @param Prescaler between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	1560	* @retval None
<>	161:2cc1468da177	1561	*/
<>	161:2cc1468da177	1562	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
<>	161:2cc1468da177	1563	{
<>	161:2cc1468da177	1564	WRITE_REG(TIMx->PSC, Prescaler);
<>	161:2cc1468da177	1565	}
<>	161:2cc1468da177	1566
<>	161:2cc1468da177	1567	/**
<>	161:2cc1468da177	1568	* @brief Get the prescaler value.
<>	161:2cc1468da177	1569	* @rmtoll PSC PSC LL_TIM_GetPrescaler
<>	161:2cc1468da177	1570	* @param TIMx Timer instance
<>	161:2cc1468da177	1571	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	1572	*/
<>	161:2cc1468da177	1573	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1574	{
<>	161:2cc1468da177	1575	return (uint32_t)(READ_REG(TIMx->PSC));
<>	161:2cc1468da177	1576	}
<>	161:2cc1468da177	1577
<>	161:2cc1468da177	1578	/**
<>	161:2cc1468da177	1579	* @brief Set the auto-reload value.
<>	161:2cc1468da177	1580	* @note The counter is blocked while the auto-reload value is null.
<>	161:2cc1468da177	1581	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1582	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	1583	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
<>	161:2cc1468da177	1584	* @rmtoll ARR ARR LL_TIM_SetAutoReload
<>	161:2cc1468da177	1585	* @param TIMx Timer instance
<>	161:2cc1468da177	1586	* @param AutoReload between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	1587	* @retval None
<>	161:2cc1468da177	1588	*/
<>	161:2cc1468da177	1589	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
<>	161:2cc1468da177	1590	{
<>	161:2cc1468da177	1591	WRITE_REG(TIMx->ARR, AutoReload);
<>	161:2cc1468da177	1592	}
<>	161:2cc1468da177	1593
<>	161:2cc1468da177	1594	/**
<>	161:2cc1468da177	1595	* @brief Get the auto-reload value.
<>	161:2cc1468da177	1596	* @rmtoll ARR ARR LL_TIM_GetAutoReload
<>	161:2cc1468da177	1597	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1598	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	1599	* @param TIMx Timer instance
<>	161:2cc1468da177	1600	* @retval Auto-reload value
<>	161:2cc1468da177	1601	*/
<>	161:2cc1468da177	1602	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1603	{
<>	161:2cc1468da177	1604	return (uint32_t)(READ_REG(TIMx->ARR));
<>	161:2cc1468da177	1605	}
<>	161:2cc1468da177	1606
<>	161:2cc1468da177	1607	/**
<>	161:2cc1468da177	1608	* @brief Set the repetition counter value.
<>	161:2cc1468da177	1609	* @note For advanced timer instances RepetitionCounter can be up to 65535.
<>	161:2cc1468da177	1610	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1611	* whether or not a timer instance supports a repetition counter.
<>	161:2cc1468da177	1612	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
<>	161:2cc1468da177	1613	* @param TIMx Timer instance
<>	161:2cc1468da177	1614	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
<>	161:2cc1468da177	1615	* @retval None
<>	161:2cc1468da177	1616	*/
<>	161:2cc1468da177	1617	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
<>	161:2cc1468da177	1618	{
<>	161:2cc1468da177	1619	WRITE_REG(TIMx->RCR, RepetitionCounter);
<>	161:2cc1468da177	1620	}
<>	161:2cc1468da177	1621
<>	161:2cc1468da177	1622	/**
<>	161:2cc1468da177	1623	* @brief Get the repetition counter value.
<>	161:2cc1468da177	1624	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1625	* whether or not a timer instance supports a repetition counter.
<>	161:2cc1468da177	1626	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
<>	161:2cc1468da177	1627	* @param TIMx Timer instance
<>	161:2cc1468da177	1628	* @retval Repetition counter value
<>	161:2cc1468da177	1629	*/
<>	161:2cc1468da177	1630	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1631	{
<>	161:2cc1468da177	1632	return (uint32_t)(READ_REG(TIMx->RCR));
<>	161:2cc1468da177	1633	}
<>	161:2cc1468da177	1634
<>	161:2cc1468da177	1635	/**
<>	161:2cc1468da177	1636	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
<>	161:2cc1468da177	1637	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
<>	161:2cc1468da177	1638	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
<>	161:2cc1468da177	1639	* @param TIMx Timer instance
<>	161:2cc1468da177	1640	* @retval None
<>	161:2cc1468da177	1641	*/
<>	161:2cc1468da177	1642	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1643	{
<>	161:2cc1468da177	1644	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
<>	161:2cc1468da177	1645	}
<>	161:2cc1468da177	1646
<>	161:2cc1468da177	1647	/**
<>	161:2cc1468da177	1648	* @brief Disable update interrupt flag (UIF) remapping.
<>	161:2cc1468da177	1649	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
<>	161:2cc1468da177	1650	* @param TIMx Timer instance
<>	161:2cc1468da177	1651	* @retval None
<>	161:2cc1468da177	1652	*/
<>	161:2cc1468da177	1653	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1654	{
<>	161:2cc1468da177	1655	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
<>	161:2cc1468da177	1656	}
<>	161:2cc1468da177	1657
<>	161:2cc1468da177	1658	/**
<>	161:2cc1468da177	1659	* @}
<>	161:2cc1468da177	1660	*/
<>	161:2cc1468da177	1661
<>	161:2cc1468da177	1662	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
<>	161:2cc1468da177	1663	* @{
<>	161:2cc1468da177	1664	*/
<>	161:2cc1468da177	1665	/**
<>	161:2cc1468da177	1666	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	161:2cc1468da177	1667	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
<>	161:2cc1468da177	1668	* they are updated only when a commutation event (COM) occurs.
<>	161:2cc1468da177	1669	* @note Only on channels that have a complementary output.
<>	161:2cc1468da177	1670	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1671	* whether or not a timer instance is able to generate a commutation event.
<>	161:2cc1468da177	1672	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
<>	161:2cc1468da177	1673	* @param TIMx Timer instance
<>	161:2cc1468da177	1674	* @retval None
<>	161:2cc1468da177	1675	*/
<>	161:2cc1468da177	1676	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1677	{
<>	161:2cc1468da177	1678	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	161:2cc1468da177	1679	}
<>	161:2cc1468da177	1680
<>	161:2cc1468da177	1681	/**
<>	161:2cc1468da177	1682	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
<>	161:2cc1468da177	1683	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1684	* whether or not a timer instance is able to generate a commutation event.
<>	161:2cc1468da177	1685	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
<>	161:2cc1468da177	1686	* @param TIMx Timer instance
<>	161:2cc1468da177	1687	* @retval None
<>	161:2cc1468da177	1688	*/
<>	161:2cc1468da177	1689	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1690	{
<>	161:2cc1468da177	1691	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
<>	161:2cc1468da177	1692	}
<>	161:2cc1468da177	1693
<>	161:2cc1468da177	1694	/**
<>	161:2cc1468da177	1695	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
<>	161:2cc1468da177	1696	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	1697	* whether or not a timer instance is able to generate a commutation event.
<>	161:2cc1468da177	1698	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
<>	161:2cc1468da177	1699	* @param TIMx Timer instance
<>	161:2cc1468da177	1700	* @param CCUpdateSource This parameter can be one of the following values:
<>	161:2cc1468da177	1701	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
<>	161:2cc1468da177	1702	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
<>	161:2cc1468da177	1703	* @retval None
<>	161:2cc1468da177	1704	*/
<>	161:2cc1468da177	1705	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
<>	161:2cc1468da177	1706	{
<>	161:2cc1468da177	1707	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
<>	161:2cc1468da177	1708	}
<>	161:2cc1468da177	1709
<>	161:2cc1468da177	1710	/**
<>	161:2cc1468da177	1711	* @brief Set the trigger of the capture/compare DMA request.
<>	161:2cc1468da177	1712	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
<>	161:2cc1468da177	1713	* @param TIMx Timer instance
<>	161:2cc1468da177	1714	* @param DMAReqTrigger This parameter can be one of the following values:
<>	161:2cc1468da177	1715	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	161:2cc1468da177	1716	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	161:2cc1468da177	1717	* @retval None
<>	161:2cc1468da177	1718	*/
<>	161:2cc1468da177	1719	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
<>	161:2cc1468da177	1720	{
<>	161:2cc1468da177	1721	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
<>	161:2cc1468da177	1722	}
<>	161:2cc1468da177	1723
<>	161:2cc1468da177	1724	/**
<>	161:2cc1468da177	1725	* @brief Get actual trigger of the capture/compare DMA request.
<>	161:2cc1468da177	1726	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
<>	161:2cc1468da177	1727	* @param TIMx Timer instance
<>	161:2cc1468da177	1728	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1729	* @arg @ref LL_TIM_CCDMAREQUEST_CC
<>	161:2cc1468da177	1730	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
<>	161:2cc1468da177	1731	*/
<>	161:2cc1468da177	1732	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	1733	{
<>	161:2cc1468da177	1734	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
<>	161:2cc1468da177	1735	}
<>	161:2cc1468da177	1736
<>	161:2cc1468da177	1737	/**
<>	161:2cc1468da177	1738	* @brief Set the lock level to freeze the
<>	161:2cc1468da177	1739	* configuration of several capture/compare parameters.
<>	161:2cc1468da177	1740	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	1741	* the lock mechanism is supported by a timer instance.
<>	161:2cc1468da177	1742	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
<>	161:2cc1468da177	1743	* @param TIMx Timer instance
<>	161:2cc1468da177	1744	* @param LockLevel This parameter can be one of the following values:
<>	161:2cc1468da177	1745	* @arg @ref LL_TIM_LOCKLEVEL_OFF
<>	161:2cc1468da177	1746	* @arg @ref LL_TIM_LOCKLEVEL_1
<>	161:2cc1468da177	1747	* @arg @ref LL_TIM_LOCKLEVEL_2
<>	161:2cc1468da177	1748	* @arg @ref LL_TIM_LOCKLEVEL_3
<>	161:2cc1468da177	1749	* @retval None
<>	161:2cc1468da177	1750	*/
<>	161:2cc1468da177	1751	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
<>	161:2cc1468da177	1752	{
<>	161:2cc1468da177	1753	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
<>	161:2cc1468da177	1754	}
<>	161:2cc1468da177	1755
<>	161:2cc1468da177	1756	/**
<>	161:2cc1468da177	1757	* @brief Enable capture/compare channels.
<>	161:2cc1468da177	1758	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1759	* CCER CC1NE LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1760	* CCER CC2E LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1761	* CCER CC2NE LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1762	* CCER CC3E LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1763	* CCER CC3NE LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1764	* CCER CC4E LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1765	* CCER CC5E LL_TIM_CC_EnableChannel\n
<>	161:2cc1468da177	1766	* CCER CC6E LL_TIM_CC_EnableChannel
<>	161:2cc1468da177	1767	* @param TIMx Timer instance
<>	161:2cc1468da177	1768	* @param Channels This parameter can be a combination of the following values:
<>	161:2cc1468da177	1769	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	1770	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	1771	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	1772	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	1773	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	1774	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	1775	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	1776	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	1777	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	1778	* @retval None
<>	161:2cc1468da177	1779	*/
<>	161:2cc1468da177	1780	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	161:2cc1468da177	1781	{
<>	161:2cc1468da177	1782	SET_BIT(TIMx->CCER, Channels);
<>	161:2cc1468da177	1783	}
<>	161:2cc1468da177	1784
<>	161:2cc1468da177	1785	/**
<>	161:2cc1468da177	1786	* @brief Disable capture/compare channels.
<>	161:2cc1468da177	1787	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1788	* CCER CC1NE LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1789	* CCER CC2E LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1790	* CCER CC2NE LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1791	* CCER CC3E LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1792	* CCER CC3NE LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1793	* CCER CC4E LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1794	* CCER CC5E LL_TIM_CC_DisableChannel\n
<>	161:2cc1468da177	1795	* CCER CC6E LL_TIM_CC_DisableChannel
<>	161:2cc1468da177	1796	* @param TIMx Timer instance
<>	161:2cc1468da177	1797	* @param Channels This parameter can be a combination of the following values:
<>	161:2cc1468da177	1798	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	1799	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	1800	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	1801	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	1802	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	1803	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	1804	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	1805	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	1806	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	1807	* @retval None
<>	161:2cc1468da177	1808	*/
<>	161:2cc1468da177	1809	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	161:2cc1468da177	1810	{
<>	161:2cc1468da177	1811	CLEAR_BIT(TIMx->CCER, Channels);
<>	161:2cc1468da177	1812	}
<>	161:2cc1468da177	1813
<>	161:2cc1468da177	1814	/**
<>	161:2cc1468da177	1815	* @brief Indicate whether channel(s) is(are) enabled.
<>	161:2cc1468da177	1816	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1817	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1818	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1819	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1820	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1821	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1822	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1823	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
<>	161:2cc1468da177	1824	* CCER CC6E LL_TIM_CC_IsEnabledChannel
<>	161:2cc1468da177	1825	* @param TIMx Timer instance
<>	161:2cc1468da177	1826	* @param Channels This parameter can be a combination of the following values:
<>	161:2cc1468da177	1827	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	1828	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	1829	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	1830	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	1831	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	1832	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	1833	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	1834	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	1835	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	1836	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1837	*/
<>	161:2cc1468da177	1838	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
<>	161:2cc1468da177	1839	{
<>	161:2cc1468da177	1840	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
<>	161:2cc1468da177	1841	}
<>	161:2cc1468da177	1842
<>	161:2cc1468da177	1843	/**
<>	161:2cc1468da177	1844	* @}
<>	161:2cc1468da177	1845	*/
<>	161:2cc1468da177	1846
<>	161:2cc1468da177	1847	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
<>	161:2cc1468da177	1848	* @{
<>	161:2cc1468da177	1849	*/
<>	161:2cc1468da177	1850	/**
<>	161:2cc1468da177	1851	* @brief Configure an output channel.
<>	161:2cc1468da177	1852	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1853	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1854	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1855	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1856	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1857	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1858	* CCER CC1P LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1859	* CCER CC2P LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1860	* CCER CC3P LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1861	* CCER CC4P LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1862	* CCER CC5P LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1863	* CCER CC6P LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1864	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1865	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1866	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1867	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1868	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
<>	161:2cc1468da177	1869	* CR2 OIS6 LL_TIM_OC_ConfigOutput
<>	161:2cc1468da177	1870	* @param TIMx Timer instance
<>	161:2cc1468da177	1871	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	1872	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	1873	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	1874	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	1875	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	1876	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	1877	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	1878	* @param Configuration This parameter must be a combination of all the following values:
<>	161:2cc1468da177	1879	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
<>	161:2cc1468da177	1880	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
<>	161:2cc1468da177	1881	* @retval None
<>	161:2cc1468da177	1882	*/
<>	161:2cc1468da177	1883	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	161:2cc1468da177	1884	{
<>	161:2cc1468da177	1885	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	1886	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	1887	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
<>	161:2cc1468da177	1888	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
<>	161:2cc1468da177	1889	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
<>	161:2cc1468da177	1890	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
<>	161:2cc1468da177	1891	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
<>	161:2cc1468da177	1892	}
<>	161:2cc1468da177	1893
<>	161:2cc1468da177	1894	/**
<>	161:2cc1468da177	1895	* @brief Define the behavior of the output reference signal OCxREF from which
<>	161:2cc1468da177	1896	* OCx and OCxN (when relevant) are derived.
<>	161:2cc1468da177	1897	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
<>	161:2cc1468da177	1898	* CCMR1 OC2M LL_TIM_OC_SetMode\n
<>	161:2cc1468da177	1899	* CCMR2 OC3M LL_TIM_OC_SetMode\n
<>	161:2cc1468da177	1900	* CCMR2 OC4M LL_TIM_OC_SetMode\n
<>	161:2cc1468da177	1901	* CCMR3 OC5M LL_TIM_OC_SetMode\n
<>	161:2cc1468da177	1902	* CCMR3 OC6M LL_TIM_OC_SetMode
<>	161:2cc1468da177	1903	* @param TIMx Timer instance
<>	161:2cc1468da177	1904	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	1905	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	1906	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	1907	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	1908	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	1909	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	1910	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	1911	* @param Mode This parameter can be one of the following values:
<>	161:2cc1468da177	1912	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	161:2cc1468da177	1913	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	161:2cc1468da177	1914	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	161:2cc1468da177	1915	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	161:2cc1468da177	1916	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	161:2cc1468da177	1917	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	161:2cc1468da177	1918	* @arg @ref LL_TIM_OCMODE_PWM1
<>	161:2cc1468da177	1919	* @arg @ref LL_TIM_OCMODE_PWM2
<>	161:2cc1468da177	1920	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
<>	161:2cc1468da177	1921	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
<>	161:2cc1468da177	1922	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
<>	161:2cc1468da177	1923	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
<>	161:2cc1468da177	1924	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	161:2cc1468da177	1925	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	161:2cc1468da177	1926	* @retval None
<>	161:2cc1468da177	1927	*/
<>	161:2cc1468da177	1928	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
<>	161:2cc1468da177	1929	{
<>	161:2cc1468da177	1930	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	1931	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	1932	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
<>	161:2cc1468da177	1933	}
<>	161:2cc1468da177	1934
<>	161:2cc1468da177	1935	/**
<>	161:2cc1468da177	1936	* @brief Get the output compare mode of an output channel.
<>	161:2cc1468da177	1937	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
<>	161:2cc1468da177	1938	* CCMR1 OC2M LL_TIM_OC_GetMode\n
<>	161:2cc1468da177	1939	* CCMR2 OC3M LL_TIM_OC_GetMode\n
<>	161:2cc1468da177	1940	* CCMR2 OC4M LL_TIM_OC_GetMode\n
<>	161:2cc1468da177	1941	* CCMR3 OC5M LL_TIM_OC_GetMode\n
<>	161:2cc1468da177	1942	* CCMR3 OC6M LL_TIM_OC_GetMode
<>	161:2cc1468da177	1943	* @param TIMx Timer instance
<>	161:2cc1468da177	1944	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	1945	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	1946	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	1947	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	1948	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	1949	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	1950	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	1951	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1952	* @arg @ref LL_TIM_OCMODE_FROZEN
<>	161:2cc1468da177	1953	* @arg @ref LL_TIM_OCMODE_ACTIVE
<>	161:2cc1468da177	1954	* @arg @ref LL_TIM_OCMODE_INACTIVE
<>	161:2cc1468da177	1955	* @arg @ref LL_TIM_OCMODE_TOGGLE
<>	161:2cc1468da177	1956	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
<>	161:2cc1468da177	1957	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
<>	161:2cc1468da177	1958	* @arg @ref LL_TIM_OCMODE_PWM1
<>	161:2cc1468da177	1959	* @arg @ref LL_TIM_OCMODE_PWM2
<>	161:2cc1468da177	1960	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
<>	161:2cc1468da177	1961	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
<>	161:2cc1468da177	1962	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
<>	161:2cc1468da177	1963	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
<>	161:2cc1468da177	1964	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
<>	161:2cc1468da177	1965	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
<>	161:2cc1468da177	1966	*/
<>	161:2cc1468da177	1967	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	1968	{
<>	161:2cc1468da177	1969	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	1970	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	1971	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
<>	161:2cc1468da177	1972	}
<>	161:2cc1468da177	1973
<>	161:2cc1468da177	1974	/**
<>	161:2cc1468da177	1975	* @brief Set the polarity of an output channel.
<>	161:2cc1468da177	1976	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1977	* CCER CC1NP LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1978	* CCER CC2P LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1979	* CCER CC2NP LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1980	* CCER CC3P LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1981	* CCER CC3NP LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1982	* CCER CC4P LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1983	* CCER CC5P LL_TIM_OC_SetPolarity\n
<>	161:2cc1468da177	1984	* CCER CC6P LL_TIM_OC_SetPolarity
<>	161:2cc1468da177	1985	* @param TIMx Timer instance
<>	161:2cc1468da177	1986	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	1987	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	1988	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	1989	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	1990	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	1991	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	1992	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	1993	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	1994	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	1995	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	1996	* @param Polarity This parameter can be one of the following values:
<>	161:2cc1468da177	1997	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	161:2cc1468da177	1998	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	161:2cc1468da177	1999	* @retval None
<>	161:2cc1468da177	2000	*/
<>	161:2cc1468da177	2001	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
<>	161:2cc1468da177	2002	{
<>	161:2cc1468da177	2003	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2004	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
<>	161:2cc1468da177	2005	}
<>	161:2cc1468da177	2006
<>	161:2cc1468da177	2007	/**
<>	161:2cc1468da177	2008	* @brief Get the polarity of an output channel.
<>	161:2cc1468da177	2009	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2010	* CCER CC1NP LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2011	* CCER CC2P LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2012	* CCER CC2NP LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2013	* CCER CC3P LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2014	* CCER CC3NP LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2015	* CCER CC4P LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2016	* CCER CC5P LL_TIM_OC_GetPolarity\n
<>	161:2cc1468da177	2017	* CCER CC6P LL_TIM_OC_GetPolarity
<>	161:2cc1468da177	2018	* @param TIMx Timer instance
<>	161:2cc1468da177	2019	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2020	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2021	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	2022	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2023	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	2024	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2025	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	2026	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2027	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2028	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2029	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2030	* @arg @ref LL_TIM_OCPOLARITY_HIGH
<>	161:2cc1468da177	2031	* @arg @ref LL_TIM_OCPOLARITY_LOW
<>	161:2cc1468da177	2032	*/
<>	161:2cc1468da177	2033	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2034	{
<>	161:2cc1468da177	2035	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2036	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
<>	161:2cc1468da177	2037	}
<>	161:2cc1468da177	2038
<>	161:2cc1468da177	2039	/**
<>	161:2cc1468da177	2040	* @brief Set the IDLE state of an output channel
<>	161:2cc1468da177	2041	* @note This function is significant only for the timer instances
<>	161:2cc1468da177	2042	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
<>	161:2cc1468da177	2043	* can be used to check whether or not a timer instance provides
<>	161:2cc1468da177	2044	* a break input.
<>	161:2cc1468da177	2045	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2046	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2047	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2048	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2049	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2050	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2051	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2052	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
<>	161:2cc1468da177	2053	* CR2 OIS6 LL_TIM_OC_SetIdleState
<>	161:2cc1468da177	2054	* @param TIMx Timer instance
<>	161:2cc1468da177	2055	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2056	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2057	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	2058	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2059	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	2060	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2061	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	2062	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2063	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2064	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2065	* @param IdleState This parameter can be one of the following values:
<>	161:2cc1468da177	2066	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	161:2cc1468da177	2067	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	161:2cc1468da177	2068	* @retval None
<>	161:2cc1468da177	2069	*/
<>	161:2cc1468da177	2070	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
<>	161:2cc1468da177	2071	{
<>	161:2cc1468da177	2072	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2073	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
<>	161:2cc1468da177	2074	}
<>	161:2cc1468da177	2075
<>	161:2cc1468da177	2076	/**
<>	161:2cc1468da177	2077	* @brief Get the IDLE state of an output channel
<>	161:2cc1468da177	2078	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2079	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2080	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2081	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2082	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2083	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2084	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2085	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
<>	161:2cc1468da177	2086	* CR2 OIS6 LL_TIM_OC_GetIdleState
<>	161:2cc1468da177	2087	* @param TIMx Timer instance
<>	161:2cc1468da177	2088	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2089	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2090	* @arg @ref LL_TIM_CHANNEL_CH1N
<>	161:2cc1468da177	2091	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2092	* @arg @ref LL_TIM_CHANNEL_CH2N
<>	161:2cc1468da177	2093	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2094	* @arg @ref LL_TIM_CHANNEL_CH3N
<>	161:2cc1468da177	2095	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2096	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2097	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2098	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2099	* @arg @ref LL_TIM_OCIDLESTATE_LOW
<>	161:2cc1468da177	2100	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
<>	161:2cc1468da177	2101	*/
<>	161:2cc1468da177	2102	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2103	{
<>	161:2cc1468da177	2104	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2105	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
<>	161:2cc1468da177	2106	}
<>	161:2cc1468da177	2107
<>	161:2cc1468da177	2108	/**
<>	161:2cc1468da177	2109	* @brief Enable fast mode for the output channel.
<>	161:2cc1468da177	2110	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
<>	161:2cc1468da177	2111	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
<>	161:2cc1468da177	2112	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
<>	161:2cc1468da177	2113	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
<>	161:2cc1468da177	2114	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
<>	161:2cc1468da177	2115	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
<>	161:2cc1468da177	2116	* CCMR3 OC6FE LL_TIM_OC_EnableFast
<>	161:2cc1468da177	2117	* @param TIMx Timer instance
<>	161:2cc1468da177	2118	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2119	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2120	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2121	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2122	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2123	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2124	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2125	* @retval None
<>	161:2cc1468da177	2126	*/
<>	161:2cc1468da177	2127	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2128	{
<>	161:2cc1468da177	2129	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2130	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2131	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	161:2cc1468da177	2132
<>	161:2cc1468da177	2133	}
<>	161:2cc1468da177	2134
<>	161:2cc1468da177	2135	/**
<>	161:2cc1468da177	2136	* @brief Disable fast mode for the output channel.
<>	161:2cc1468da177	2137	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
<>	161:2cc1468da177	2138	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
<>	161:2cc1468da177	2139	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
<>	161:2cc1468da177	2140	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
<>	161:2cc1468da177	2141	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
<>	161:2cc1468da177	2142	* CCMR3 OC6FE LL_TIM_OC_DisableFast
<>	161:2cc1468da177	2143	* @param TIMx Timer instance
<>	161:2cc1468da177	2144	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2145	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2146	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2147	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2148	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2149	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2150	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2151	* @retval None
<>	161:2cc1468da177	2152	*/
<>	161:2cc1468da177	2153	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2154	{
<>	161:2cc1468da177	2155	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2156	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2157	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
<>	161:2cc1468da177	2158
<>	161:2cc1468da177	2159	}
<>	161:2cc1468da177	2160
<>	161:2cc1468da177	2161	/**
<>	161:2cc1468da177	2162	* @brief Indicates whether fast mode is enabled for the output channel.
<>	161:2cc1468da177	2163	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
<>	161:2cc1468da177	2164	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
<>	161:2cc1468da177	2165	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
<>	161:2cc1468da177	2166	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
<>	161:2cc1468da177	2167	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
<>	161:2cc1468da177	2168	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
<>	161:2cc1468da177	2169	* @param TIMx Timer instance
<>	161:2cc1468da177	2170	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2171	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2172	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2173	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2174	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2175	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2176	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2177	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2178	*/
<>	161:2cc1468da177	2179	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2180	{
<>	161:2cc1468da177	2181	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2182	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2183	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
<>	161:2cc1468da177	2184	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	161:2cc1468da177	2185	}
<>	161:2cc1468da177	2186
<>	161:2cc1468da177	2187	/**
<>	161:2cc1468da177	2188	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
<>	161:2cc1468da177	2189	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
<>	161:2cc1468da177	2190	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
<>	161:2cc1468da177	2191	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
<>	161:2cc1468da177	2192	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
<>	161:2cc1468da177	2193	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
<>	161:2cc1468da177	2194	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
<>	161:2cc1468da177	2195	* @param TIMx Timer instance
<>	161:2cc1468da177	2196	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2197	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2198	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2199	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2200	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2201	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2202	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2203	* @retval None
<>	161:2cc1468da177	2204	*/
<>	161:2cc1468da177	2205	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2206	{
<>	161:2cc1468da177	2207	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2208	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2209	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	161:2cc1468da177	2210	}
<>	161:2cc1468da177	2211
<>	161:2cc1468da177	2212	/**
<>	161:2cc1468da177	2213	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
<>	161:2cc1468da177	2214	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
<>	161:2cc1468da177	2215	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
<>	161:2cc1468da177	2216	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
<>	161:2cc1468da177	2217	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
<>	161:2cc1468da177	2218	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
<>	161:2cc1468da177	2219	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
<>	161:2cc1468da177	2220	* @param TIMx Timer instance
<>	161:2cc1468da177	2221	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2222	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2223	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2224	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2225	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2226	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2227	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2228	* @retval None
<>	161:2cc1468da177	2229	*/
<>	161:2cc1468da177	2230	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2231	{
<>	161:2cc1468da177	2232	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2233	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2234	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
<>	161:2cc1468da177	2235	}
<>	161:2cc1468da177	2236
<>	161:2cc1468da177	2237	/**
<>	161:2cc1468da177	2238	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
<>	161:2cc1468da177	2239	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
<>	161:2cc1468da177	2240	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
<>	161:2cc1468da177	2241	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
<>	161:2cc1468da177	2242	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
<>	161:2cc1468da177	2243	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
<>	161:2cc1468da177	2244	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
<>	161:2cc1468da177	2245	* @param TIMx Timer instance
<>	161:2cc1468da177	2246	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2247	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2248	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2249	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2250	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2251	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2252	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2253	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2254	*/
<>	161:2cc1468da177	2255	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2256	{
<>	161:2cc1468da177	2257	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2258	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2259	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
<>	161:2cc1468da177	2260	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	161:2cc1468da177	2261	}
<>	161:2cc1468da177	2262
<>	161:2cc1468da177	2263	/**
<>	161:2cc1468da177	2264	* @brief Enable clearing the output channel on an external event.
<>	161:2cc1468da177	2265	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	161:2cc1468da177	2266	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	161:2cc1468da177	2267	* or not a timer instance can clear the OCxREF signal on an external event.
<>	161:2cc1468da177	2268	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
<>	161:2cc1468da177	2269	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
<>	161:2cc1468da177	2270	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
<>	161:2cc1468da177	2271	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
<>	161:2cc1468da177	2272	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
<>	161:2cc1468da177	2273	* CCMR3 OC6CE LL_TIM_OC_EnableClear
<>	161:2cc1468da177	2274	* @param TIMx Timer instance
<>	161:2cc1468da177	2275	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2276	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2277	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2278	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2279	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2280	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2281	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2282	* @retval None
<>	161:2cc1468da177	2283	*/
<>	161:2cc1468da177	2284	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2285	{
<>	161:2cc1468da177	2286	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2287	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2288	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	161:2cc1468da177	2289	}
<>	161:2cc1468da177	2290
<>	161:2cc1468da177	2291	/**
<>	161:2cc1468da177	2292	* @brief Disable clearing the output channel on an external event.
<>	161:2cc1468da177	2293	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	161:2cc1468da177	2294	* or not a timer instance can clear the OCxREF signal on an external event.
<>	161:2cc1468da177	2295	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
<>	161:2cc1468da177	2296	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
<>	161:2cc1468da177	2297	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
<>	161:2cc1468da177	2298	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
<>	161:2cc1468da177	2299	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
<>	161:2cc1468da177	2300	* CCMR3 OC6CE LL_TIM_OC_DisableClear
<>	161:2cc1468da177	2301	* @param TIMx Timer instance
<>	161:2cc1468da177	2302	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2303	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2304	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2305	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2306	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2307	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2308	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2309	* @retval None
<>	161:2cc1468da177	2310	*/
<>	161:2cc1468da177	2311	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2312	{
<>	161:2cc1468da177	2313	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2314	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2315	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
<>	161:2cc1468da177	2316	}
<>	161:2cc1468da177	2317
<>	161:2cc1468da177	2318	/**
<>	161:2cc1468da177	2319	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
<>	161:2cc1468da177	2320	* @note This function enables clearing the output channel on an external event.
<>	161:2cc1468da177	2321	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
<>	161:2cc1468da177	2322	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
<>	161:2cc1468da177	2323	* or not a timer instance can clear the OCxREF signal on an external event.
<>	161:2cc1468da177	2324	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
<>	161:2cc1468da177	2325	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
<>	161:2cc1468da177	2326	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
<>	161:2cc1468da177	2327	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
<>	161:2cc1468da177	2328	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
<>	161:2cc1468da177	2329	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
<>	161:2cc1468da177	2330	* @param TIMx Timer instance
<>	161:2cc1468da177	2331	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2332	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2333	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2334	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2335	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2336	* @arg @ref LL_TIM_CHANNEL_CH5
<>	161:2cc1468da177	2337	* @arg @ref LL_TIM_CHANNEL_CH6
<>	161:2cc1468da177	2338	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2339	*/
<>	161:2cc1468da177	2340	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2341	{
<>	161:2cc1468da177	2342	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2343	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2344	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
<>	161:2cc1468da177	2345	return (READ_BIT(*pReg, bitfield) == bitfield);
<>	161:2cc1468da177	2346	}
<>	161:2cc1468da177	2347
<>	161:2cc1468da177	2348	/**
<>	161:2cc1468da177	2349	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
<>	161:2cc1468da177	2350	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2351	* dead-time insertion feature is supported by a timer instance.
<>	161:2cc1468da177	2352	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
<>	161:2cc1468da177	2353	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
<>	161:2cc1468da177	2354	* @param TIMx Timer instance
<>	161:2cc1468da177	2355	* @param DeadTime between Min_Data=0 and Max_Data=255
<>	161:2cc1468da177	2356	* @retval None
<>	161:2cc1468da177	2357	*/
<>	161:2cc1468da177	2358	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
<>	161:2cc1468da177	2359	{
<>	161:2cc1468da177	2360	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
<>	161:2cc1468da177	2361	}
<>	161:2cc1468da177	2362
<>	161:2cc1468da177	2363	/**
<>	161:2cc1468da177	2364	* @brief Set compare value for output channel 1 (TIMx_CCR1).
<>	161:2cc1468da177	2365	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2366	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2367	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2368	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2369	* output channel 1 is supported by a timer instance.
<>	161:2cc1468da177	2370	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
<>	161:2cc1468da177	2371	* @param TIMx Timer instance
<>	161:2cc1468da177	2372	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	2373	* @retval None
<>	161:2cc1468da177	2374	*/
<>	161:2cc1468da177	2375	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	161:2cc1468da177	2376	{
<>	161:2cc1468da177	2377	WRITE_REG(TIMx->CCR1, CompareValue);
<>	161:2cc1468da177	2378	}
<>	161:2cc1468da177	2379
<>	161:2cc1468da177	2380	/**
<>	161:2cc1468da177	2381	* @brief Set compare value for output channel 2 (TIMx_CCR2).
<>	161:2cc1468da177	2382	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2383	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2384	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2385	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2386	* output channel 2 is supported by a timer instance.
<>	161:2cc1468da177	2387	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
<>	161:2cc1468da177	2388	* @param TIMx Timer instance
<>	161:2cc1468da177	2389	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	2390	* @retval None
<>	161:2cc1468da177	2391	*/
<>	161:2cc1468da177	2392	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	161:2cc1468da177	2393	{
<>	161:2cc1468da177	2394	WRITE_REG(TIMx->CCR2, CompareValue);
<>	161:2cc1468da177	2395	}
<>	161:2cc1468da177	2396
<>	161:2cc1468da177	2397	/**
<>	161:2cc1468da177	2398	* @brief Set compare value for output channel 3 (TIMx_CCR3).
<>	161:2cc1468da177	2399	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2400	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2401	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2402	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2403	* output channel is supported by a timer instance.
<>	161:2cc1468da177	2404	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
<>	161:2cc1468da177	2405	* @param TIMx Timer instance
<>	161:2cc1468da177	2406	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	2407	* @retval None
<>	161:2cc1468da177	2408	*/
<>	161:2cc1468da177	2409	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	161:2cc1468da177	2410	{
<>	161:2cc1468da177	2411	WRITE_REG(TIMx->CCR3, CompareValue);
<>	161:2cc1468da177	2412	}
<>	161:2cc1468da177	2413
<>	161:2cc1468da177	2414	/**
<>	161:2cc1468da177	2415	* @brief Set compare value for output channel 4 (TIMx_CCR4).
<>	161:2cc1468da177	2416	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2417	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2418	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2419	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2420	* output channel 4 is supported by a timer instance.
<>	161:2cc1468da177	2421	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
<>	161:2cc1468da177	2422	* @param TIMx Timer instance
<>	161:2cc1468da177	2423	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	2424	* @retval None
<>	161:2cc1468da177	2425	*/
<>	161:2cc1468da177	2426	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	161:2cc1468da177	2427	{
<>	161:2cc1468da177	2428	WRITE_REG(TIMx->CCR4, CompareValue);
<>	161:2cc1468da177	2429	}
<>	161:2cc1468da177	2430
<>	161:2cc1468da177	2431	/**
<>	161:2cc1468da177	2432	* @brief Set compare value for output channel 5 (TIMx_CCR5).
<>	161:2cc1468da177	2433	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2434	* output channel 5 is supported by a timer instance.
<>	161:2cc1468da177	2435	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
<>	161:2cc1468da177	2436	* @param TIMx Timer instance
<>	161:2cc1468da177	2437	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	2438	* @retval None
<>	161:2cc1468da177	2439	*/
<>	161:2cc1468da177	2440	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	161:2cc1468da177	2441	{
<>	161:2cc1468da177	2442	WRITE_REG(TIMx->CCR5, CompareValue);
<>	161:2cc1468da177	2443	}
<>	161:2cc1468da177	2444
<>	161:2cc1468da177	2445	/**
<>	161:2cc1468da177	2446	* @brief Set compare value for output channel 6 (TIMx_CCR6).
<>	161:2cc1468da177	2447	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2448	* output channel 6 is supported by a timer instance.
<>	161:2cc1468da177	2449	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
<>	161:2cc1468da177	2450	* @param TIMx Timer instance
<>	161:2cc1468da177	2451	* @param CompareValue between Min_Data=0 and Max_Data=65535
<>	161:2cc1468da177	2452	* @retval None
<>	161:2cc1468da177	2453	*/
<>	161:2cc1468da177	2454	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
<>	161:2cc1468da177	2455	{
<>	161:2cc1468da177	2456	WRITE_REG(TIMx->CCR6, CompareValue);
<>	161:2cc1468da177	2457	}
<>	161:2cc1468da177	2458
<>	161:2cc1468da177	2459	/**
<>	161:2cc1468da177	2460	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
<>	161:2cc1468da177	2461	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2462	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2463	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2464	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2465	* output channel 1 is supported by a timer instance.
<>	161:2cc1468da177	2466	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
<>	161:2cc1468da177	2467	* @param TIMx Timer instance
<>	161:2cc1468da177	2468	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2469	*/
<>	161:2cc1468da177	2470	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2471	{
<>	161:2cc1468da177	2472	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	161:2cc1468da177	2473	}
<>	161:2cc1468da177	2474
<>	161:2cc1468da177	2475	/**
<>	161:2cc1468da177	2476	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
<>	161:2cc1468da177	2477	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2478	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2479	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2480	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2481	* output channel 2 is supported by a timer instance.
<>	161:2cc1468da177	2482	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
<>	161:2cc1468da177	2483	* @param TIMx Timer instance
<>	161:2cc1468da177	2484	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2485	*/
<>	161:2cc1468da177	2486	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2487	{
<>	161:2cc1468da177	2488	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	161:2cc1468da177	2489	}
<>	161:2cc1468da177	2490
<>	161:2cc1468da177	2491	/**
<>	161:2cc1468da177	2492	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
<>	161:2cc1468da177	2493	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2494	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2495	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2496	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2497	* output channel 3 is supported by a timer instance.
<>	161:2cc1468da177	2498	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
<>	161:2cc1468da177	2499	* @param TIMx Timer instance
<>	161:2cc1468da177	2500	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2501	*/
<>	161:2cc1468da177	2502	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2503	{
<>	161:2cc1468da177	2504	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	161:2cc1468da177	2505	}
<>	161:2cc1468da177	2506
<>	161:2cc1468da177	2507	/**
<>	161:2cc1468da177	2508	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
<>	161:2cc1468da177	2509	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2510	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2511	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2512	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2513	* output channel 4 is supported by a timer instance.
<>	161:2cc1468da177	2514	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
<>	161:2cc1468da177	2515	* @param TIMx Timer instance
<>	161:2cc1468da177	2516	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2517	*/
<>	161:2cc1468da177	2518	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2519	{
<>	161:2cc1468da177	2520	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	161:2cc1468da177	2521	}
<>	161:2cc1468da177	2522
<>	161:2cc1468da177	2523	/**
<>	161:2cc1468da177	2524	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
<>	161:2cc1468da177	2525	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2526	* output channel 5 is supported by a timer instance.
<>	161:2cc1468da177	2527	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
<>	161:2cc1468da177	2528	* @param TIMx Timer instance
<>	161:2cc1468da177	2529	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2530	*/
<>	161:2cc1468da177	2531	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2532	{
<>	161:2cc1468da177	2533	return (uint32_t)(READ_REG(TIMx->CCR5));
<>	161:2cc1468da177	2534	}
<>	161:2cc1468da177	2535
<>	161:2cc1468da177	2536	/**
<>	161:2cc1468da177	2537	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
<>	161:2cc1468da177	2538	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2539	* output channel 6 is supported by a timer instance.
<>	161:2cc1468da177	2540	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
<>	161:2cc1468da177	2541	* @param TIMx Timer instance
<>	161:2cc1468da177	2542	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2543	*/
<>	161:2cc1468da177	2544	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2545	{
<>	161:2cc1468da177	2546	return (uint32_t)(READ_REG(TIMx->CCR6));
<>	161:2cc1468da177	2547	}
<>	161:2cc1468da177	2548
<>	161:2cc1468da177	2549	/**
<>	161:2cc1468da177	2550	* @brief Select on which reference signal the OC5REF is combined to.
<>	161:2cc1468da177	2551	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2552	* whether or not a timer instance supports the combined 3-phase PWM mode.
<>	161:2cc1468da177	2553	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
<>	161:2cc1468da177	2554	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
<>	161:2cc1468da177	2555	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
<>	161:2cc1468da177	2556	* @param TIMx Timer instance
<>	161:2cc1468da177	2557	* @param GroupCH5 This parameter can be one of the following values:
<>	161:2cc1468da177	2558	* @arg @ref LL_TIM_GROUPCH5_NONE
<>	161:2cc1468da177	2559	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
<>	161:2cc1468da177	2560	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
<>	161:2cc1468da177	2561	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
<>	161:2cc1468da177	2562	* @retval None
<>	161:2cc1468da177	2563	*/
<>	161:2cc1468da177	2564	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
<>	161:2cc1468da177	2565	{
<>	161:2cc1468da177	2566	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
<>	161:2cc1468da177	2567	}
<>	161:2cc1468da177	2568
<>	161:2cc1468da177	2569	/**
<>	161:2cc1468da177	2570	* @}
<>	161:2cc1468da177	2571	*/
<>	161:2cc1468da177	2572
<>	161:2cc1468da177	2573	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
<>	161:2cc1468da177	2574	* @{
<>	161:2cc1468da177	2575	*/
<>	161:2cc1468da177	2576	/**
<>	161:2cc1468da177	2577	* @brief Configure input channel.
<>	161:2cc1468da177	2578	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
<>	161:2cc1468da177	2579	* CCMR1 IC1PSC LL_TIM_IC_Config\n
<>	161:2cc1468da177	2580	* CCMR1 IC1F LL_TIM_IC_Config\n
<>	161:2cc1468da177	2581	* CCMR1 CC2S LL_TIM_IC_Config\n
<>	161:2cc1468da177	2582	* CCMR1 IC2PSC LL_TIM_IC_Config\n
<>	161:2cc1468da177	2583	* CCMR1 IC2F LL_TIM_IC_Config\n
<>	161:2cc1468da177	2584	* CCMR2 CC3S LL_TIM_IC_Config\n
<>	161:2cc1468da177	2585	* CCMR2 IC3PSC LL_TIM_IC_Config\n
<>	161:2cc1468da177	2586	* CCMR2 IC3F LL_TIM_IC_Config\n
<>	161:2cc1468da177	2587	* CCMR2 CC4S LL_TIM_IC_Config\n
<>	161:2cc1468da177	2588	* CCMR2 IC4PSC LL_TIM_IC_Config\n
<>	161:2cc1468da177	2589	* CCMR2 IC4F LL_TIM_IC_Config\n
<>	161:2cc1468da177	2590	* CCER CC1P LL_TIM_IC_Config\n
<>	161:2cc1468da177	2591	* CCER CC1NP LL_TIM_IC_Config\n
<>	161:2cc1468da177	2592	* CCER CC2P LL_TIM_IC_Config\n
<>	161:2cc1468da177	2593	* CCER CC2NP LL_TIM_IC_Config\n
<>	161:2cc1468da177	2594	* CCER CC3P LL_TIM_IC_Config\n
<>	161:2cc1468da177	2595	* CCER CC3NP LL_TIM_IC_Config\n
<>	161:2cc1468da177	2596	* CCER CC4P LL_TIM_IC_Config\n
<>	161:2cc1468da177	2597	* CCER CC4NP LL_TIM_IC_Config
<>	161:2cc1468da177	2598	* @param TIMx Timer instance
<>	161:2cc1468da177	2599	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2600	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2601	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2602	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2603	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2604	* @param Configuration This parameter must be a combination of all the following values:
<>	161:2cc1468da177	2605	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
<>	161:2cc1468da177	2606	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
<>	161:2cc1468da177	2607	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	161:2cc1468da177	2608	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	161:2cc1468da177	2609	* @retval None
<>	161:2cc1468da177	2610	*/
<>	161:2cc1468da177	2611	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
<>	161:2cc1468da177	2612	{
<>	161:2cc1468da177	2613	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2614	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2615	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
<>	161:2cc1468da177	2616	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
<>	161:2cc1468da177	2617	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	161:2cc1468da177	2618	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
<>	161:2cc1468da177	2619	}
<>	161:2cc1468da177	2620
<>	161:2cc1468da177	2621	/**
<>	161:2cc1468da177	2622	* @brief Set the active input.
<>	161:2cc1468da177	2623	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
<>	161:2cc1468da177	2624	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
<>	161:2cc1468da177	2625	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
<>	161:2cc1468da177	2626	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
<>	161:2cc1468da177	2627	* @param TIMx Timer instance
<>	161:2cc1468da177	2628	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2629	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2630	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2631	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2632	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2633	* @param ICActiveInput This parameter can be one of the following values:
<>	161:2cc1468da177	2634	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	161:2cc1468da177	2635	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	161:2cc1468da177	2636	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	161:2cc1468da177	2637	* @retval None
<>	161:2cc1468da177	2638	*/
<>	161:2cc1468da177	2639	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
<>	161:2cc1468da177	2640	{
<>	161:2cc1468da177	2641	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2642	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2643	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	161:2cc1468da177	2644	}
<>	161:2cc1468da177	2645
<>	161:2cc1468da177	2646	/**
<>	161:2cc1468da177	2647	* @brief Get the current active input.
<>	161:2cc1468da177	2648	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
<>	161:2cc1468da177	2649	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
<>	161:2cc1468da177	2650	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
<>	161:2cc1468da177	2651	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
<>	161:2cc1468da177	2652	* @param TIMx Timer instance
<>	161:2cc1468da177	2653	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2654	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2655	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2656	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2657	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2658	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2659	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
<>	161:2cc1468da177	2660	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
<>	161:2cc1468da177	2661	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
<>	161:2cc1468da177	2662	*/
<>	161:2cc1468da177	2663	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2664	{
<>	161:2cc1468da177	2665	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2666	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2667	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	161:2cc1468da177	2668	}
<>	161:2cc1468da177	2669
<>	161:2cc1468da177	2670	/**
<>	161:2cc1468da177	2671	* @brief Set the prescaler of input channel.
<>	161:2cc1468da177	2672	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
<>	161:2cc1468da177	2673	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
<>	161:2cc1468da177	2674	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
<>	161:2cc1468da177	2675	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
<>	161:2cc1468da177	2676	* @param TIMx Timer instance
<>	161:2cc1468da177	2677	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2678	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2679	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2680	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2681	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2682	* @param ICPrescaler This parameter can be one of the following values:
<>	161:2cc1468da177	2683	* @arg @ref LL_TIM_ICPSC_DIV1
<>	161:2cc1468da177	2684	* @arg @ref LL_TIM_ICPSC_DIV2
<>	161:2cc1468da177	2685	* @arg @ref LL_TIM_ICPSC_DIV4
<>	161:2cc1468da177	2686	* @arg @ref LL_TIM_ICPSC_DIV8
<>	161:2cc1468da177	2687	* @retval None
<>	161:2cc1468da177	2688	*/
<>	161:2cc1468da177	2689	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
<>	161:2cc1468da177	2690	{
<>	161:2cc1468da177	2691	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2692	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2693	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	161:2cc1468da177	2694	}
<>	161:2cc1468da177	2695
<>	161:2cc1468da177	2696	/**
<>	161:2cc1468da177	2697	* @brief Get the current prescaler value acting on an input channel.
<>	161:2cc1468da177	2698	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
<>	161:2cc1468da177	2699	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
<>	161:2cc1468da177	2700	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
<>	161:2cc1468da177	2701	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
<>	161:2cc1468da177	2702	* @param TIMx Timer instance
<>	161:2cc1468da177	2703	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2704	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2705	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2706	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2707	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2708	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2709	* @arg @ref LL_TIM_ICPSC_DIV1
<>	161:2cc1468da177	2710	* @arg @ref LL_TIM_ICPSC_DIV2
<>	161:2cc1468da177	2711	* @arg @ref LL_TIM_ICPSC_DIV4
<>	161:2cc1468da177	2712	* @arg @ref LL_TIM_ICPSC_DIV8
<>	161:2cc1468da177	2713	*/
<>	161:2cc1468da177	2714	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2715	{
<>	161:2cc1468da177	2716	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2717	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2718	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	161:2cc1468da177	2719	}
<>	161:2cc1468da177	2720
<>	161:2cc1468da177	2721	/**
<>	161:2cc1468da177	2722	* @brief Set the input filter duration.
<>	161:2cc1468da177	2723	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
<>	161:2cc1468da177	2724	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
<>	161:2cc1468da177	2725	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
<>	161:2cc1468da177	2726	* CCMR2 IC4F LL_TIM_IC_SetFilter
<>	161:2cc1468da177	2727	* @param TIMx Timer instance
<>	161:2cc1468da177	2728	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2729	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2730	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2731	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2732	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2733	* @param ICFilter This parameter can be one of the following values:
<>	161:2cc1468da177	2734	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	161:2cc1468da177	2735	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	161:2cc1468da177	2736	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	161:2cc1468da177	2737	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	161:2cc1468da177	2738	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	161:2cc1468da177	2739	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	161:2cc1468da177	2740	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	161:2cc1468da177	2741	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	161:2cc1468da177	2742	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	161:2cc1468da177	2743	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	161:2cc1468da177	2744	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	161:2cc1468da177	2745	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	161:2cc1468da177	2746	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	161:2cc1468da177	2747	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	161:2cc1468da177	2748	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	161:2cc1468da177	2749	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	161:2cc1468da177	2750	* @retval None
<>	161:2cc1468da177	2751	*/
<>	161:2cc1468da177	2752	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
<>	161:2cc1468da177	2753	{
<>	161:2cc1468da177	2754	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2755	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2756	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
<>	161:2cc1468da177	2757	}
<>	161:2cc1468da177	2758
<>	161:2cc1468da177	2759	/**
<>	161:2cc1468da177	2760	* @brief Get the input filter duration.
<>	161:2cc1468da177	2761	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
<>	161:2cc1468da177	2762	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
<>	161:2cc1468da177	2763	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
<>	161:2cc1468da177	2764	* CCMR2 IC4F LL_TIM_IC_GetFilter
<>	161:2cc1468da177	2765	* @param TIMx Timer instance
<>	161:2cc1468da177	2766	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2767	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2768	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2769	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2770	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2771	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2772	* @arg @ref LL_TIM_IC_FILTER_FDIV1
<>	161:2cc1468da177	2773	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
<>	161:2cc1468da177	2774	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
<>	161:2cc1468da177	2775	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
<>	161:2cc1468da177	2776	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
<>	161:2cc1468da177	2777	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
<>	161:2cc1468da177	2778	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
<>	161:2cc1468da177	2779	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
<>	161:2cc1468da177	2780	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
<>	161:2cc1468da177	2781	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
<>	161:2cc1468da177	2782	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
<>	161:2cc1468da177	2783	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
<>	161:2cc1468da177	2784	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
<>	161:2cc1468da177	2785	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
<>	161:2cc1468da177	2786	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
<>	161:2cc1468da177	2787	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
<>	161:2cc1468da177	2788	*/
<>	161:2cc1468da177	2789	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2790	{
<>	161:2cc1468da177	2791	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2792	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
<>	161:2cc1468da177	2793	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
<>	161:2cc1468da177	2794	}
<>	161:2cc1468da177	2795
<>	161:2cc1468da177	2796	/**
<>	161:2cc1468da177	2797	* @brief Set the input channel polarity.
<>	161:2cc1468da177	2798	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
<>	161:2cc1468da177	2799	* CCER CC1NP LL_TIM_IC_SetPolarity\n
<>	161:2cc1468da177	2800	* CCER CC2P LL_TIM_IC_SetPolarity\n
<>	161:2cc1468da177	2801	* CCER CC2NP LL_TIM_IC_SetPolarity\n
<>	161:2cc1468da177	2802	* CCER CC3P LL_TIM_IC_SetPolarity\n
<>	161:2cc1468da177	2803	* CCER CC3NP LL_TIM_IC_SetPolarity\n
<>	161:2cc1468da177	2804	* CCER CC4P LL_TIM_IC_SetPolarity\n
<>	161:2cc1468da177	2805	* CCER CC4NP LL_TIM_IC_SetPolarity
<>	161:2cc1468da177	2806	* @param TIMx Timer instance
<>	161:2cc1468da177	2807	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2808	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2809	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2810	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2811	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2812	* @param ICPolarity This parameter can be one of the following values:
<>	161:2cc1468da177	2813	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	161:2cc1468da177	2814	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	161:2cc1468da177	2815	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	161:2cc1468da177	2816	* @retval None
<>	161:2cc1468da177	2817	*/
<>	161:2cc1468da177	2818	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
<>	161:2cc1468da177	2819	{
<>	161:2cc1468da177	2820	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2821	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
<>	161:2cc1468da177	2822	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
<>	161:2cc1468da177	2823	}
<>	161:2cc1468da177	2824
<>	161:2cc1468da177	2825	/**
<>	161:2cc1468da177	2826	* @brief Get the current input channel polarity.
<>	161:2cc1468da177	2827	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
<>	161:2cc1468da177	2828	* CCER CC1NP LL_TIM_IC_GetPolarity\n
<>	161:2cc1468da177	2829	* CCER CC2P LL_TIM_IC_GetPolarity\n
<>	161:2cc1468da177	2830	* CCER CC2NP LL_TIM_IC_GetPolarity\n
<>	161:2cc1468da177	2831	* CCER CC3P LL_TIM_IC_GetPolarity\n
<>	161:2cc1468da177	2832	* CCER CC3NP LL_TIM_IC_GetPolarity\n
<>	161:2cc1468da177	2833	* CCER CC4P LL_TIM_IC_GetPolarity\n
<>	161:2cc1468da177	2834	* CCER CC4NP LL_TIM_IC_GetPolarity
<>	161:2cc1468da177	2835	* @param TIMx Timer instance
<>	161:2cc1468da177	2836	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2837	* @arg @ref LL_TIM_CHANNEL_CH1
<>	161:2cc1468da177	2838	* @arg @ref LL_TIM_CHANNEL_CH2
<>	161:2cc1468da177	2839	* @arg @ref LL_TIM_CHANNEL_CH3
<>	161:2cc1468da177	2840	* @arg @ref LL_TIM_CHANNEL_CH4
<>	161:2cc1468da177	2841	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2842	* @arg @ref LL_TIM_IC_POLARITY_RISING
<>	161:2cc1468da177	2843	* @arg @ref LL_TIM_IC_POLARITY_FALLING
<>	161:2cc1468da177	2844	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
<>	161:2cc1468da177	2845	*/
<>	161:2cc1468da177	2846	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
<>	161:2cc1468da177	2847	{
<>	161:2cc1468da177	2848	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
<>	161:2cc1468da177	2849	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
<>	161:2cc1468da177	2850	SHIFT_TAB_CCxP[iChannel]);
<>	161:2cc1468da177	2851	}
<>	161:2cc1468da177	2852
<>	161:2cc1468da177	2853	/**
<>	161:2cc1468da177	2854	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
<>	161:2cc1468da177	2855	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2856	* a timer instance provides an XOR input.
<>	161:2cc1468da177	2857	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
<>	161:2cc1468da177	2858	* @param TIMx Timer instance
<>	161:2cc1468da177	2859	* @retval None
<>	161:2cc1468da177	2860	*/
<>	161:2cc1468da177	2861	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2862	{
<>	161:2cc1468da177	2863	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	161:2cc1468da177	2864	}
<>	161:2cc1468da177	2865
<>	161:2cc1468da177	2866	/**
<>	161:2cc1468da177	2867	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
<>	161:2cc1468da177	2868	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2869	* a timer instance provides an XOR input.
<>	161:2cc1468da177	2870	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
<>	161:2cc1468da177	2871	* @param TIMx Timer instance
<>	161:2cc1468da177	2872	* @retval None
<>	161:2cc1468da177	2873	*/
<>	161:2cc1468da177	2874	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2875	{
<>	161:2cc1468da177	2876	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
<>	161:2cc1468da177	2877	}
<>	161:2cc1468da177	2878
<>	161:2cc1468da177	2879	/**
<>	161:2cc1468da177	2880	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
<>	161:2cc1468da177	2881	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2882	* a timer instance provides an XOR input.
<>	161:2cc1468da177	2883	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
<>	161:2cc1468da177	2884	* @param TIMx Timer instance
<>	161:2cc1468da177	2885	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2886	*/
<>	161:2cc1468da177	2887	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2888	{
<>	161:2cc1468da177	2889	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
<>	161:2cc1468da177	2890	}
<>	161:2cc1468da177	2891
<>	161:2cc1468da177	2892	/**
<>	161:2cc1468da177	2893	* @brief Get captured value for input channel 1.
<>	161:2cc1468da177	2894	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2895	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2896	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2897	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2898	* input channel 1 is supported by a timer instance.
<>	161:2cc1468da177	2899	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
<>	161:2cc1468da177	2900	* @param TIMx Timer instance
<>	161:2cc1468da177	2901	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2902	*/
<>	161:2cc1468da177	2903	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2904	{
<>	161:2cc1468da177	2905	return (uint32_t)(READ_REG(TIMx->CCR1));
<>	161:2cc1468da177	2906	}
<>	161:2cc1468da177	2907
<>	161:2cc1468da177	2908	/**
<>	161:2cc1468da177	2909	* @brief Get captured value for input channel 2.
<>	161:2cc1468da177	2910	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2911	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2912	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2913	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2914	* input channel 2 is supported by a timer instance.
<>	161:2cc1468da177	2915	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
<>	161:2cc1468da177	2916	* @param TIMx Timer instance
<>	161:2cc1468da177	2917	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2918	*/
<>	161:2cc1468da177	2919	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2920	{
<>	161:2cc1468da177	2921	return (uint32_t)(READ_REG(TIMx->CCR2));
<>	161:2cc1468da177	2922	}
<>	161:2cc1468da177	2923
<>	161:2cc1468da177	2924	/**
<>	161:2cc1468da177	2925	* @brief Get captured value for input channel 3.
<>	161:2cc1468da177	2926	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2927	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2928	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2929	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2930	* input channel 3 is supported by a timer instance.
<>	161:2cc1468da177	2931	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
<>	161:2cc1468da177	2932	* @param TIMx Timer instance
<>	161:2cc1468da177	2933	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2934	*/
<>	161:2cc1468da177	2935	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2936	{
<>	161:2cc1468da177	2937	return (uint32_t)(READ_REG(TIMx->CCR3));
<>	161:2cc1468da177	2938	}
<>	161:2cc1468da177	2939
<>	161:2cc1468da177	2940	/**
<>	161:2cc1468da177	2941	* @brief Get captured value for input channel 4.
<>	161:2cc1468da177	2942	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
<>	161:2cc1468da177	2943	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2944	* whether or not a timer instance supports a 32 bits counter.
<>	161:2cc1468da177	2945	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	2946	* input channel 4 is supported by a timer instance.
<>	161:2cc1468da177	2947	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
<>	161:2cc1468da177	2948	* @param TIMx Timer instance
<>	161:2cc1468da177	2949	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
<>	161:2cc1468da177	2950	*/
<>	161:2cc1468da177	2951	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2952	{
<>	161:2cc1468da177	2953	return (uint32_t)(READ_REG(TIMx->CCR4));
<>	161:2cc1468da177	2954	}
<>	161:2cc1468da177	2955
<>	161:2cc1468da177	2956	/**
<>	161:2cc1468da177	2957	* @}
<>	161:2cc1468da177	2958	*/
<>	161:2cc1468da177	2959
<>	161:2cc1468da177	2960	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
<>	161:2cc1468da177	2961	* @{
<>	161:2cc1468da177	2962	*/
<>	161:2cc1468da177	2963	/**
<>	161:2cc1468da177	2964	* @brief Enable external clock mode 2.
<>	161:2cc1468da177	2965	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
<>	161:2cc1468da177	2966	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2967	* whether or not a timer instance supports external clock mode2.
<>	161:2cc1468da177	2968	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
<>	161:2cc1468da177	2969	* @param TIMx Timer instance
<>	161:2cc1468da177	2970	* @retval None
<>	161:2cc1468da177	2971	*/
<>	161:2cc1468da177	2972	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2973	{
<>	161:2cc1468da177	2974	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	161:2cc1468da177	2975	}
<>	161:2cc1468da177	2976
<>	161:2cc1468da177	2977	/**
<>	161:2cc1468da177	2978	* @brief Disable external clock mode 2.
<>	161:2cc1468da177	2979	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2980	* whether or not a timer instance supports external clock mode2.
<>	161:2cc1468da177	2981	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
<>	161:2cc1468da177	2982	* @param TIMx Timer instance
<>	161:2cc1468da177	2983	* @retval None
<>	161:2cc1468da177	2984	*/
<>	161:2cc1468da177	2985	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2986	{
<>	161:2cc1468da177	2987	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
<>	161:2cc1468da177	2988	}
<>	161:2cc1468da177	2989
<>	161:2cc1468da177	2990	/**
<>	161:2cc1468da177	2991	* @brief Indicate whether external clock mode 2 is enabled.
<>	161:2cc1468da177	2992	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	2993	* whether or not a timer instance supports external clock mode2.
<>	161:2cc1468da177	2994	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
<>	161:2cc1468da177	2995	* @param TIMx Timer instance
<>	161:2cc1468da177	2996	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2997	*/
<>	161:2cc1468da177	2998	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	2999	{
<>	161:2cc1468da177	3000	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
<>	161:2cc1468da177	3001	}
<>	161:2cc1468da177	3002
<>	161:2cc1468da177	3003	/**
<>	161:2cc1468da177	3004	* @brief Set the clock source of the counter clock.
<>	161:2cc1468da177	3005	* @note when selected clock source is external clock mode 1, the timer input
<>	161:2cc1468da177	3006	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
<>	161:2cc1468da177	3007	* function. This timer input must be configured by calling
<>	161:2cc1468da177	3008	* the @ref LL_TIM_IC_Config() function.
<>	161:2cc1468da177	3009	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	3010	* whether or not a timer instance supports external clock mode1.
<>	161:2cc1468da177	3011	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	3012	* whether or not a timer instance supports external clock mode2.
<>	161:2cc1468da177	3013	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
<>	161:2cc1468da177	3014	* SMCR ECE LL_TIM_SetClockSource
<>	161:2cc1468da177	3015	* @param TIMx Timer instance
<>	161:2cc1468da177	3016	* @param ClockSource This parameter can be one of the following values:
<>	161:2cc1468da177	3017	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
<>	161:2cc1468da177	3018	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
<>	161:2cc1468da177	3019	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
<>	161:2cc1468da177	3020	* @retval None
<>	161:2cc1468da177	3021	*/
<>	161:2cc1468da177	3022	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
<>	161:2cc1468da177	3023	{
<>	161:2cc1468da177	3024	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
<>	161:2cc1468da177	3025	}
<>	161:2cc1468da177	3026
<>	161:2cc1468da177	3027	/**
<>	161:2cc1468da177	3028	* @brief Set the encoder interface mode.
<>	161:2cc1468da177	3029	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	3030	* whether or not a timer instance supports the encoder mode.
<>	161:2cc1468da177	3031	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
<>	161:2cc1468da177	3032	* @param TIMx Timer instance
<>	161:2cc1468da177	3033	* @param EncoderMode This parameter can be one of the following values:
<>	161:2cc1468da177	3034	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
<>	161:2cc1468da177	3035	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
<>	161:2cc1468da177	3036	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
<>	161:2cc1468da177	3037	* @retval None
<>	161:2cc1468da177	3038	*/
<>	161:2cc1468da177	3039	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
<>	161:2cc1468da177	3040	{
<>	161:2cc1468da177	3041	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
<>	161:2cc1468da177	3042	}
<>	161:2cc1468da177	3043
<>	161:2cc1468da177	3044	/**
<>	161:2cc1468da177	3045	* @}
<>	161:2cc1468da177	3046	*/
<>	161:2cc1468da177	3047
<>	161:2cc1468da177	3048	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
<>	161:2cc1468da177	3049	* @{
<>	161:2cc1468da177	3050	*/
<>	161:2cc1468da177	3051	/**
<>	161:2cc1468da177	3052	* @brief Set the trigger output (TRGO) used for timer synchronization .
<>	161:2cc1468da177	3053	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	3054	* whether or not a timer instance can operate as a master timer.
<>	161:2cc1468da177	3055	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
<>	161:2cc1468da177	3056	* @param TIMx Timer instance
<>	161:2cc1468da177	3057	* @param TimerSynchronization This parameter can be one of the following values:
<>	161:2cc1468da177	3058	* @arg @ref LL_TIM_TRGO_RESET
<>	161:2cc1468da177	3059	* @arg @ref LL_TIM_TRGO_ENABLE
<>	161:2cc1468da177	3060	* @arg @ref LL_TIM_TRGO_UPDATE
<>	161:2cc1468da177	3061	* @arg @ref LL_TIM_TRGO_CC1IF
<>	161:2cc1468da177	3062	* @arg @ref LL_TIM_TRGO_OC1REF
<>	161:2cc1468da177	3063	* @arg @ref LL_TIM_TRGO_OC2REF
<>	161:2cc1468da177	3064	* @arg @ref LL_TIM_TRGO_OC3REF
<>	161:2cc1468da177	3065	* @arg @ref LL_TIM_TRGO_OC4REF
<>	161:2cc1468da177	3066	* @retval None
<>	161:2cc1468da177	3067	*/
<>	161:2cc1468da177	3068	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
<>	161:2cc1468da177	3069	{
<>	161:2cc1468da177	3070	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
<>	161:2cc1468da177	3071	}
<>	161:2cc1468da177	3072
<>	161:2cc1468da177	3073	/**
<>	161:2cc1468da177	3074	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
<>	161:2cc1468da177	3075	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
<>	161:2cc1468da177	3076	* whether or not a timer instance can be used for ADC synchronization.
<>	161:2cc1468da177	3077	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
<>	161:2cc1468da177	3078	* @param TIMx Timer Instance
<>	161:2cc1468da177	3079	* @param ADCSynchronization This parameter can be one of the following values:
<>	161:2cc1468da177	3080	* @arg @ref LL_TIM_TRGO2_RESET
<>	161:2cc1468da177	3081	* @arg @ref LL_TIM_TRGO2_ENABLE
<>	161:2cc1468da177	3082	* @arg @ref LL_TIM_TRGO2_UPDATE
<>	161:2cc1468da177	3083	* @arg @ref LL_TIM_TRGO2_CC1F
<>	161:2cc1468da177	3084	* @arg @ref LL_TIM_TRGO2_OC1
<>	161:2cc1468da177	3085	* @arg @ref LL_TIM_TRGO2_OC2
<>	161:2cc1468da177	3086	* @arg @ref LL_TIM_TRGO2_OC3
<>	161:2cc1468da177	3087	* @arg @ref LL_TIM_TRGO2_OC4
<>	161:2cc1468da177	3088	* @arg @ref LL_TIM_TRGO2_OC5
<>	161:2cc1468da177	3089	* @arg @ref LL_TIM_TRGO2_OC6
<>	161:2cc1468da177	3090	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
<>	161:2cc1468da177	3091	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
<>	161:2cc1468da177	3092	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
<>	161:2cc1468da177	3093	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
<>	161:2cc1468da177	3094	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
<>	161:2cc1468da177	3095	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
<>	161:2cc1468da177	3096	* @retval None
<>	161:2cc1468da177	3097	*/
<>	161:2cc1468da177	3098	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
<>	161:2cc1468da177	3099	{
<>	161:2cc1468da177	3100	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
<>	161:2cc1468da177	3101	}
<>	161:2cc1468da177	3102
<>	161:2cc1468da177	3103	/**
<>	161:2cc1468da177	3104	* @brief Set the synchronization mode of a slave timer.
<>	161:2cc1468da177	3105	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3106	* a timer instance can operate as a slave timer.
<>	161:2cc1468da177	3107	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
<>	161:2cc1468da177	3108	* @param TIMx Timer instance
<>	161:2cc1468da177	3109	* @param SlaveMode This parameter can be one of the following values:
<>	161:2cc1468da177	3110	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
<>	161:2cc1468da177	3111	* @arg @ref LL_TIM_SLAVEMODE_RESET
<>	161:2cc1468da177	3112	* @arg @ref LL_TIM_SLAVEMODE_GATED
<>	161:2cc1468da177	3113	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
<>	161:2cc1468da177	3114	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
<>	161:2cc1468da177	3115	* @retval None
<>	161:2cc1468da177	3116	*/
<>	161:2cc1468da177	3117	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
<>	161:2cc1468da177	3118	{
<>	161:2cc1468da177	3119	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
<>	161:2cc1468da177	3120	}
<>	161:2cc1468da177	3121
<>	161:2cc1468da177	3122	/**
<>	161:2cc1468da177	3123	* @brief Set the selects the trigger input to be used to synchronize the counter.
<>	161:2cc1468da177	3124	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3125	* a timer instance can operate as a slave timer.
<>	161:2cc1468da177	3126	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
<>	161:2cc1468da177	3127	* @param TIMx Timer instance
<>	161:2cc1468da177	3128	* @param TriggerInput This parameter can be one of the following values:
<>	161:2cc1468da177	3129	* @arg @ref LL_TIM_TS_ITR0
<>	161:2cc1468da177	3130	* @arg @ref LL_TIM_TS_ITR1
<>	161:2cc1468da177	3131	* @arg @ref LL_TIM_TS_ITR2
<>	161:2cc1468da177	3132	* @arg @ref LL_TIM_TS_ITR3
<>	161:2cc1468da177	3133	* @arg @ref LL_TIM_TS_TI1F_ED
<>	161:2cc1468da177	3134	* @arg @ref LL_TIM_TS_TI1FP1
<>	161:2cc1468da177	3135	* @arg @ref LL_TIM_TS_TI2FP2
<>	161:2cc1468da177	3136	* @arg @ref LL_TIM_TS_ETRF
<>	161:2cc1468da177	3137	* @retval None
<>	161:2cc1468da177	3138	*/
<>	161:2cc1468da177	3139	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
<>	161:2cc1468da177	3140	{
<>	161:2cc1468da177	3141	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
<>	161:2cc1468da177	3142	}
<>	161:2cc1468da177	3143
<>	161:2cc1468da177	3144	/**
<>	161:2cc1468da177	3145	* @brief Enable the Master/Slave mode.
<>	161:2cc1468da177	3146	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3147	* a timer instance can operate as a slave timer.
<>	161:2cc1468da177	3148	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
<>	161:2cc1468da177	3149	* @param TIMx Timer instance
<>	161:2cc1468da177	3150	* @retval None
<>	161:2cc1468da177	3151	*/
<>	161:2cc1468da177	3152	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3153	{
<>	161:2cc1468da177	3154	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	161:2cc1468da177	3155	}
<>	161:2cc1468da177	3156
<>	161:2cc1468da177	3157	/**
<>	161:2cc1468da177	3158	* @brief Disable the Master/Slave mode.
<>	161:2cc1468da177	3159	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3160	* a timer instance can operate as a slave timer.
<>	161:2cc1468da177	3161	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
<>	161:2cc1468da177	3162	* @param TIMx Timer instance
<>	161:2cc1468da177	3163	* @retval None
<>	161:2cc1468da177	3164	*/
<>	161:2cc1468da177	3165	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3166	{
<>	161:2cc1468da177	3167	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
<>	161:2cc1468da177	3168	}
<>	161:2cc1468da177	3169
<>	161:2cc1468da177	3170	/**
<>	161:2cc1468da177	3171	* @brief Indicates whether the Master/Slave mode is enabled.
<>	161:2cc1468da177	3172	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3173	* a timer instance can operate as a slave timer.
<>	161:2cc1468da177	3174	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
<>	161:2cc1468da177	3175	* @param TIMx Timer instance
<>	161:2cc1468da177	3176	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3177	*/
<>	161:2cc1468da177	3178	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3179	{
<>	161:2cc1468da177	3180	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
<>	161:2cc1468da177	3181	}
<>	161:2cc1468da177	3182
<>	161:2cc1468da177	3183	/**
<>	161:2cc1468da177	3184	* @brief Configure the external trigger (ETR) input.
<>	161:2cc1468da177	3185	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3186	* a timer instance provides an external trigger input.
<>	161:2cc1468da177	3187	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
<>	161:2cc1468da177	3188	* SMCR ETPS LL_TIM_ConfigETR\n
<>	161:2cc1468da177	3189	* SMCR ETF LL_TIM_ConfigETR
<>	161:2cc1468da177	3190	* @param TIMx Timer instance
<>	161:2cc1468da177	3191	* @param ETRPolarity This parameter can be one of the following values:
<>	161:2cc1468da177	3192	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
<>	161:2cc1468da177	3193	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
<>	161:2cc1468da177	3194	* @param ETRPrescaler This parameter can be one of the following values:
<>	161:2cc1468da177	3195	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
<>	161:2cc1468da177	3196	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
<>	161:2cc1468da177	3197	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
<>	161:2cc1468da177	3198	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
<>	161:2cc1468da177	3199	* @param ETRFilter This parameter can be one of the following values:
<>	161:2cc1468da177	3200	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
<>	161:2cc1468da177	3201	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
<>	161:2cc1468da177	3202	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
<>	161:2cc1468da177	3203	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
<>	161:2cc1468da177	3204	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
<>	161:2cc1468da177	3205	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
<>	161:2cc1468da177	3206	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
<>	161:2cc1468da177	3207	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
<>	161:2cc1468da177	3208	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
<>	161:2cc1468da177	3209	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
<>	161:2cc1468da177	3210	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
<>	161:2cc1468da177	3211	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
<>	161:2cc1468da177	3212	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
<>	161:2cc1468da177	3213	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
<>	161:2cc1468da177	3214	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
<>	161:2cc1468da177	3215	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
<>	161:2cc1468da177	3216	* @retval None
<>	161:2cc1468da177	3217	*/
<>	161:2cc1468da177	3218	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
<>	161:2cc1468da177	3219	uint32_t ETRFilter)
<>	161:2cc1468da177	3220	{
<>	161:2cc1468da177	3221	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
<>	161:2cc1468da177	3222	}
<>	161:2cc1468da177	3223
<>	161:2cc1468da177	3224	/**
<>	161:2cc1468da177	3225	* @}
<>	161:2cc1468da177	3226	*/
<>	161:2cc1468da177	3227
<>	161:2cc1468da177	3228	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
<>	161:2cc1468da177	3229	* @{
<>	161:2cc1468da177	3230	*/
<>	161:2cc1468da177	3231	/**
<>	161:2cc1468da177	3232	* @brief Enable the break function.
<>	161:2cc1468da177	3233	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3234	* a timer instance provides a break input.
<>	161:2cc1468da177	3235	* @rmtoll BDTR BKE LL_TIM_EnableBRK
<>	161:2cc1468da177	3236	* @param TIMx Timer instance
<>	161:2cc1468da177	3237	* @retval None
<>	161:2cc1468da177	3238	*/
<>	161:2cc1468da177	3239	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3240	{
<>	161:2cc1468da177	3241	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	161:2cc1468da177	3242	}
<>	161:2cc1468da177	3243
<>	161:2cc1468da177	3244	/**
<>	161:2cc1468da177	3245	* @brief Disable the break function.
<>	161:2cc1468da177	3246	* @rmtoll BDTR BKE LL_TIM_DisableBRK
<>	161:2cc1468da177	3247	* @param TIMx Timer instance
<>	161:2cc1468da177	3248	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3249	* a timer instance provides a break input.
<>	161:2cc1468da177	3250	* @retval None
<>	161:2cc1468da177	3251	*/
<>	161:2cc1468da177	3252	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3253	{
<>	161:2cc1468da177	3254	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
<>	161:2cc1468da177	3255	}
<>	161:2cc1468da177	3256
<>	161:2cc1468da177	3257	/**
<>	161:2cc1468da177	3258	* @brief Configure the break input.
<>	161:2cc1468da177	3259	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3260	* a timer instance provides a break input.
<>	161:2cc1468da177	3261	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
<>	161:2cc1468da177	3262	* BDTR BKF LL_TIM_ConfigBRK
<>	161:2cc1468da177	3263	* @param TIMx Timer instance
<>	161:2cc1468da177	3264	* @param BreakPolarity This parameter can be one of the following values:
<>	161:2cc1468da177	3265	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
<>	161:2cc1468da177	3266	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
<>	161:2cc1468da177	3267	* @param BreakFilter This parameter can be one of the following values:
<>	161:2cc1468da177	3268	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
<>	161:2cc1468da177	3269	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
<>	161:2cc1468da177	3270	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
<>	161:2cc1468da177	3271	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
<>	161:2cc1468da177	3272	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
<>	161:2cc1468da177	3273	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
<>	161:2cc1468da177	3274	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
<>	161:2cc1468da177	3275	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
<>	161:2cc1468da177	3276	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
<>	161:2cc1468da177	3277	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
<>	161:2cc1468da177	3278	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
<>	161:2cc1468da177	3279	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
<>	161:2cc1468da177	3280	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
<>	161:2cc1468da177	3281	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
<>	161:2cc1468da177	3282	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
<>	161:2cc1468da177	3283	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
<>	161:2cc1468da177	3284	* @retval None
<>	161:2cc1468da177	3285	*/
<>	161:2cc1468da177	3286	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
<>	161:2cc1468da177	3287	{
<>	161:2cc1468da177	3288	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
<>	161:2cc1468da177	3289	}
<>	161:2cc1468da177	3290
<>	161:2cc1468da177	3291	/**
<>	161:2cc1468da177	3292	* @brief Enable the break 2 function.
<>	161:2cc1468da177	3293	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3294	* a timer instance provides a second break input.
<>	161:2cc1468da177	3295	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
<>	161:2cc1468da177	3296	* @param TIMx Timer instance
<>	161:2cc1468da177	3297	* @retval None
<>	161:2cc1468da177	3298	*/
<>	161:2cc1468da177	3299	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3300	{
<>	161:2cc1468da177	3301	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
<>	161:2cc1468da177	3302	}
<>	161:2cc1468da177	3303
<>	161:2cc1468da177	3304	/**
<>	161:2cc1468da177	3305	* @brief Disable the break 2 function.
<>	161:2cc1468da177	3306	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3307	* a timer instance provides a second break input.
<>	161:2cc1468da177	3308	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
<>	161:2cc1468da177	3309	* @param TIMx Timer instance
<>	161:2cc1468da177	3310	* @retval None
<>	161:2cc1468da177	3311	*/
<>	161:2cc1468da177	3312	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3313	{
<>	161:2cc1468da177	3314	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
<>	161:2cc1468da177	3315	}
<>	161:2cc1468da177	3316
<>	161:2cc1468da177	3317	/**
<>	161:2cc1468da177	3318	* @brief Configure the break 2 input.
<>	161:2cc1468da177	3319	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3320	* a timer instance provides a second break input.
<>	161:2cc1468da177	3321	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
<>	161:2cc1468da177	3322	* BDTR BK2F LL_TIM_ConfigBRK2
<>	161:2cc1468da177	3323	* @param TIMx Timer instance
<>	161:2cc1468da177	3324	* @param Break2Polarity This parameter can be one of the following values:
<>	161:2cc1468da177	3325	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
<>	161:2cc1468da177	3326	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
<>	161:2cc1468da177	3327	* @param Break2Filter This parameter can be one of the following values:
<>	161:2cc1468da177	3328	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
<>	161:2cc1468da177	3329	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
<>	161:2cc1468da177	3330	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
<>	161:2cc1468da177	3331	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
<>	161:2cc1468da177	3332	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
<>	161:2cc1468da177	3333	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
<>	161:2cc1468da177	3334	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
<>	161:2cc1468da177	3335	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
<>	161:2cc1468da177	3336	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
<>	161:2cc1468da177	3337	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
<>	161:2cc1468da177	3338	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
<>	161:2cc1468da177	3339	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
<>	161:2cc1468da177	3340	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
<>	161:2cc1468da177	3341	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
<>	161:2cc1468da177	3342	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
<>	161:2cc1468da177	3343	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
<>	161:2cc1468da177	3344	* @retval None
<>	161:2cc1468da177	3345	*/
<>	161:2cc1468da177	3346	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
<>	161:2cc1468da177	3347	{
<>	161:2cc1468da177	3348	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
<>	161:2cc1468da177	3349	}
<>	161:2cc1468da177	3350
<>	161:2cc1468da177	3351	/**
<>	161:2cc1468da177	3352	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
<>	161:2cc1468da177	3353	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3354	* a timer instance provides a break input.
<>	161:2cc1468da177	3355	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
<>	161:2cc1468da177	3356	* BDTR OSSR LL_TIM_SetOffStates
<>	161:2cc1468da177	3357	* @param TIMx Timer instance
<>	161:2cc1468da177	3358	* @param OffStateIdle This parameter can be one of the following values:
<>	161:2cc1468da177	3359	* @arg @ref LL_TIM_OSSI_DISABLE
<>	161:2cc1468da177	3360	* @arg @ref LL_TIM_OSSI_ENABLE
<>	161:2cc1468da177	3361	* @param OffStateRun This parameter can be one of the following values:
<>	161:2cc1468da177	3362	* @arg @ref LL_TIM_OSSR_DISABLE
<>	161:2cc1468da177	3363	* @arg @ref LL_TIM_OSSR_ENABLE
<>	161:2cc1468da177	3364	* @retval None
<>	161:2cc1468da177	3365	*/
<>	161:2cc1468da177	3366	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
<>	161:2cc1468da177	3367	{
<>	161:2cc1468da177	3368	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
<>	161:2cc1468da177	3369	}
<>	161:2cc1468da177	3370
<>	161:2cc1468da177	3371	/**
<>	161:2cc1468da177	3372	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
<>	161:2cc1468da177	3373	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3374	* a timer instance provides a break input.
<>	161:2cc1468da177	3375	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
<>	161:2cc1468da177	3376	* @param TIMx Timer instance
<>	161:2cc1468da177	3377	* @retval None
<>	161:2cc1468da177	3378	*/
<>	161:2cc1468da177	3379	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3380	{
<>	161:2cc1468da177	3381	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	161:2cc1468da177	3382	}
<>	161:2cc1468da177	3383
<>	161:2cc1468da177	3384	/**
<>	161:2cc1468da177	3385	* @brief Disable automatic output (MOE can be set only by software).
<>	161:2cc1468da177	3386	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3387	* a timer instance provides a break input.
<>	161:2cc1468da177	3388	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
<>	161:2cc1468da177	3389	* @param TIMx Timer instance
<>	161:2cc1468da177	3390	* @retval None
<>	161:2cc1468da177	3391	*/
<>	161:2cc1468da177	3392	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3393	{
<>	161:2cc1468da177	3394	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
<>	161:2cc1468da177	3395	}
<>	161:2cc1468da177	3396
<>	161:2cc1468da177	3397	/**
<>	161:2cc1468da177	3398	* @brief Indicate whether automatic output is enabled.
<>	161:2cc1468da177	3399	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3400	* a timer instance provides a break input.
<>	161:2cc1468da177	3401	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
<>	161:2cc1468da177	3402	* @param TIMx Timer instance
<>	161:2cc1468da177	3403	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3404	*/
<>	161:2cc1468da177	3405	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3406	{
<>	161:2cc1468da177	3407	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
<>	161:2cc1468da177	3408	}
<>	161:2cc1468da177	3409
<>	161:2cc1468da177	3410	/**
<>	161:2cc1468da177	3411	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
<>	161:2cc1468da177	3412	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	161:2cc1468da177	3413	* software and is reset in case of break or break2 event
<>	161:2cc1468da177	3414	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3415	* a timer instance provides a break input.
<>	161:2cc1468da177	3416	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
<>	161:2cc1468da177	3417	* @param TIMx Timer instance
<>	161:2cc1468da177	3418	* @retval None
<>	161:2cc1468da177	3419	*/
<>	161:2cc1468da177	3420	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3421	{
<>	161:2cc1468da177	3422	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	161:2cc1468da177	3423	}
<>	161:2cc1468da177	3424
<>	161:2cc1468da177	3425	/**
<>	161:2cc1468da177	3426	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
<>	161:2cc1468da177	3427	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
<>	161:2cc1468da177	3428	* software and is reset in case of break or break2 event.
<>	161:2cc1468da177	3429	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3430	* a timer instance provides a break input.
<>	161:2cc1468da177	3431	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
<>	161:2cc1468da177	3432	* @param TIMx Timer instance
<>	161:2cc1468da177	3433	* @retval None
<>	161:2cc1468da177	3434	*/
<>	161:2cc1468da177	3435	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3436	{
<>	161:2cc1468da177	3437	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
<>	161:2cc1468da177	3438	}
<>	161:2cc1468da177	3439
<>	161:2cc1468da177	3440	/**
<>	161:2cc1468da177	3441	* @brief Indicates whether outputs are enabled.
<>	161:2cc1468da177	3442	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3443	* a timer instance provides a break input.
<>	161:2cc1468da177	3444	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
<>	161:2cc1468da177	3445	* @param TIMx Timer instance
<>	161:2cc1468da177	3446	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3447	*/
<>	161:2cc1468da177	3448	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3449	{
<>	161:2cc1468da177	3450	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
<>	161:2cc1468da177	3451	}
<>	161:2cc1468da177	3452
<>	161:2cc1468da177	3453	#if defined(TIM_BREAK_INPUT_SUPPORT)
<>	161:2cc1468da177	3454	/**
<>	161:2cc1468da177	3455	* @brief Enable the signals connected to the designated timer break input.
<>	161:2cc1468da177	3456	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
<>	161:2cc1468da177	3457	* or not a timer instance allows for break input selection.
<>	161:2cc1468da177	3458	* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
<>	161:2cc1468da177	3459	* AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n
<>	161:2cc1468da177	3460	* AF2 BK2INE LL_TIM_EnableBreakInputSource\n
<>	161:2cc1468da177	3461	* AF2 BK2DFBKE LL_TIM_EnableBreakInputSource
<>	161:2cc1468da177	3462	* @param TIMx Timer instance
<>	161:2cc1468da177	3463	* @param BreakInput This parameter can be one of the following values:
<>	161:2cc1468da177	3464	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
<>	161:2cc1468da177	3465	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
<>	161:2cc1468da177	3466	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3467	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
<>	161:2cc1468da177	3468	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
<>	161:2cc1468da177	3469	* @retval None
<>	161:2cc1468da177	3470	*/
<>	161:2cc1468da177	3471	__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
<>	161:2cc1468da177	3472	{
<>	161:2cc1468da177	3473	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
<>	161:2cc1468da177	3474	SET_BIT(*pReg , Source);
<>	161:2cc1468da177	3475	}
<>	161:2cc1468da177	3476
<>	161:2cc1468da177	3477	/**
<>	161:2cc1468da177	3478	* @brief Disable the signals connected to the designated timer break input.
<>	161:2cc1468da177	3479	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
<>	161:2cc1468da177	3480	* or not a timer instance allows for break input selection.
<>	161:2cc1468da177	3481	* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
<>	161:2cc1468da177	3482	* AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n
<>	161:2cc1468da177	3483	* AF2 BK2INE LL_TIM_DisableBreakInputSource\n
<>	161:2cc1468da177	3484	* AF2 BK2DFBKE LL_TIM_DisableBreakInputSource
<>	161:2cc1468da177	3485	* @param TIMx Timer instance
<>	161:2cc1468da177	3486	* @param BreakInput This parameter can be one of the following values:
<>	161:2cc1468da177	3487	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
<>	161:2cc1468da177	3488	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
<>	161:2cc1468da177	3489	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3490	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
<>	161:2cc1468da177	3491	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
<>	161:2cc1468da177	3492	* @retval None
<>	161:2cc1468da177	3493	*/
<>	161:2cc1468da177	3494	__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
<>	161:2cc1468da177	3495	{
<>	161:2cc1468da177	3496	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
<>	161:2cc1468da177	3497	CLEAR_BIT(*pReg, Source);
<>	161:2cc1468da177	3498	}
<>	161:2cc1468da177	3499
<>	161:2cc1468da177	3500	/**
<>	161:2cc1468da177	3501	* @brief Set the polarity of the break signal for the timer break input.
<>	161:2cc1468da177	3502	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
<>	161:2cc1468da177	3503	* or not a timer instance allows for break input selection.
<>	161:2cc1468da177	3504	* @rmtoll AF1 BKINE LL_TIM_SetBreakInputSourcePolarity\n
<>	161:2cc1468da177	3505	* AF1 BKDFBKE LL_TIM_SetBreakInputSourcePolarity\n
<>	161:2cc1468da177	3506	* AF2 BK2INE LL_TIM_SetBreakInputSourcePolarity\n
<>	161:2cc1468da177	3507	* AF2 BK2DFBKE LL_TIM_SetBreakInputSourcePolarity
<>	161:2cc1468da177	3508	* @param TIMx Timer instance
<>	161:2cc1468da177	3509	* @param BreakInput This parameter can be one of the following values:
<>	161:2cc1468da177	3510	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
<>	161:2cc1468da177	3511	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
<>	161:2cc1468da177	3512	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3513	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
<>	161:2cc1468da177	3514	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
<>	161:2cc1468da177	3515	* @param Polarity This parameter can be one of the following values:
<>	161:2cc1468da177	3516	* @arg @ref LL_TIM_BKIN_POLARITY_LOW
<>	161:2cc1468da177	3517	* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
<>	161:2cc1468da177	3518	* @retval None
<>	161:2cc1468da177	3519	*/
<>	161:2cc1468da177	3520	__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
<>	161:2cc1468da177	3521	uint32_t Polarity)
<>	161:2cc1468da177	3522	{
<>	161:2cc1468da177	3523	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
<>	161:2cc1468da177	3524	MODIFY_REG(*pReg, (TIMx_AF1_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE)));
<>	161:2cc1468da177	3525	}
<>	161:2cc1468da177	3526	#endif /* TIM_BREAK_INPUT_SUPPORT */
<>	161:2cc1468da177	3527	/**
<>	161:2cc1468da177	3528	* @}
<>	161:2cc1468da177	3529	*/
<>	161:2cc1468da177	3530
<>	161:2cc1468da177	3531	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
<>	161:2cc1468da177	3532	* @{
<>	161:2cc1468da177	3533	*/
<>	161:2cc1468da177	3534	/**
<>	161:2cc1468da177	3535	* @brief Configures the timer DMA burst feature.
<>	161:2cc1468da177	3536	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
<>	161:2cc1468da177	3537	* not a timer instance supports the DMA burst mode.
<>	161:2cc1468da177	3538	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
<>	161:2cc1468da177	3539	* DCR DBA LL_TIM_ConfigDMABurst
<>	161:2cc1468da177	3540	* @param TIMx Timer instance
<>	161:2cc1468da177	3541	* @param DMABurstBaseAddress This parameter can be one of the following values:
<>	161:2cc1468da177	3542	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
<>	161:2cc1468da177	3543	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
<>	161:2cc1468da177	3544	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
<>	161:2cc1468da177	3545	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
<>	161:2cc1468da177	3546	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
<>	161:2cc1468da177	3547	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
<>	161:2cc1468da177	3548	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
<>	161:2cc1468da177	3549	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
<>	161:2cc1468da177	3550	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
<>	161:2cc1468da177	3551	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
<>	161:2cc1468da177	3552	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
<>	161:2cc1468da177	3553	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
<>	161:2cc1468da177	3554	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
<>	161:2cc1468da177	3555	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
<>	161:2cc1468da177	3556	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
<>	161:2cc1468da177	3557	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
<>	161:2cc1468da177	3558	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
<>	161:2cc1468da177	3559	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
<>	161:2cc1468da177	3560	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
<>	161:2cc1468da177	3561	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
<>	161:2cc1468da177	3562	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
<>	161:2cc1468da177	3563	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
<>	161:2cc1468da177	3564	* @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
<>	161:2cc1468da177	3565	* @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
<>	161:2cc1468da177	3566	* @param DMABurstLength This parameter can be one of the following values:
<>	161:2cc1468da177	3567	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
<>	161:2cc1468da177	3568	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
<>	161:2cc1468da177	3569	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
<>	161:2cc1468da177	3570	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
<>	161:2cc1468da177	3571	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
<>	161:2cc1468da177	3572	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
<>	161:2cc1468da177	3573	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
<>	161:2cc1468da177	3574	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
<>	161:2cc1468da177	3575	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
<>	161:2cc1468da177	3576	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
<>	161:2cc1468da177	3577	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
<>	161:2cc1468da177	3578	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
<>	161:2cc1468da177	3579	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
<>	161:2cc1468da177	3580	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
<>	161:2cc1468da177	3581	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
<>	161:2cc1468da177	3582	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
<>	161:2cc1468da177	3583	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
<>	161:2cc1468da177	3584	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
<>	161:2cc1468da177	3585	* @retval None
<>	161:2cc1468da177	3586	*/
<>	161:2cc1468da177	3587	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
<>	161:2cc1468da177	3588	{
<>	161:2cc1468da177	3589	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
<>	161:2cc1468da177	3590	}
<>	161:2cc1468da177	3591
<>	161:2cc1468da177	3592	/**
<>	161:2cc1468da177	3593	* @}
<>	161:2cc1468da177	3594	*/
<>	161:2cc1468da177	3595
<>	161:2cc1468da177	3596	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
<>	161:2cc1468da177	3597	* @{
<>	161:2cc1468da177	3598	*/
<>	161:2cc1468da177	3599	/**
<>	161:2cc1468da177	3600	* @brief Remap TIM inputs (input channel, internal/external triggers).
<>	161:2cc1468da177	3601	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
<>	161:2cc1468da177	3602	* a some timer inputs can be remapped.
<>	161:2cc1468da177	3603	* @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
<>	161:2cc1468da177	3604	* TIM5_OR TI4_RMP LL_TIM_SetRemap\n
<>	161:2cc1468da177	3605	* TIM11_OR TI1_RMP LL_TIM_SetRemap
<>	161:2cc1468da177	3606	* @param TIMx Timer instance
<>	161:2cc1468da177	3607	* @param Remap Remap param depends on the TIMx. Description available only
<>	161:2cc1468da177	3608	* in CHM version of the User Manual (not in .pdf).
<>	161:2cc1468da177	3609	* Otherwise see Reference Manual description of OR registers.
<>	161:2cc1468da177	3610	*
<>	161:2cc1468da177	3611	* Below description summarizes "Timer Instance" and "Remap" param combinations:
<>	161:2cc1468da177	3612	*
<>	161:2cc1468da177	3613	* TIM2: one of the following values
<>	161:2cc1468da177	3614	*
<>	161:2cc1468da177	3615	* ITR1_RMP can be one of the following values
<>	161:2cc1468da177	3616	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
<>	161:2cc1468da177	3617	* @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
<>	161:2cc1468da177	3618	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
<>	161:2cc1468da177	3619	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
<>	161:2cc1468da177	3620	*
<>	161:2cc1468da177	3621	* TIM5: one of the following values
<>	161:2cc1468da177	3622	*
<>	161:2cc1468da177	3623	* @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
<>	161:2cc1468da177	3624	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
<>	161:2cc1468da177	3625	* @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
<>	161:2cc1468da177	3626	* @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
<>	161:2cc1468da177	3627	*
<>	161:2cc1468da177	3628	* TIM11: one of the following values
<>	161:2cc1468da177	3629	*
<>	161:2cc1468da177	3630	* @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
<>	161:2cc1468da177	3631	* @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
<>	161:2cc1468da177	3632	* @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
<>	161:2cc1468da177	3633	* @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
<>	161:2cc1468da177	3634	*
<>	161:2cc1468da177	3635	* @retval None
<>	161:2cc1468da177	3636	*/
<>	161:2cc1468da177	3637	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
<>	161:2cc1468da177	3638	{
<>	161:2cc1468da177	3639	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
<>	161:2cc1468da177	3640	}
<>	161:2cc1468da177	3641
<>	161:2cc1468da177	3642	/**
<>	161:2cc1468da177	3643	* @}
<>	161:2cc1468da177	3644	*/
<>	161:2cc1468da177	3645
<>	161:2cc1468da177	3646
<>	161:2cc1468da177	3647	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
<>	161:2cc1468da177	3648	* @{
<>	161:2cc1468da177	3649	*/
<>	161:2cc1468da177	3650	/**
<>	161:2cc1468da177	3651	* @brief Clear the update interrupt flag (UIF).
<>	161:2cc1468da177	3652	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
<>	161:2cc1468da177	3653	* @param TIMx Timer instance
<>	161:2cc1468da177	3654	* @retval None
<>	161:2cc1468da177	3655	*/
<>	161:2cc1468da177	3656	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3657	{
<>	161:2cc1468da177	3658	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
<>	161:2cc1468da177	3659	}
<>	161:2cc1468da177	3660
<>	161:2cc1468da177	3661	/**
<>	161:2cc1468da177	3662	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
<>	161:2cc1468da177	3663	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
<>	161:2cc1468da177	3664	* @param TIMx Timer instance
<>	161:2cc1468da177	3665	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3666	*/
<>	161:2cc1468da177	3667	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3668	{
<>	161:2cc1468da177	3669	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
<>	161:2cc1468da177	3670	}
<>	161:2cc1468da177	3671
<>	161:2cc1468da177	3672	/**
<>	161:2cc1468da177	3673	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
<>	161:2cc1468da177	3674	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
<>	161:2cc1468da177	3675	* @param TIMx Timer instance
<>	161:2cc1468da177	3676	* @retval None
<>	161:2cc1468da177	3677	*/
<>	161:2cc1468da177	3678	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3679	{
<>	161:2cc1468da177	3680	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
<>	161:2cc1468da177	3681	}
<>	161:2cc1468da177	3682
<>	161:2cc1468da177	3683	/**
<>	161:2cc1468da177	3684	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
<>	161:2cc1468da177	3685	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
<>	161:2cc1468da177	3686	* @param TIMx Timer instance
<>	161:2cc1468da177	3687	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3688	*/
<>	161:2cc1468da177	3689	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3690	{
<>	161:2cc1468da177	3691	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
<>	161:2cc1468da177	3692	}
<>	161:2cc1468da177	3693
<>	161:2cc1468da177	3694	/**
<>	161:2cc1468da177	3695	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
<>	161:2cc1468da177	3696	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
<>	161:2cc1468da177	3697	* @param TIMx Timer instance
<>	161:2cc1468da177	3698	* @retval None
<>	161:2cc1468da177	3699	*/
<>	161:2cc1468da177	3700	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3701	{
<>	161:2cc1468da177	3702	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
<>	161:2cc1468da177	3703	}
<>	161:2cc1468da177	3704
<>	161:2cc1468da177	3705	/**
<>	161:2cc1468da177	3706	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
<>	161:2cc1468da177	3707	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
<>	161:2cc1468da177	3708	* @param TIMx Timer instance
<>	161:2cc1468da177	3709	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3710	*/
<>	161:2cc1468da177	3711	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3712	{
<>	161:2cc1468da177	3713	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
<>	161:2cc1468da177	3714	}
<>	161:2cc1468da177	3715
<>	161:2cc1468da177	3716	/**
<>	161:2cc1468da177	3717	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
<>	161:2cc1468da177	3718	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
<>	161:2cc1468da177	3719	* @param TIMx Timer instance
<>	161:2cc1468da177	3720	* @retval None
<>	161:2cc1468da177	3721	*/
<>	161:2cc1468da177	3722	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3723	{
<>	161:2cc1468da177	3724	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
<>	161:2cc1468da177	3725	}
<>	161:2cc1468da177	3726
<>	161:2cc1468da177	3727	/**
<>	161:2cc1468da177	3728	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
<>	161:2cc1468da177	3729	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
<>	161:2cc1468da177	3730	* @param TIMx Timer instance
<>	161:2cc1468da177	3731	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3732	*/
<>	161:2cc1468da177	3733	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3734	{
<>	161:2cc1468da177	3735	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
<>	161:2cc1468da177	3736	}
<>	161:2cc1468da177	3737
<>	161:2cc1468da177	3738	/**
<>	161:2cc1468da177	3739	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
<>	161:2cc1468da177	3740	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
<>	161:2cc1468da177	3741	* @param TIMx Timer instance
<>	161:2cc1468da177	3742	* @retval None
<>	161:2cc1468da177	3743	*/
<>	161:2cc1468da177	3744	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3745	{
<>	161:2cc1468da177	3746	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
<>	161:2cc1468da177	3747	}
<>	161:2cc1468da177	3748
<>	161:2cc1468da177	3749	/**
<>	161:2cc1468da177	3750	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
<>	161:2cc1468da177	3751	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
<>	161:2cc1468da177	3752	* @param TIMx Timer instance
<>	161:2cc1468da177	3753	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3754	*/
<>	161:2cc1468da177	3755	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3756	{
<>	161:2cc1468da177	3757	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
<>	161:2cc1468da177	3758	}
<>	161:2cc1468da177	3759
<>	161:2cc1468da177	3760	/**
<>	161:2cc1468da177	3761	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
<>	161:2cc1468da177	3762	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
<>	161:2cc1468da177	3763	* @param TIMx Timer instance
<>	161:2cc1468da177	3764	* @retval None
<>	161:2cc1468da177	3765	*/
<>	161:2cc1468da177	3766	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3767	{
<>	161:2cc1468da177	3768	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
<>	161:2cc1468da177	3769	}
<>	161:2cc1468da177	3770
<>	161:2cc1468da177	3771	/**
<>	161:2cc1468da177	3772	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
<>	161:2cc1468da177	3773	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
<>	161:2cc1468da177	3774	* @param TIMx Timer instance
<>	161:2cc1468da177	3775	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3776	*/
<>	161:2cc1468da177	3777	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3778	{
<>	161:2cc1468da177	3779	return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
<>	161:2cc1468da177	3780	}
<>	161:2cc1468da177	3781
<>	161:2cc1468da177	3782	/**
<>	161:2cc1468da177	3783	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
<>	161:2cc1468da177	3784	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
<>	161:2cc1468da177	3785	* @param TIMx Timer instance
<>	161:2cc1468da177	3786	* @retval None
<>	161:2cc1468da177	3787	*/
<>	161:2cc1468da177	3788	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3789	{
<>	161:2cc1468da177	3790	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
<>	161:2cc1468da177	3791	}
<>	161:2cc1468da177	3792
<>	161:2cc1468da177	3793	/**
<>	161:2cc1468da177	3794	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
<>	161:2cc1468da177	3795	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
<>	161:2cc1468da177	3796	* @param TIMx Timer instance
<>	161:2cc1468da177	3797	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3798	*/
<>	161:2cc1468da177	3799	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3800	{
<>	161:2cc1468da177	3801	return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
<>	161:2cc1468da177	3802	}
<>	161:2cc1468da177	3803
<>	161:2cc1468da177	3804	/**
<>	161:2cc1468da177	3805	* @brief Clear the commutation interrupt flag (COMIF).
<>	161:2cc1468da177	3806	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
<>	161:2cc1468da177	3807	* @param TIMx Timer instance
<>	161:2cc1468da177	3808	* @retval None
<>	161:2cc1468da177	3809	*/
<>	161:2cc1468da177	3810	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3811	{
<>	161:2cc1468da177	3812	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
<>	161:2cc1468da177	3813	}
<>	161:2cc1468da177	3814
<>	161:2cc1468da177	3815	/**
<>	161:2cc1468da177	3816	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
<>	161:2cc1468da177	3817	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
<>	161:2cc1468da177	3818	* @param TIMx Timer instance
<>	161:2cc1468da177	3819	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3820	*/
<>	161:2cc1468da177	3821	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3822	{
<>	161:2cc1468da177	3823	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
<>	161:2cc1468da177	3824	}
<>	161:2cc1468da177	3825
<>	161:2cc1468da177	3826	/**
<>	161:2cc1468da177	3827	* @brief Clear the trigger interrupt flag (TIF).
<>	161:2cc1468da177	3828	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
<>	161:2cc1468da177	3829	* @param TIMx Timer instance
<>	161:2cc1468da177	3830	* @retval None
<>	161:2cc1468da177	3831	*/
<>	161:2cc1468da177	3832	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3833	{
<>	161:2cc1468da177	3834	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
<>	161:2cc1468da177	3835	}
<>	161:2cc1468da177	3836
<>	161:2cc1468da177	3837	/**
<>	161:2cc1468da177	3838	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
<>	161:2cc1468da177	3839	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
<>	161:2cc1468da177	3840	* @param TIMx Timer instance
<>	161:2cc1468da177	3841	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3842	*/
<>	161:2cc1468da177	3843	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3844	{
<>	161:2cc1468da177	3845	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
<>	161:2cc1468da177	3846	}
<>	161:2cc1468da177	3847
<>	161:2cc1468da177	3848	/**
<>	161:2cc1468da177	3849	* @brief Clear the break interrupt flag (BIF).
<>	161:2cc1468da177	3850	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
<>	161:2cc1468da177	3851	* @param TIMx Timer instance
<>	161:2cc1468da177	3852	* @retval None
<>	161:2cc1468da177	3853	*/
<>	161:2cc1468da177	3854	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3855	{
<>	161:2cc1468da177	3856	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
<>	161:2cc1468da177	3857	}
<>	161:2cc1468da177	3858
<>	161:2cc1468da177	3859	/**
<>	161:2cc1468da177	3860	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
<>	161:2cc1468da177	3861	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
<>	161:2cc1468da177	3862	* @param TIMx Timer instance
<>	161:2cc1468da177	3863	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3864	*/
<>	161:2cc1468da177	3865	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3866	{
<>	161:2cc1468da177	3867	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
<>	161:2cc1468da177	3868	}
<>	161:2cc1468da177	3869
<>	161:2cc1468da177	3870	/**
<>	161:2cc1468da177	3871	* @brief Clear the break 2 interrupt flag (B2IF).
<>	161:2cc1468da177	3872	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
<>	161:2cc1468da177	3873	* @param TIMx Timer instance
<>	161:2cc1468da177	3874	* @retval None
<>	161:2cc1468da177	3875	*/
<>	161:2cc1468da177	3876	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3877	{
<>	161:2cc1468da177	3878	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
<>	161:2cc1468da177	3879	}
<>	161:2cc1468da177	3880
<>	161:2cc1468da177	3881	/**
<>	161:2cc1468da177	3882	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
<>	161:2cc1468da177	3883	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
<>	161:2cc1468da177	3884	* @param TIMx Timer instance
<>	161:2cc1468da177	3885	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3886	*/
<>	161:2cc1468da177	3887	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3888	{
<>	161:2cc1468da177	3889	return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
<>	161:2cc1468da177	3890	}
<>	161:2cc1468da177	3891
<>	161:2cc1468da177	3892	/**
<>	161:2cc1468da177	3893	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
<>	161:2cc1468da177	3894	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
<>	161:2cc1468da177	3895	* @param TIMx Timer instance
<>	161:2cc1468da177	3896	* @retval None
<>	161:2cc1468da177	3897	*/
<>	161:2cc1468da177	3898	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3899	{
<>	161:2cc1468da177	3900	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
<>	161:2cc1468da177	3901	}
<>	161:2cc1468da177	3902
<>	161:2cc1468da177	3903	/**
<>	161:2cc1468da177	3904	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
<>	161:2cc1468da177	3905	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
<>	161:2cc1468da177	3906	* @param TIMx Timer instance
<>	161:2cc1468da177	3907	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3908	*/
<>	161:2cc1468da177	3909	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3910	{
<>	161:2cc1468da177	3911	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
<>	161:2cc1468da177	3912	}
<>	161:2cc1468da177	3913
<>	161:2cc1468da177	3914	/**
<>	161:2cc1468da177	3915	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
<>	161:2cc1468da177	3916	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
<>	161:2cc1468da177	3917	* @param TIMx Timer instance
<>	161:2cc1468da177	3918	* @retval None
<>	161:2cc1468da177	3919	*/
<>	161:2cc1468da177	3920	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3921	{
<>	161:2cc1468da177	3922	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
<>	161:2cc1468da177	3923	}
<>	161:2cc1468da177	3924
<>	161:2cc1468da177	3925	/**
<>	161:2cc1468da177	3926	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
<>	161:2cc1468da177	3927	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
<>	161:2cc1468da177	3928	* @param TIMx Timer instance
<>	161:2cc1468da177	3929	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3930	*/
<>	161:2cc1468da177	3931	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3932	{
<>	161:2cc1468da177	3933	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
<>	161:2cc1468da177	3934	}
<>	161:2cc1468da177	3935
<>	161:2cc1468da177	3936	/**
<>	161:2cc1468da177	3937	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
<>	161:2cc1468da177	3938	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
<>	161:2cc1468da177	3939	* @param TIMx Timer instance
<>	161:2cc1468da177	3940	* @retval None
<>	161:2cc1468da177	3941	*/
<>	161:2cc1468da177	3942	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3943	{
<>	161:2cc1468da177	3944	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
<>	161:2cc1468da177	3945	}
<>	161:2cc1468da177	3946
<>	161:2cc1468da177	3947	/**
<>	161:2cc1468da177	3948	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
<>	161:2cc1468da177	3949	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
<>	161:2cc1468da177	3950	* @param TIMx Timer instance
<>	161:2cc1468da177	3951	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3952	*/
<>	161:2cc1468da177	3953	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3954	{
<>	161:2cc1468da177	3955	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
<>	161:2cc1468da177	3956	}
<>	161:2cc1468da177	3957
<>	161:2cc1468da177	3958	/**
<>	161:2cc1468da177	3959	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
<>	161:2cc1468da177	3960	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
<>	161:2cc1468da177	3961	* @param TIMx Timer instance
<>	161:2cc1468da177	3962	* @retval None
<>	161:2cc1468da177	3963	*/
<>	161:2cc1468da177	3964	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3965	{
<>	161:2cc1468da177	3966	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
<>	161:2cc1468da177	3967	}
<>	161:2cc1468da177	3968
<>	161:2cc1468da177	3969	/**
<>	161:2cc1468da177	3970	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
<>	161:2cc1468da177	3971	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
<>	161:2cc1468da177	3972	* @param TIMx Timer instance
<>	161:2cc1468da177	3973	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3974	*/
<>	161:2cc1468da177	3975	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3976	{
<>	161:2cc1468da177	3977	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
<>	161:2cc1468da177	3978	}
<>	161:2cc1468da177	3979
<>	161:2cc1468da177	3980	/**
<>	161:2cc1468da177	3981	* @brief Clear the system break interrupt flag (SBIF).
<>	161:2cc1468da177	3982	* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
<>	161:2cc1468da177	3983	* @param TIMx Timer instance
<>	161:2cc1468da177	3984	* @retval None
<>	161:2cc1468da177	3985	*/
<>	161:2cc1468da177	3986	__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3987	{
<>	161:2cc1468da177	3988	WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
<>	161:2cc1468da177	3989	}
<>	161:2cc1468da177	3990
<>	161:2cc1468da177	3991	/**
<>	161:2cc1468da177	3992	* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
<>	161:2cc1468da177	3993	* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
<>	161:2cc1468da177	3994	* @param TIMx Timer instance
<>	161:2cc1468da177	3995	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3996	*/
<>	161:2cc1468da177	3997	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	3998	{
<>	161:2cc1468da177	3999	return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
<>	161:2cc1468da177	4000	}
<>	161:2cc1468da177	4001
<>	161:2cc1468da177	4002	/**
<>	161:2cc1468da177	4003	* @}
<>	161:2cc1468da177	4004	*/
<>	161:2cc1468da177	4005
<>	161:2cc1468da177	4006	/** @defgroup TIM_LL_EF_IT_Management IT-Management
<>	161:2cc1468da177	4007	* @{
<>	161:2cc1468da177	4008	*/
<>	161:2cc1468da177	4009	/**
<>	161:2cc1468da177	4010	* @brief Enable update interrupt (UIE).
<>	161:2cc1468da177	4011	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
<>	161:2cc1468da177	4012	* @param TIMx Timer instance
<>	161:2cc1468da177	4013	* @retval None
<>	161:2cc1468da177	4014	*/
<>	161:2cc1468da177	4015	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4016	{
<>	161:2cc1468da177	4017	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	161:2cc1468da177	4018	}
<>	161:2cc1468da177	4019
<>	161:2cc1468da177	4020	/**
<>	161:2cc1468da177	4021	* @brief Disable update interrupt (UIE).
<>	161:2cc1468da177	4022	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
<>	161:2cc1468da177	4023	* @param TIMx Timer instance
<>	161:2cc1468da177	4024	* @retval None
<>	161:2cc1468da177	4025	*/
<>	161:2cc1468da177	4026	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4027	{
<>	161:2cc1468da177	4028	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
<>	161:2cc1468da177	4029	}
<>	161:2cc1468da177	4030
<>	161:2cc1468da177	4031	/**
<>	161:2cc1468da177	4032	* @brief Indicates whether the update interrupt (UIE) is enabled.
<>	161:2cc1468da177	4033	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
<>	161:2cc1468da177	4034	* @param TIMx Timer instance
<>	161:2cc1468da177	4035	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4036	*/
<>	161:2cc1468da177	4037	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4038	{
<>	161:2cc1468da177	4039	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
<>	161:2cc1468da177	4040	}
<>	161:2cc1468da177	4041
<>	161:2cc1468da177	4042	/**
<>	161:2cc1468da177	4043	* @brief Enable capture/compare 1 interrupt (CC1IE).
<>	161:2cc1468da177	4044	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
<>	161:2cc1468da177	4045	* @param TIMx Timer instance
<>	161:2cc1468da177	4046	* @retval None
<>	161:2cc1468da177	4047	*/
<>	161:2cc1468da177	4048	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4049	{
<>	161:2cc1468da177	4050	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	161:2cc1468da177	4051	}
<>	161:2cc1468da177	4052
<>	161:2cc1468da177	4053	/**
<>	161:2cc1468da177	4054	* @brief Disable capture/compare 1 interrupt (CC1IE).
<>	161:2cc1468da177	4055	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
<>	161:2cc1468da177	4056	* @param TIMx Timer instance
<>	161:2cc1468da177	4057	* @retval None
<>	161:2cc1468da177	4058	*/
<>	161:2cc1468da177	4059	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4060	{
<>	161:2cc1468da177	4061	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
<>	161:2cc1468da177	4062	}
<>	161:2cc1468da177	4063
<>	161:2cc1468da177	4064	/**
<>	161:2cc1468da177	4065	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
<>	161:2cc1468da177	4066	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
<>	161:2cc1468da177	4067	* @param TIMx Timer instance
<>	161:2cc1468da177	4068	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4069	*/
<>	161:2cc1468da177	4070	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4071	{
<>	161:2cc1468da177	4072	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
<>	161:2cc1468da177	4073	}
<>	161:2cc1468da177	4074
<>	161:2cc1468da177	4075	/**
<>	161:2cc1468da177	4076	* @brief Enable capture/compare 2 interrupt (CC2IE).
<>	161:2cc1468da177	4077	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
<>	161:2cc1468da177	4078	* @param TIMx Timer instance
<>	161:2cc1468da177	4079	* @retval None
<>	161:2cc1468da177	4080	*/
<>	161:2cc1468da177	4081	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4082	{
<>	161:2cc1468da177	4083	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	161:2cc1468da177	4084	}
<>	161:2cc1468da177	4085
<>	161:2cc1468da177	4086	/**
<>	161:2cc1468da177	4087	* @brief Disable capture/compare 2 interrupt (CC2IE).
<>	161:2cc1468da177	4088	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
<>	161:2cc1468da177	4089	* @param TIMx Timer instance
<>	161:2cc1468da177	4090	* @retval None
<>	161:2cc1468da177	4091	*/
<>	161:2cc1468da177	4092	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4093	{
<>	161:2cc1468da177	4094	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
<>	161:2cc1468da177	4095	}
<>	161:2cc1468da177	4096
<>	161:2cc1468da177	4097	/**
<>	161:2cc1468da177	4098	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
<>	161:2cc1468da177	4099	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
<>	161:2cc1468da177	4100	* @param TIMx Timer instance
<>	161:2cc1468da177	4101	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4102	*/
<>	161:2cc1468da177	4103	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4104	{
<>	161:2cc1468da177	4105	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
<>	161:2cc1468da177	4106	}
<>	161:2cc1468da177	4107
<>	161:2cc1468da177	4108	/**
<>	161:2cc1468da177	4109	* @brief Enable capture/compare 3 interrupt (CC3IE).
<>	161:2cc1468da177	4110	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
<>	161:2cc1468da177	4111	* @param TIMx Timer instance
<>	161:2cc1468da177	4112	* @retval None
<>	161:2cc1468da177	4113	*/
<>	161:2cc1468da177	4114	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4115	{
<>	161:2cc1468da177	4116	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	161:2cc1468da177	4117	}
<>	161:2cc1468da177	4118
<>	161:2cc1468da177	4119	/**
<>	161:2cc1468da177	4120	* @brief Disable capture/compare 3 interrupt (CC3IE).
<>	161:2cc1468da177	4121	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
<>	161:2cc1468da177	4122	* @param TIMx Timer instance
<>	161:2cc1468da177	4123	* @retval None
<>	161:2cc1468da177	4124	*/
<>	161:2cc1468da177	4125	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4126	{
<>	161:2cc1468da177	4127	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
<>	161:2cc1468da177	4128	}
<>	161:2cc1468da177	4129
<>	161:2cc1468da177	4130	/**
<>	161:2cc1468da177	4131	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
<>	161:2cc1468da177	4132	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
<>	161:2cc1468da177	4133	* @param TIMx Timer instance
<>	161:2cc1468da177	4134	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4135	*/
<>	161:2cc1468da177	4136	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4137	{
<>	161:2cc1468da177	4138	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
<>	161:2cc1468da177	4139	}
<>	161:2cc1468da177	4140
<>	161:2cc1468da177	4141	/**
<>	161:2cc1468da177	4142	* @brief Enable capture/compare 4 interrupt (CC4IE).
<>	161:2cc1468da177	4143	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
<>	161:2cc1468da177	4144	* @param TIMx Timer instance
<>	161:2cc1468da177	4145	* @retval None
<>	161:2cc1468da177	4146	*/
<>	161:2cc1468da177	4147	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4148	{
<>	161:2cc1468da177	4149	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	161:2cc1468da177	4150	}
<>	161:2cc1468da177	4151
<>	161:2cc1468da177	4152	/**
<>	161:2cc1468da177	4153	* @brief Disable capture/compare 4 interrupt (CC4IE).
<>	161:2cc1468da177	4154	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
<>	161:2cc1468da177	4155	* @param TIMx Timer instance
<>	161:2cc1468da177	4156	* @retval None
<>	161:2cc1468da177	4157	*/
<>	161:2cc1468da177	4158	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4159	{
<>	161:2cc1468da177	4160	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
<>	161:2cc1468da177	4161	}
<>	161:2cc1468da177	4162
<>	161:2cc1468da177	4163	/**
<>	161:2cc1468da177	4164	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
<>	161:2cc1468da177	4165	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
<>	161:2cc1468da177	4166	* @param TIMx Timer instance
<>	161:2cc1468da177	4167	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4168	*/
<>	161:2cc1468da177	4169	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4170	{
<>	161:2cc1468da177	4171	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
<>	161:2cc1468da177	4172	}
<>	161:2cc1468da177	4173
<>	161:2cc1468da177	4174	/**
<>	161:2cc1468da177	4175	* @brief Enable commutation interrupt (COMIE).
<>	161:2cc1468da177	4176	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
<>	161:2cc1468da177	4177	* @param TIMx Timer instance
<>	161:2cc1468da177	4178	* @retval None
<>	161:2cc1468da177	4179	*/
<>	161:2cc1468da177	4180	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4181	{
<>	161:2cc1468da177	4182	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	161:2cc1468da177	4183	}
<>	161:2cc1468da177	4184
<>	161:2cc1468da177	4185	/**
<>	161:2cc1468da177	4186	* @brief Disable commutation interrupt (COMIE).
<>	161:2cc1468da177	4187	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
<>	161:2cc1468da177	4188	* @param TIMx Timer instance
<>	161:2cc1468da177	4189	* @retval None
<>	161:2cc1468da177	4190	*/
<>	161:2cc1468da177	4191	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4192	{
<>	161:2cc1468da177	4193	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
<>	161:2cc1468da177	4194	}
<>	161:2cc1468da177	4195
<>	161:2cc1468da177	4196	/**
<>	161:2cc1468da177	4197	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
<>	161:2cc1468da177	4198	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
<>	161:2cc1468da177	4199	* @param TIMx Timer instance
<>	161:2cc1468da177	4200	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4201	*/
<>	161:2cc1468da177	4202	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4203	{
<>	161:2cc1468da177	4204	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
<>	161:2cc1468da177	4205	}
<>	161:2cc1468da177	4206
<>	161:2cc1468da177	4207	/**
<>	161:2cc1468da177	4208	* @brief Enable trigger interrupt (TIE).
<>	161:2cc1468da177	4209	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
<>	161:2cc1468da177	4210	* @param TIMx Timer instance
<>	161:2cc1468da177	4211	* @retval None
<>	161:2cc1468da177	4212	*/
<>	161:2cc1468da177	4213	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4214	{
<>	161:2cc1468da177	4215	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	161:2cc1468da177	4216	}
<>	161:2cc1468da177	4217
<>	161:2cc1468da177	4218	/**
<>	161:2cc1468da177	4219	* @brief Disable trigger interrupt (TIE).
<>	161:2cc1468da177	4220	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
<>	161:2cc1468da177	4221	* @param TIMx Timer instance
<>	161:2cc1468da177	4222	* @retval None
<>	161:2cc1468da177	4223	*/
<>	161:2cc1468da177	4224	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4225	{
<>	161:2cc1468da177	4226	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
<>	161:2cc1468da177	4227	}
<>	161:2cc1468da177	4228
<>	161:2cc1468da177	4229	/**
<>	161:2cc1468da177	4230	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
<>	161:2cc1468da177	4231	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
<>	161:2cc1468da177	4232	* @param TIMx Timer instance
<>	161:2cc1468da177	4233	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4234	*/
<>	161:2cc1468da177	4235	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4236	{
<>	161:2cc1468da177	4237	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
<>	161:2cc1468da177	4238	}
<>	161:2cc1468da177	4239
<>	161:2cc1468da177	4240	/**
<>	161:2cc1468da177	4241	* @brief Enable break interrupt (BIE).
<>	161:2cc1468da177	4242	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
<>	161:2cc1468da177	4243	* @param TIMx Timer instance
<>	161:2cc1468da177	4244	* @retval None
<>	161:2cc1468da177	4245	*/
<>	161:2cc1468da177	4246	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4247	{
<>	161:2cc1468da177	4248	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	161:2cc1468da177	4249	}
<>	161:2cc1468da177	4250
<>	161:2cc1468da177	4251	/**
<>	161:2cc1468da177	4252	* @brief Disable break interrupt (BIE).
<>	161:2cc1468da177	4253	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
<>	161:2cc1468da177	4254	* @param TIMx Timer instance
<>	161:2cc1468da177	4255	* @retval None
<>	161:2cc1468da177	4256	*/
<>	161:2cc1468da177	4257	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4258	{
<>	161:2cc1468da177	4259	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
<>	161:2cc1468da177	4260	}
<>	161:2cc1468da177	4261
<>	161:2cc1468da177	4262	/**
<>	161:2cc1468da177	4263	* @brief Indicates whether the break interrupt (BIE) is enabled.
<>	161:2cc1468da177	4264	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
<>	161:2cc1468da177	4265	* @param TIMx Timer instance
<>	161:2cc1468da177	4266	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4267	*/
<>	161:2cc1468da177	4268	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4269	{
<>	161:2cc1468da177	4270	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
<>	161:2cc1468da177	4271	}
<>	161:2cc1468da177	4272
<>	161:2cc1468da177	4273	/**
<>	161:2cc1468da177	4274	* @}
<>	161:2cc1468da177	4275	*/
<>	161:2cc1468da177	4276
<>	161:2cc1468da177	4277	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
<>	161:2cc1468da177	4278	* @{
<>	161:2cc1468da177	4279	*/
<>	161:2cc1468da177	4280	/**
<>	161:2cc1468da177	4281	* @brief Enable update DMA request (UDE).
<>	161:2cc1468da177	4282	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
<>	161:2cc1468da177	4283	* @param TIMx Timer instance
<>	161:2cc1468da177	4284	* @retval None
<>	161:2cc1468da177	4285	*/
<>	161:2cc1468da177	4286	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4287	{
<>	161:2cc1468da177	4288	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	161:2cc1468da177	4289	}
<>	161:2cc1468da177	4290
<>	161:2cc1468da177	4291	/**
<>	161:2cc1468da177	4292	* @brief Disable update DMA request (UDE).
<>	161:2cc1468da177	4293	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
<>	161:2cc1468da177	4294	* @param TIMx Timer instance
<>	161:2cc1468da177	4295	* @retval None
<>	161:2cc1468da177	4296	*/
<>	161:2cc1468da177	4297	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4298	{
<>	161:2cc1468da177	4299	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
<>	161:2cc1468da177	4300	}
<>	161:2cc1468da177	4301
<>	161:2cc1468da177	4302	/**
<>	161:2cc1468da177	4303	* @brief Indicates whether the update DMA request (UDE) is enabled.
<>	161:2cc1468da177	4304	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
<>	161:2cc1468da177	4305	* @param TIMx Timer instance
<>	161:2cc1468da177	4306	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4307	*/
<>	161:2cc1468da177	4308	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4309	{
<>	161:2cc1468da177	4310	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
<>	161:2cc1468da177	4311	}
<>	161:2cc1468da177	4312
<>	161:2cc1468da177	4313	/**
<>	161:2cc1468da177	4314	* @brief Enable capture/compare 1 DMA request (CC1DE).
<>	161:2cc1468da177	4315	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
<>	161:2cc1468da177	4316	* @param TIMx Timer instance
<>	161:2cc1468da177	4317	* @retval None
<>	161:2cc1468da177	4318	*/
<>	161:2cc1468da177	4319	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4320	{
<>	161:2cc1468da177	4321	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	161:2cc1468da177	4322	}
<>	161:2cc1468da177	4323
<>	161:2cc1468da177	4324	/**
<>	161:2cc1468da177	4325	* @brief Disable capture/compare 1 DMA request (CC1DE).
<>	161:2cc1468da177	4326	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
<>	161:2cc1468da177	4327	* @param TIMx Timer instance
<>	161:2cc1468da177	4328	* @retval None
<>	161:2cc1468da177	4329	*/
<>	161:2cc1468da177	4330	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4331	{
<>	161:2cc1468da177	4332	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
<>	161:2cc1468da177	4333	}
<>	161:2cc1468da177	4334
<>	161:2cc1468da177	4335	/**
<>	161:2cc1468da177	4336	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
<>	161:2cc1468da177	4337	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
<>	161:2cc1468da177	4338	* @param TIMx Timer instance
<>	161:2cc1468da177	4339	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4340	*/
<>	161:2cc1468da177	4341	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4342	{
<>	161:2cc1468da177	4343	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
<>	161:2cc1468da177	4344	}
<>	161:2cc1468da177	4345
<>	161:2cc1468da177	4346	/**
<>	161:2cc1468da177	4347	* @brief Enable capture/compare 2 DMA request (CC2DE).
<>	161:2cc1468da177	4348	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
<>	161:2cc1468da177	4349	* @param TIMx Timer instance
<>	161:2cc1468da177	4350	* @retval None
<>	161:2cc1468da177	4351	*/
<>	161:2cc1468da177	4352	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4353	{
<>	161:2cc1468da177	4354	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	161:2cc1468da177	4355	}
<>	161:2cc1468da177	4356
<>	161:2cc1468da177	4357	/**
<>	161:2cc1468da177	4358	* @brief Disable capture/compare 2 DMA request (CC2DE).
<>	161:2cc1468da177	4359	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
<>	161:2cc1468da177	4360	* @param TIMx Timer instance
<>	161:2cc1468da177	4361	* @retval None
<>	161:2cc1468da177	4362	*/
<>	161:2cc1468da177	4363	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4364	{
<>	161:2cc1468da177	4365	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
<>	161:2cc1468da177	4366	}
<>	161:2cc1468da177	4367
<>	161:2cc1468da177	4368	/**
<>	161:2cc1468da177	4369	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
<>	161:2cc1468da177	4370	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
<>	161:2cc1468da177	4371	* @param TIMx Timer instance
<>	161:2cc1468da177	4372	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4373	*/
<>	161:2cc1468da177	4374	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4375	{
<>	161:2cc1468da177	4376	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
<>	161:2cc1468da177	4377	}
<>	161:2cc1468da177	4378
<>	161:2cc1468da177	4379	/**
<>	161:2cc1468da177	4380	* @brief Enable capture/compare 3 DMA request (CC3DE).
<>	161:2cc1468da177	4381	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
<>	161:2cc1468da177	4382	* @param TIMx Timer instance
<>	161:2cc1468da177	4383	* @retval None
<>	161:2cc1468da177	4384	*/
<>	161:2cc1468da177	4385	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4386	{
<>	161:2cc1468da177	4387	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	161:2cc1468da177	4388	}
<>	161:2cc1468da177	4389
<>	161:2cc1468da177	4390	/**
<>	161:2cc1468da177	4391	* @brief Disable capture/compare 3 DMA request (CC3DE).
<>	161:2cc1468da177	4392	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
<>	161:2cc1468da177	4393	* @param TIMx Timer instance
<>	161:2cc1468da177	4394	* @retval None
<>	161:2cc1468da177	4395	*/
<>	161:2cc1468da177	4396	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4397	{
<>	161:2cc1468da177	4398	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
<>	161:2cc1468da177	4399	}
<>	161:2cc1468da177	4400
<>	161:2cc1468da177	4401	/**
<>	161:2cc1468da177	4402	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
<>	161:2cc1468da177	4403	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
<>	161:2cc1468da177	4404	* @param TIMx Timer instance
<>	161:2cc1468da177	4405	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4406	*/
<>	161:2cc1468da177	4407	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4408	{
<>	161:2cc1468da177	4409	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
<>	161:2cc1468da177	4410	}
<>	161:2cc1468da177	4411
<>	161:2cc1468da177	4412	/**
<>	161:2cc1468da177	4413	* @brief Enable capture/compare 4 DMA request (CC4DE).
<>	161:2cc1468da177	4414	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
<>	161:2cc1468da177	4415	* @param TIMx Timer instance
<>	161:2cc1468da177	4416	* @retval None
<>	161:2cc1468da177	4417	*/
<>	161:2cc1468da177	4418	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4419	{
<>	161:2cc1468da177	4420	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	161:2cc1468da177	4421	}
<>	161:2cc1468da177	4422
<>	161:2cc1468da177	4423	/**
<>	161:2cc1468da177	4424	* @brief Disable capture/compare 4 DMA request (CC4DE).
<>	161:2cc1468da177	4425	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
<>	161:2cc1468da177	4426	* @param TIMx Timer instance
<>	161:2cc1468da177	4427	* @retval None
<>	161:2cc1468da177	4428	*/
<>	161:2cc1468da177	4429	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4430	{
<>	161:2cc1468da177	4431	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
<>	161:2cc1468da177	4432	}
<>	161:2cc1468da177	4433
<>	161:2cc1468da177	4434	/**
<>	161:2cc1468da177	4435	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
<>	161:2cc1468da177	4436	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
<>	161:2cc1468da177	4437	* @param TIMx Timer instance
<>	161:2cc1468da177	4438	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4439	*/
<>	161:2cc1468da177	4440	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4441	{
<>	161:2cc1468da177	4442	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
<>	161:2cc1468da177	4443	}
<>	161:2cc1468da177	4444
<>	161:2cc1468da177	4445	/**
<>	161:2cc1468da177	4446	* @brief Enable commutation DMA request (COMDE).
<>	161:2cc1468da177	4447	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
<>	161:2cc1468da177	4448	* @param TIMx Timer instance
<>	161:2cc1468da177	4449	* @retval None
<>	161:2cc1468da177	4450	*/
<>	161:2cc1468da177	4451	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4452	{
<>	161:2cc1468da177	4453	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	161:2cc1468da177	4454	}
<>	161:2cc1468da177	4455
<>	161:2cc1468da177	4456	/**
<>	161:2cc1468da177	4457	* @brief Disable commutation DMA request (COMDE).
<>	161:2cc1468da177	4458	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
<>	161:2cc1468da177	4459	* @param TIMx Timer instance
<>	161:2cc1468da177	4460	* @retval None
<>	161:2cc1468da177	4461	*/
<>	161:2cc1468da177	4462	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4463	{
<>	161:2cc1468da177	4464	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
<>	161:2cc1468da177	4465	}
<>	161:2cc1468da177	4466
<>	161:2cc1468da177	4467	/**
<>	161:2cc1468da177	4468	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
<>	161:2cc1468da177	4469	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
<>	161:2cc1468da177	4470	* @param TIMx Timer instance
<>	161:2cc1468da177	4471	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4472	*/
<>	161:2cc1468da177	4473	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4474	{
<>	161:2cc1468da177	4475	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
<>	161:2cc1468da177	4476	}
<>	161:2cc1468da177	4477
<>	161:2cc1468da177	4478	/**
<>	161:2cc1468da177	4479	* @brief Enable trigger interrupt (TDE).
<>	161:2cc1468da177	4480	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
<>	161:2cc1468da177	4481	* @param TIMx Timer instance
<>	161:2cc1468da177	4482	* @retval None
<>	161:2cc1468da177	4483	*/
<>	161:2cc1468da177	4484	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4485	{
<>	161:2cc1468da177	4486	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	161:2cc1468da177	4487	}
<>	161:2cc1468da177	4488
<>	161:2cc1468da177	4489	/**
<>	161:2cc1468da177	4490	* @brief Disable trigger interrupt (TDE).
<>	161:2cc1468da177	4491	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
<>	161:2cc1468da177	4492	* @param TIMx Timer instance
<>	161:2cc1468da177	4493	* @retval None
<>	161:2cc1468da177	4494	*/
<>	161:2cc1468da177	4495	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4496	{
<>	161:2cc1468da177	4497	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
<>	161:2cc1468da177	4498	}
<>	161:2cc1468da177	4499
<>	161:2cc1468da177	4500	/**
<>	161:2cc1468da177	4501	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
<>	161:2cc1468da177	4502	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
<>	161:2cc1468da177	4503	* @param TIMx Timer instance
<>	161:2cc1468da177	4504	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4505	*/
<>	161:2cc1468da177	4506	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4507	{
<>	161:2cc1468da177	4508	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
<>	161:2cc1468da177	4509	}
<>	161:2cc1468da177	4510
<>	161:2cc1468da177	4511	/**
<>	161:2cc1468da177	4512	* @}
<>	161:2cc1468da177	4513	*/
<>	161:2cc1468da177	4514
<>	161:2cc1468da177	4515	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
<>	161:2cc1468da177	4516	* @{
<>	161:2cc1468da177	4517	*/
<>	161:2cc1468da177	4518	/**
<>	161:2cc1468da177	4519	* @brief Generate an update event.
<>	161:2cc1468da177	4520	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
<>	161:2cc1468da177	4521	* @param TIMx Timer instance
<>	161:2cc1468da177	4522	* @retval None
<>	161:2cc1468da177	4523	*/
<>	161:2cc1468da177	4524	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4525	{
<>	161:2cc1468da177	4526	SET_BIT(TIMx->EGR, TIM_EGR_UG);
<>	161:2cc1468da177	4527	}
<>	161:2cc1468da177	4528
<>	161:2cc1468da177	4529	/**
<>	161:2cc1468da177	4530	* @brief Generate Capture/Compare 1 event.
<>	161:2cc1468da177	4531	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
<>	161:2cc1468da177	4532	* @param TIMx Timer instance
<>	161:2cc1468da177	4533	* @retval None
<>	161:2cc1468da177	4534	*/
<>	161:2cc1468da177	4535	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4536	{
<>	161:2cc1468da177	4537	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
<>	161:2cc1468da177	4538	}
<>	161:2cc1468da177	4539
<>	161:2cc1468da177	4540	/**
<>	161:2cc1468da177	4541	* @brief Generate Capture/Compare 2 event.
<>	161:2cc1468da177	4542	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
<>	161:2cc1468da177	4543	* @param TIMx Timer instance
<>	161:2cc1468da177	4544	* @retval None
<>	161:2cc1468da177	4545	*/
<>	161:2cc1468da177	4546	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4547	{
<>	161:2cc1468da177	4548	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
<>	161:2cc1468da177	4549	}
<>	161:2cc1468da177	4550
<>	161:2cc1468da177	4551	/**
<>	161:2cc1468da177	4552	* @brief Generate Capture/Compare 3 event.
<>	161:2cc1468da177	4553	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
<>	161:2cc1468da177	4554	* @param TIMx Timer instance
<>	161:2cc1468da177	4555	* @retval None
<>	161:2cc1468da177	4556	*/
<>	161:2cc1468da177	4557	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4558	{
<>	161:2cc1468da177	4559	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
<>	161:2cc1468da177	4560	}
<>	161:2cc1468da177	4561
<>	161:2cc1468da177	4562	/**
<>	161:2cc1468da177	4563	* @brief Generate Capture/Compare 4 event.
<>	161:2cc1468da177	4564	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
<>	161:2cc1468da177	4565	* @param TIMx Timer instance
<>	161:2cc1468da177	4566	* @retval None
<>	161:2cc1468da177	4567	*/
<>	161:2cc1468da177	4568	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4569	{
<>	161:2cc1468da177	4570	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
<>	161:2cc1468da177	4571	}
<>	161:2cc1468da177	4572
<>	161:2cc1468da177	4573	/**
<>	161:2cc1468da177	4574	* @brief Generate commutation event.
<>	161:2cc1468da177	4575	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
<>	161:2cc1468da177	4576	* @param TIMx Timer instance
<>	161:2cc1468da177	4577	* @retval None
<>	161:2cc1468da177	4578	*/
<>	161:2cc1468da177	4579	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4580	{
<>	161:2cc1468da177	4581	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
<>	161:2cc1468da177	4582	}
<>	161:2cc1468da177	4583
<>	161:2cc1468da177	4584	/**
<>	161:2cc1468da177	4585	* @brief Generate trigger event.
<>	161:2cc1468da177	4586	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
<>	161:2cc1468da177	4587	* @param TIMx Timer instance
<>	161:2cc1468da177	4588	* @retval None
<>	161:2cc1468da177	4589	*/
<>	161:2cc1468da177	4590	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4591	{
<>	161:2cc1468da177	4592	SET_BIT(TIMx->EGR, TIM_EGR_TG);
<>	161:2cc1468da177	4593	}
<>	161:2cc1468da177	4594
<>	161:2cc1468da177	4595	/**
<>	161:2cc1468da177	4596	* @brief Generate break event.
<>	161:2cc1468da177	4597	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
<>	161:2cc1468da177	4598	* @param TIMx Timer instance
<>	161:2cc1468da177	4599	* @retval None
<>	161:2cc1468da177	4600	*/
<>	161:2cc1468da177	4601	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4602	{
<>	161:2cc1468da177	4603	SET_BIT(TIMx->EGR, TIM_EGR_BG);
<>	161:2cc1468da177	4604	}
<>	161:2cc1468da177	4605
<>	161:2cc1468da177	4606	/**
<>	161:2cc1468da177	4607	* @brief Generate break 2 event.
<>	161:2cc1468da177	4608	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
<>	161:2cc1468da177	4609	* @param TIMx Timer instance
<>	161:2cc1468da177	4610	* @retval None
<>	161:2cc1468da177	4611	*/
<>	161:2cc1468da177	4612	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
<>	161:2cc1468da177	4613	{
<>	161:2cc1468da177	4614	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
<>	161:2cc1468da177	4615	}
<>	161:2cc1468da177	4616
<>	161:2cc1468da177	4617	/**
<>	161:2cc1468da177	4618	* @}
<>	161:2cc1468da177	4619	*/
<>	161:2cc1468da177	4620
<>	161:2cc1468da177	4621	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	4622	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
<>	161:2cc1468da177	4623	* @{
<>	161:2cc1468da177	4624	*/
<>	161:2cc1468da177	4625
<>	161:2cc1468da177	4626	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
<>	161:2cc1468da177	4627	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
<>	161:2cc1468da177	4628	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
<>	161:2cc1468da177	4629	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
<>	161:2cc1468da177	4630	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
<>	161:2cc1468da177	4631	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
<>	161:2cc1468da177	4632	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
<>	161:2cc1468da177	4633	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
<>	161:2cc1468da177	4634	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
<>	161:2cc1468da177	4635	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
<>	161:2cc1468da177	4636	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
<>	161:2cc1468da177	4637	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
<>	161:2cc1468da177	4638	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
<>	161:2cc1468da177	4639	/**
<>	161:2cc1468da177	4640	* @}
<>	161:2cc1468da177	4641	*/
<>	161:2cc1468da177	4642	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	4643
<>	161:2cc1468da177	4644	/**
<>	161:2cc1468da177	4645	* @}
<>	161:2cc1468da177	4646	*/
<>	161:2cc1468da177	4647
<>	161:2cc1468da177	4648	/**
<>	161:2cc1468da177	4649	* @}
<>	161:2cc1468da177	4650	*/
<>	161:2cc1468da177	4651
<>	161:2cc1468da177	4652	#endif /* TIM1 \|\| TIM8 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\|TIM9 \|\| TIM10 \|\| TIM11 \|\| TIM12 \|\| TIM13 \|\| TIM14 \|\| TIM6 \|\| TIM7 */
<>	161:2cc1468da177	4653
<>	161:2cc1468da177	4654	/**
<>	161:2cc1468da177	4655	* @}
<>	161:2cc1468da177	4656	*/
<>	161:2cc1468da177	4657
<>	161:2cc1468da177	4658	#ifdef __cplusplus
<>	161:2cc1468da177	4659	}
<>	161:2cc1468da177	4660	#endif
<>	161:2cc1468da177	4661
<>	161:2cc1468da177	4662	#endif /* __STM32F7xx_LL_TIM_H */
<>	161:2cc1468da177	4663	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/