mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
161:2cc1468da177
Child:
182:a56a73fd2a6f
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**
<> 161:2cc1468da177 2 ******************************************************************************
<> 161:2cc1468da177 3 * @file stm32f7xx_ll_spi.c
<> 161:2cc1468da177 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 161:2cc1468da177 7 * @brief SPI LL module driver.
<> 161:2cc1468da177 8 ******************************************************************************
<> 161:2cc1468da177 9 * @attention
<> 161:2cc1468da177 10 *
<> 161:2cc1468da177 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 161:2cc1468da177 12 *
<> 161:2cc1468da177 13 * Redistribution and use in source and binary forms, with or without modification,
<> 161:2cc1468da177 14 * are permitted provided that the following conditions are met:
<> 161:2cc1468da177 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 161:2cc1468da177 16 * this list of conditions and the following disclaimer.
<> 161:2cc1468da177 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 161:2cc1468da177 18 * this list of conditions and the following disclaimer in the documentation
<> 161:2cc1468da177 19 * and/or other materials provided with the distribution.
<> 161:2cc1468da177 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 161:2cc1468da177 21 * may be used to endorse or promote products derived from this software
<> 161:2cc1468da177 22 * without specific prior written permission.
<> 161:2cc1468da177 23 *
<> 161:2cc1468da177 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 161:2cc1468da177 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 161:2cc1468da177 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 161:2cc1468da177 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 161:2cc1468da177 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 161:2cc1468da177 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 161:2cc1468da177 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 161:2cc1468da177 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 34 *
<> 161:2cc1468da177 35 ******************************************************************************
<> 161:2cc1468da177 36 */
<> 161:2cc1468da177 37 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 38
<> 161:2cc1468da177 39 /* Includes ------------------------------------------------------------------*/
<> 161:2cc1468da177 40 #include "stm32f7xx_ll_spi.h"
<> 161:2cc1468da177 41 #include "stm32f7xx_ll_bus.h"
<> 161:2cc1468da177 42 #include "stm32f7xx_ll_rcc.h"
<> 161:2cc1468da177 43
<> 161:2cc1468da177 44 #ifdef USE_FULL_ASSERT
<> 161:2cc1468da177 45 #include "stm32_assert.h"
<> 161:2cc1468da177 46 #else
<> 161:2cc1468da177 47 #define assert_param(expr) ((void)0U)
<> 161:2cc1468da177 48 #endif
<> 161:2cc1468da177 49
<> 161:2cc1468da177 50 /** @addtogroup STM32F7xx_LL_Driver
<> 161:2cc1468da177 51 * @{
<> 161:2cc1468da177 52 */
<> 161:2cc1468da177 53
<> 161:2cc1468da177 54 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
<> 161:2cc1468da177 55
<> 161:2cc1468da177 56 /** @addtogroup SPI_LL
<> 161:2cc1468da177 57 * @{
<> 161:2cc1468da177 58 */
<> 161:2cc1468da177 59
<> 161:2cc1468da177 60 /* Private types -------------------------------------------------------------*/
<> 161:2cc1468da177 61 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 62
<> 161:2cc1468da177 63 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 64 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
<> 161:2cc1468da177 65 * @{
<> 161:2cc1468da177 66 */
<> 161:2cc1468da177 67 /* SPI registers Masks */
<> 161:2cc1468da177 68 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
<> 161:2cc1468da177 69 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
<> 161:2cc1468da177 70 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
<> 161:2cc1468da177 71 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
<> 161:2cc1468da177 72 SPI_CR1_BIDIMODE)
<> 161:2cc1468da177 73 /**
<> 161:2cc1468da177 74 * @}
<> 161:2cc1468da177 75 */
<> 161:2cc1468da177 76
<> 161:2cc1468da177 77 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 78 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
<> 161:2cc1468da177 79 * @{
<> 161:2cc1468da177 80 */
<> 161:2cc1468da177 81 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
<> 161:2cc1468da177 82 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
<> 161:2cc1468da177 83 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
<> 161:2cc1468da177 84 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
<> 161:2cc1468da177 85
<> 161:2cc1468da177 86 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
<> 161:2cc1468da177 87 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
<> 161:2cc1468da177 88
<> 161:2cc1468da177 89 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
<> 161:2cc1468da177 90 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
<> 161:2cc1468da177 91 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
<> 161:2cc1468da177 92 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
<> 161:2cc1468da177 93 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
<> 161:2cc1468da177 94 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
<> 161:2cc1468da177 95 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
<> 161:2cc1468da177 96 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
<> 161:2cc1468da177 97 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
<> 161:2cc1468da177 98 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
<> 161:2cc1468da177 99 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
<> 161:2cc1468da177 100 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
<> 161:2cc1468da177 101 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
<> 161:2cc1468da177 102
<> 161:2cc1468da177 103 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
<> 161:2cc1468da177 104 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
<> 161:2cc1468da177 105
<> 161:2cc1468da177 106 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
<> 161:2cc1468da177 107 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
<> 161:2cc1468da177 108
<> 161:2cc1468da177 109 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
<> 161:2cc1468da177 110 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
<> 161:2cc1468da177 111 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
<> 161:2cc1468da177 112
<> 161:2cc1468da177 113 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
<> 161:2cc1468da177 114 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
<> 161:2cc1468da177 115 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
<> 161:2cc1468da177 116 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
<> 161:2cc1468da177 117 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
<> 161:2cc1468da177 118 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
<> 161:2cc1468da177 119 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
<> 161:2cc1468da177 120 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
<> 161:2cc1468da177 121
<> 161:2cc1468da177 122 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
<> 161:2cc1468da177 123 || ((__VALUE__) == LL_SPI_MSB_FIRST))
<> 161:2cc1468da177 124
<> 161:2cc1468da177 125 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
<> 161:2cc1468da177 126 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
<> 161:2cc1468da177 127
<> 161:2cc1468da177 128 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
<> 161:2cc1468da177 129
<> 161:2cc1468da177 130 /**
<> 161:2cc1468da177 131 * @}
<> 161:2cc1468da177 132 */
<> 161:2cc1468da177 133
<> 161:2cc1468da177 134 /* Private function prototypes -----------------------------------------------*/
<> 161:2cc1468da177 135
<> 161:2cc1468da177 136 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 137 /** @addtogroup SPI_LL_Exported_Functions
<> 161:2cc1468da177 138 * @{
<> 161:2cc1468da177 139 */
<> 161:2cc1468da177 140
<> 161:2cc1468da177 141 /** @addtogroup SPI_LL_EF_Init
<> 161:2cc1468da177 142 * @{
<> 161:2cc1468da177 143 */
<> 161:2cc1468da177 144
<> 161:2cc1468da177 145 /**
<> 161:2cc1468da177 146 * @brief De-initialize the SPI registers to their default reset values.
<> 161:2cc1468da177 147 * @param SPIx SPI Instance
<> 161:2cc1468da177 148 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 149 * - SUCCESS: SPI registers are de-initialized
<> 161:2cc1468da177 150 * - ERROR: SPI registers are not de-initialized
<> 161:2cc1468da177 151 */
<> 161:2cc1468da177 152 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 153 {
<> 161:2cc1468da177 154 ErrorStatus status = ERROR;
<> 161:2cc1468da177 155
<> 161:2cc1468da177 156 /* Check the parameters */
<> 161:2cc1468da177 157 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 161:2cc1468da177 158
<> 161:2cc1468da177 159 #if defined(SPI1)
<> 161:2cc1468da177 160 if (SPIx == SPI1)
<> 161:2cc1468da177 161 {
<> 161:2cc1468da177 162 /* Force reset of SPI clock */
<> 161:2cc1468da177 163 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
<> 161:2cc1468da177 164
<> 161:2cc1468da177 165 /* Release reset of SPI clock */
<> 161:2cc1468da177 166 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
<> 161:2cc1468da177 167
<> 161:2cc1468da177 168 status = SUCCESS;
<> 161:2cc1468da177 169 }
<> 161:2cc1468da177 170 #endif /* SPI1 */
<> 161:2cc1468da177 171 #if defined(SPI2)
<> 161:2cc1468da177 172 if (SPIx == SPI2)
<> 161:2cc1468da177 173 {
<> 161:2cc1468da177 174 /* Force reset of SPI clock */
<> 161:2cc1468da177 175 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 161:2cc1468da177 176
<> 161:2cc1468da177 177 /* Release reset of SPI clock */
<> 161:2cc1468da177 178 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
<> 161:2cc1468da177 179
<> 161:2cc1468da177 180 status = SUCCESS;
<> 161:2cc1468da177 181 }
<> 161:2cc1468da177 182 #endif /* SPI2 */
<> 161:2cc1468da177 183 #if defined(SPI3)
<> 161:2cc1468da177 184 if (SPIx == SPI3)
<> 161:2cc1468da177 185 {
<> 161:2cc1468da177 186 /* Force reset of SPI clock */
<> 161:2cc1468da177 187 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
<> 161:2cc1468da177 188
<> 161:2cc1468da177 189 /* Release reset of SPI clock */
<> 161:2cc1468da177 190 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
<> 161:2cc1468da177 191
<> 161:2cc1468da177 192 status = SUCCESS;
<> 161:2cc1468da177 193 }
<> 161:2cc1468da177 194 #endif /* SPI3 */
<> 161:2cc1468da177 195 #if defined(SPI4)
<> 161:2cc1468da177 196 if (SPIx == SPI4)
<> 161:2cc1468da177 197 {
<> 161:2cc1468da177 198 /* Force reset of SPI clock */
<> 161:2cc1468da177 199 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
<> 161:2cc1468da177 200
<> 161:2cc1468da177 201 /* Release reset of SPI clock */
<> 161:2cc1468da177 202 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
<> 161:2cc1468da177 203
<> 161:2cc1468da177 204 status = SUCCESS;
<> 161:2cc1468da177 205 }
<> 161:2cc1468da177 206 #endif /* SPI4 */
<> 161:2cc1468da177 207 #if defined(SPI5)
<> 161:2cc1468da177 208 if (SPIx == SPI5)
<> 161:2cc1468da177 209 {
<> 161:2cc1468da177 210 /* Force reset of SPI clock */
<> 161:2cc1468da177 211 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
<> 161:2cc1468da177 212
<> 161:2cc1468da177 213 /* Release reset of SPI clock */
<> 161:2cc1468da177 214 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
<> 161:2cc1468da177 215
<> 161:2cc1468da177 216 status = SUCCESS;
<> 161:2cc1468da177 217 }
<> 161:2cc1468da177 218 #endif /* SPI5 */
<> 161:2cc1468da177 219 #if defined(SPI6)
<> 161:2cc1468da177 220 if (SPIx == SPI6)
<> 161:2cc1468da177 221 {
<> 161:2cc1468da177 222 /* Force reset of SPI clock */
<> 161:2cc1468da177 223 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
<> 161:2cc1468da177 224
<> 161:2cc1468da177 225 /* Release reset of SPI clock */
<> 161:2cc1468da177 226 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
<> 161:2cc1468da177 227
<> 161:2cc1468da177 228 status = SUCCESS;
<> 161:2cc1468da177 229 }
<> 161:2cc1468da177 230 #endif /* SPI6 */
<> 161:2cc1468da177 231
<> 161:2cc1468da177 232 return status;
<> 161:2cc1468da177 233 }
<> 161:2cc1468da177 234
<> 161:2cc1468da177 235 /**
<> 161:2cc1468da177 236 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
<> 161:2cc1468da177 237 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
<> 161:2cc1468da177 238 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 161:2cc1468da177 239 * @param SPIx SPI Instance
<> 161:2cc1468da177 240 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 161:2cc1468da177 241 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
<> 161:2cc1468da177 242 */
<> 161:2cc1468da177 243 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
<> 161:2cc1468da177 244 {
<> 161:2cc1468da177 245 ErrorStatus status = ERROR;
<> 161:2cc1468da177 246
<> 161:2cc1468da177 247 /* Check the SPI Instance SPIx*/
<> 161:2cc1468da177 248 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
<> 161:2cc1468da177 249
<> 161:2cc1468da177 250 /* Check the SPI parameters from SPI_InitStruct*/
<> 161:2cc1468da177 251 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
<> 161:2cc1468da177 252 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
<> 161:2cc1468da177 253 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
<> 161:2cc1468da177 254 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
<> 161:2cc1468da177 255 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
<> 161:2cc1468da177 256 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
<> 161:2cc1468da177 257 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
<> 161:2cc1468da177 258 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
<> 161:2cc1468da177 259 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
<> 161:2cc1468da177 260
<> 161:2cc1468da177 261 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
<> 161:2cc1468da177 262 {
<> 161:2cc1468da177 263 /*---------------------------- SPIx CR1 Configuration ------------------------
<> 161:2cc1468da177 264 * Configure SPIx CR1 with parameters:
<> 161:2cc1468da177 265 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
<> 161:2cc1468da177 266 * - Master/Slave Mode: SPI_CR1_MSTR bit
<> 161:2cc1468da177 267 * - ClockPolarity: SPI_CR1_CPOL bit
<> 161:2cc1468da177 268 * - ClockPhase: SPI_CR1_CPHA bit
<> 161:2cc1468da177 269 * - NSS management: SPI_CR1_SSM bit
<> 161:2cc1468da177 270 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
<> 161:2cc1468da177 271 * - BitOrder: SPI_CR1_LSBFIRST bit
<> 161:2cc1468da177 272 * - CRCCalculation: SPI_CR1_CRCEN bit
<> 161:2cc1468da177 273 */
<> 161:2cc1468da177 274 MODIFY_REG(SPIx->CR1,
<> 161:2cc1468da177 275 SPI_CR1_CLEAR_MASK,
<> 161:2cc1468da177 276 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
<> 161:2cc1468da177 277 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
<> 161:2cc1468da177 278 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
<> 161:2cc1468da177 279 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
<> 161:2cc1468da177 280
<> 161:2cc1468da177 281 /*---------------------------- SPIx CR2 Configuration ------------------------
<> 161:2cc1468da177 282 * Configure SPIx CR2 with parameters:
<> 161:2cc1468da177 283 * - DataWidth: DS[3:0] bits
<> 161:2cc1468da177 284 * - NSS management: SSOE bit
<> 161:2cc1468da177 285 */
<> 161:2cc1468da177 286 MODIFY_REG(SPIx->CR2,
<> 161:2cc1468da177 287 SPI_CR2_DS | SPI_CR2_SSOE,
<> 161:2cc1468da177 288 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
<> 161:2cc1468da177 289
<> 161:2cc1468da177 290 /*---------------------------- SPIx CRCPR Configuration ----------------------
<> 161:2cc1468da177 291 * Configure SPIx CRCPR with parameters:
<> 161:2cc1468da177 292 * - CRCPoly: CRCPOLY[15:0] bits
<> 161:2cc1468da177 293 */
<> 161:2cc1468da177 294 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
<> 161:2cc1468da177 295 {
<> 161:2cc1468da177 296 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
<> 161:2cc1468da177 297 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
<> 161:2cc1468da177 298 }
<> 161:2cc1468da177 299 status = SUCCESS;
<> 161:2cc1468da177 300 }
<> 161:2cc1468da177 301
<> 161:2cc1468da177 302 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
<> 161:2cc1468da177 303 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 161:2cc1468da177 304 return status;
<> 161:2cc1468da177 305 }
<> 161:2cc1468da177 306
<> 161:2cc1468da177 307 /**
<> 161:2cc1468da177 308 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
<> 161:2cc1468da177 309 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
<> 161:2cc1468da177 310 * whose fields will be set to default values.
<> 161:2cc1468da177 311 * @retval None
<> 161:2cc1468da177 312 */
<> 161:2cc1468da177 313 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
<> 161:2cc1468da177 314 {
<> 161:2cc1468da177 315 /* Set SPI_InitStruct fields to default values */
<> 161:2cc1468da177 316 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
<> 161:2cc1468da177 317 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
<> 161:2cc1468da177 318 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
<> 161:2cc1468da177 319 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
<> 161:2cc1468da177 320 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
<> 161:2cc1468da177 321 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
<> 161:2cc1468da177 322 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
<> 161:2cc1468da177 323 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
<> 161:2cc1468da177 324 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
<> 161:2cc1468da177 325 SPI_InitStruct->CRCPoly = 7U;
<> 161:2cc1468da177 326 }
<> 161:2cc1468da177 327
<> 161:2cc1468da177 328 /**
<> 161:2cc1468da177 329 * @}
<> 161:2cc1468da177 330 */
<> 161:2cc1468da177 331
<> 161:2cc1468da177 332 /**
<> 161:2cc1468da177 333 * @}
<> 161:2cc1468da177 334 */
<> 161:2cc1468da177 335
<> 161:2cc1468da177 336 /**
<> 161:2cc1468da177 337 * @}
<> 161:2cc1468da177 338 */
<> 161:2cc1468da177 339
<> 161:2cc1468da177 340 /** @addtogroup I2S_LL
<> 161:2cc1468da177 341 * @{
<> 161:2cc1468da177 342 */
<> 161:2cc1468da177 343
<> 161:2cc1468da177 344 /* Private types -------------------------------------------------------------*/
<> 161:2cc1468da177 345 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 346 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 347 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
<> 161:2cc1468da177 348 * @{
<> 161:2cc1468da177 349 */
<> 161:2cc1468da177 350 /* I2S registers Masks */
<> 161:2cc1468da177 351 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
<> 161:2cc1468da177 352 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
<> 161:2cc1468da177 353 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
<> 161:2cc1468da177 354
<> 161:2cc1468da177 355 #define I2S_I2SPR_CLEAR_MASK 0x0002U
<> 161:2cc1468da177 356 /**
<> 161:2cc1468da177 357 * @}
<> 161:2cc1468da177 358 */
<> 161:2cc1468da177 359 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 360 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
<> 161:2cc1468da177 361 * @{
<> 161:2cc1468da177 362 */
<> 161:2cc1468da177 363
<> 161:2cc1468da177 364 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
<> 161:2cc1468da177 365 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
<> 161:2cc1468da177 366 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
<> 161:2cc1468da177 367 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
<> 161:2cc1468da177 368
<> 161:2cc1468da177 369 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
<> 161:2cc1468da177 370 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
<> 161:2cc1468da177 371
<> 161:2cc1468da177 372 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
<> 161:2cc1468da177 373 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
<> 161:2cc1468da177 374 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
<> 161:2cc1468da177 375 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
<> 161:2cc1468da177 376 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
<> 161:2cc1468da177 377
<> 161:2cc1468da177 378 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
<> 161:2cc1468da177 379 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
<> 161:2cc1468da177 380 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
<> 161:2cc1468da177 381 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
<> 161:2cc1468da177 382
<> 161:2cc1468da177 383 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
<> 161:2cc1468da177 384 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
<> 161:2cc1468da177 385
<> 161:2cc1468da177 386 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
<> 161:2cc1468da177 387 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
<> 161:2cc1468da177 388 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
<> 161:2cc1468da177 389
<> 161:2cc1468da177 390 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
<> 161:2cc1468da177 391
<> 161:2cc1468da177 392 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
<> 161:2cc1468da177 393 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
<> 161:2cc1468da177 394 /**
<> 161:2cc1468da177 395 * @}
<> 161:2cc1468da177 396 */
<> 161:2cc1468da177 397
<> 161:2cc1468da177 398 /* Private function prototypes -----------------------------------------------*/
<> 161:2cc1468da177 399
<> 161:2cc1468da177 400 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 401 /** @addtogroup I2S_LL_Exported_Functions
<> 161:2cc1468da177 402 * @{
<> 161:2cc1468da177 403 */
<> 161:2cc1468da177 404
<> 161:2cc1468da177 405 /** @addtogroup I2S_LL_EF_Init
<> 161:2cc1468da177 406 * @{
<> 161:2cc1468da177 407 */
<> 161:2cc1468da177 408
<> 161:2cc1468da177 409 /**
<> 161:2cc1468da177 410 * @brief De-initialize the SPI/I2S registers to their default reset values.
<> 161:2cc1468da177 411 * @param SPIx SPI Instance
<> 161:2cc1468da177 412 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 413 * - SUCCESS: SPI registers are de-initialized
<> 161:2cc1468da177 414 * - ERROR: SPI registers are not de-initialized
<> 161:2cc1468da177 415 */
<> 161:2cc1468da177 416 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
<> 161:2cc1468da177 417 {
<> 161:2cc1468da177 418 return LL_SPI_DeInit(SPIx);
<> 161:2cc1468da177 419 }
<> 161:2cc1468da177 420
<> 161:2cc1468da177 421 /**
<> 161:2cc1468da177 422 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
<> 161:2cc1468da177 423 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
<> 161:2cc1468da177 424 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 161:2cc1468da177 425 * @param SPIx SPI Instance
<> 161:2cc1468da177 426 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
<> 161:2cc1468da177 427 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 428 * - SUCCESS: SPI registers are Initialized
<> 161:2cc1468da177 429 * - ERROR: SPI registers are not Initialized
<> 161:2cc1468da177 430 */
<> 161:2cc1468da177 431 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
<> 161:2cc1468da177 432 {
<> 161:2cc1468da177 433 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
<> 161:2cc1468da177 434 uint32_t tmp = 0U;
<> 161:2cc1468da177 435 uint32_t sourceclock = 0U;
<> 161:2cc1468da177 436 ErrorStatus status = ERROR;
<> 161:2cc1468da177 437
<> 161:2cc1468da177 438 /* Check the I2S parameters */
<> 161:2cc1468da177 439 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
<> 161:2cc1468da177 440 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
<> 161:2cc1468da177 441 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
<> 161:2cc1468da177 442 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
<> 161:2cc1468da177 443 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
<> 161:2cc1468da177 444 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
<> 161:2cc1468da177 445 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
<> 161:2cc1468da177 446
<> 161:2cc1468da177 447 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
<> 161:2cc1468da177 448 {
<> 161:2cc1468da177 449 /*---------------------------- SPIx I2SCFGR Configuration --------------------
<> 161:2cc1468da177 450 * Configure SPIx I2SCFGR with parameters:
<> 161:2cc1468da177 451 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
<> 161:2cc1468da177 452 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
<> 161:2cc1468da177 453 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
<> 161:2cc1468da177 454 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
<> 161:2cc1468da177 455 */
<> 161:2cc1468da177 456
<> 161:2cc1468da177 457 /* Write to SPIx I2SCFGR */
<> 161:2cc1468da177 458 MODIFY_REG(SPIx->I2SCFGR,
<> 161:2cc1468da177 459 I2S_I2SCFGR_CLEAR_MASK,
<> 161:2cc1468da177 460 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
<> 161:2cc1468da177 461 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
<> 161:2cc1468da177 462 SPI_I2SCFGR_I2SMOD);
<> 161:2cc1468da177 463
<> 161:2cc1468da177 464 /*---------------------------- SPIx I2SPR Configuration ----------------------
<> 161:2cc1468da177 465 * Configure SPIx I2SPR with parameters:
<> 161:2cc1468da177 466 * - MCLKOutput: SPI_I2SPR_MCKOE bit
<> 161:2cc1468da177 467 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
<> 161:2cc1468da177 468 */
<> 161:2cc1468da177 469
<> 161:2cc1468da177 470 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
<> 161:2cc1468da177 471 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
<> 161:2cc1468da177 472 */
<> 161:2cc1468da177 473 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
<> 161:2cc1468da177 474 {
<> 161:2cc1468da177 475 /* Check the frame length (For the Prescaler computing)
<> 161:2cc1468da177 476 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
<> 161:2cc1468da177 477 */
<> 161:2cc1468da177 478 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
<> 161:2cc1468da177 479 {
<> 161:2cc1468da177 480 /* Packet length is 32 bits */
<> 161:2cc1468da177 481 packetlength = 2U;
<> 161:2cc1468da177 482 }
<> 161:2cc1468da177 483
<> 161:2cc1468da177 484 /* If an external I2S clock has to be used, the specific define should be set
<> 161:2cc1468da177 485 in the project configuration or in the stm32f7xx_ll_rcc.h file */
<> 161:2cc1468da177 486 /* Get the I2S source clock value */
<> 161:2cc1468da177 487 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
<> 161:2cc1468da177 488
<> 161:2cc1468da177 489 /* Compute the Real divider depending on the MCLK output state with a floating point */
<> 161:2cc1468da177 490 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
<> 161:2cc1468da177 491 {
<> 161:2cc1468da177 492 /* MCLK output is enabled */
<> 161:2cc1468da177 493 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
<> 161:2cc1468da177 494 }
<> 161:2cc1468da177 495 else
<> 161:2cc1468da177 496 {
<> 161:2cc1468da177 497 /* MCLK output is disabled */
<> 161:2cc1468da177 498 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
<> 161:2cc1468da177 499 }
<> 161:2cc1468da177 500
<> 161:2cc1468da177 501 /* Remove the floating point */
<> 161:2cc1468da177 502 tmp = tmp / 10U;
<> 161:2cc1468da177 503
<> 161:2cc1468da177 504 /* Check the parity of the divider */
<> 161:2cc1468da177 505 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
<> 161:2cc1468da177 506
<> 161:2cc1468da177 507 /* Compute the i2sdiv prescaler */
<> 161:2cc1468da177 508 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
<> 161:2cc1468da177 509
<> 161:2cc1468da177 510 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 161:2cc1468da177 511 i2sodd = (uint16_t)(i2sodd << 8U);
<> 161:2cc1468da177 512 }
<> 161:2cc1468da177 513
<> 161:2cc1468da177 514 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 161:2cc1468da177 515 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
<> 161:2cc1468da177 516 {
<> 161:2cc1468da177 517 /* Set the default values */
<> 161:2cc1468da177 518 i2sdiv = 2U;
<> 161:2cc1468da177 519 i2sodd = 0U;
<> 161:2cc1468da177 520 }
<> 161:2cc1468da177 521
<> 161:2cc1468da177 522 /* Write to SPIx I2SPR register the computed value */
<> 161:2cc1468da177 523 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
<> 161:2cc1468da177 524
<> 161:2cc1468da177 525 status = SUCCESS;
<> 161:2cc1468da177 526 }
<> 161:2cc1468da177 527 return status;
<> 161:2cc1468da177 528 }
<> 161:2cc1468da177 529
<> 161:2cc1468da177 530 /**
<> 161:2cc1468da177 531 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
<> 161:2cc1468da177 532 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
<> 161:2cc1468da177 533 * whose fields will be set to default values.
<> 161:2cc1468da177 534 * @retval None
<> 161:2cc1468da177 535 */
<> 161:2cc1468da177 536 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
<> 161:2cc1468da177 537 {
<> 161:2cc1468da177 538 /*--------------- Reset I2S init structure parameters values -----------------*/
<> 161:2cc1468da177 539 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
<> 161:2cc1468da177 540 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
<> 161:2cc1468da177 541 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
<> 161:2cc1468da177 542 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
<> 161:2cc1468da177 543 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
<> 161:2cc1468da177 544 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
<> 161:2cc1468da177 545 }
<> 161:2cc1468da177 546
<> 161:2cc1468da177 547 /**
<> 161:2cc1468da177 548 * @brief Set linear and parity prescaler.
<> 161:2cc1468da177 549 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
<> 161:2cc1468da177 550 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
<> 161:2cc1468da177 551 * @param SPIx SPI Instance
<> 161:2cc1468da177 552 * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
<> 161:2cc1468da177 553 * @param PrescalerParity This parameter can be one of the following values:
<> 161:2cc1468da177 554 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
<> 161:2cc1468da177 555 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
<> 161:2cc1468da177 556 * @retval None
<> 161:2cc1468da177 557 */
<> 161:2cc1468da177 558 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
<> 161:2cc1468da177 559 {
<> 161:2cc1468da177 560 /* Check the I2S parameters */
<> 161:2cc1468da177 561 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
<> 161:2cc1468da177 562 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
<> 161:2cc1468da177 563 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
<> 161:2cc1468da177 564
<> 161:2cc1468da177 565 /* Write to SPIx I2SPR */
<> 161:2cc1468da177 566 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
<> 161:2cc1468da177 567 }
<> 161:2cc1468da177 568
<> 161:2cc1468da177 569 /**
<> 161:2cc1468da177 570 * @}
<> 161:2cc1468da177 571 */
<> 161:2cc1468da177 572
<> 161:2cc1468da177 573 /**
<> 161:2cc1468da177 574 * @}
<> 161:2cc1468da177 575 */
<> 161:2cc1468da177 576
<> 161:2cc1468da177 577 /**
<> 161:2cc1468da177 578 * @}
<> 161:2cc1468da177 579 */
<> 161:2cc1468da177 580
<> 161:2cc1468da177 581 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
<> 161:2cc1468da177 582
<> 161:2cc1468da177 583 /**
<> 161:2cc1468da177 584 * @}
<> 161:2cc1468da177 585 */
<> 161:2cc1468da177 586
<> 161:2cc1468da177 587 #endif /* USE_FULL_LL_DRIVER */
<> 161:2cc1468da177 588
<> 161:2cc1468da177 589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/