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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 168:9672193075cf

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_ll_sdmmc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of SDMMC HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F7xx_LL_SDMMC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F7xx_LL_SDMMC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f7xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F7xx_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup SDMMC_LL
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief SDMMC Configuration Structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
<>	144:ef7eb2e8f9f7	68	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
<>	144:ef7eb2e8f9f7	71	enabled or disabled.
<>	144:ef7eb2e8f9f7	72	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
<>	144:ef7eb2e8f9f7	73
<>	144:ef7eb2e8f9f7	74	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
<>	144:ef7eb2e8f9f7	75	disabled when the bus is idle.
<>	144:ef7eb2e8f9f7	76	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
<>	144:ef7eb2e8f9f7	79	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
<>	144:ef7eb2e8f9f7	80
<>	144:ef7eb2e8f9f7	81	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
<>	144:ef7eb2e8f9f7	82	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
<>	144:ef7eb2e8f9f7	85	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	}SDMMC_InitTypeDef;
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	/**
<>	144:ef7eb2e8f9f7	91	* @brief SDMMC Command Control structure
<>	144:ef7eb2e8f9f7	92	*/
<>	144:ef7eb2e8f9f7	93	typedef struct
<>	144:ef7eb2e8f9f7	94	{
<>	144:ef7eb2e8f9f7	95	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
<>	144:ef7eb2e8f9f7	96	to a card as part of a command message. If a command
<>	144:ef7eb2e8f9f7	97	contains an argument, it must be loaded into this register
<>	144:ef7eb2e8f9f7	98	before writing the command to the command register. */
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
<>	144:ef7eb2e8f9f7	101	Max_Data = 64 */
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	uint32_t Response; /*!< Specifies the SDMMC response type.
<>	144:ef7eb2e8f9f7	104	This parameter can be a value of @ref SDMMC_LL_Response_Type */
<>	144:ef7eb2e8f9f7	105
<>	144:ef7eb2e8f9f7	106	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
<>	144:ef7eb2e8f9f7	107	enabled or disabled.
<>	144:ef7eb2e8f9f7	108	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
<>	144:ef7eb2e8f9f7	111	is enabled or disabled.
<>	144:ef7eb2e8f9f7	112	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
<>	144:ef7eb2e8f9f7	113	}SDMMC_CmdInitTypeDef;
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	/**
<>	144:ef7eb2e8f9f7	117	* @brief SDMMC Data Control structure
<>	144:ef7eb2e8f9f7	118	*/
<>	144:ef7eb2e8f9f7	119	typedef struct
<>	144:ef7eb2e8f9f7	120	{
<>	144:ef7eb2e8f9f7	121	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
<>	144:ef7eb2e8f9f7	126	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
<>	144:ef7eb2e8f9f7	129	is a read or write.
<>	144:ef7eb2e8f9f7	130	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
<>	144:ef7eb2e8f9f7	133	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
<>	144:ef7eb2e8f9f7	136	is enabled or disabled.
<>	144:ef7eb2e8f9f7	137	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
<>	144:ef7eb2e8f9f7	138	}SDMMC_DataInitTypeDef;
<>	144:ef7eb2e8f9f7	139
<>	144:ef7eb2e8f9f7	140	/**
<>	144:ef7eb2e8f9f7	141	* @}
<>	144:ef7eb2e8f9f7	142	*/
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	145	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
<>	144:ef7eb2e8f9f7	146	* @{
<>	144:ef7eb2e8f9f7	147	*/
<>	161:2cc1468da177	148	#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
<>	161:2cc1468da177	149	#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /!< Command response received (but CRC check failed) /
<>	161:2cc1468da177	150	#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /!< Data block sent/received (CRC check failed) /
<>	161:2cc1468da177	151	#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /!< Command response timeout /
<>	161:2cc1468da177	152	#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /!< Data timeout /
<>	161:2cc1468da177	153	#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /!< Transmit FIFO underrun /
<>	161:2cc1468da177	154	#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /!< Receive FIFO overrun /
<>	161:2cc1468da177	155	#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /!< Misaligned address /
<>	161:2cc1468da177	156	#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
<>	161:2cc1468da177	157	number of transferred bytes does not match the block length */
<>	161:2cc1468da177	158	#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /!< An error in the sequence of erase command occurs /
<>	161:2cc1468da177	159	#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /!< An invalid selection for erase groups /
<>	161:2cc1468da177	160	#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /!< Attempt to program a write protect block /
<>	161:2cc1468da177	161	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
<>	161:2cc1468da177	162	command or if there was an attempt to access a locked card */
<>	161:2cc1468da177	163	#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /!< CRC check of the previous command failed /
<>	161:2cc1468da177	164	#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /!< Command is not legal for the card state /
<>	161:2cc1468da177	165	#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /!< Card internal ECC was applied but failed to correct the data /
<>	161:2cc1468da177	166	#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /!< Internal card controller error /
<>	161:2cc1468da177	167	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /!< General or unknown error /
<>	161:2cc1468da177	168	#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /!< The card could not sustain data reading in stream rmode /
<>	161:2cc1468da177	169	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /!< The card could not sustain data programming in stream mode /
<>	161:2cc1468da177	170	#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /!< CID/CSD overwrite error /
<>	161:2cc1468da177	171	#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /!< Only partial address space was erased /
<>	161:2cc1468da177	172	#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /!< Command has been executed without using internal ECC /
<>	161:2cc1468da177	173	#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
<>	161:2cc1468da177	174	of erase sequence command was received */
<>	161:2cc1468da177	175	#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /!< Error in sequence of authentication /
<>	161:2cc1468da177	176	#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /!< Error in case of invalid voltage range /
<>	161:2cc1468da177	177	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /!< Error when addressed block is out of range /
<>	161:2cc1468da177	178	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /!< Error when command request is not applicable /
<>	161:2cc1468da177	179	#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /!< the used parameter is not valid /
<>	161:2cc1468da177	180	#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /!< Error when feature is not insupported /
<>	161:2cc1468da177	181	#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /!< Error when transfer process is busy /
<>	161:2cc1468da177	182	#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /!< Error while DMA transfer /
<>	161:2cc1468da177	183	#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /!< Timeout error /
<>	161:2cc1468da177	184
<>	161:2cc1468da177	185	/**
<>	161:2cc1468da177	186	* @brief SDMMC Commands Index
<>	161:2cc1468da177	187	*/
<>	161:2cc1468da177	188	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /!< Resets the SD memory card. /
<>	161:2cc1468da177	189	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /!< Sends host capacity support information and activates the card's initialization process. /
<>	161:2cc1468da177	190	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
<>	161:2cc1468da177	191	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /!< Asks the card to publish a new relative address (RCA). /
<>	161:2cc1468da177	192	#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /!< Programs the DSR of all cards. /
<>	161:2cc1468da177	193	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
<>	161:2cc1468da177	194	operating condition register (OCR) content in the response on the CMD line. */
<>	161:2cc1468da177	195	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
<>	161:2cc1468da177	196	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /!< Selects the card by its own relative address and gets deselected by any other address /
<>	161:2cc1468da177	197	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
<>	161:2cc1468da177	198	and asks the card whether card supports voltage. */
<>	161:2cc1468da177	199	#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
<>	161:2cc1468da177	200	#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /!< Addressed card sends its card identification (CID) on the CMD line. /
<>	161:2cc1468da177	201	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /!< SD card doesn't support it. /
<>	161:2cc1468da177	202	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /!< Forces the card to stop transmission. /
<>	161:2cc1468da177	203	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /!< Addressed card sends its status register. /
<>	161:2cc1468da177	204	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /!< Reserved /
<>	161:2cc1468da177	205	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /!< Sends an addressed card into the inactive state. /
<>	161:2cc1468da177	206	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
<>	161:2cc1468da177	207	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
<>	161:2cc1468da177	208	for SDHS and SDXC. */
<>	161:2cc1468da177	209	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
<>	161:2cc1468da177	210	fixed 512 bytes in case of SDHC and SDXC. */
<>	161:2cc1468da177	211	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
<>	161:2cc1468da177	212	STOP_TRANSMISSION command. */
<>	161:2cc1468da177	213	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
<>	161:2cc1468da177	214	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /!< Speed class control command. /
<>	161:2cc1468da177	215	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /!< Specify block count for CMD18 and CMD25. /
<>	161:2cc1468da177	216	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
<>	161:2cc1468da177	217	fixed 512 bytes in case of SDHC and SDXC. */
<>	161:2cc1468da177	218	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
<>	161:2cc1468da177	219	#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /!< Reserved for manufacturers. /
<>	161:2cc1468da177	220	#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /!< Programming of the programmable bits of the CSD. /
<>	161:2cc1468da177	221	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /!< Sets the write protection bit of the addressed group. /
<>	161:2cc1468da177	222	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /!< Clears the write protection bit of the addressed group. /
<>	161:2cc1468da177	223	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /!< Asks the card to send the status of the write protection bits. /
<>	161:2cc1468da177	224	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /!< Sets the address of the first write block to be erased. (For SD card only). /
<>	161:2cc1468da177	225	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /!< Sets the address of the last write block of the continuous range to be erased. /
<>	161:2cc1468da177	226	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
<>	161:2cc1468da177	227	system set by switch function command (CMD6). */
<>	161:2cc1468da177	228	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
<>	161:2cc1468da177	229	Reserved for each command system set by switch function command (CMD6). */
<>	161:2cc1468da177	230	#define SDMMC_CMD_ERASE ((uint8_t)38U) /!< Reserved for SD security applications. /
<>	161:2cc1468da177	231	#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /!< SD card doesn't support it (Reserved). /
<>	161:2cc1468da177	232	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /!< SD card doesn't support it (Reserved). /
<>	161:2cc1468da177	233	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
<>	161:2cc1468da177	234	the SET_BLOCK_LEN command. */
<>	161:2cc1468da177	235	#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
<>	161:2cc1468da177	236	than a standard command. */
<>	161:2cc1468da177	237	#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
<>	161:2cc1468da177	238	for general purpose/application specific commands. */
<>	161:2cc1468da177	239	#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /!< No command /
<>	161:2cc1468da177	240
<>	161:2cc1468da177	241	/**
<>	161:2cc1468da177	242	* @brief Following commands are SD Card Specific commands.
<>	161:2cc1468da177	243	* SDMMC_APP_CMD should be sent before sending these commands.
<>	161:2cc1468da177	244	*/
<>	161:2cc1468da177	245	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
<>	161:2cc1468da177	246	widths are given in SCR register. */
<>	161:2cc1468da177	247	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /!< (ACMD13) Sends the SD status. /
<>	161:2cc1468da177	248	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
<>	161:2cc1468da177	249	32bit+CRC data block. */
<>	161:2cc1468da177	250	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
<>	161:2cc1468da177	251	send its operating condition register (OCR) content in the response on the CMD line. */
<>	161:2cc1468da177	252	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
<>	161:2cc1468da177	253	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /!< Reads the SD Configuration Register (SCR). /
<>	161:2cc1468da177	254	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /!< For SD I/O card only, reserved for security specification. /
<>	161:2cc1468da177	255	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /!< For SD I/O card only, reserved for security specification. /
<>	161:2cc1468da177	256
<>	161:2cc1468da177	257	/**
<>	161:2cc1468da177	258	* @brief Following commands are SD Card Specific security commands.
<>	161:2cc1468da177	259	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
<>	161:2cc1468da177	260	*/
<>	161:2cc1468da177	261	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
<>	161:2cc1468da177	262	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
<>	161:2cc1468da177	263	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
<>	161:2cc1468da177	264	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
<>	161:2cc1468da177	265	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
<>	161:2cc1468da177	266	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
<>	161:2cc1468da177	267	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
<>	161:2cc1468da177	268	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
<>	161:2cc1468da177	269	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
<>	161:2cc1468da177	270	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
<>	161:2cc1468da177	271	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
<>	161:2cc1468da177	272
<>	161:2cc1468da177	273	/**
<>	161:2cc1468da177	274	* @brief Masks for errors Card Status R1 (OCR Register)
<>	161:2cc1468da177	275	*/
<>	161:2cc1468da177	276	#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
<>	161:2cc1468da177	277	#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
<>	161:2cc1468da177	278	#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
<>	161:2cc1468da177	279	#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
<>	161:2cc1468da177	280	#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
<>	161:2cc1468da177	281	#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
<>	161:2cc1468da177	282	#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
<>	161:2cc1468da177	283	#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
<>	161:2cc1468da177	284	#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
<>	161:2cc1468da177	285	#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
<>	161:2cc1468da177	286	#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
<>	161:2cc1468da177	287	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
<>	161:2cc1468da177	288	#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
<>	161:2cc1468da177	289	#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
<>	161:2cc1468da177	290	#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
<>	161:2cc1468da177	291	#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
<>	161:2cc1468da177	292	#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
<>	161:2cc1468da177	293	#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
<>	161:2cc1468da177	294	#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
<>	161:2cc1468da177	295	#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
<>	161:2cc1468da177	296
<>	161:2cc1468da177	297	/**
<>	161:2cc1468da177	298	* @brief Masks for R6 Response
<>	161:2cc1468da177	299	*/
<>	161:2cc1468da177	300	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
<>	161:2cc1468da177	301	#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
<>	161:2cc1468da177	302	#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
<>	161:2cc1468da177	303
<>	161:2cc1468da177	304	#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
<>	161:2cc1468da177	305	#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
<>	161:2cc1468da177	306	#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
<>	161:2cc1468da177	307	#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
<>	161:2cc1468da177	308
<>	161:2cc1468da177	309	#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
<>	161:2cc1468da177	310
<>	161:2cc1468da177	311	#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
<>	161:2cc1468da177	312
<>	161:2cc1468da177	313	#define SDMMC_ALLZERO ((uint32_t)0x00000000U)
<>	161:2cc1468da177	314
<>	161:2cc1468da177	315	#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
<>	161:2cc1468da177	316	#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
<>	161:2cc1468da177	317	#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
<>	161:2cc1468da177	318
<>	161:2cc1468da177	319	#define SDMMC_DATATIMEOUT ((uint32_t)0x00100000U)
<>	161:2cc1468da177	320
<>	161:2cc1468da177	321	#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
<>	161:2cc1468da177	322	#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
<>	161:2cc1468da177	323	#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
<>	161:2cc1468da177	324	#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
<>	161:2cc1468da177	325	#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
<>	161:2cc1468da177	326
<>	161:2cc1468da177	327	#define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
<>	161:2cc1468da177	328	#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
<>	161:2cc1468da177	329
<>	161:2cc1468da177	330	/**
<>	161:2cc1468da177	331	* @brief Command Class supported
<>	161:2cc1468da177	332	*/
<>	161:2cc1468da177	333	#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
<>	161:2cc1468da177	334
<>	161:2cc1468da177	335	#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
<>	161:2cc1468da177	336	#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
<>	161:2cc1468da177	337
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
<>	144:ef7eb2e8f9f7	340	* @{
<>	144:ef7eb2e8f9f7	341	*/
<>	144:ef7eb2e8f9f7	342	#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	343	#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
<>	144:ef7eb2e8f9f7	344
<>	144:ef7eb2e8f9f7	345	#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) \|\| \
<>	161:2cc1468da177	346	((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
<>	144:ef7eb2e8f9f7	347	/**
<>	144:ef7eb2e8f9f7	348	* @}
<>	144:ef7eb2e8f9f7	349	*/
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
<>	144:ef7eb2e8f9f7	352	* @{
<>	144:ef7eb2e8f9f7	353	*/
<>	144:ef7eb2e8f9f7	354	#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	355	#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) \|\| \
<>	161:2cc1468da177	358	((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
<>	144:ef7eb2e8f9f7	359	/**
<>	144:ef7eb2e8f9f7	360	* @}
<>	144:ef7eb2e8f9f7	361	*/
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363	/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
<>	144:ef7eb2e8f9f7	364	* @{
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366	#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	367	#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) \|\| \
<>	161:2cc1468da177	370	((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
<>	144:ef7eb2e8f9f7	371	/**
<>	144:ef7eb2e8f9f7	372	* @}
<>	144:ef7eb2e8f9f7	373	*/
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	/** @defgroup SDMMC_LL_Bus_Wide Bus Width
<>	144:ef7eb2e8f9f7	376	* @{
<>	144:ef7eb2e8f9f7	377	*/
<>	144:ef7eb2e8f9f7	378	#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	379	#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
<>	144:ef7eb2e8f9f7	380	#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) \|\| \
<>	161:2cc1468da177	383	((WIDE) == SDMMC_BUS_WIDE_4B) \|\| \
<>	161:2cc1468da177	384	((WIDE) == SDMMC_BUS_WIDE_8B))
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @}
<>	144:ef7eb2e8f9f7	387	*/
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
<>	144:ef7eb2e8f9f7	390	* @{
<>	144:ef7eb2e8f9f7	391	*/
<>	144:ef7eb2e8f9f7	392	#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	393	#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
<>	161:2cc1468da177	396	((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
<>	144:ef7eb2e8f9f7	397	/**
<>	144:ef7eb2e8f9f7	398	* @}
<>	144:ef7eb2e8f9f7	399	*/
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	/** @defgroup SDMMC_LL_Clock_Division Clock Division
<>	144:ef7eb2e8f9f7	402	* @{
<>	144:ef7eb2e8f9f7	403	*/
<>	144:ef7eb2e8f9f7	404	#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
<>	144:ef7eb2e8f9f7	405	/**
<>	144:ef7eb2e8f9f7	406	* @}
<>	144:ef7eb2e8f9f7	407	*/
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/** @defgroup SDMMC_LL_Command_Index Command Index
<>	144:ef7eb2e8f9f7	410	* @{
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412	#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
<>	144:ef7eb2e8f9f7	413	/**
<>	144:ef7eb2e8f9f7	414	* @}
<>	144:ef7eb2e8f9f7	415	*/
<>	144:ef7eb2e8f9f7	416
<>	144:ef7eb2e8f9f7	417	/** @defgroup SDMMC_LL_Response_Type Response Type
<>	144:ef7eb2e8f9f7	418	* @{
<>	144:ef7eb2e8f9f7	419	*/
<>	144:ef7eb2e8f9f7	420	#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	421	#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
<>	144:ef7eb2e8f9f7	422	#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) \|\| \
<>	161:2cc1468da177	425	((RESPONSE) == SDMMC_RESPONSE_SHORT) \|\| \
<>	161:2cc1468da177	426	((RESPONSE) == SDMMC_RESPONSE_LONG))
<>	144:ef7eb2e8f9f7	427	/**
<>	144:ef7eb2e8f9f7	428	* @}
<>	144:ef7eb2e8f9f7	429	*/
<>	144:ef7eb2e8f9f7	430
<>	144:ef7eb2e8f9f7	431	/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
<>	144:ef7eb2e8f9f7	432	* @{
<>	144:ef7eb2e8f9f7	433	*/
<>	144:ef7eb2e8f9f7	434	#define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	435	#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
<>	144:ef7eb2e8f9f7	436	#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) \|\| \
<>	161:2cc1468da177	439	((WAIT) == SDMMC_WAIT_IT) \|\| \
<>	161:2cc1468da177	440	((WAIT) == SDMMC_WAIT_PEND))
<>	144:ef7eb2e8f9f7	441	/**
<>	144:ef7eb2e8f9f7	442	* @}
<>	144:ef7eb2e8f9f7	443	*/
<>	144:ef7eb2e8f9f7	444
<>	144:ef7eb2e8f9f7	445	/** @defgroup SDMMC_LL_CPSM_State CPSM State
<>	144:ef7eb2e8f9f7	446	* @{
<>	144:ef7eb2e8f9f7	447	*/
<>	144:ef7eb2e8f9f7	448	#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	449	#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) \|\| \
<>	161:2cc1468da177	452	((CPSM) == SDMMC_CPSM_ENABLE))
<>	144:ef7eb2e8f9f7	453	/**
<>	144:ef7eb2e8f9f7	454	* @}
<>	144:ef7eb2e8f9f7	455	*/
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	/** @defgroup SDMMC_LL_Response_Registers Response Register
<>	144:ef7eb2e8f9f7	458	* @{
<>	144:ef7eb2e8f9f7	459	*/
<>	144:ef7eb2e8f9f7	460	#define SDMMC_RESP1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	461	#define SDMMC_RESP2 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	462	#define SDMMC_RESP3 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	463	#define SDMMC_RESP4 ((uint32_t)0x0000000C)
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) \|\| \
<>	161:2cc1468da177	466	((RESP) == SDMMC_RESP2) \|\| \
<>	161:2cc1468da177	467	((RESP) == SDMMC_RESP3) \|\| \
<>	161:2cc1468da177	468	((RESP) == SDMMC_RESP4))
<>	144:ef7eb2e8f9f7	469	/**
<>	144:ef7eb2e8f9f7	470	* @}
<>	144:ef7eb2e8f9f7	471	*/
<>	144:ef7eb2e8f9f7	472
<>	144:ef7eb2e8f9f7	473	/** @defgroup SDMMC_LL_Data_Length Data Lenght
<>	144:ef7eb2e8f9f7	474	* @{
<>	144:ef7eb2e8f9f7	475	*/
<>	144:ef7eb2e8f9f7	476	#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
<>	144:ef7eb2e8f9f7	477	/**
<>	144:ef7eb2e8f9f7	478	* @}
<>	144:ef7eb2e8f9f7	479	*/
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
<>	144:ef7eb2e8f9f7	482	* @{
<>	144:ef7eb2e8f9f7	483	*/
<>	144:ef7eb2e8f9f7	484	#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	485	#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
<>	144:ef7eb2e8f9f7	486	#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
<>	144:ef7eb2e8f9f7	487	#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1)
<>	144:ef7eb2e8f9f7	488	#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
<>	144:ef7eb2e8f9f7	489	#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2)
<>	144:ef7eb2e8f9f7	490	#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
<>	144:ef7eb2e8f9f7	491	#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2)
<>	144:ef7eb2e8f9f7	492	#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
<>	144:ef7eb2e8f9f7	493	#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_3)
<>	144:ef7eb2e8f9f7	494	#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
<>	144:ef7eb2e8f9f7	495	#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_3)
<>	144:ef7eb2e8f9f7	496	#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
<>	144:ef7eb2e8f9f7	497	#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
<>	144:ef7eb2e8f9f7	498	#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1\|SDMMC_DCTRL_DBLOCKSIZE_2\|SDMMC_DCTRL_DBLOCKSIZE_3)
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) \|\| \
<>	161:2cc1468da177	501	((SIZE) == SDMMC_DATABLOCK_SIZE_2B) \|\| \
<>	161:2cc1468da177	502	((SIZE) == SDMMC_DATABLOCK_SIZE_4B) \|\| \
<>	161:2cc1468da177	503	((SIZE) == SDMMC_DATABLOCK_SIZE_8B) \|\| \
<>	161:2cc1468da177	504	((SIZE) == SDMMC_DATABLOCK_SIZE_16B) \|\| \
<>	161:2cc1468da177	505	((SIZE) == SDMMC_DATABLOCK_SIZE_32B) \|\| \
<>	161:2cc1468da177	506	((SIZE) == SDMMC_DATABLOCK_SIZE_64B) \|\| \
<>	161:2cc1468da177	507	((SIZE) == SDMMC_DATABLOCK_SIZE_128B) \|\| \
<>	161:2cc1468da177	508	((SIZE) == SDMMC_DATABLOCK_SIZE_256B) \|\| \
<>	161:2cc1468da177	509	((SIZE) == SDMMC_DATABLOCK_SIZE_512B) \|\| \
<>	161:2cc1468da177	510	((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) \|\| \
<>	161:2cc1468da177	511	((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) \|\| \
<>	161:2cc1468da177	512	((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) \|\| \
<>	161:2cc1468da177	513	((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) \|\| \
<>	161:2cc1468da177	514	((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
<>	144:ef7eb2e8f9f7	515	/**
<>	144:ef7eb2e8f9f7	516	* @}
<>	144:ef7eb2e8f9f7	517	*/
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
<>	144:ef7eb2e8f9f7	520	* @{
<>	144:ef7eb2e8f9f7	521	*/
<>	144:ef7eb2e8f9f7	522	#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	523	#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) \|\| \
<>	161:2cc1468da177	526	((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
<>	144:ef7eb2e8f9f7	527	/**
<>	144:ef7eb2e8f9f7	528	* @}
<>	144:ef7eb2e8f9f7	529	*/
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
<>	144:ef7eb2e8f9f7	532	* @{
<>	144:ef7eb2e8f9f7	533	*/
<>	144:ef7eb2e8f9f7	534	#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	535	#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
<>	144:ef7eb2e8f9f7	536
<>	144:ef7eb2e8f9f7	537	#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) \|\| \
<>	161:2cc1468da177	538	((MODE) == SDMMC_TRANSFER_MODE_STREAM))
<>	144:ef7eb2e8f9f7	539	/**
<>	144:ef7eb2e8f9f7	540	* @}
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/** @defgroup SDMMC_LL_DPSM_State DPSM State
<>	144:ef7eb2e8f9f7	544	* @{
<>	144:ef7eb2e8f9f7	545	*/
<>	144:ef7eb2e8f9f7	546	#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	547	#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
<>	144:ef7eb2e8f9f7	548
<>	144:ef7eb2e8f9f7	549	#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) \|\|\
<>	161:2cc1468da177	550	((DPSM) == SDMMC_DPSM_ENABLE))
<>	144:ef7eb2e8f9f7	551	/**
<>	144:ef7eb2e8f9f7	552	* @}
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
<>	144:ef7eb2e8f9f7	556	* @{
<>	144:ef7eb2e8f9f7	557	*/
<>	144:ef7eb2e8f9f7	558	#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	559	#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561	#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) \|\| \
<>	161:2cc1468da177	562	((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
<>	144:ef7eb2e8f9f7	563	/**
<>	144:ef7eb2e8f9f7	564	* @}
<>	144:ef7eb2e8f9f7	565	*/
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
<>	144:ef7eb2e8f9f7	568	* @{
<>	144:ef7eb2e8f9f7	569	*/
<>	144:ef7eb2e8f9f7	570	#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
<>	144:ef7eb2e8f9f7	571	#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
<>	144:ef7eb2e8f9f7	572	#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
<>	144:ef7eb2e8f9f7	573	#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
<>	144:ef7eb2e8f9f7	574	#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
<>	144:ef7eb2e8f9f7	575	#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
<>	144:ef7eb2e8f9f7	576	#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
<>	144:ef7eb2e8f9f7	577	#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
<>	144:ef7eb2e8f9f7	578	#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
<>	144:ef7eb2e8f9f7	579	#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
<>	144:ef7eb2e8f9f7	580	#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
<>	144:ef7eb2e8f9f7	581	#define SDMMC_IT_TXACT SDMMC_STA_TXACT
<>	144:ef7eb2e8f9f7	582	#define SDMMC_IT_RXACT SDMMC_STA_RXACT
<>	144:ef7eb2e8f9f7	583	#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
<>	144:ef7eb2e8f9f7	584	#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
<>	144:ef7eb2e8f9f7	585	#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
<>	144:ef7eb2e8f9f7	586	#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
<>	144:ef7eb2e8f9f7	587	#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
<>	144:ef7eb2e8f9f7	588	#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
<>	144:ef7eb2e8f9f7	589	#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
<>	144:ef7eb2e8f9f7	590	#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
<>	144:ef7eb2e8f9f7	591	#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
<>	144:ef7eb2e8f9f7	592	/**
<>	144:ef7eb2e8f9f7	593	* @}
<>	144:ef7eb2e8f9f7	594	*/
<>	144:ef7eb2e8f9f7	595
<>	144:ef7eb2e8f9f7	596	/** @defgroup SDMMC_LL_Flags Flags
<>	144:ef7eb2e8f9f7	597	* @{
<>	144:ef7eb2e8f9f7	598	*/
<>	144:ef7eb2e8f9f7	599	#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
<>	144:ef7eb2e8f9f7	600	#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
<>	144:ef7eb2e8f9f7	601	#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
<>	144:ef7eb2e8f9f7	602	#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
<>	144:ef7eb2e8f9f7	603	#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
<>	144:ef7eb2e8f9f7	604	#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
<>	144:ef7eb2e8f9f7	605	#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
<>	144:ef7eb2e8f9f7	606	#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
<>	144:ef7eb2e8f9f7	607	#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
<>	144:ef7eb2e8f9f7	608	#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
<>	144:ef7eb2e8f9f7	609	#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
<>	144:ef7eb2e8f9f7	610	#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
<>	144:ef7eb2e8f9f7	611	#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
<>	144:ef7eb2e8f9f7	612	#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
<>	144:ef7eb2e8f9f7	613	#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
<>	144:ef7eb2e8f9f7	614	#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
<>	144:ef7eb2e8f9f7	615	#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
<>	144:ef7eb2e8f9f7	616	#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
<>	144:ef7eb2e8f9f7	617	#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
<>	144:ef7eb2e8f9f7	618	#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
<>	144:ef7eb2e8f9f7	619	#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
<>	144:ef7eb2e8f9f7	620	#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
<>	161:2cc1468da177	621	#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL \| SDMMC_FLAG_DCRCFAIL \| SDMMC_FLAG_CTIMEOUT \|\
<>	161:2cc1468da177	622	SDMMC_FLAG_DTIMEOUT \| SDMMC_FLAG_TXUNDERR \| SDMMC_FLAG_RXOVERR \|\
<>	161:2cc1468da177	623	SDMMC_FLAG_CMDREND \| SDMMC_FLAG_CMDSENT \| SDMMC_FLAG_DATAEND \|\
<>	161:2cc1468da177	624	SDMMC_FLAG_DBCKEND))
<>	144:ef7eb2e8f9f7	625	/**
<>	144:ef7eb2e8f9f7	626	* @}
<>	144:ef7eb2e8f9f7	627	*/
<>	144:ef7eb2e8f9f7	628
<>	144:ef7eb2e8f9f7	629	/**
<>	144:ef7eb2e8f9f7	630	* @}
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	634	/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
<>	144:ef7eb2e8f9f7	635	* @{
<>	144:ef7eb2e8f9f7	636	*/
<>	144:ef7eb2e8f9f7	637
<>	144:ef7eb2e8f9f7	638	/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
<>	144:ef7eb2e8f9f7	639	* @brief SDMMC_LL registers bit address in the alias region
<>	144:ef7eb2e8f9f7	640	* @{
<>	144:ef7eb2e8f9f7	641	*/
<>	144:ef7eb2e8f9f7	642	/* ---------------------- SDMMC registers bit mask --------------------------- */
<>	144:ef7eb2e8f9f7	643	/* --- CLKCR Register ---*/
<>	144:ef7eb2e8f9f7	644	/* CLKCR register clear mask */
<>	144:ef7eb2e8f9f7	645	#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV \| SDMMC_CLKCR_PWRSAV \|\
<>	144:ef7eb2e8f9f7	646	SDMMC_CLKCR_BYPASS \| SDMMC_CLKCR_WIDBUS \|\
<>	144:ef7eb2e8f9f7	647	SDMMC_CLKCR_NEGEDGE \| SDMMC_CLKCR_HWFC_EN))
<>	144:ef7eb2e8f9f7	648
<>	144:ef7eb2e8f9f7	649	/* --- DCTRL Register ---*/
<>	144:ef7eb2e8f9f7	650	/* SDMMC DCTRL Clear Mask */
<>	144:ef7eb2e8f9f7	651	#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN \| SDMMC_DCTRL_DTDIR \|\
<>	144:ef7eb2e8f9f7	652	SDMMC_DCTRL_DTMODE \| SDMMC_DCTRL_DBLOCKSIZE))
<>	144:ef7eb2e8f9f7	653
<>	144:ef7eb2e8f9f7	654	/* --- CMD Register ---*/
<>	144:ef7eb2e8f9f7	655	/* CMD Register clear mask */
<>	144:ef7eb2e8f9f7	656	#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX \| SDMMC_CMD_WAITRESP \|\
<>	144:ef7eb2e8f9f7	657	SDMMC_CMD_WAITINT \| SDMMC_CMD_WAITPEND \|\
<>	144:ef7eb2e8f9f7	658	SDMMC_CMD_CPSMEN \| SDMMC_CMD_SDIOSUSPEND))
<>	144:ef7eb2e8f9f7	659
<>	144:ef7eb2e8f9f7	660	/* SDMMC Initialization Frequency (400KHz max) */
<>	161:2cc1468da177	661	#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663	/* SDMMC Data Transfer Frequency (25MHz max) */
<>	144:ef7eb2e8f9f7	664	#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
<>	144:ef7eb2e8f9f7	665
<>	144:ef7eb2e8f9f7	666	/**
<>	144:ef7eb2e8f9f7	667	* @}
<>	144:ef7eb2e8f9f7	668	*/
<>	144:ef7eb2e8f9f7	669
<>	144:ef7eb2e8f9f7	670	/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
<>	144:ef7eb2e8f9f7	671	* @brief macros to handle interrupts and specific clock configurations
<>	144:ef7eb2e8f9f7	672	* @{
<>	144:ef7eb2e8f9f7	673	*/
<>	144:ef7eb2e8f9f7	674
<>	144:ef7eb2e8f9f7	675	/**
<>	144:ef7eb2e8f9f7	676	* @brief Enable the SDMMC device.
<>	144:ef7eb2e8f9f7	677	* @param __INSTANCE__: SDMMC Instance
<>	144:ef7eb2e8f9f7	678	* @retval None
<>	144:ef7eb2e8f9f7	679	*/
<>	144:ef7eb2e8f9f7	680	#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR \|= SDMMC_CLKCR_CLKEN)
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	/**
<>	144:ef7eb2e8f9f7	683	* @brief Disable the SDMMC device.
<>	144:ef7eb2e8f9f7	684	* @param __INSTANCE__: SDMMC Instance
<>	144:ef7eb2e8f9f7	685	* @retval None
<>	144:ef7eb2e8f9f7	686	*/
<>	144:ef7eb2e8f9f7	687	#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689	/**
<>	144:ef7eb2e8f9f7	690	* @brief Enable the SDMMC DMA transfer.
<>	144:ef7eb2e8f9f7	691	* @param __INSTANCE__: SDMMC Instance
<>	144:ef7eb2e8f9f7	692	* @retval None
<>	144:ef7eb2e8f9f7	693	*/
<>	144:ef7eb2e8f9f7	694	#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_DMAEN)
<>	144:ef7eb2e8f9f7	695	/**
<>	144:ef7eb2e8f9f7	696	* @brief Disable the SDMMC DMA transfer.
<>	144:ef7eb2e8f9f7	697	* @param __INSTANCE__: SDMMC Instance
<>	144:ef7eb2e8f9f7	698	* @retval None
<>	144:ef7eb2e8f9f7	699	*/
<>	144:ef7eb2e8f9f7	700	#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702	/**
<>	144:ef7eb2e8f9f7	703	* @brief Enable the SDMMC device interrupt.
<>	144:ef7eb2e8f9f7	704	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	705	* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	706	* This parameter can be one or a combination of the following values:
<>	144:ef7eb2e8f9f7	707	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	708	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	709	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<>	144:ef7eb2e8f9f7	710	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<>	144:ef7eb2e8f9f7	711	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	144:ef7eb2e8f9f7	712	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<>	144:ef7eb2e8f9f7	713	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	144:ef7eb2e8f9f7	714	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<>	144:ef7eb2e8f9f7	715	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<>	144:ef7eb2e8f9f7	716	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<>	144:ef7eb2e8f9f7	717	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
<>	144:ef7eb2e8f9f7	718	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
<>	144:ef7eb2e8f9f7	719	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
<>	144:ef7eb2e8f9f7	720	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<>	144:ef7eb2e8f9f7	721	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<>	144:ef7eb2e8f9f7	722	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
<>	144:ef7eb2e8f9f7	723	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
<>	144:ef7eb2e8f9f7	724	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
<>	144:ef7eb2e8f9f7	725	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
<>	144:ef7eb2e8f9f7	726	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
<>	144:ef7eb2e8f9f7	727	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
<>	144:ef7eb2e8f9f7	728	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<>	144:ef7eb2e8f9f7	729	* @retval None
<>	144:ef7eb2e8f9f7	730	*/
<>	144:ef7eb2e8f9f7	731	#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	732
<>	144:ef7eb2e8f9f7	733	/**
<>	144:ef7eb2e8f9f7	734	* @brief Disable the SDMMC device interrupt.
<>	144:ef7eb2e8f9f7	735	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	736	* @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	737	* This parameter can be one or a combination of the following values:
<>	144:ef7eb2e8f9f7	738	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	739	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	740	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<>	144:ef7eb2e8f9f7	741	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<>	144:ef7eb2e8f9f7	742	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	144:ef7eb2e8f9f7	743	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<>	144:ef7eb2e8f9f7	744	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	144:ef7eb2e8f9f7	745	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<>	144:ef7eb2e8f9f7	746	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<>	144:ef7eb2e8f9f7	747	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<>	144:ef7eb2e8f9f7	748	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
<>	144:ef7eb2e8f9f7	749	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
<>	144:ef7eb2e8f9f7	750	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
<>	144:ef7eb2e8f9f7	751	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<>	144:ef7eb2e8f9f7	752	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<>	144:ef7eb2e8f9f7	753	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
<>	144:ef7eb2e8f9f7	754	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
<>	144:ef7eb2e8f9f7	755	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
<>	144:ef7eb2e8f9f7	756	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
<>	144:ef7eb2e8f9f7	757	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
<>	144:ef7eb2e8f9f7	758	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
<>	144:ef7eb2e8f9f7	759	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<>	144:ef7eb2e8f9f7	760	* @retval None
<>	144:ef7eb2e8f9f7	761	*/
<>	144:ef7eb2e8f9f7	762	#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	/**
<>	144:ef7eb2e8f9f7	765	* @brief Checks whether the specified SDMMC flag is set or not.
<>	144:ef7eb2e8f9f7	766	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	767	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	768	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	769	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
<>	144:ef7eb2e8f9f7	770	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<>	144:ef7eb2e8f9f7	771	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
<>	144:ef7eb2e8f9f7	772	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
<>	144:ef7eb2e8f9f7	773	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
<>	144:ef7eb2e8f9f7	774	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
<>	144:ef7eb2e8f9f7	775	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
<>	144:ef7eb2e8f9f7	776	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
<>	144:ef7eb2e8f9f7	777	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<>	144:ef7eb2e8f9f7	778	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<>	144:ef7eb2e8f9f7	779	* @arg SDMMC_FLAG_CMDACT: Command transfer in progress
<>	144:ef7eb2e8f9f7	780	* @arg SDMMC_FLAG_TXACT: Data transmit in progress
<>	144:ef7eb2e8f9f7	781	* @arg SDMMC_FLAG_RXACT: Data receive in progress
<>	144:ef7eb2e8f9f7	782	* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<>	144:ef7eb2e8f9f7	783	* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
<>	144:ef7eb2e8f9f7	784	* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
<>	144:ef7eb2e8f9f7	785	* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
<>	144:ef7eb2e8f9f7	786	* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
<>	144:ef7eb2e8f9f7	787	* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
<>	144:ef7eb2e8f9f7	788	* @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
<>	144:ef7eb2e8f9f7	789	* @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
<>	144:ef7eb2e8f9f7	790	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
<>	144:ef7eb2e8f9f7	791	* @retval The new state of SDMMC_FLAG (SET or RESET).
<>	144:ef7eb2e8f9f7	792	*/
<>	144:ef7eb2e8f9f7	793	#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
<>	144:ef7eb2e8f9f7	794
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/**
<>	144:ef7eb2e8f9f7	797	* @brief Clears the SDMMC pending flags.
<>	144:ef7eb2e8f9f7	798	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	799	* @param __FLAG__: specifies the flag to clear.
<>	144:ef7eb2e8f9f7	800	* This parameter can be one or a combination of the following values:
<>	144:ef7eb2e8f9f7	801	* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
<>	144:ef7eb2e8f9f7	802	* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<>	144:ef7eb2e8f9f7	803	* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
<>	144:ef7eb2e8f9f7	804	* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
<>	144:ef7eb2e8f9f7	805	* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
<>	144:ef7eb2e8f9f7	806	* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
<>	144:ef7eb2e8f9f7	807	* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
<>	144:ef7eb2e8f9f7	808	* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
<>	144:ef7eb2e8f9f7	809	* @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<>	144:ef7eb2e8f9f7	810	* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<>	144:ef7eb2e8f9f7	811	* @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
<>	144:ef7eb2e8f9f7	812	* @retval None
<>	144:ef7eb2e8f9f7	813	*/
<>	144:ef7eb2e8f9f7	814	#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
<>	144:ef7eb2e8f9f7	815
<>	144:ef7eb2e8f9f7	816	/**
<>	144:ef7eb2e8f9f7	817	* @brief Checks whether the specified SDMMC interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	818	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	819	* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
<>	144:ef7eb2e8f9f7	820	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	821	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	822	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	823	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<>	144:ef7eb2e8f9f7	824	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<>	144:ef7eb2e8f9f7	825	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	144:ef7eb2e8f9f7	826	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<>	144:ef7eb2e8f9f7	827	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	144:ef7eb2e8f9f7	828	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<>	144:ef7eb2e8f9f7	829	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<>	144:ef7eb2e8f9f7	830	* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<>	144:ef7eb2e8f9f7	831	* @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
<>	144:ef7eb2e8f9f7	832	* @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
<>	144:ef7eb2e8f9f7	833	* @arg SDMMC_IT_RXACT: Data receive in progress interrupt
<>	144:ef7eb2e8f9f7	834	* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<>	144:ef7eb2e8f9f7	835	* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<>	144:ef7eb2e8f9f7	836	* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
<>	144:ef7eb2e8f9f7	837	* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
<>	144:ef7eb2e8f9f7	838	* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
<>	144:ef7eb2e8f9f7	839	* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
<>	144:ef7eb2e8f9f7	840	* @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
<>	144:ef7eb2e8f9f7	841	* @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
<>	144:ef7eb2e8f9f7	842	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<>	144:ef7eb2e8f9f7	843	* @retval The new state of SDMMC_IT (SET or RESET).
<>	144:ef7eb2e8f9f7	844	*/
<>	144:ef7eb2e8f9f7	845	#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	846
<>	144:ef7eb2e8f9f7	847	/**
<>	144:ef7eb2e8f9f7	848	* @brief Clears the SDMMC's interrupt pending bits.
<>	144:ef7eb2e8f9f7	849	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	850	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	851	* This parameter can be one or a combination of the following values:
<>	144:ef7eb2e8f9f7	852	* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	853	* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<>	144:ef7eb2e8f9f7	854	* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
<>	144:ef7eb2e8f9f7	855	* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
<>	144:ef7eb2e8f9f7	856	* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<>	144:ef7eb2e8f9f7	857	* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
<>	144:ef7eb2e8f9f7	858	* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
<>	144:ef7eb2e8f9f7	859	* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
<>	144:ef7eb2e8f9f7	860	* @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
<>	144:ef7eb2e8f9f7	861	* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
<>	144:ef7eb2e8f9f7	862	* @retval None
<>	144:ef7eb2e8f9f7	863	*/
<>	144:ef7eb2e8f9f7	864	#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	865
<>	144:ef7eb2e8f9f7	866	/**
<>	144:ef7eb2e8f9f7	867	* @brief Enable Start the SD I/O Read Wait operation.
<>	144:ef7eb2e8f9f7	868	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	869	* @retval None
<>	144:ef7eb2e8f9f7	870	*/
<>	144:ef7eb2e8f9f7	871	#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTART)
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	/**
<>	144:ef7eb2e8f9f7	874	* @brief Disable Start the SD I/O Read Wait operations.
<>	144:ef7eb2e8f9f7	875	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	876	* @retval None
<>	144:ef7eb2e8f9f7	877	*/
<>	144:ef7eb2e8f9f7	878	#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
<>	144:ef7eb2e8f9f7	879
<>	144:ef7eb2e8f9f7	880	/**
<>	144:ef7eb2e8f9f7	881	* @brief Enable Start the SD I/O Read Wait operation.
<>	144:ef7eb2e8f9f7	882	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	883	* @retval None
<>	144:ef7eb2e8f9f7	884	*/
<>	144:ef7eb2e8f9f7	885	#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_RWSTOP)
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/**
<>	144:ef7eb2e8f9f7	888	* @brief Disable Stop the SD I/O Read Wait operations.
<>	144:ef7eb2e8f9f7	889	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	890	* @retval None
<>	144:ef7eb2e8f9f7	891	*/
<>	144:ef7eb2e8f9f7	892	#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	/**
<>	144:ef7eb2e8f9f7	895	* @brief Enable the SD I/O Mode Operation.
<>	144:ef7eb2e8f9f7	896	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	897	* @retval None
<>	144:ef7eb2e8f9f7	898	*/
<>	144:ef7eb2e8f9f7	899	#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL \|= SDMMC_DCTRL_SDIOEN)
<>	144:ef7eb2e8f9f7	900
<>	144:ef7eb2e8f9f7	901	/**
<>	144:ef7eb2e8f9f7	902	* @brief Disable the SD I/O Mode Operation.
<>	144:ef7eb2e8f9f7	903	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	904	* @retval None
<>	144:ef7eb2e8f9f7	905	*/
<>	144:ef7eb2e8f9f7	906	#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908	/**
<>	144:ef7eb2e8f9f7	909	* @brief Enable the SD I/O Suspend command sending.
<>	144:ef7eb2e8f9f7	910	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	911	* @retval None
<>	144:ef7eb2e8f9f7	912	*/
<>	144:ef7eb2e8f9f7	913	#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD \|= SDMMC_CMD_SDIOSUSPEND)
<>	144:ef7eb2e8f9f7	914
<>	144:ef7eb2e8f9f7	915	/**
<>	144:ef7eb2e8f9f7	916	* @brief Disable the SD I/O Suspend command sending.
<>	144:ef7eb2e8f9f7	917	* @param __INSTANCE__ : Pointer to SDMMC register base
<>	144:ef7eb2e8f9f7	918	* @retval None
<>	144:ef7eb2e8f9f7	919	*/
<>	144:ef7eb2e8f9f7	920	#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/**
<>	144:ef7eb2e8f9f7	923	* @}
<>	144:ef7eb2e8f9f7	924	*/
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/**
<>	144:ef7eb2e8f9f7	927	* @}
<>	144:ef7eb2e8f9f7	928	*/
<>	144:ef7eb2e8f9f7	929
<>	144:ef7eb2e8f9f7	930	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	931	/** @addtogroup SDMMC_LL_Exported_Functions
<>	144:ef7eb2e8f9f7	932	* @{
<>	144:ef7eb2e8f9f7	933	*/
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	/* Initialization/de-initialization functions **********************************/
<>	144:ef7eb2e8f9f7	936	/** @addtogroup HAL_SDMMC_LL_Group1
<>	144:ef7eb2e8f9f7	937	* @{
<>	144:ef7eb2e8f9f7	938	*/
<>	144:ef7eb2e8f9f7	939	HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
<>	144:ef7eb2e8f9f7	940	/**
<>	144:ef7eb2e8f9f7	941	* @}
<>	144:ef7eb2e8f9f7	942	*/
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* I/O operation functions *****************************************************/
<>	144:ef7eb2e8f9f7	945	/** @addtogroup HAL_SDMMC_LL_Group2
<>	144:ef7eb2e8f9f7	946	* @{
<>	144:ef7eb2e8f9f7	947	*/
<>	144:ef7eb2e8f9f7	948	uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
<>	144:ef7eb2e8f9f7	949	HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef SDMMCx, uint32_t pWriteData);
<>	144:ef7eb2e8f9f7	950	/**
<>	144:ef7eb2e8f9f7	951	* @}
<>	144:ef7eb2e8f9f7	952	*/
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	955	/** @addtogroup HAL_SDMMC_LL_Group3
<>	144:ef7eb2e8f9f7	956	* @{
<>	144:ef7eb2e8f9f7	957	*/
<>	144:ef7eb2e8f9f7	958	HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
<>	144:ef7eb2e8f9f7	959	HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
<>	144:ef7eb2e8f9f7	960	uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
<>	144:ef7eb2e8f9f7	961
<>	144:ef7eb2e8f9f7	962	/* Command path state machine (CPSM) management functions */
<>	144:ef7eb2e8f9f7	963	HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef SDMMCx, SDMMC_CmdInitTypeDef Command);
<>	144:ef7eb2e8f9f7	964	uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
<>	144:ef7eb2e8f9f7	965	uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
<>	144:ef7eb2e8f9f7	966
<>	144:ef7eb2e8f9f7	967	/* Data path state machine (DPSM) management functions */
<>	161:2cc1468da177	968	HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef SDMMCx, SDMMC_DataInitTypeDef Data);
<>	144:ef7eb2e8f9f7	969	uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
<>	144:ef7eb2e8f9f7	970	uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
<>	144:ef7eb2e8f9f7	971
<>	144:ef7eb2e8f9f7	972	/* SDMMC Cards mode management functions */
<>	144:ef7eb2e8f9f7	973	HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
<>	144:ef7eb2e8f9f7	974
<>	161:2cc1468da177	975	/* SDMMC Commands management functions */
<>	161:2cc1468da177	976	uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
<>	161:2cc1468da177	977	uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
<>	161:2cc1468da177	978	uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
<>	161:2cc1468da177	979	uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
<>	161:2cc1468da177	980	uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
<>	161:2cc1468da177	981	uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
<>	161:2cc1468da177	982	uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
<>	161:2cc1468da177	983	uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
<>	161:2cc1468da177	984	uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
<>	161:2cc1468da177	985	uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
<>	161:2cc1468da177	986	uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
<>	161:2cc1468da177	987	uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
<>	161:2cc1468da177	988	uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
<>	161:2cc1468da177	989	uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
<>	161:2cc1468da177	990	uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
<>	161:2cc1468da177	991	uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
<>	161:2cc1468da177	992	uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
<>	161:2cc1468da177	993	uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
<>	161:2cc1468da177	994	uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
<>	161:2cc1468da177	995	uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
<>	161:2cc1468da177	996	uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef SDMMCx, uint16_t pRCA);
<>	161:2cc1468da177	997	uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
<>	161:2cc1468da177	998	uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
<>	161:2cc1468da177	999	uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
<>	161:2cc1468da177	1000	uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
<>	161:2cc1468da177	1001
<>	144:ef7eb2e8f9f7	1002	/**
<>	144:ef7eb2e8f9f7	1003	* @}
<>	144:ef7eb2e8f9f7	1004	*/
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	/**
<>	144:ef7eb2e8f9f7	1007	* @}
<>	144:ef7eb2e8f9f7	1008	*/
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	/**
<>	144:ef7eb2e8f9f7	1011	* @}
<>	144:ef7eb2e8f9f7	1012	*/
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	/**
<>	144:ef7eb2e8f9f7	1015	* @}
<>	144:ef7eb2e8f9f7	1016	*/
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1019	}
<>	144:ef7eb2e8f9f7	1020	#endif
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	#endif /* __STM32F7xx_LL_SDMMC_H */
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/