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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_rcc.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief Header file of RCC LL module.
<>	161:2cc1468da177	8	******************************************************************************
<>	161:2cc1468da177	9	* @attention
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	12	*
<>	161:2cc1468da177	13	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	14	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	18	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	19	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	21	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	22	* without specific prior written permission.
<>	161:2cc1468da177	23	*
<>	161:2cc1468da177	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	34	*
<>	161:2cc1468da177	35	******************************************************************************
<>	161:2cc1468da177	36	*/
<>	161:2cc1468da177	37
<>	161:2cc1468da177	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	39	#ifndef __STM32F7xx_LL_RCC_H
<>	161:2cc1468da177	40	#define __STM32F7xx_LL_RCC_H
<>	161:2cc1468da177	41
<>	161:2cc1468da177	42	#ifdef __cplusplus
<>	161:2cc1468da177	43	extern "C" {
<>	161:2cc1468da177	44	#endif
<>	161:2cc1468da177	45
<>	161:2cc1468da177	46	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	47	#include "stm32f7xx.h"
<>	161:2cc1468da177	48
<>	161:2cc1468da177	49	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	50	* @{
<>	161:2cc1468da177	51	*/
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	#if defined(RCC)
<>	161:2cc1468da177	54
<>	161:2cc1468da177	55	/** @defgroup RCC_LL RCC
<>	161:2cc1468da177	56	* @{
<>	161:2cc1468da177	57	*/
<>	161:2cc1468da177	58
<>	161:2cc1468da177	59	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	60	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
<>	161:2cc1468da177	62	* @{
<>	161:2cc1468da177	63	*/
<>	161:2cc1468da177	64
<>	161:2cc1468da177	65	#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
<>	161:2cc1468da177	66	static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
<>	161:2cc1468da177	67	#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
<>	161:2cc1468da177	68
<>	161:2cc1468da177	69	/**
<>	161:2cc1468da177	70	* @}
<>	161:2cc1468da177	71	*/
<>	161:2cc1468da177	72	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	73	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	74	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	75	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
<>	161:2cc1468da177	76	* @{
<>	161:2cc1468da177	77	*/
<>	161:2cc1468da177	78	/**
<>	161:2cc1468da177	79	* @}
<>	161:2cc1468da177	80	*/
<>	161:2cc1468da177	81	#endif /USE_FULL_LL_DRIVER/
<>	161:2cc1468da177	82	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	83	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	84	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
<>	161:2cc1468da177	85	* @{
<>	161:2cc1468da177	86	*/
<>	161:2cc1468da177	87
<>	161:2cc1468da177	88	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
<>	161:2cc1468da177	89	* @{
<>	161:2cc1468da177	90	*/
<>	161:2cc1468da177	91
<>	161:2cc1468da177	92	/**
<>	161:2cc1468da177	93	* @brief RCC Clocks Frequency Structure
<>	161:2cc1468da177	94	*/
<>	161:2cc1468da177	95	typedef struct
<>	161:2cc1468da177	96	{
<>	161:2cc1468da177	97	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
<>	161:2cc1468da177	98	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
<>	161:2cc1468da177	99	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
<>	161:2cc1468da177	100	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
<>	161:2cc1468da177	101	} LL_RCC_ClocksTypeDef;
<>	161:2cc1468da177	102
<>	161:2cc1468da177	103	/**
<>	161:2cc1468da177	104	* @}
<>	161:2cc1468da177	105	*/
<>	161:2cc1468da177	106
<>	161:2cc1468da177	107	/**
<>	161:2cc1468da177	108	* @}
<>	161:2cc1468da177	109	*/
<>	161:2cc1468da177	110	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	111
<>	161:2cc1468da177	112	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	113	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
<>	161:2cc1468da177	114	* @{
<>	161:2cc1468da177	115	*/
<>	161:2cc1468da177	116
<>	161:2cc1468da177	117	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
<>	161:2cc1468da177	118	* @brief Defines used to adapt values of different oscillators
<>	161:2cc1468da177	119	* @note These values could be modified in the user environment according to
<>	161:2cc1468da177	120	* HW set-up.
<>	161:2cc1468da177	121	* @{
<>	161:2cc1468da177	122	*/
<>	161:2cc1468da177	123	#if !defined (HSE_VALUE)
<>	161:2cc1468da177	124	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
<>	161:2cc1468da177	125	#endif /* HSE_VALUE */
<>	161:2cc1468da177	126
<>	161:2cc1468da177	127	#if !defined (HSI_VALUE)
<>	161:2cc1468da177	128	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
<>	161:2cc1468da177	129	#endif /* HSI_VALUE */
<>	161:2cc1468da177	130
<>	161:2cc1468da177	131	#if !defined (LSE_VALUE)
<>	161:2cc1468da177	132	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
<>	161:2cc1468da177	133	#endif /* LSE_VALUE */
<>	161:2cc1468da177	134
<>	161:2cc1468da177	135	#if !defined (LSI_VALUE)
<>	161:2cc1468da177	136	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
<>	161:2cc1468da177	137	#endif /* LSI_VALUE */
<>	161:2cc1468da177	138
<>	161:2cc1468da177	139	#if !defined (EXTERNAL_CLOCK_VALUE)
<>	161:2cc1468da177	140	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
<>	161:2cc1468da177	141	#endif /* EXTERNAL_CLOCK_VALUE */
<>	161:2cc1468da177	142	/**
<>	161:2cc1468da177	143	* @}
<>	161:2cc1468da177	144	*/
<>	161:2cc1468da177	145
<>	161:2cc1468da177	146	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	161:2cc1468da177	147	* @brief Flags defines which can be used with LL_RCC_WriteReg function
<>	161:2cc1468da177	148	* @{
<>	161:2cc1468da177	149	*/
<>	161:2cc1468da177	150	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
<>	161:2cc1468da177	151	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
<>	161:2cc1468da177	152	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
<>	161:2cc1468da177	153	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
<>	161:2cc1468da177	154	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
<>	161:2cc1468da177	155	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
<>	161:2cc1468da177	156	#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /!< PLLSAI Ready Interrupt Clear /
<>	161:2cc1468da177	157	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
<>	161:2cc1468da177	158	/**
<>	161:2cc1468da177	159	* @}
<>	161:2cc1468da177	160	*/
<>	161:2cc1468da177	161
<>	161:2cc1468da177	162	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
<>	161:2cc1468da177	163	* @brief Flags defines which can be used with LL_RCC_ReadReg function
<>	161:2cc1468da177	164	* @{
<>	161:2cc1468da177	165	*/
<>	161:2cc1468da177	166	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
<>	161:2cc1468da177	167	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
<>	161:2cc1468da177	168	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
<>	161:2cc1468da177	169	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
<>	161:2cc1468da177	170	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
<>	161:2cc1468da177	171	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
<>	161:2cc1468da177	172	#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /!< PLLSAI Ready Interrupt flag /
<>	161:2cc1468da177	173	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
<>	161:2cc1468da177	174	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
<>	161:2cc1468da177	175	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
<>	161:2cc1468da177	176	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
<>	161:2cc1468da177	177	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
<>	161:2cc1468da177	178	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
<>	161:2cc1468da177	179	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
<>	161:2cc1468da177	180	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
<>	161:2cc1468da177	181	/**
<>	161:2cc1468da177	182	* @}
<>	161:2cc1468da177	183	*/
<>	161:2cc1468da177	184
<>	161:2cc1468da177	185	/** @defgroup RCC_LL_EC_IT IT Defines
<>	161:2cc1468da177	186	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
<>	161:2cc1468da177	187	* @{
<>	161:2cc1468da177	188	*/
<>	161:2cc1468da177	189	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
<>	161:2cc1468da177	190	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
<>	161:2cc1468da177	191	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
<>	161:2cc1468da177	192	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
<>	161:2cc1468da177	193	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
<>	161:2cc1468da177	194	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
<>	161:2cc1468da177	195	#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /!< PLLSAI Ready Interrupt Enable /
<>	161:2cc1468da177	196	/**
<>	161:2cc1468da177	197	* @}
<>	161:2cc1468da177	198	*/
<>	161:2cc1468da177	199
<>	161:2cc1468da177	200	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
<>	161:2cc1468da177	201	* @{
<>	161:2cc1468da177	202	*/
<>	161:2cc1468da177	203	#define LL_RCC_LSEDRIVE_LOW 0x00000000U /!< Xtal mode lower driving capability /
<>	161:2cc1468da177	204	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
<>	161:2cc1468da177	205	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
<>	161:2cc1468da177	206	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
<>	161:2cc1468da177	207	/**
<>	161:2cc1468da177	208	* @}
<>	161:2cc1468da177	209	*/
<>	161:2cc1468da177	210
<>	161:2cc1468da177	211	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
<>	161:2cc1468da177	212	* @{
<>	161:2cc1468da177	213	*/
<>	161:2cc1468da177	214	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
<>	161:2cc1468da177	215	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
<>	161:2cc1468da177	216	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
<>	161:2cc1468da177	217	/**
<>	161:2cc1468da177	218	* @}
<>	161:2cc1468da177	219	*/
<>	161:2cc1468da177	220
<>	161:2cc1468da177	221	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
<>	161:2cc1468da177	222	* @{
<>	161:2cc1468da177	223	*/
<>	161:2cc1468da177	224	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	161:2cc1468da177	225	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	161:2cc1468da177	226	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	161:2cc1468da177	227	/**
<>	161:2cc1468da177	228	* @}
<>	161:2cc1468da177	229	*/
<>	161:2cc1468da177	230
<>	161:2cc1468da177	231	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
<>	161:2cc1468da177	232	* @{
<>	161:2cc1468da177	233	*/
<>	161:2cc1468da177	234	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	161:2cc1468da177	235	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	161:2cc1468da177	236	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	161:2cc1468da177	237	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	161:2cc1468da177	238	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	161:2cc1468da177	239	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	161:2cc1468da177	240	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	161:2cc1468da177	241	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	161:2cc1468da177	242	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	161:2cc1468da177	243	/**
<>	161:2cc1468da177	244	* @}
<>	161:2cc1468da177	245	*/
<>	161:2cc1468da177	246
<>	161:2cc1468da177	247	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
<>	161:2cc1468da177	248	* @{
<>	161:2cc1468da177	249	*/
<>	161:2cc1468da177	250	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
<>	161:2cc1468da177	251	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
<>	161:2cc1468da177	252	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
<>	161:2cc1468da177	253	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
<>	161:2cc1468da177	254	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	161:2cc1468da177	255	/**
<>	161:2cc1468da177	256	* @}
<>	161:2cc1468da177	257	*/
<>	161:2cc1468da177	258	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
<>	161:2cc1468da177	259	* @{
<>	161:2cc1468da177	260	*/
<>	161:2cc1468da177	261	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
<>	161:2cc1468da177	262	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
<>	161:2cc1468da177	263	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
<>	161:2cc1468da177	264	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
<>	161:2cc1468da177	265	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
<>	161:2cc1468da177	266	/**
<>	161:2cc1468da177	267	* @}
<>	161:2cc1468da177	268	*/
<>	161:2cc1468da177	269
<>	161:2cc1468da177	270	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
<>	161:2cc1468da177	271	* @{
<>	161:2cc1468da177	272	*/
<>	161:2cc1468da177	273	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
<>	161:2cc1468da177	274	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
<>	161:2cc1468da177	275	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
<>	161:2cc1468da177	276	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
<>	161:2cc1468da177	277	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
<>	161:2cc1468da177	278	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
<>	161:2cc1468da177	279	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
<>	161:2cc1468da177	280	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
<>	161:2cc1468da177	281	/**
<>	161:2cc1468da177	282	* @}
<>	161:2cc1468da177	283	*/
<>	161:2cc1468da177	284
<>	161:2cc1468da177	285	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
<>	161:2cc1468da177	286	* @{
<>	161:2cc1468da177	287	*/
<>	161:2cc1468da177	288	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
<>	161:2cc1468da177	289	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
<>	161:2cc1468da177	290	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
<>	161:2cc1468da177	291	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
<>	161:2cc1468da177	292	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
<>	161:2cc1468da177	293	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
<>	161:2cc1468da177	294	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
<>	161:2cc1468da177	295	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
<>	161:2cc1468da177	296	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
<>	161:2cc1468da177	297	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
<>	161:2cc1468da177	298	/**
<>	161:2cc1468da177	299	* @}
<>	161:2cc1468da177	300	*/
<>	161:2cc1468da177	301
<>	161:2cc1468da177	302	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
<>	161:2cc1468da177	303	* @{
<>	161:2cc1468da177	304	*/
<>	161:2cc1468da177	305	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
<>	161:2cc1468da177	306	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
<>	161:2cc1468da177	307	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
<>	161:2cc1468da177	308	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
<>	161:2cc1468da177	309	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
<>	161:2cc1468da177	310	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
<>	161:2cc1468da177	311	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
<>	161:2cc1468da177	312	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
<>	161:2cc1468da177	313	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
<>	161:2cc1468da177	314	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
<>	161:2cc1468da177	315	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
<>	161:2cc1468da177	316	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
<>	161:2cc1468da177	317	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
<>	161:2cc1468da177	318	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
<>	161:2cc1468da177	319	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
<>	161:2cc1468da177	320	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
<>	161:2cc1468da177	321	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
<>	161:2cc1468da177	322	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
<>	161:2cc1468da177	323	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
<>	161:2cc1468da177	324	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
<>	161:2cc1468da177	325	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
<>	161:2cc1468da177	326	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
<>	161:2cc1468da177	327	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
<>	161:2cc1468da177	328	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
<>	161:2cc1468da177	329	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
<>	161:2cc1468da177	330	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
<>	161:2cc1468da177	331	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
<>	161:2cc1468da177	332	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
<>	161:2cc1468da177	333	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
<>	161:2cc1468da177	334	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
<>	161:2cc1468da177	335	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
<>	161:2cc1468da177	336	/**
<>	161:2cc1468da177	337	* @}
<>	161:2cc1468da177	338	*/
<>	161:2cc1468da177	339
<>	161:2cc1468da177	340	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	341	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
<>	161:2cc1468da177	342	* @{
<>	161:2cc1468da177	343	*/
<>	161:2cc1468da177	344	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
<>	161:2cc1468da177	345	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
<>	161:2cc1468da177	346	/**
<>	161:2cc1468da177	347	* @}
<>	161:2cc1468da177	348	*/
<>	161:2cc1468da177	349	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	350
<>	161:2cc1468da177	351	/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
<>	161:2cc1468da177	352	* @{
<>	161:2cc1468da177	353	*/
<>	161:2cc1468da177	354	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| 0x00000000U) /!< PCLK2 clock used as USART1 clock source /
<>	161:2cc1468da177	355	#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| RCC_DCKCFGR2_USART1SEL_0) /!< SYSCLK clock used as USART1 clock source /
<>	161:2cc1468da177	356	#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| RCC_DCKCFGR2_USART1SEL_1) /!< HSI clock used as USART1 clock source /
<>	161:2cc1468da177	357	#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) \| RCC_DCKCFGR2_USART1SEL) /!< LSE clock used as USART1 clock source /
<>	161:2cc1468da177	358	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as USART2 clock source /
<>	161:2cc1468da177	359	#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| RCC_DCKCFGR2_USART2SEL_0) /!< SYSCLK clock used as USART2 clock source /
<>	161:2cc1468da177	360	#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| RCC_DCKCFGR2_USART2SEL_1) /!< HSI clock used as USART2 clock source /
<>	161:2cc1468da177	361	#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) \| RCC_DCKCFGR2_USART2SEL) /!< LSE clock used as USART2 clock source /
<>	161:2cc1468da177	362	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as USART3 clock source /
<>	161:2cc1468da177	363	#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| RCC_DCKCFGR2_USART3SEL_0) /!< SYSCLK clock used as USART3 clock source /
<>	161:2cc1468da177	364	#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| RCC_DCKCFGR2_USART3SEL_1) /!< HSI clock used as USART3 clock source /
<>	161:2cc1468da177	365	#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) \| RCC_DCKCFGR2_USART3SEL) /!< LSE clock used as USART3 clock source /
<>	161:2cc1468da177	366	#define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| 0x00000000U) /!< PCLK2 clock used as USART6 clock source /
<>	161:2cc1468da177	367	#define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| RCC_DCKCFGR2_USART6SEL_0) /!< SYSCLK clock used as USART6 clock source /
<>	161:2cc1468da177	368	#define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| RCC_DCKCFGR2_USART6SEL_1) /!< HSI clock used as USART6 clock source /
<>	161:2cc1468da177	369	#define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) \| RCC_DCKCFGR2_USART6SEL) /!< LSE clock used as USART6 clock source /
<>	161:2cc1468da177	370	/**
<>	161:2cc1468da177	371	* @}
<>	161:2cc1468da177	372	*/
<>	161:2cc1468da177	373
<>	161:2cc1468da177	374	/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
<>	161:2cc1468da177	375	* @{
<>	161:2cc1468da177	376	*/
<>	161:2cc1468da177	377	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART4 clock source /
<>	161:2cc1468da177	378	#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| RCC_DCKCFGR2_UART4SEL_0) /!< SYSCLK clock used as UART4 clock source /
<>	161:2cc1468da177	379	#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| RCC_DCKCFGR2_UART4SEL_1) /!< HSI clock used as UART4 clock source /
<>	161:2cc1468da177	380	#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) \| RCC_DCKCFGR2_UART4SEL) /!< LSE clock used as UART4 clock source /
<>	161:2cc1468da177	381	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART5 clock source /
<>	161:2cc1468da177	382	#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| RCC_DCKCFGR2_UART5SEL_0) /!< SYSCLK clock used as UART5 clock source /
<>	161:2cc1468da177	383	#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| RCC_DCKCFGR2_UART5SEL_1) /!< HSI clock used as UART5 clock source /
<>	161:2cc1468da177	384	#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) \| RCC_DCKCFGR2_UART5SEL) /!< LSE clock used as UART5 clock source /
<>	161:2cc1468da177	385	#define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART7 clock source /
<>	161:2cc1468da177	386	#define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| RCC_DCKCFGR2_UART7SEL_0) /!< SYSCLK clock used as UART7 clock source /
<>	161:2cc1468da177	387	#define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| RCC_DCKCFGR2_UART7SEL_1) /!< HSI clock used as UART7 clock source /
<>	161:2cc1468da177	388	#define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) \| RCC_DCKCFGR2_UART7SEL) /!< LSE clock used as UART7 clock source /
<>	161:2cc1468da177	389	#define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| 0x00000000U) /!< PCLK1 clock used as UART8 clock source /
<>	161:2cc1468da177	390	#define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| RCC_DCKCFGR2_UART8SEL_0) /!< SYSCLK clock used as UART8 clock source /
<>	161:2cc1468da177	391	#define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| RCC_DCKCFGR2_UART8SEL_1) /!< HSI clock used as UART8 clock source /
<>	161:2cc1468da177	392	#define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) \| RCC_DCKCFGR2_UART8SEL) /!< LSE clock used as UART8 clock source /
<>	161:2cc1468da177	393	/**
<>	161:2cc1468da177	394	* @}
<>	161:2cc1468da177	395	*/
<>	161:2cc1468da177	396
<>	161:2cc1468da177	397	/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
<>	161:2cc1468da177	398	* @{
<>	161:2cc1468da177	399	*/
<>	161:2cc1468da177	400	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL\|0x00000000U) /!< PCLK1 clock used as I2C1 clock source /
<>	161:2cc1468da177	401	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL\|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /!< SYSCLK clock used as I2C1 clock source /
<>	161:2cc1468da177	402	#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL\|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /!< HSI clock used as I2C1 clock source /
<>	161:2cc1468da177	403	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL\|0x00000000U) /!< PCLK1 clock used as I2C2 clock source /
<>	161:2cc1468da177	404	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL\|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /!< SYSCLK clock used as I2C2 clock source /
<>	161:2cc1468da177	405	#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL\|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /!< HSI clock used as I2C2 clock source /
<>	161:2cc1468da177	406	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL\|0x00000000U) /!< PCLK1 clock used as I2C3 clock source /
<>	161:2cc1468da177	407	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL\|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /!< SYSCLK clock used as I2C3 clock source /
<>	161:2cc1468da177	408	#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL\|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /!< HSI clock used as I2C3 clock source /
<>	161:2cc1468da177	409	#if defined(I2C4)
<>	161:2cc1468da177	410	#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL\|0x00000000U) /!< PCLK1 clock used as I2C4 clock source /
<>	161:2cc1468da177	411	#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL\|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /!< SYSCLK clock used as I2C4 clock source /
<>	161:2cc1468da177	412	#define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL\|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /!< HSI clock used as I2C4 clock source /
<>	161:2cc1468da177	413	#endif /* I2C4 */
<>	161:2cc1468da177	414	/**
<>	161:2cc1468da177	415	* @}
<>	161:2cc1468da177	416	*/
<>	161:2cc1468da177	417
<>	161:2cc1468da177	418	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
<>	161:2cc1468da177	419	* @{
<>	161:2cc1468da177	420	*/
<>	161:2cc1468da177	421	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPTIM1 clock /
<>	161:2cc1468da177	422	#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /!< LSI oscillator clock used as LPTIM1 clock /
<>	161:2cc1468da177	423	#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /!< HSI oscillator clock used as LPTIM1 clock /
<>	161:2cc1468da177	424	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 \| RCC_DCKCFGR2_LPTIM1SEL_0) /!< LSE oscillator clock used as LPTIM1 clock /
<>	161:2cc1468da177	425	/**
<>	161:2cc1468da177	426	* @}
<>	161:2cc1468da177	427	*/
<>	161:2cc1468da177	428
<>	161:2cc1468da177	429	/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
<>	161:2cc1468da177	430	* @{
<>	161:2cc1468da177	431	*/
<>	161:2cc1468da177	432	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| 0x00000000U) /!< PLLSAI clock used as SAI1 clock source /
<>	161:2cc1468da177	433	#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /!< PLLI2S clock used as SAI1 clock source /
<>	161:2cc1468da177	434	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /!< External pin clock used as SAI1 clock source /
<>	161:2cc1468da177	435	#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
<>	161:2cc1468da177	436	#define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL \| (RCC_DCKCFGR1_SAI1SEL >> 16U)) /!< Main source clock used as SAI1 clock source /
<>	161:2cc1468da177	437	#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
<>	161:2cc1468da177	438	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| 0x00000000U) /!< PLLSAI clock used as SAI2 clock source /
<>	161:2cc1468da177	439	#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /!< PLLI2S clock used as SAI2 clock source /
<>	161:2cc1468da177	440	#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /!< External pin clock used as SAI2 clock source /
<>	161:2cc1468da177	441	#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
<>	161:2cc1468da177	442	#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL \| (RCC_DCKCFGR1_SAI2SEL >> 16U)) /!< Main source clock used as SAI2 clock source /
<>	161:2cc1468da177	443	#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
<>	161:2cc1468da177	444	/**
<>	161:2cc1468da177	445	* @}
<>	161:2cc1468da177	446	*/
<>	161:2cc1468da177	447
<>	161:2cc1468da177	448	/** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection
<>	161:2cc1468da177	449	* @{
<>	161:2cc1468da177	450	*/
<>	161:2cc1468da177	451	#define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL \| 0x00000000U) /!< PLL 48M domain clock used as SDMMC1 clock /
<>	161:2cc1468da177	452	#define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL \| (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /!< System clock clock used as SDMMC1 clock /
<>	161:2cc1468da177	453	#if defined(SDMMC2)
<>	161:2cc1468da177	454	#define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL \| 0x00000000U) /!< PLL 48M domain clock used as SDMMC2 clock /
<>	161:2cc1468da177	455	#define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL \| (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /!< System clock clock used as SDMMC2 clock /
<>	161:2cc1468da177	456	#endif /* SDMMC2 */
<>	161:2cc1468da177	457	/**
<>	161:2cc1468da177	458	* @}
<>	161:2cc1468da177	459	*/
<>	161:2cc1468da177	460
<>	161:2cc1468da177	461	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
<>	161:2cc1468da177	462	* @{
<>	161:2cc1468da177	463	*/
<>	161:2cc1468da177	464	#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as RNG clock source /
<>	161:2cc1468da177	465	#define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI clock used as RNG clock source /
<>	161:2cc1468da177	466	/**
<>	161:2cc1468da177	467	* @}
<>	161:2cc1468da177	468	*/
<>	161:2cc1468da177	469
<>	161:2cc1468da177	470	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
<>	161:2cc1468da177	471	* @{
<>	161:2cc1468da177	472	*/
<>	161:2cc1468da177	473	#define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /!< PLL clock used as USB clock source /
<>	161:2cc1468da177	474	#define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI1 clock used as USB clock source /
<>	161:2cc1468da177	475	/**
<>	161:2cc1468da177	476	* @}
<>	161:2cc1468da177	477	*/
<>	161:2cc1468da177	478
<>	161:2cc1468da177	479	#if defined(DSI)
<>	161:2cc1468da177	480	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
<>	161:2cc1468da177	481	* @{
<>	161:2cc1468da177	482	*/
<>	161:2cc1468da177	483	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
<>	161:2cc1468da177	484	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /!< PLL clock used as DSI byte lane clock source /
<>	161:2cc1468da177	485	/**
<>	161:2cc1468da177	486	* @}
<>	161:2cc1468da177	487	*/
<>	161:2cc1468da177	488	#endif /* DSI */
<>	161:2cc1468da177	489
<>	161:2cc1468da177	490	#if defined(CEC)
<>	161:2cc1468da177	491	/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
<>	161:2cc1468da177	492	* @{
<>	161:2cc1468da177	493	*/
<>	161:2cc1468da177	494	#define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /!< LSE oscillator clock used as CEC clock /
<>	161:2cc1468da177	495	#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /!< HSI oscillator clock divided by 488 used as CEC clock /
<>	161:2cc1468da177	496	/**
<>	161:2cc1468da177	497	* @}
<>	161:2cc1468da177	498	*/
<>	161:2cc1468da177	499	#endif /* CEC */
<>	161:2cc1468da177	500
<>	161:2cc1468da177	501	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
<>	161:2cc1468da177	502	* @{
<>	161:2cc1468da177	503	*/
<>	161:2cc1468da177	504	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
<>	161:2cc1468da177	505	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
<>	161:2cc1468da177	506	/**
<>	161:2cc1468da177	507	* @}
<>	161:2cc1468da177	508	*/
<>	161:2cc1468da177	509
<>	161:2cc1468da177	510	/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
<>	161:2cc1468da177	511	* @{
<>	161:2cc1468da177	512	*/
<>	161:2cc1468da177	513	#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /!< PLL oscillator clock used as 48Mhz domain clock /
<>	161:2cc1468da177	514	#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /!< PLLSAI oscillator clock used as 48Mhz domain clock /
<>	161:2cc1468da177	515	/**
<>	161:2cc1468da177	516	* @}
<>	161:2cc1468da177	517	*/
<>	161:2cc1468da177	518
<>	161:2cc1468da177	519	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	520	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
<>	161:2cc1468da177	521	* @{
<>	161:2cc1468da177	522	*/
<>	161:2cc1468da177	523	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /!< SAI1 clock used as DFSDM1 Audio clock /
<>	161:2cc1468da177	524	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /!< SAI2 clock used as DFSDM1 Audio clock /
<>	161:2cc1468da177	525	/**
<>	161:2cc1468da177	526	* @}
<>	161:2cc1468da177	527	*/
<>	161:2cc1468da177	528
<>	161:2cc1468da177	529	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
<>	161:2cc1468da177	530	* @{
<>	161:2cc1468da177	531	*/
<>	161:2cc1468da177	532	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 clock used as DFSDM1 clock /
<>	161:2cc1468da177	533	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /!< System clock used as DFSDM1 clock /
<>	161:2cc1468da177	534	/**
<>	161:2cc1468da177	535	* @}
<>	161:2cc1468da177	536	*/
<>	161:2cc1468da177	537	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	538
<>	161:2cc1468da177	539	/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
<>	161:2cc1468da177	540	* @{
<>	161:2cc1468da177	541	*/
<>	161:2cc1468da177	542	#define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /!< USART1 Clock source selection /
<>	161:2cc1468da177	543	#define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /!< USART2 Clock source selection /
<>	161:2cc1468da177	544	#define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /!< USART3 Clock source selection /
<>	161:2cc1468da177	545	#define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /!< USART6 Clock source selection /
<>	161:2cc1468da177	546	/**
<>	161:2cc1468da177	547	* @}
<>	161:2cc1468da177	548	*/
<>	161:2cc1468da177	549
<>	161:2cc1468da177	550	/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
<>	161:2cc1468da177	551	* @{
<>	161:2cc1468da177	552	*/
<>	161:2cc1468da177	553	#define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /!< UART4 Clock source selection /
<>	161:2cc1468da177	554	#define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /!< UART5 Clock source selection /
<>	161:2cc1468da177	555	#define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /!< UART7 Clock source selection /
<>	161:2cc1468da177	556	#define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /!< UART8 Clock source selection /
<>	161:2cc1468da177	557	/**
<>	161:2cc1468da177	558	* @}
<>	161:2cc1468da177	559	*/
<>	161:2cc1468da177	560
<>	161:2cc1468da177	561	/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
<>	161:2cc1468da177	562	* @{
<>	161:2cc1468da177	563	*/
<>	161:2cc1468da177	564	#define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /!< I2C1 Clock source selection /
<>	161:2cc1468da177	565	#define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /!< I2C2 Clock source selection /
<>	161:2cc1468da177	566	#define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /!< I2C3 Clock source selection /
<>	161:2cc1468da177	567	#if defined(I2C4)
<>	161:2cc1468da177	568	#define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /!< I2C4 Clock source selection /
<>	161:2cc1468da177	569	#endif /* I2C4 */
<>	161:2cc1468da177	570	/**
<>	161:2cc1468da177	571	* @}
<>	161:2cc1468da177	572	*/
<>	161:2cc1468da177	573
<>	161:2cc1468da177	574	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
<>	161:2cc1468da177	575	* @{
<>	161:2cc1468da177	576	*/
<>	161:2cc1468da177	577	#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /!< LPTIM1 Clock source selection /
<>	161:2cc1468da177	578	/**
<>	161:2cc1468da177	579	* @}
<>	161:2cc1468da177	580	*/
<>	161:2cc1468da177	581
<>	161:2cc1468da177	582	/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
<>	161:2cc1468da177	583	* @{
<>	161:2cc1468da177	584	*/
<>	161:2cc1468da177	585	#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /!< SAI1 Clock source selection /
<>	161:2cc1468da177	586	#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /!< SAI2 Clock source selection /
<>	161:2cc1468da177	587	/**
<>	161:2cc1468da177	588	* @}
<>	161:2cc1468da177	589	*/
<>	161:2cc1468da177	590
<>	161:2cc1468da177	591	/** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source
<>	161:2cc1468da177	592	* @{
<>	161:2cc1468da177	593	*/
<>	161:2cc1468da177	594	#define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /!< SDMMC1 Clock source selection /
<>	161:2cc1468da177	595	#if defined(SDMMC2)
<>	161:2cc1468da177	596	#define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /!< SDMMC2 Clock source selection /
<>	161:2cc1468da177	597	#endif /* SDMMC2 */
<>	161:2cc1468da177	598	/**
<>	161:2cc1468da177	599	* @}
<>	161:2cc1468da177	600	*/
<>	161:2cc1468da177	601
<>	161:2cc1468da177	602	/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
<>	161:2cc1468da177	603	* @{
<>	161:2cc1468da177	604	*/
<>	161:2cc1468da177	605	#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< CK48M Domain clock source selection /
<>	161:2cc1468da177	606	/**
<>	161:2cc1468da177	607	* @}
<>	161:2cc1468da177	608	*/
<>	161:2cc1468da177	609
<>	161:2cc1468da177	610	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
<>	161:2cc1468da177	611	* @{
<>	161:2cc1468da177	612	*/
<>	161:2cc1468da177	613	#define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< RNG Clock source selection /
<>	161:2cc1468da177	614	/**
<>	161:2cc1468da177	615	* @}
<>	161:2cc1468da177	616	*/
<>	161:2cc1468da177	617
<>	161:2cc1468da177	618	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
<>	161:2cc1468da177	619	* @{
<>	161:2cc1468da177	620	*/
<>	161:2cc1468da177	621	#define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /!< USB Clock source selection /
<>	161:2cc1468da177	622	/**
<>	161:2cc1468da177	623	* @}
<>	161:2cc1468da177	624	*/
<>	161:2cc1468da177	625
<>	161:2cc1468da177	626	#if defined(CEC)
<>	161:2cc1468da177	627	/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
<>	161:2cc1468da177	628	* @{
<>	161:2cc1468da177	629	*/
<>	161:2cc1468da177	630	#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /!< CEC Clock source selection /
<>	161:2cc1468da177	631	/**
<>	161:2cc1468da177	632	* @}
<>	161:2cc1468da177	633	*/
<>	161:2cc1468da177	634	#endif /* CEC */
<>	161:2cc1468da177	635
<>	161:2cc1468da177	636	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
<>	161:2cc1468da177	637	* @{
<>	161:2cc1468da177	638	*/
<>	161:2cc1468da177	639	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S Clock source selection /
<>	161:2cc1468da177	640	/**
<>	161:2cc1468da177	641	* @}
<>	161:2cc1468da177	642	*/
<>	161:2cc1468da177	643	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	644	/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
<>	161:2cc1468da177	645	* @{
<>	161:2cc1468da177	646	*/
<>	161:2cc1468da177	647	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /!< DFSDM Audio Clock source selection /
<>	161:2cc1468da177	648	/**
<>	161:2cc1468da177	649	* @}
<>	161:2cc1468da177	650	*/
<>	161:2cc1468da177	651
<>	161:2cc1468da177	652	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
<>	161:2cc1468da177	653	* @{
<>	161:2cc1468da177	654	*/
<>	161:2cc1468da177	655	#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /!< DFSDM Clock source selection /
<>	161:2cc1468da177	656	/**
<>	161:2cc1468da177	657	* @}
<>	161:2cc1468da177	658	*/
<>	161:2cc1468da177	659	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	660
<>	161:2cc1468da177	661	#if defined(DSI)
<>	161:2cc1468da177	662	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
<>	161:2cc1468da177	663	* @{
<>	161:2cc1468da177	664	*/
<>	161:2cc1468da177	665	#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /!< DSI Clock source selection /
<>	161:2cc1468da177	666	/**
<>	161:2cc1468da177	667	* @}
<>	161:2cc1468da177	668	*/
<>	161:2cc1468da177	669	#endif /* DSI */
<>	161:2cc1468da177	670
<>	161:2cc1468da177	671	#if defined(LTDC)
<>	161:2cc1468da177	672	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
<>	161:2cc1468da177	673	* @{
<>	161:2cc1468da177	674	*/
<>	161:2cc1468da177	675	#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /!< LTDC Clock source selection /
<>	161:2cc1468da177	676	/**
<>	161:2cc1468da177	677	* @}
<>	161:2cc1468da177	678	*/
<>	161:2cc1468da177	679	#endif /* LTDC */
<>	161:2cc1468da177	680
<>	161:2cc1468da177	681	#if defined(SPDIFRX)
<>	161:2cc1468da177	682	/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
<>	161:2cc1468da177	683	* @{
<>	161:2cc1468da177	684	*/
<>	161:2cc1468da177	685	#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /!< SPDIFRX Clock source selection /
<>	161:2cc1468da177	686	/**
<>	161:2cc1468da177	687	* @}
<>	161:2cc1468da177	688	*/
<>	161:2cc1468da177	689	#endif /* SPDIFRX */
<>	161:2cc1468da177	690
<>	161:2cc1468da177	691	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
<>	161:2cc1468da177	692	* @{
<>	161:2cc1468da177	693	*/
<>	161:2cc1468da177	694	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
<>	161:2cc1468da177	695	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
<>	161:2cc1468da177	696	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
<>	161:2cc1468da177	697	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
<>	161:2cc1468da177	698	/**
<>	161:2cc1468da177	699	* @}
<>	161:2cc1468da177	700	*/
<>	161:2cc1468da177	701
<>	161:2cc1468da177	702	/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
<>	161:2cc1468da177	703	* @{
<>	161:2cc1468da177	704	*/
<>	161:2cc1468da177	705	#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /!< Timers clock to twice PCLK /
<>	161:2cc1468da177	706	#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /!< Timers clock to four time PCLK /
<>	161:2cc1468da177	707	/**
<>	161:2cc1468da177	708	* @}
<>	161:2cc1468da177	709	*/
<>	161:2cc1468da177	710
<>	161:2cc1468da177	711	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
<>	161:2cc1468da177	712	* @{
<>	161:2cc1468da177	713	*/
<>	161:2cc1468da177	714	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
<>	161:2cc1468da177	715	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
<>	161:2cc1468da177	716	/**
<>	161:2cc1468da177	717	* @}
<>	161:2cc1468da177	718	*/
<>	161:2cc1468da177	719
<>	161:2cc1468da177	720	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
<>	161:2cc1468da177	721	* @{
<>	161:2cc1468da177	722	*/
<>	161:2cc1468da177	723	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 2 /
<>	161:2cc1468da177	724	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 3 /
<>	161:2cc1468da177	725	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 4 /
<>	161:2cc1468da177	726	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 5 /
<>	161:2cc1468da177	727	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 6 /
<>	161:2cc1468da177	728	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 7 /
<>	161:2cc1468da177	729	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 8 /
<>	161:2cc1468da177	730	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 9 /
<>	161:2cc1468da177	731	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 10 /
<>	161:2cc1468da177	732	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 11 /
<>	161:2cc1468da177	733	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 12 /
<>	161:2cc1468da177	734	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 13 /
<>	161:2cc1468da177	735	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 14 /
<>	161:2cc1468da177	736	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 15 /
<>	161:2cc1468da177	737	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 16 /
<>	161:2cc1468da177	738	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 17 /
<>	161:2cc1468da177	739	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 18 /
<>	161:2cc1468da177	740	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 19 /
<>	161:2cc1468da177	741	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 20 /
<>	161:2cc1468da177	742	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 21 /
<>	161:2cc1468da177	743	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 22 /
<>	161:2cc1468da177	744	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 23 /
<>	161:2cc1468da177	745	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 24 /
<>	161:2cc1468da177	746	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 25 /
<>	161:2cc1468da177	747	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 26 /
<>	161:2cc1468da177	748	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 27 /
<>	161:2cc1468da177	749	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 28 /
<>	161:2cc1468da177	750	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 29 /
<>	161:2cc1468da177	751	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 30 /
<>	161:2cc1468da177	752	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 31 /
<>	161:2cc1468da177	753	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL, PLLI2S and PLLSAI division factor by 32 /
<>	161:2cc1468da177	754	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 33 /
<>	161:2cc1468da177	755	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 34 /
<>	161:2cc1468da177	756	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 35 /
<>	161:2cc1468da177	757	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 36 /
<>	161:2cc1468da177	758	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 37 /
<>	161:2cc1468da177	759	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 38 /
<>	161:2cc1468da177	760	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 39 /
<>	161:2cc1468da177	761	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 40 /
<>	161:2cc1468da177	762	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 41 /
<>	161:2cc1468da177	763	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 42 /
<>	161:2cc1468da177	764	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 43 /
<>	161:2cc1468da177	765	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 44 /
<>	161:2cc1468da177	766	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 45 /
<>	161:2cc1468da177	767	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 46 /
<>	161:2cc1468da177	768	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 47 /
<>	161:2cc1468da177	769	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL, PLLI2S and PLLSAI division factor by 48 /
<>	161:2cc1468da177	770	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 49 /
<>	161:2cc1468da177	771	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 50 /
<>	161:2cc1468da177	772	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 51 /
<>	161:2cc1468da177	773	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 52 /
<>	161:2cc1468da177	774	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 53 /
<>	161:2cc1468da177	775	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 54 /
<>	161:2cc1468da177	776	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 55 /
<>	161:2cc1468da177	777	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL, PLLI2S and PLLSAI division factor by 56 /
<>	161:2cc1468da177	778	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 57 /
<>	161:2cc1468da177	779	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 58 /
<>	161:2cc1468da177	780	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 59 /
<>	161:2cc1468da177	781	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL, PLLI2S and PLLSAI division factor by 60 /
<>	161:2cc1468da177	782	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 61 /
<>	161:2cc1468da177	783	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL, PLLI2S and PLLSAI division factor by 62 /
<>	161:2cc1468da177	784	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL, PLLI2S and PLLSAI division factor by 63 /
<>	161:2cc1468da177	785	/**
<>	161:2cc1468da177	786	* @}
<>	161:2cc1468da177	787	*/
<>	161:2cc1468da177	788
<>	161:2cc1468da177	789	#if defined(RCC_PLLCFGR_PLLR)
<>	161:2cc1468da177	790	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
<>	161:2cc1468da177	791	* @{
<>	161:2cc1468da177	792	*/
<>	161:2cc1468da177	793	#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 2 /
<>	161:2cc1468da177	794	#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 3 /
<>	161:2cc1468da177	795	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
<>	161:2cc1468da177	796	#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 5 /
<>	161:2cc1468da177	797	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2\|RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
<>	161:2cc1468da177	798	#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 7 /
<>	161:2cc1468da177	799	/**
<>	161:2cc1468da177	800	* @}
<>	161:2cc1468da177	801	*/
<>	161:2cc1468da177	802	#endif /* RCC_PLLCFGR_PLLR */
<>	161:2cc1468da177	803
<>	161:2cc1468da177	804	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
<>	161:2cc1468da177	805	* @{
<>	161:2cc1468da177	806	*/
<>	161:2cc1468da177	807	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
<>	161:2cc1468da177	808	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
<>	161:2cc1468da177	809	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
<>	161:2cc1468da177	810	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
<>	161:2cc1468da177	811	/**
<>	161:2cc1468da177	812	* @}
<>	161:2cc1468da177	813	*/
<>	161:2cc1468da177	814
<>	161:2cc1468da177	815	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
<>	161:2cc1468da177	816	* @{
<>	161:2cc1468da177	817	*/
<>	161:2cc1468da177	818	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
<>	161:2cc1468da177	819	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
<>	161:2cc1468da177	820	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
<>	161:2cc1468da177	821	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
<>	161:2cc1468da177	822	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
<>	161:2cc1468da177	823	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
<>	161:2cc1468da177	824	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
<>	161:2cc1468da177	825	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
<>	161:2cc1468da177	826	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
<>	161:2cc1468da177	827	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
<>	161:2cc1468da177	828	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
<>	161:2cc1468da177	829	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
<>	161:2cc1468da177	830	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
<>	161:2cc1468da177	831	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
<>	161:2cc1468da177	832	/**
<>	161:2cc1468da177	833	* @}
<>	161:2cc1468da177	834	*/
<>	161:2cc1468da177	835
<>	161:2cc1468da177	836	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
<>	161:2cc1468da177	837	* @{
<>	161:2cc1468da177	838	*/
<>	161:2cc1468da177	839	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
<>	161:2cc1468da177	840	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
<>	161:2cc1468da177	841	/**
<>	161:2cc1468da177	842	* @}
<>	161:2cc1468da177	843	*/
<>	161:2cc1468da177	844
<>	161:2cc1468da177	845	/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
<>	161:2cc1468da177	846	* @{
<>	161:2cc1468da177	847	*/
<>	161:2cc1468da177	848	#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /!< PLLI2S division factor for PLLI2SQ output by 2 /
<>	161:2cc1468da177	849	#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 3 /
<>	161:2cc1468da177	850	#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /!< PLLI2S division factor for PLLI2SQ output by 4 /
<>	161:2cc1468da177	851	#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 5 /
<>	161:2cc1468da177	852	#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 6 /
<>	161:2cc1468da177	853	#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 7 /
<>	161:2cc1468da177	854	#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /!< PLLI2S division factor for PLLI2SQ output by 8 /
<>	161:2cc1468da177	855	#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 9 /
<>	161:2cc1468da177	856	#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 10 /
<>	161:2cc1468da177	857	#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 11 /
<>	161:2cc1468da177	858	#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2) /!< PLLI2S division factor for PLLI2SQ output by 12 /
<>	161:2cc1468da177	859	#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 13 /
<>	161:2cc1468da177	860	#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1) /!< PLLI2S division factor for PLLI2SQ output by 14 /
<>	161:2cc1468da177	861	#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 \| RCC_PLLI2SCFGR_PLLI2SQ_2 \| RCC_PLLI2SCFGR_PLLI2SQ_1 \| RCC_PLLI2SCFGR_PLLI2SQ_0) /!< PLLI2S division factor for PLLI2SQ output by 15 /
<>	161:2cc1468da177	862	/**
<>	161:2cc1468da177	863	* @}
<>	161:2cc1468da177	864	*/
<>	161:2cc1468da177	865
<>	161:2cc1468da177	866	/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
<>	161:2cc1468da177	867	* @{
<>	161:2cc1468da177	868	*/
<>	161:2cc1468da177	869	#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /!< PLLI2S division factor for PLLI2SDIVQ output by 1 /
<>	161:2cc1468da177	870	#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /!< PLLI2S division factor for PLLI2SDIVQ output by 2 /
<>	161:2cc1468da177	871	#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /!< PLLI2S division factor for PLLI2SDIVQ output by 3 /
<>	161:2cc1468da177	872	#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 4 /
<>	161:2cc1468da177	873	#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /!< PLLI2S division factor for PLLI2SDIVQ output by 5 /
<>	161:2cc1468da177	874	#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 6 /
<>	161:2cc1468da177	875	#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 7 /
<>	161:2cc1468da177	876	#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 8 /
<>	161:2cc1468da177	877	#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /!< PLLI2S division factor for PLLI2SDIVQ output by 9 /
<>	161:2cc1468da177	878	#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 10 /
<>	161:2cc1468da177	879	#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 11 /
<>	161:2cc1468da177	880	#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 12 /
<>	161:2cc1468da177	881	#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 13 /
<>	161:2cc1468da177	882	#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 14 /
<>	161:2cc1468da177	883	#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 15 /
<>	161:2cc1468da177	884	#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 16 /
<>	161:2cc1468da177	885	#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /!< PLLI2S division factor for PLLI2SDIVQ output by 17 /
<>	161:2cc1468da177	886	#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 18 /
<>	161:2cc1468da177	887	#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 19 /
<>	161:2cc1468da177	888	#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 20 /
<>	161:2cc1468da177	889	#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 21 /
<>	161:2cc1468da177	890	#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 22 /
<>	161:2cc1468da177	891	#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 23 /
<>	161:2cc1468da177	892	#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 24 /
<>	161:2cc1468da177	893	#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3) /!< PLLI2S division factor for PLLI2SDIVQ output by 25 /
<>	161:2cc1468da177	894	#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 26 /
<>	161:2cc1468da177	895	#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 27 /
<>	161:2cc1468da177	896	#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 28 /
<>	161:2cc1468da177	897	#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2) /!< PLLI2S division factor for PLLI2SDIVQ output by 29 /
<>	161:2cc1468da177	898	#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 30 /
<>	161:2cc1468da177	899	#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1) /!< PLLI2S division factor for PLLI2SDIVQ output by 31 /
<>	161:2cc1468da177	900	#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 \| RCC_DCKCFGR1_PLLI2SDIVQ_3 \| RCC_DCKCFGR1_PLLI2SDIVQ_2 \| RCC_DCKCFGR1_PLLI2SDIVQ_1 \| RCC_DCKCFGR1_PLLI2SDIVQ_0) /!< PLLI2S division factor for PLLI2SDIVQ output by 32 /
<>	161:2cc1468da177	901	/**
<>	161:2cc1468da177	902	* @}
<>	161:2cc1468da177	903	*/
<>	161:2cc1468da177	904
<>	161:2cc1468da177	905	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
<>	161:2cc1468da177	906	* @{
<>	161:2cc1468da177	907	*/
<>	161:2cc1468da177	908	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
<>	161:2cc1468da177	909	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
<>	161:2cc1468da177	910	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
<>	161:2cc1468da177	911	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
<>	161:2cc1468da177	912	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
<>	161:2cc1468da177	913	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
<>	161:2cc1468da177	914	/**
<>	161:2cc1468da177	915	* @}
<>	161:2cc1468da177	916	*/
<>	161:2cc1468da177	917
<>	161:2cc1468da177	918	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
<>	161:2cc1468da177	919	/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
<>	161:2cc1468da177	920	* @{
<>	161:2cc1468da177	921	*/
<>	161:2cc1468da177	922	#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /!< PLLI2S division factor for PLLI2SP output by 2 /
<>	161:2cc1468da177	923	#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /!< PLLI2S division factor for PLLI2SP output by 4 /
<>	161:2cc1468da177	924	#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /!< PLLI2S division factor for PLLI2SP output by 6 /
<>	161:2cc1468da177	925	#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 \| RCC_PLLI2SCFGR_PLLI2SP_0) /!< PLLI2S division factor for PLLI2SP output by 8 /
<>	161:2cc1468da177	926	/**
<>	161:2cc1468da177	927	* @}
<>	161:2cc1468da177	928	*/
<>	161:2cc1468da177	929	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
<>	161:2cc1468da177	930
<>	161:2cc1468da177	931	/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
<>	161:2cc1468da177	932	* @{
<>	161:2cc1468da177	933	*/
<>	161:2cc1468da177	934	#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /!< PLLSAI division factor for PLLSAIQ output by 2 /
<>	161:2cc1468da177	935	#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 3 /
<>	161:2cc1468da177	936	#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /!< PLLSAI division factor for PLLSAIQ output by 4 /
<>	161:2cc1468da177	937	#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 5 /
<>	161:2cc1468da177	938	#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 6 /
<>	161:2cc1468da177	939	#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 7 /
<>	161:2cc1468da177	940	#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /!< PLLSAI division factor for PLLSAIQ output by 8 /
<>	161:2cc1468da177	941	#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 9 /
<>	161:2cc1468da177	942	#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 10 /
<>	161:2cc1468da177	943	#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 11 /
<>	161:2cc1468da177	944	#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2) /!< PLLSAI division factor for PLLSAIQ output by 12 /
<>	161:2cc1468da177	945	#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 13 /
<>	161:2cc1468da177	946	#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1) /!< PLLSAI division factor for PLLSAIQ output by 14 /
<>	161:2cc1468da177	947	#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 \| RCC_PLLSAICFGR_PLLSAIQ_2 \| RCC_PLLSAICFGR_PLLSAIQ_1 \| RCC_PLLSAICFGR_PLLSAIQ_0) /!< PLLSAI division factor for PLLSAIQ output by 15 /
<>	161:2cc1468da177	948	/**
<>	161:2cc1468da177	949	* @}
<>	161:2cc1468da177	950	*/
<>	161:2cc1468da177	951
<>	161:2cc1468da177	952	/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
<>	161:2cc1468da177	953	* @{
<>	161:2cc1468da177	954	*/
<>	161:2cc1468da177	955	#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /!< PLLSAI division factor for PLLSAIDIVQ output by 1 /
<>	161:2cc1468da177	956	#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /!< PLLSAI division factor for PLLSAIDIVQ output by 2 /
<>	161:2cc1468da177	957	#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /!< PLLSAI division factor for PLLSAIDIVQ output by 3 /
<>	161:2cc1468da177	958	#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 4 /
<>	161:2cc1468da177	959	#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /!< PLLSAI division factor for PLLSAIDIVQ output by 5 /
<>	161:2cc1468da177	960	#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 6 /
<>	161:2cc1468da177	961	#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 7 /
<>	161:2cc1468da177	962	#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 8 /
<>	161:2cc1468da177	963	#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /!< PLLSAI division factor for PLLSAIDIVQ output by 9 /
<>	161:2cc1468da177	964	#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 10 /
<>	161:2cc1468da177	965	#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 11 /
<>	161:2cc1468da177	966	#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 12 /
<>	161:2cc1468da177	967	#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 13 /
<>	161:2cc1468da177	968	#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 14 /
<>	161:2cc1468da177	969	#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 15 /
<>	161:2cc1468da177	970	#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 16 /
<>	161:2cc1468da177	971	#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /!< PLLSAI division factor for PLLSAIDIVQ output by 17 /
<>	161:2cc1468da177	972	#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 18 /
<>	161:2cc1468da177	973	#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 19 /
<>	161:2cc1468da177	974	#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 20 /
<>	161:2cc1468da177	975	#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 21 /
<>	161:2cc1468da177	976	#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 22 /
<>	161:2cc1468da177	977	#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 23 /
<>	161:2cc1468da177	978	#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 24 /
<>	161:2cc1468da177	979	#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3) /!< PLLSAI division factor for PLLSAIDIVQ output by 25 /
<>	161:2cc1468da177	980	#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 26 /
<>	161:2cc1468da177	981	#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 27 /
<>	161:2cc1468da177	982	#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 28 /
<>	161:2cc1468da177	983	#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2) /!< PLLSAI division factor for PLLSAIDIVQ output by 29 /
<>	161:2cc1468da177	984	#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 30 /
<>	161:2cc1468da177	985	#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1) /!< PLLSAI division factor for PLLSAIDIVQ output by 31 /
<>	161:2cc1468da177	986	#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 \| RCC_DCKCFGR1_PLLSAIDIVQ_3 \| RCC_DCKCFGR1_PLLSAIDIVQ_2 \| RCC_DCKCFGR1_PLLSAIDIVQ_1 \| RCC_DCKCFGR1_PLLSAIDIVQ_0) /!< PLLSAI division factor for PLLSAIDIVQ output by 32 /
<>	161:2cc1468da177	987	/**
<>	161:2cc1468da177	988	* @}
<>	161:2cc1468da177	989	*/
<>	161:2cc1468da177	990
<>	161:2cc1468da177	991	#if defined(RCC_PLLSAICFGR_PLLSAIR)
<>	161:2cc1468da177	992	/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
<>	161:2cc1468da177	993	* @{
<>	161:2cc1468da177	994	*/
<>	161:2cc1468da177	995	#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /!< PLLSAI division factor for PLLSAIR output by 2 /
<>	161:2cc1468da177	996	#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 3 /
<>	161:2cc1468da177	997	#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /!< PLLSAI division factor for PLLSAIR output by 4 /
<>	161:2cc1468da177	998	#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 5 /
<>	161:2cc1468da177	999	#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1) /!< PLLSAI division factor for PLLSAIR output by 6 /
<>	161:2cc1468da177	1000	#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 \| RCC_PLLSAICFGR_PLLSAIR_1 \| RCC_PLLSAICFGR_PLLSAIR_0) /!< PLLSAI division factor for PLLSAIR output by 7 /
<>	161:2cc1468da177	1001	/**
<>	161:2cc1468da177	1002	* @}
<>	161:2cc1468da177	1003	*/
<>	161:2cc1468da177	1004	#endif /* RCC_PLLSAICFGR_PLLSAIR */
<>	161:2cc1468da177	1005
<>	161:2cc1468da177	1006	#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
<>	161:2cc1468da177	1007	/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
<>	161:2cc1468da177	1008	* @{
<>	161:2cc1468da177	1009	*/
<>	161:2cc1468da177	1010	#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIDIVR output by 2 /
<>	161:2cc1468da177	1011	#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /!< PLLSAI division factor for PLLSAIDIVR output by 4 /
<>	161:2cc1468da177	1012	#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /!< PLLSAI division factor for PLLSAIDIVR output by 8 /
<>	161:2cc1468da177	1013	#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 \| RCC_DCKCFGR1_PLLSAIDIVR_0) /!< PLLSAI division factor for PLLSAIDIVR output by 16 /
<>	161:2cc1468da177	1014	/**
<>	161:2cc1468da177	1015	* @}
<>	161:2cc1468da177	1016	*/
<>	161:2cc1468da177	1017	#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
<>	161:2cc1468da177	1018
<>	161:2cc1468da177	1019	/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
<>	161:2cc1468da177	1020	* @{
<>	161:2cc1468da177	1021	*/
<>	161:2cc1468da177	1022	#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /!< PLLSAI division factor for PLLSAIP output by 2 /
<>	161:2cc1468da177	1023	#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /!< PLLSAI division factor for PLLSAIP output by 4 /
<>	161:2cc1468da177	1024	#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /!< PLLSAI division factor for PLLSAIP output by 6 /
<>	161:2cc1468da177	1025	#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 \| RCC_PLLSAICFGR_PLLSAIP_0) /!< PLLSAI division factor for PLLSAIP output by 8 /
<>	161:2cc1468da177	1026	/**
<>	161:2cc1468da177	1027	* @}
<>	161:2cc1468da177	1028	*/
<>	161:2cc1468da177	1029
<>	161:2cc1468da177	1030	/**
<>	161:2cc1468da177	1031	* @}
<>	161:2cc1468da177	1032	*/
<>	161:2cc1468da177	1033
<>	161:2cc1468da177	1034	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	1035	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
<>	161:2cc1468da177	1036	* @{
<>	161:2cc1468da177	1037	*/
<>	161:2cc1468da177	1038
<>	161:2cc1468da177	1039	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
<>	161:2cc1468da177	1040	* @{
<>	161:2cc1468da177	1041	*/
<>	161:2cc1468da177	1042
<>	161:2cc1468da177	1043	/**
<>	161:2cc1468da177	1044	* @brief Write a value in RCC register
<>	161:2cc1468da177	1045	* @param __REG__ Register to be written
<>	161:2cc1468da177	1046	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	1047	* @retval None
<>	161:2cc1468da177	1048	*/
<>	161:2cc1468da177	1049	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
<>	161:2cc1468da177	1050
<>	161:2cc1468da177	1051	/**
<>	161:2cc1468da177	1052	* @brief Read a value in RCC register
<>	161:2cc1468da177	1053	* @param __REG__ Register to be read
<>	161:2cc1468da177	1054	* @retval Register value
<>	161:2cc1468da177	1055	*/
<>	161:2cc1468da177	1056	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
<>	161:2cc1468da177	1057	/**
<>	161:2cc1468da177	1058	* @}
<>	161:2cc1468da177	1059	*/
<>	161:2cc1468da177	1060
<>	161:2cc1468da177	1061	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
<>	161:2cc1468da177	1062	* @{
<>	161:2cc1468da177	1063	*/
<>	161:2cc1468da177	1064
<>	161:2cc1468da177	1065	/**
<>	161:2cc1468da177	1066	* @brief Helper macro to calculate the PLLCLK frequency on system domain
<>	161:2cc1468da177	1067	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1068	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
<>	161:2cc1468da177	1069	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1070	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1071	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1072	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1073	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1074	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1075	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1076	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1077	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1078	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1079	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1080	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1081	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1082	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1083	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1084	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1085	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1086	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1087	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1088	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1089	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1090	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1091	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1092	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1093	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1094	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1095	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1096	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1097	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1098	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1099	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1100	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1101	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1102	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1103	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1104	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1105	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1106	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1107	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1108	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1109	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1110	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1111	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1112	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1113	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1114	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1115	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1116	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1117	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1118	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1119	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1120	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1121	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1122	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1123	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1124	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1125	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1126	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1127	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1128	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1129	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1130	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1131	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1132	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1133	* @param __PLLN__ Between 50 and 432
<>	161:2cc1468da177	1134	* @param __PLLP__ This parameter can be one of the following values:
<>	161:2cc1468da177	1135	* @arg @ref LL_RCC_PLLP_DIV_2
<>	161:2cc1468da177	1136	* @arg @ref LL_RCC_PLLP_DIV_4
<>	161:2cc1468da177	1137	* @arg @ref LL_RCC_PLLP_DIV_6
<>	161:2cc1468da177	1138	* @arg @ref LL_RCC_PLLP_DIV_8
<>	161:2cc1468da177	1139	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1140	*/
<>	161:2cc1468da177	1141	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
<>	161:2cc1468da177	1142	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
<>	161:2cc1468da177	1143
<>	161:2cc1468da177	1144	/**
<>	161:2cc1468da177	1145	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
<>	161:2cc1468da177	1146	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1147	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
<>	161:2cc1468da177	1148	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1149	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1150	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1151	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1152	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1153	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1154	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1155	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1156	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1157	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1158	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1159	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1160	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1161	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1162	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1163	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1164	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1165	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1166	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1167	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1168	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1169	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1170	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1171	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1172	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1173	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1174	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1175	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1176	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1177	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1178	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1179	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1180	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1181	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1182	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1183	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1184	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1185	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1186	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1187	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1188	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1189	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1190	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1191	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1192	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1193	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1194	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1195	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1196	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1197	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1198	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1199	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1200	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1201	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1202	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1203	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1204	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1205	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1206	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1207	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1208	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1209	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1210	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1211	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1212	* @param __PLLN__ Between 50 and 432
<>	161:2cc1468da177	1213	* @param __PLLQ__ This parameter can be one of the following values:
<>	161:2cc1468da177	1214	* @arg @ref LL_RCC_PLLQ_DIV_2
<>	161:2cc1468da177	1215	* @arg @ref LL_RCC_PLLQ_DIV_3
<>	161:2cc1468da177	1216	* @arg @ref LL_RCC_PLLQ_DIV_4
<>	161:2cc1468da177	1217	* @arg @ref LL_RCC_PLLQ_DIV_5
<>	161:2cc1468da177	1218	* @arg @ref LL_RCC_PLLQ_DIV_6
<>	161:2cc1468da177	1219	* @arg @ref LL_RCC_PLLQ_DIV_7
<>	161:2cc1468da177	1220	* @arg @ref LL_RCC_PLLQ_DIV_8
<>	161:2cc1468da177	1221	* @arg @ref LL_RCC_PLLQ_DIV_9
<>	161:2cc1468da177	1222	* @arg @ref LL_RCC_PLLQ_DIV_10
<>	161:2cc1468da177	1223	* @arg @ref LL_RCC_PLLQ_DIV_11
<>	161:2cc1468da177	1224	* @arg @ref LL_RCC_PLLQ_DIV_12
<>	161:2cc1468da177	1225	* @arg @ref LL_RCC_PLLQ_DIV_13
<>	161:2cc1468da177	1226	* @arg @ref LL_RCC_PLLQ_DIV_14
<>	161:2cc1468da177	1227	* @arg @ref LL_RCC_PLLQ_DIV_15
<>	161:2cc1468da177	1228	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1229	*/
<>	161:2cc1468da177	1230	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
<>	161:2cc1468da177	1231	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
<>	161:2cc1468da177	1232
<>	161:2cc1468da177	1233	#if defined(DSI)
<>	161:2cc1468da177	1234	/**
<>	161:2cc1468da177	1235	* @brief Helper macro to calculate the PLLCLK frequency used on DSI
<>	161:2cc1468da177	1236	* @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1237	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
<>	161:2cc1468da177	1238	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1239	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1240	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1241	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1242	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1243	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1244	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1245	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1246	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1247	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1248	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1249	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1250	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1251	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1252	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1253	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1254	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1255	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1256	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1257	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1258	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1259	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1260	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1261	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1262	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1263	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1264	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1265	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1266	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1267	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1268	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1269	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1270	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1271	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1272	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1273	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1274	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1275	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1276	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1277	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1278	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1279	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1280	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1281	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1282	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1283	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1284	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1285	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1286	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1287	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1288	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1289	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1290	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1291	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1292	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1293	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1294	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1295	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1296	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1297	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1298	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1299	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1300	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1301	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1302	* @param __PLLN__ Between 50 and 432
<>	161:2cc1468da177	1303	* @param __PLLR__ This parameter can be one of the following values:
<>	161:2cc1468da177	1304	* @arg @ref LL_RCC_PLLR_DIV_2
<>	161:2cc1468da177	1305	* @arg @ref LL_RCC_PLLR_DIV_3
<>	161:2cc1468da177	1306	* @arg @ref LL_RCC_PLLR_DIV_4
<>	161:2cc1468da177	1307	* @arg @ref LL_RCC_PLLR_DIV_5
<>	161:2cc1468da177	1308	* @arg @ref LL_RCC_PLLR_DIV_6
<>	161:2cc1468da177	1309	* @arg @ref LL_RCC_PLLR_DIV_7
<>	161:2cc1468da177	1310	* @retval PLL clock frequency (in Hz)
<>	161:2cc1468da177	1311	*/
<>	161:2cc1468da177	1312	#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
<>	161:2cc1468da177	1313	((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
<>	161:2cc1468da177	1314	#endif /* DSI */
<>	161:2cc1468da177	1315
<>	161:2cc1468da177	1316	/**
<>	161:2cc1468da177	1317	* @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
<>	161:2cc1468da177	1318	* @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1319	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
<>	161:2cc1468da177	1320	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1321	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1322	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1323	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1324	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1325	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1326	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1327	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1328	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1329	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1330	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1331	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1332	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1333	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1334	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1335	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1336	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1337	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1338	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1339	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1340	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1341	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1342	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1343	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1344	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1345	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1346	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1347	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1348	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1349	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1350	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1351	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1352	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1353	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1354	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1355	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1356	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1357	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1358	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1359	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1360	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1361	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1362	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1363	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1364	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1365	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1366	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1367	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1368	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1369	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1370	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1371	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1372	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1373	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1374	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1375	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1376	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1377	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1378	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1379	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1380	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1381	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1382	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1383	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1384	* @param __PLLSAIN__ Between 50 and 432
<>	161:2cc1468da177	1385	* @param __PLLSAIQ__ This parameter can be one of the following values:
<>	161:2cc1468da177	1386	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
<>	161:2cc1468da177	1387	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
<>	161:2cc1468da177	1388	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
<>	161:2cc1468da177	1389	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
<>	161:2cc1468da177	1390	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
<>	161:2cc1468da177	1391	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
<>	161:2cc1468da177	1392	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
<>	161:2cc1468da177	1393	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
<>	161:2cc1468da177	1394	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
<>	161:2cc1468da177	1395	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
<>	161:2cc1468da177	1396	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
<>	161:2cc1468da177	1397	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
<>	161:2cc1468da177	1398	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
<>	161:2cc1468da177	1399	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
<>	161:2cc1468da177	1400	* @param __PLLSAIDIVQ__ This parameter can be one of the following values:
<>	161:2cc1468da177	1401	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
<>	161:2cc1468da177	1402	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
<>	161:2cc1468da177	1403	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
<>	161:2cc1468da177	1404	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
<>	161:2cc1468da177	1405	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
<>	161:2cc1468da177	1406	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
<>	161:2cc1468da177	1407	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
<>	161:2cc1468da177	1408	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
<>	161:2cc1468da177	1409	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
<>	161:2cc1468da177	1410	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
<>	161:2cc1468da177	1411	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
<>	161:2cc1468da177	1412	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
<>	161:2cc1468da177	1413	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
<>	161:2cc1468da177	1414	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
<>	161:2cc1468da177	1415	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
<>	161:2cc1468da177	1416	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
<>	161:2cc1468da177	1417	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
<>	161:2cc1468da177	1418	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
<>	161:2cc1468da177	1419	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
<>	161:2cc1468da177	1420	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
<>	161:2cc1468da177	1421	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
<>	161:2cc1468da177	1422	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
<>	161:2cc1468da177	1423	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
<>	161:2cc1468da177	1424	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
<>	161:2cc1468da177	1425	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
<>	161:2cc1468da177	1426	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
<>	161:2cc1468da177	1427	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
<>	161:2cc1468da177	1428	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
<>	161:2cc1468da177	1429	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
<>	161:2cc1468da177	1430	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
<>	161:2cc1468da177	1431	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
<>	161:2cc1468da177	1432	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
<>	161:2cc1468da177	1433	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1434	*/
<>	161:2cc1468da177	1435	#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
<>	161:2cc1468da177	1436	(((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U)))
<>	161:2cc1468da177	1437
<>	161:2cc1468da177	1438	/**
<>	161:2cc1468da177	1439	* @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
<>	161:2cc1468da177	1440	* @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1441	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
<>	161:2cc1468da177	1442	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1443	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1444	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1445	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1446	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1447	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1448	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1449	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1450	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1451	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1452	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1453	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1454	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1455	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1456	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1457	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1458	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1459	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1460	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1461	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1462	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1463	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1464	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1465	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1466	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1467	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1468	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1469	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1470	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1471	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1472	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1473	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1474	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1475	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1476	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1477	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1478	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1479	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1480	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1481	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1482	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1483	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1484	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1485	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1486	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1487	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1488	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1489	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1490	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1491	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1492	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1493	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1494	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1495	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1496	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1497	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1498	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1499	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1500	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1501	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1502	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1503	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1504	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1505	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1506	* @param __PLLSAIN__ Between 50 and 432
<>	161:2cc1468da177	1507	* @param __PLLSAIP__ This parameter can be one of the following values:
<>	161:2cc1468da177	1508	* @arg @ref LL_RCC_PLLSAIP_DIV_2
<>	161:2cc1468da177	1509	* @arg @ref LL_RCC_PLLSAIP_DIV_4
<>	161:2cc1468da177	1510	* @arg @ref LL_RCC_PLLSAIP_DIV_6
<>	161:2cc1468da177	1511	* @arg @ref LL_RCC_PLLSAIP_DIV_8
<>	161:2cc1468da177	1512	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1513	*/
<>	161:2cc1468da177	1514	#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
<>	161:2cc1468da177	1515	((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
<>	161:2cc1468da177	1516
<>	161:2cc1468da177	1517	#if defined(LTDC)
<>	161:2cc1468da177	1518	/**
<>	161:2cc1468da177	1519	* @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
<>	161:2cc1468da177	1520	* @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1521	* @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
<>	161:2cc1468da177	1522	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1523	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1524	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1525	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1526	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1527	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1528	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1529	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1530	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1531	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1532	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1533	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1534	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1535	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1536	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1537	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1538	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1539	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1540	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1541	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1542	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1543	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1544	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1545	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1546	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1547	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1548	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1549	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1550	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1551	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1552	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1553	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1554	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1555	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1556	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1557	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1558	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1559	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1560	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1561	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1562	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1563	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1564	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1565	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1566	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1567	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1568	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1569	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1570	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1571	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1572	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1573	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1574	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1575	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1576	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1577	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1578	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1579	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1580	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1581	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1582	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1583	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1584	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1585	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1586	* @param __PLLSAIN__ Between 50 and 432
<>	161:2cc1468da177	1587	* @param __PLLSAIR__ This parameter can be one of the following values:
<>	161:2cc1468da177	1588	* @arg @ref LL_RCC_PLLSAIR_DIV_2
<>	161:2cc1468da177	1589	* @arg @ref LL_RCC_PLLSAIR_DIV_3
<>	161:2cc1468da177	1590	* @arg @ref LL_RCC_PLLSAIR_DIV_4
<>	161:2cc1468da177	1591	* @arg @ref LL_RCC_PLLSAIR_DIV_5
<>	161:2cc1468da177	1592	* @arg @ref LL_RCC_PLLSAIR_DIV_6
<>	161:2cc1468da177	1593	* @arg @ref LL_RCC_PLLSAIR_DIV_7
<>	161:2cc1468da177	1594	* @param __PLLSAIDIVR__ This parameter can be one of the following values:
<>	161:2cc1468da177	1595	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
<>	161:2cc1468da177	1596	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
<>	161:2cc1468da177	1597	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
<>	161:2cc1468da177	1598	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
<>	161:2cc1468da177	1599	* @retval PLLSAI clock frequency (in Hz)
<>	161:2cc1468da177	1600	*/
<>	161:2cc1468da177	1601	#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
<>	161:2cc1468da177	1602	(((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos])))
<>	161:2cc1468da177	1603	#endif /* LTDC */
<>	161:2cc1468da177	1604
<>	161:2cc1468da177	1605	/**
<>	161:2cc1468da177	1606	* @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
<>	161:2cc1468da177	1607	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1608	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
<>	161:2cc1468da177	1609	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1610	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1611	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1612	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1613	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1614	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1615	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1616	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1617	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1618	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1619	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1620	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1621	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1622	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1623	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1624	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1625	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1626	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1627	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1628	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1629	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1630	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1631	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1632	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1633	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1634	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1635	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1636	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1637	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1638	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1639	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1640	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1641	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1642	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1643	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1644	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1645	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1646	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1647	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1648	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1649	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1650	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1651	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1652	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1653	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1654	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1655	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1656	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1657	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1658	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1659	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1660	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1661	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1662	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1663	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1664	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1665	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1666	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1667	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1668	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1669	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1670	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1671	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1672	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1673	* @param __PLLI2SN__ Between 50 and 432
<>	161:2cc1468da177	1674	* @param __PLLI2SQ__ This parameter can be one of the following values:
<>	161:2cc1468da177	1675	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
<>	161:2cc1468da177	1676	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
<>	161:2cc1468da177	1677	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
<>	161:2cc1468da177	1678	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
<>	161:2cc1468da177	1679	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
<>	161:2cc1468da177	1680	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
<>	161:2cc1468da177	1681	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
<>	161:2cc1468da177	1682	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
<>	161:2cc1468da177	1683	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
<>	161:2cc1468da177	1684	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
<>	161:2cc1468da177	1685	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
<>	161:2cc1468da177	1686	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
<>	161:2cc1468da177	1687	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
<>	161:2cc1468da177	1688	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
<>	161:2cc1468da177	1689	* @param __PLLI2SDIVQ__ This parameter can be one of the following values:
<>	161:2cc1468da177	1690	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
<>	161:2cc1468da177	1691	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
<>	161:2cc1468da177	1692	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
<>	161:2cc1468da177	1693	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
<>	161:2cc1468da177	1694	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
<>	161:2cc1468da177	1695	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
<>	161:2cc1468da177	1696	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
<>	161:2cc1468da177	1697	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
<>	161:2cc1468da177	1698	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
<>	161:2cc1468da177	1699	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
<>	161:2cc1468da177	1700	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
<>	161:2cc1468da177	1701	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
<>	161:2cc1468da177	1702	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
<>	161:2cc1468da177	1703	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
<>	161:2cc1468da177	1704	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
<>	161:2cc1468da177	1705	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
<>	161:2cc1468da177	1706	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
<>	161:2cc1468da177	1707	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
<>	161:2cc1468da177	1708	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
<>	161:2cc1468da177	1709	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
<>	161:2cc1468da177	1710	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
<>	161:2cc1468da177	1711	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
<>	161:2cc1468da177	1712	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
<>	161:2cc1468da177	1713	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
<>	161:2cc1468da177	1714	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
<>	161:2cc1468da177	1715	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
<>	161:2cc1468da177	1716	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
<>	161:2cc1468da177	1717	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
<>	161:2cc1468da177	1718	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
<>	161:2cc1468da177	1719	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
<>	161:2cc1468da177	1720	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
<>	161:2cc1468da177	1721	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
<>	161:2cc1468da177	1722	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1723	*/
<>	161:2cc1468da177	1724	#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
<>	161:2cc1468da177	1725	(((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U)))
<>	161:2cc1468da177	1726
<>	161:2cc1468da177	1727	#if defined(SPDIFRX)
<>	161:2cc1468da177	1728	/**
<>	161:2cc1468da177	1729	* @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
<>	161:2cc1468da177	1730	* @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1731	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
<>	161:2cc1468da177	1732	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1733	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1734	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1735	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1736	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1737	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1738	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1739	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1740	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1741	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1742	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1743	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1744	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1745	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1746	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1747	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1748	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1749	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1750	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1751	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1752	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1753	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1754	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1755	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1756	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1757	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1758	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1759	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1760	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1761	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1762	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1763	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1764	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1765	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1766	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1767	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1768	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1769	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1770	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1771	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1772	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1773	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1774	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1775	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1776	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1777	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1778	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1779	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1780	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1781	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1782	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1783	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1784	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1785	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1786	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1787	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1788	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1789	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1790	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1791	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1792	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1793	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1794	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1795	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1796	* @param __PLLI2SN__ Between 50 and 432
<>	161:2cc1468da177	1797	* @param __PLLI2SP__ This parameter can be one of the following values:
<>	161:2cc1468da177	1798	* @arg @ref LL_RCC_PLLI2SP_DIV_2
<>	161:2cc1468da177	1799	* @arg @ref LL_RCC_PLLI2SP_DIV_4
<>	161:2cc1468da177	1800	* @arg @ref LL_RCC_PLLI2SP_DIV_6
<>	161:2cc1468da177	1801	* @arg @ref LL_RCC_PLLI2SP_DIV_8
<>	161:2cc1468da177	1802	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1803	*/
<>	161:2cc1468da177	1804	#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
<>	161:2cc1468da177	1805	((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
<>	161:2cc1468da177	1806	#endif /* SPDIFRX */
<>	161:2cc1468da177	1807
<>	161:2cc1468da177	1808	/**
<>	161:2cc1468da177	1809	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
<>	161:2cc1468da177	1810	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
<>	161:2cc1468da177	1811	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
<>	161:2cc1468da177	1812	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
<>	161:2cc1468da177	1813	* @param __PLLM__ This parameter can be one of the following values:
<>	161:2cc1468da177	1814	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	1815	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	1816	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	1817	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	1818	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	1819	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	1820	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	1821	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	1822	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	1823	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	1824	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	1825	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	1826	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	1827	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	1828	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	1829	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	1830	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	1831	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	1832	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	1833	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	1834	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	1835	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	1836	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	1837	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	1838	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	1839	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	1840	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	1841	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	1842	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	1843	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	1844	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	1845	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	1846	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	1847	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	1848	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	1849	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	1850	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	1851	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	1852	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	1853	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	1854	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	1855	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	1856	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	1857	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	1858	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	1859	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	1860	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	1861	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	1862	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	1863	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	1864	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	1865	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	1866	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	1867	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	1868	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	1869	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	1870	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	1871	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	1872	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	1873	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	1874	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	1875	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	1876	* @param __PLLI2SN__ Between 50 and 432
<>	161:2cc1468da177	1877	* @param __PLLI2SR__ This parameter can be one of the following values:
<>	161:2cc1468da177	1878	* @arg @ref LL_RCC_PLLI2SR_DIV_2
<>	161:2cc1468da177	1879	* @arg @ref LL_RCC_PLLI2SR_DIV_3
<>	161:2cc1468da177	1880	* @arg @ref LL_RCC_PLLI2SR_DIV_4
<>	161:2cc1468da177	1881	* @arg @ref LL_RCC_PLLI2SR_DIV_5
<>	161:2cc1468da177	1882	* @arg @ref LL_RCC_PLLI2SR_DIV_6
<>	161:2cc1468da177	1883	* @arg @ref LL_RCC_PLLI2SR_DIV_7
<>	161:2cc1468da177	1884	* @retval PLLI2S clock frequency (in Hz)
<>	161:2cc1468da177	1885	*/
<>	161:2cc1468da177	1886	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
<>	161:2cc1468da177	1887	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
<>	161:2cc1468da177	1888
<>	161:2cc1468da177	1889	/**
<>	161:2cc1468da177	1890	* @brief Helper macro to calculate the HCLK frequency
<>	161:2cc1468da177	1891	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
<>	161:2cc1468da177	1892	* @param __AHBPRESCALER__ This parameter can be one of the following values:
<>	161:2cc1468da177	1893	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	161:2cc1468da177	1894	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	161:2cc1468da177	1895	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	161:2cc1468da177	1896	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	161:2cc1468da177	1897	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	161:2cc1468da177	1898	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	161:2cc1468da177	1899	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	161:2cc1468da177	1900	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	161:2cc1468da177	1901	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	161:2cc1468da177	1902	* @retval HCLK clock frequency (in Hz)
<>	161:2cc1468da177	1903	*/
<>	161:2cc1468da177	1904	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
<>	161:2cc1468da177	1905
<>	161:2cc1468da177	1906	/**
<>	161:2cc1468da177	1907	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
<>	161:2cc1468da177	1908	* @param __HCLKFREQ__ HCLK frequency
<>	161:2cc1468da177	1909	* @param __APB1PRESCALER__ This parameter can be one of the following values:
<>	161:2cc1468da177	1910	* @arg @ref LL_RCC_APB1_DIV_1
<>	161:2cc1468da177	1911	* @arg @ref LL_RCC_APB1_DIV_2
<>	161:2cc1468da177	1912	* @arg @ref LL_RCC_APB1_DIV_4
<>	161:2cc1468da177	1913	* @arg @ref LL_RCC_APB1_DIV_8
<>	161:2cc1468da177	1914	* @arg @ref LL_RCC_APB1_DIV_16
<>	161:2cc1468da177	1915	* @retval PCLK1 clock frequency (in Hz)
<>	161:2cc1468da177	1916	*/
<>	161:2cc1468da177	1917	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
<>	161:2cc1468da177	1918
<>	161:2cc1468da177	1919	/**
<>	161:2cc1468da177	1920	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
<>	161:2cc1468da177	1921	* @param __HCLKFREQ__ HCLK frequency
<>	161:2cc1468da177	1922	* @param __APB2PRESCALER__ This parameter can be one of the following values:
<>	161:2cc1468da177	1923	* @arg @ref LL_RCC_APB2_DIV_1
<>	161:2cc1468da177	1924	* @arg @ref LL_RCC_APB2_DIV_2
<>	161:2cc1468da177	1925	* @arg @ref LL_RCC_APB2_DIV_4
<>	161:2cc1468da177	1926	* @arg @ref LL_RCC_APB2_DIV_8
<>	161:2cc1468da177	1927	* @arg @ref LL_RCC_APB2_DIV_16
<>	161:2cc1468da177	1928	* @retval PCLK2 clock frequency (in Hz)
<>	161:2cc1468da177	1929	*/
<>	161:2cc1468da177	1930	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
<>	161:2cc1468da177	1931
<>	161:2cc1468da177	1932	/**
<>	161:2cc1468da177	1933	* @}
<>	161:2cc1468da177	1934	*/
<>	161:2cc1468da177	1935
<>	161:2cc1468da177	1936	/**
<>	161:2cc1468da177	1937	* @}
<>	161:2cc1468da177	1938	*/
<>	161:2cc1468da177	1939
<>	161:2cc1468da177	1940	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	1941	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
<>	161:2cc1468da177	1942	* @{
<>	161:2cc1468da177	1943	*/
<>	161:2cc1468da177	1944
<>	161:2cc1468da177	1945	/** @defgroup RCC_LL_EF_HSE HSE
<>	161:2cc1468da177	1946	* @{
<>	161:2cc1468da177	1947	*/
<>	161:2cc1468da177	1948
<>	161:2cc1468da177	1949	/**
<>	161:2cc1468da177	1950	* @brief Enable the Clock Security System.
<>	161:2cc1468da177	1951	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
<>	161:2cc1468da177	1952	* @retval None
<>	161:2cc1468da177	1953	*/
<>	161:2cc1468da177	1954	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
<>	161:2cc1468da177	1955	{
<>	161:2cc1468da177	1956	SET_BIT(RCC->CR, RCC_CR_CSSON);
<>	161:2cc1468da177	1957	}
<>	161:2cc1468da177	1958
<>	161:2cc1468da177	1959	/**
<>	161:2cc1468da177	1960	* @brief Enable HSE external oscillator (HSE Bypass)
<>	161:2cc1468da177	1961	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
<>	161:2cc1468da177	1962	* @retval None
<>	161:2cc1468da177	1963	*/
<>	161:2cc1468da177	1964	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
<>	161:2cc1468da177	1965	{
<>	161:2cc1468da177	1966	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	161:2cc1468da177	1967	}
<>	161:2cc1468da177	1968
<>	161:2cc1468da177	1969	/**
<>	161:2cc1468da177	1970	* @brief Disable HSE external oscillator (HSE Bypass)
<>	161:2cc1468da177	1971	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
<>	161:2cc1468da177	1972	* @retval None
<>	161:2cc1468da177	1973	*/
<>	161:2cc1468da177	1974	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
<>	161:2cc1468da177	1975	{
<>	161:2cc1468da177	1976	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	161:2cc1468da177	1977	}
<>	161:2cc1468da177	1978
<>	161:2cc1468da177	1979	/**
<>	161:2cc1468da177	1980	* @brief Enable HSE crystal oscillator (HSE ON)
<>	161:2cc1468da177	1981	* @rmtoll CR HSEON LL_RCC_HSE_Enable
<>	161:2cc1468da177	1982	* @retval None
<>	161:2cc1468da177	1983	*/
<>	161:2cc1468da177	1984	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
<>	161:2cc1468da177	1985	{
<>	161:2cc1468da177	1986	SET_BIT(RCC->CR, RCC_CR_HSEON);
<>	161:2cc1468da177	1987	}
<>	161:2cc1468da177	1988
<>	161:2cc1468da177	1989	/**
<>	161:2cc1468da177	1990	* @brief Disable HSE crystal oscillator (HSE ON)
<>	161:2cc1468da177	1991	* @rmtoll CR HSEON LL_RCC_HSE_Disable
<>	161:2cc1468da177	1992	* @retval None
<>	161:2cc1468da177	1993	*/
<>	161:2cc1468da177	1994	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
<>	161:2cc1468da177	1995	{
<>	161:2cc1468da177	1996	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
<>	161:2cc1468da177	1997	}
<>	161:2cc1468da177	1998
<>	161:2cc1468da177	1999	/**
<>	161:2cc1468da177	2000	* @brief Check if HSE oscillator Ready
<>	161:2cc1468da177	2001	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
<>	161:2cc1468da177	2002	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2003	*/
<>	161:2cc1468da177	2004	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
<>	161:2cc1468da177	2005	{
<>	161:2cc1468da177	2006	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
<>	161:2cc1468da177	2007	}
<>	161:2cc1468da177	2008
<>	161:2cc1468da177	2009	/**
<>	161:2cc1468da177	2010	* @}
<>	161:2cc1468da177	2011	*/
<>	161:2cc1468da177	2012
<>	161:2cc1468da177	2013	/** @defgroup RCC_LL_EF_HSI HSI
<>	161:2cc1468da177	2014	* @{
<>	161:2cc1468da177	2015	*/
<>	161:2cc1468da177	2016
<>	161:2cc1468da177	2017	/**
<>	161:2cc1468da177	2018	* @brief Enable HSI oscillator
<>	161:2cc1468da177	2019	* @rmtoll CR HSION LL_RCC_HSI_Enable
<>	161:2cc1468da177	2020	* @retval None
<>	161:2cc1468da177	2021	*/
<>	161:2cc1468da177	2022	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
<>	161:2cc1468da177	2023	{
<>	161:2cc1468da177	2024	SET_BIT(RCC->CR, RCC_CR_HSION);
<>	161:2cc1468da177	2025	}
<>	161:2cc1468da177	2026
<>	161:2cc1468da177	2027	/**
<>	161:2cc1468da177	2028	* @brief Disable HSI oscillator
<>	161:2cc1468da177	2029	* @rmtoll CR HSION LL_RCC_HSI_Disable
<>	161:2cc1468da177	2030	* @retval None
<>	161:2cc1468da177	2031	*/
<>	161:2cc1468da177	2032	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
<>	161:2cc1468da177	2033	{
<>	161:2cc1468da177	2034	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
<>	161:2cc1468da177	2035	}
<>	161:2cc1468da177	2036
<>	161:2cc1468da177	2037	/**
<>	161:2cc1468da177	2038	* @brief Check if HSI clock is ready
<>	161:2cc1468da177	2039	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
<>	161:2cc1468da177	2040	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2041	*/
<>	161:2cc1468da177	2042	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
<>	161:2cc1468da177	2043	{
<>	161:2cc1468da177	2044	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
<>	161:2cc1468da177	2045	}
<>	161:2cc1468da177	2046
<>	161:2cc1468da177	2047	/**
<>	161:2cc1468da177	2048	* @brief Get HSI Calibration value
<>	161:2cc1468da177	2049	* @note When HSITRIM is written, HSICAL is updated with the sum of
<>	161:2cc1468da177	2050	* HSITRIM and the factory trim value
<>	161:2cc1468da177	2051	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
<>	161:2cc1468da177	2052	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	161:2cc1468da177	2053	*/
<>	161:2cc1468da177	2054	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
<>	161:2cc1468da177	2055	{
<>	161:2cc1468da177	2056	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
<>	161:2cc1468da177	2057	}
<>	161:2cc1468da177	2058
<>	161:2cc1468da177	2059	/**
<>	161:2cc1468da177	2060	* @brief Set HSI Calibration trimming
<>	161:2cc1468da177	2061	* @note user-programmable trimming value that is added to the HSICAL
<>	161:2cc1468da177	2062	* @note Default value is 16, which, when added to the HSICAL value,
<>	161:2cc1468da177	2063	* should trim the HSI to 16 MHz +/- 1 %
<>	161:2cc1468da177	2064	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
<>	161:2cc1468da177	2065	* @param Value Between Min_Data = 0 and Max_Data = 31
<>	161:2cc1468da177	2066	* @retval None
<>	161:2cc1468da177	2067	*/
<>	161:2cc1468da177	2068	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
<>	161:2cc1468da177	2069	{
<>	161:2cc1468da177	2070	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
<>	161:2cc1468da177	2071	}
<>	161:2cc1468da177	2072
<>	161:2cc1468da177	2073	/**
<>	161:2cc1468da177	2074	* @brief Get HSI Calibration trimming
<>	161:2cc1468da177	2075	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
<>	161:2cc1468da177	2076	* @retval Between Min_Data = 0 and Max_Data = 31
<>	161:2cc1468da177	2077	*/
<>	161:2cc1468da177	2078	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
<>	161:2cc1468da177	2079	{
<>	161:2cc1468da177	2080	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
<>	161:2cc1468da177	2081	}
<>	161:2cc1468da177	2082
<>	161:2cc1468da177	2083	/**
<>	161:2cc1468da177	2084	* @}
<>	161:2cc1468da177	2085	*/
<>	161:2cc1468da177	2086
<>	161:2cc1468da177	2087	/** @defgroup RCC_LL_EF_LSE LSE
<>	161:2cc1468da177	2088	* @{
<>	161:2cc1468da177	2089	*/
<>	161:2cc1468da177	2090
<>	161:2cc1468da177	2091	/**
<>	161:2cc1468da177	2092	* @brief Enable Low Speed External (LSE) crystal.
<>	161:2cc1468da177	2093	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
<>	161:2cc1468da177	2094	* @retval None
<>	161:2cc1468da177	2095	*/
<>	161:2cc1468da177	2096	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
<>	161:2cc1468da177	2097	{
<>	161:2cc1468da177	2098	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	161:2cc1468da177	2099	}
<>	161:2cc1468da177	2100
<>	161:2cc1468da177	2101	/**
<>	161:2cc1468da177	2102	* @brief Disable Low Speed External (LSE) crystal.
<>	161:2cc1468da177	2103	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
<>	161:2cc1468da177	2104	* @retval None
<>	161:2cc1468da177	2105	*/
<>	161:2cc1468da177	2106	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
<>	161:2cc1468da177	2107	{
<>	161:2cc1468da177	2108	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	161:2cc1468da177	2109	}
<>	161:2cc1468da177	2110
<>	161:2cc1468da177	2111	/**
<>	161:2cc1468da177	2112	* @brief Enable external clock source (LSE bypass).
<>	161:2cc1468da177	2113	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
<>	161:2cc1468da177	2114	* @retval None
<>	161:2cc1468da177	2115	*/
<>	161:2cc1468da177	2116	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
<>	161:2cc1468da177	2117	{
<>	161:2cc1468da177	2118	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	161:2cc1468da177	2119	}
<>	161:2cc1468da177	2120
<>	161:2cc1468da177	2121	/**
<>	161:2cc1468da177	2122	* @brief Disable external clock source (LSE bypass).
<>	161:2cc1468da177	2123	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
<>	161:2cc1468da177	2124	* @retval None
<>	161:2cc1468da177	2125	*/
<>	161:2cc1468da177	2126	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
<>	161:2cc1468da177	2127	{
<>	161:2cc1468da177	2128	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	161:2cc1468da177	2129	}
<>	161:2cc1468da177	2130
<>	161:2cc1468da177	2131	/**
<>	161:2cc1468da177	2132	* @brief Set LSE oscillator drive capability
<>	161:2cc1468da177	2133	* @note The oscillator is in Xtal mode when it is not in bypass mode.
<>	161:2cc1468da177	2134	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
<>	161:2cc1468da177	2135	* @param LSEDrive This parameter can be one of the following values:
<>	161:2cc1468da177	2136	* @arg @ref LL_RCC_LSEDRIVE_LOW
<>	161:2cc1468da177	2137	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<>	161:2cc1468da177	2138	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<>	161:2cc1468da177	2139	* @arg @ref LL_RCC_LSEDRIVE_HIGH
<>	161:2cc1468da177	2140	* @retval None
<>	161:2cc1468da177	2141	*/
<>	161:2cc1468da177	2142	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
<>	161:2cc1468da177	2143	{
<>	161:2cc1468da177	2144	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
<>	161:2cc1468da177	2145	}
<>	161:2cc1468da177	2146
<>	161:2cc1468da177	2147	/**
<>	161:2cc1468da177	2148	* @brief Get LSE oscillator drive capability
<>	161:2cc1468da177	2149	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
<>	161:2cc1468da177	2150	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2151	* @arg @ref LL_RCC_LSEDRIVE_LOW
<>	161:2cc1468da177	2152	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
<>	161:2cc1468da177	2153	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
<>	161:2cc1468da177	2154	* @arg @ref LL_RCC_LSEDRIVE_HIGH
<>	161:2cc1468da177	2155	*/
<>	161:2cc1468da177	2156	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
<>	161:2cc1468da177	2157	{
<>	161:2cc1468da177	2158	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
<>	161:2cc1468da177	2159	}
<>	161:2cc1468da177	2160
<>	161:2cc1468da177	2161	/**
<>	161:2cc1468da177	2162	* @brief Check if LSE oscillator Ready
<>	161:2cc1468da177	2163	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
<>	161:2cc1468da177	2164	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2165	*/
<>	161:2cc1468da177	2166	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
<>	161:2cc1468da177	2167	{
<>	161:2cc1468da177	2168	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
<>	161:2cc1468da177	2169	}
<>	161:2cc1468da177	2170
<>	161:2cc1468da177	2171	/**
<>	161:2cc1468da177	2172	* @}
<>	161:2cc1468da177	2173	*/
<>	161:2cc1468da177	2174
<>	161:2cc1468da177	2175	/** @defgroup RCC_LL_EF_LSI LSI
<>	161:2cc1468da177	2176	* @{
<>	161:2cc1468da177	2177	*/
<>	161:2cc1468da177	2178
<>	161:2cc1468da177	2179	/**
<>	161:2cc1468da177	2180	* @brief Enable LSI Oscillator
<>	161:2cc1468da177	2181	* @rmtoll CSR LSION LL_RCC_LSI_Enable
<>	161:2cc1468da177	2182	* @retval None
<>	161:2cc1468da177	2183	*/
<>	161:2cc1468da177	2184	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
<>	161:2cc1468da177	2185	{
<>	161:2cc1468da177	2186	SET_BIT(RCC->CSR, RCC_CSR_LSION);
<>	161:2cc1468da177	2187	}
<>	161:2cc1468da177	2188
<>	161:2cc1468da177	2189	/**
<>	161:2cc1468da177	2190	* @brief Disable LSI Oscillator
<>	161:2cc1468da177	2191	* @rmtoll CSR LSION LL_RCC_LSI_Disable
<>	161:2cc1468da177	2192	* @retval None
<>	161:2cc1468da177	2193	*/
<>	161:2cc1468da177	2194	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
<>	161:2cc1468da177	2195	{
<>	161:2cc1468da177	2196	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
<>	161:2cc1468da177	2197	}
<>	161:2cc1468da177	2198
<>	161:2cc1468da177	2199	/**
<>	161:2cc1468da177	2200	* @brief Check if LSI is Ready
<>	161:2cc1468da177	2201	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
<>	161:2cc1468da177	2202	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2203	*/
<>	161:2cc1468da177	2204	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
<>	161:2cc1468da177	2205	{
<>	161:2cc1468da177	2206	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
<>	161:2cc1468da177	2207	}
<>	161:2cc1468da177	2208
<>	161:2cc1468da177	2209	/**
<>	161:2cc1468da177	2210	* @}
<>	161:2cc1468da177	2211	*/
<>	161:2cc1468da177	2212
<>	161:2cc1468da177	2213	/** @defgroup RCC_LL_EF_System System
<>	161:2cc1468da177	2214	* @{
<>	161:2cc1468da177	2215	*/
<>	161:2cc1468da177	2216
<>	161:2cc1468da177	2217	/**
<>	161:2cc1468da177	2218	* @brief Configure the system clock source
<>	161:2cc1468da177	2219	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
<>	161:2cc1468da177	2220	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	2221	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
<>	161:2cc1468da177	2222	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
<>	161:2cc1468da177	2223	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
<>	161:2cc1468da177	2224	* @retval None
<>	161:2cc1468da177	2225	*/
<>	161:2cc1468da177	2226	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
<>	161:2cc1468da177	2227	{
<>	161:2cc1468da177	2228	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
<>	161:2cc1468da177	2229	}
<>	161:2cc1468da177	2230
<>	161:2cc1468da177	2231	/**
<>	161:2cc1468da177	2232	* @brief Get the system clock source
<>	161:2cc1468da177	2233	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
<>	161:2cc1468da177	2234	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2235	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
<>	161:2cc1468da177	2236	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
<>	161:2cc1468da177	2237	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
<>	161:2cc1468da177	2238	*/
<>	161:2cc1468da177	2239	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
<>	161:2cc1468da177	2240	{
<>	161:2cc1468da177	2241	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
<>	161:2cc1468da177	2242	}
<>	161:2cc1468da177	2243
<>	161:2cc1468da177	2244	/**
<>	161:2cc1468da177	2245	* @brief Set AHB prescaler
<>	161:2cc1468da177	2246	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
<>	161:2cc1468da177	2247	* @param Prescaler This parameter can be one of the following values:
<>	161:2cc1468da177	2248	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	161:2cc1468da177	2249	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	161:2cc1468da177	2250	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	161:2cc1468da177	2251	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	161:2cc1468da177	2252	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	161:2cc1468da177	2253	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	161:2cc1468da177	2254	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	161:2cc1468da177	2255	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	161:2cc1468da177	2256	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	161:2cc1468da177	2257	* @retval None
<>	161:2cc1468da177	2258	*/
<>	161:2cc1468da177	2259	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
<>	161:2cc1468da177	2260	{
<>	161:2cc1468da177	2261	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
<>	161:2cc1468da177	2262	}
<>	161:2cc1468da177	2263
<>	161:2cc1468da177	2264	/**
<>	161:2cc1468da177	2265	* @brief Set APB1 prescaler
<>	161:2cc1468da177	2266	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
<>	161:2cc1468da177	2267	* @param Prescaler This parameter can be one of the following values:
<>	161:2cc1468da177	2268	* @arg @ref LL_RCC_APB1_DIV_1
<>	161:2cc1468da177	2269	* @arg @ref LL_RCC_APB1_DIV_2
<>	161:2cc1468da177	2270	* @arg @ref LL_RCC_APB1_DIV_4
<>	161:2cc1468da177	2271	* @arg @ref LL_RCC_APB1_DIV_8
<>	161:2cc1468da177	2272	* @arg @ref LL_RCC_APB1_DIV_16
<>	161:2cc1468da177	2273	* @retval None
<>	161:2cc1468da177	2274	*/
<>	161:2cc1468da177	2275	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
<>	161:2cc1468da177	2276	{
<>	161:2cc1468da177	2277	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
<>	161:2cc1468da177	2278	}
<>	161:2cc1468da177	2279
<>	161:2cc1468da177	2280	/**
<>	161:2cc1468da177	2281	* @brief Set APB2 prescaler
<>	161:2cc1468da177	2282	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
<>	161:2cc1468da177	2283	* @param Prescaler This parameter can be one of the following values:
<>	161:2cc1468da177	2284	* @arg @ref LL_RCC_APB2_DIV_1
<>	161:2cc1468da177	2285	* @arg @ref LL_RCC_APB2_DIV_2
<>	161:2cc1468da177	2286	* @arg @ref LL_RCC_APB2_DIV_4
<>	161:2cc1468da177	2287	* @arg @ref LL_RCC_APB2_DIV_8
<>	161:2cc1468da177	2288	* @arg @ref LL_RCC_APB2_DIV_16
<>	161:2cc1468da177	2289	* @retval None
<>	161:2cc1468da177	2290	*/
<>	161:2cc1468da177	2291	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
<>	161:2cc1468da177	2292	{
<>	161:2cc1468da177	2293	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
<>	161:2cc1468da177	2294	}
<>	161:2cc1468da177	2295
<>	161:2cc1468da177	2296	/**
<>	161:2cc1468da177	2297	* @brief Get AHB prescaler
<>	161:2cc1468da177	2298	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
<>	161:2cc1468da177	2299	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2300	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	161:2cc1468da177	2301	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	161:2cc1468da177	2302	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	161:2cc1468da177	2303	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	161:2cc1468da177	2304	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	161:2cc1468da177	2305	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	161:2cc1468da177	2306	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	161:2cc1468da177	2307	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	161:2cc1468da177	2308	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	161:2cc1468da177	2309	*/
<>	161:2cc1468da177	2310	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
<>	161:2cc1468da177	2311	{
<>	161:2cc1468da177	2312	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
<>	161:2cc1468da177	2313	}
<>	161:2cc1468da177	2314
<>	161:2cc1468da177	2315	/**
<>	161:2cc1468da177	2316	* @brief Get APB1 prescaler
<>	161:2cc1468da177	2317	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
<>	161:2cc1468da177	2318	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2319	* @arg @ref LL_RCC_APB1_DIV_1
<>	161:2cc1468da177	2320	* @arg @ref LL_RCC_APB1_DIV_2
<>	161:2cc1468da177	2321	* @arg @ref LL_RCC_APB1_DIV_4
<>	161:2cc1468da177	2322	* @arg @ref LL_RCC_APB1_DIV_8
<>	161:2cc1468da177	2323	* @arg @ref LL_RCC_APB1_DIV_16
<>	161:2cc1468da177	2324	*/
<>	161:2cc1468da177	2325	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
<>	161:2cc1468da177	2326	{
<>	161:2cc1468da177	2327	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
<>	161:2cc1468da177	2328	}
<>	161:2cc1468da177	2329
<>	161:2cc1468da177	2330	/**
<>	161:2cc1468da177	2331	* @brief Get APB2 prescaler
<>	161:2cc1468da177	2332	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
<>	161:2cc1468da177	2333	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2334	* @arg @ref LL_RCC_APB2_DIV_1
<>	161:2cc1468da177	2335	* @arg @ref LL_RCC_APB2_DIV_2
<>	161:2cc1468da177	2336	* @arg @ref LL_RCC_APB2_DIV_4
<>	161:2cc1468da177	2337	* @arg @ref LL_RCC_APB2_DIV_8
<>	161:2cc1468da177	2338	* @arg @ref LL_RCC_APB2_DIV_16
<>	161:2cc1468da177	2339	*/
<>	161:2cc1468da177	2340	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
<>	161:2cc1468da177	2341	{
<>	161:2cc1468da177	2342	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
<>	161:2cc1468da177	2343	}
<>	161:2cc1468da177	2344
<>	161:2cc1468da177	2345	/**
<>	161:2cc1468da177	2346	* @}
<>	161:2cc1468da177	2347	*/
<>	161:2cc1468da177	2348
<>	161:2cc1468da177	2349	/** @defgroup RCC_LL_EF_MCO MCO
<>	161:2cc1468da177	2350	* @{
<>	161:2cc1468da177	2351	*/
<>	161:2cc1468da177	2352
<>	161:2cc1468da177	2353	/**
<>	161:2cc1468da177	2354	* @brief Configure MCOx
<>	161:2cc1468da177	2355	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
<>	161:2cc1468da177	2356	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
<>	161:2cc1468da177	2357	* CFGR MCO2 LL_RCC_ConfigMCO\n
<>	161:2cc1468da177	2358	* CFGR MCO2PRE LL_RCC_ConfigMCO
<>	161:2cc1468da177	2359	* @param MCOxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2360	* @arg @ref LL_RCC_MCO1SOURCE_HSI
<>	161:2cc1468da177	2361	* @arg @ref LL_RCC_MCO1SOURCE_LSE
<>	161:2cc1468da177	2362	* @arg @ref LL_RCC_MCO1SOURCE_HSE
<>	161:2cc1468da177	2363	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
<>	161:2cc1468da177	2364	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
<>	161:2cc1468da177	2365	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
<>	161:2cc1468da177	2366	* @arg @ref LL_RCC_MCO2SOURCE_HSE
<>	161:2cc1468da177	2367	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
<>	161:2cc1468da177	2368	* @param MCOxPrescaler This parameter can be one of the following values:
<>	161:2cc1468da177	2369	* @arg @ref LL_RCC_MCO1_DIV_1
<>	161:2cc1468da177	2370	* @arg @ref LL_RCC_MCO1_DIV_2
<>	161:2cc1468da177	2371	* @arg @ref LL_RCC_MCO1_DIV_3
<>	161:2cc1468da177	2372	* @arg @ref LL_RCC_MCO1_DIV_4
<>	161:2cc1468da177	2373	* @arg @ref LL_RCC_MCO1_DIV_5
<>	161:2cc1468da177	2374	* @arg @ref LL_RCC_MCO2_DIV_1
<>	161:2cc1468da177	2375	* @arg @ref LL_RCC_MCO2_DIV_2
<>	161:2cc1468da177	2376	* @arg @ref LL_RCC_MCO2_DIV_3
<>	161:2cc1468da177	2377	* @arg @ref LL_RCC_MCO2_DIV_4
<>	161:2cc1468da177	2378	* @arg @ref LL_RCC_MCO2_DIV_5
<>	161:2cc1468da177	2379	* @retval None
<>	161:2cc1468da177	2380	*/
<>	161:2cc1468da177	2381	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
<>	161:2cc1468da177	2382	{
<>	161:2cc1468da177	2383	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
<>	161:2cc1468da177	2384	}
<>	161:2cc1468da177	2385
<>	161:2cc1468da177	2386	/**
<>	161:2cc1468da177	2387	* @}
<>	161:2cc1468da177	2388	*/
<>	161:2cc1468da177	2389
<>	161:2cc1468da177	2390	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
<>	161:2cc1468da177	2391	* @{
<>	161:2cc1468da177	2392	*/
<>	161:2cc1468da177	2393
<>	161:2cc1468da177	2394	/**
<>	161:2cc1468da177	2395	* @brief Configure USARTx clock source
<>	161:2cc1468da177	2396	* @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n
<>	161:2cc1468da177	2397	* DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n
<>	161:2cc1468da177	2398	* DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n
<>	161:2cc1468da177	2399	* DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource
<>	161:2cc1468da177	2400	* @param USARTxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2401	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
<>	161:2cc1468da177	2402	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2403	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<>	161:2cc1468da177	2404	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<>	161:2cc1468da177	2405	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2406	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2407	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
<>	161:2cc1468da177	2408	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
<>	161:2cc1468da177	2409	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2410	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2411	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
<>	161:2cc1468da177	2412	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
<>	161:2cc1468da177	2413	* @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
<>	161:2cc1468da177	2414	* @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2415	* @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
<>	161:2cc1468da177	2416	* @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
<>	161:2cc1468da177	2417	* @retval None
<>	161:2cc1468da177	2418	*/
<>	161:2cc1468da177	2419	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
<>	161:2cc1468da177	2420	{
<>	161:2cc1468da177	2421	MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
<>	161:2cc1468da177	2422	}
<>	161:2cc1468da177	2423
<>	161:2cc1468da177	2424	/**
<>	161:2cc1468da177	2425	* @brief Configure UARTx clock source
<>	161:2cc1468da177	2426	* @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n
<>	161:2cc1468da177	2427	* DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n
<>	161:2cc1468da177	2428	* DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n
<>	161:2cc1468da177	2429	* DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource
<>	161:2cc1468da177	2430	* @param UARTxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2431	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2432	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2433	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
<>	161:2cc1468da177	2434	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
<>	161:2cc1468da177	2435	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2436	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2437	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
<>	161:2cc1468da177	2438	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
<>	161:2cc1468da177	2439	* @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2440	* @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2441	* @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
<>	161:2cc1468da177	2442	* @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
<>	161:2cc1468da177	2443	* @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2444	* @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2445	* @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
<>	161:2cc1468da177	2446	* @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
<>	161:2cc1468da177	2447	* @retval None
<>	161:2cc1468da177	2448	*/
<>	161:2cc1468da177	2449	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
<>	161:2cc1468da177	2450	{
<>	161:2cc1468da177	2451	MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
<>	161:2cc1468da177	2452	}
<>	161:2cc1468da177	2453
<>	161:2cc1468da177	2454	/**
<>	161:2cc1468da177	2455	* @brief Configure I2Cx clock source
<>	161:2cc1468da177	2456	* @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n
<>	161:2cc1468da177	2457	* DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n
<>	161:2cc1468da177	2458	* DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n
<>	161:2cc1468da177	2459	* DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource
<>	161:2cc1468da177	2460	* @param I2CxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2461	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2462	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2463	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<>	161:2cc1468da177	2464	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2465	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2466	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
<>	161:2cc1468da177	2467	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2468	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2469	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
<>	161:2cc1468da177	2470	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
<>	161:2cc1468da177	2471	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
<>	161:2cc1468da177	2472	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
<>	161:2cc1468da177	2473	*
<>	161:2cc1468da177	2474	* (*) value not defined in all devices.
<>	161:2cc1468da177	2475	* @retval None
<>	161:2cc1468da177	2476	*/
<>	161:2cc1468da177	2477	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
<>	161:2cc1468da177	2478	{
<>	161:2cc1468da177	2479	MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U));
<>	161:2cc1468da177	2480	}
<>	161:2cc1468da177	2481
<>	161:2cc1468da177	2482	/**
<>	161:2cc1468da177	2483	* @brief Configure LPTIMx clock source
<>	161:2cc1468da177	2484	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
<>	161:2cc1468da177	2485	* @param LPTIMxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2486	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2487	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
<>	161:2cc1468da177	2488	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
<>	161:2cc1468da177	2489	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
<>	161:2cc1468da177	2490	* @retval None
<>	161:2cc1468da177	2491	*/
<>	161:2cc1468da177	2492	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
<>	161:2cc1468da177	2493	{
<>	161:2cc1468da177	2494	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
<>	161:2cc1468da177	2495	}
<>	161:2cc1468da177	2496
<>	161:2cc1468da177	2497	/**
<>	161:2cc1468da177	2498	* @brief Configure SAIx clock source
<>	161:2cc1468da177	2499	* @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n
<>	161:2cc1468da177	2500	* DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource
<>	161:2cc1468da177	2501	* @param SAIxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2502	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2503	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
<>	161:2cc1468da177	2504	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
<>	161:2cc1468da177	2505	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
<>	161:2cc1468da177	2506	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2507	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
<>	161:2cc1468da177	2508	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
<>	161:2cc1468da177	2509	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
<>	161:2cc1468da177	2510	*
<>	161:2cc1468da177	2511	* (*) value not defined in all devices.
<>	161:2cc1468da177	2512	* @retval None
<>	161:2cc1468da177	2513	*/
<>	161:2cc1468da177	2514	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
<>	161:2cc1468da177	2515	{
<>	161:2cc1468da177	2516	MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
<>	161:2cc1468da177	2517	}
<>	161:2cc1468da177	2518
<>	161:2cc1468da177	2519	/**
<>	161:2cc1468da177	2520	* @brief Configure SDMMC clock source
<>	161:2cc1468da177	2521	* @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n
<>	161:2cc1468da177	2522	* DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource
<>	161:2cc1468da177	2523	* @param SDMMCxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2524	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
<>	161:2cc1468da177	2525	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2526	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
<>	161:2cc1468da177	2527	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
<>	161:2cc1468da177	2528	*
<>	161:2cc1468da177	2529	* (*) value not defined in all devices.
<>	161:2cc1468da177	2530	* @retval None
<>	161:2cc1468da177	2531	*/
<>	161:2cc1468da177	2532	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
<>	161:2cc1468da177	2533	{
<>	161:2cc1468da177	2534	MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
<>	161:2cc1468da177	2535	}
<>	161:2cc1468da177	2536
<>	161:2cc1468da177	2537	/**
<>	161:2cc1468da177	2538	* @brief Configure 48Mhz domain clock source
<>	161:2cc1468da177	2539	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
<>	161:2cc1468da177	2540	* @param CK48MxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2541	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
<>	161:2cc1468da177	2542	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2543	* @retval None
<>	161:2cc1468da177	2544	*/
<>	161:2cc1468da177	2545	__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
<>	161:2cc1468da177	2546	{
<>	161:2cc1468da177	2547	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
<>	161:2cc1468da177	2548	}
<>	161:2cc1468da177	2549
<>	161:2cc1468da177	2550	/**
<>	161:2cc1468da177	2551	* @brief Configure RNG clock source
<>	161:2cc1468da177	2552	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
<>	161:2cc1468da177	2553	* @param RNGxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2554	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
<>	161:2cc1468da177	2555	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2556	* @retval None
<>	161:2cc1468da177	2557	*/
<>	161:2cc1468da177	2558	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
<>	161:2cc1468da177	2559	{
<>	161:2cc1468da177	2560	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
<>	161:2cc1468da177	2561	}
<>	161:2cc1468da177	2562
<>	161:2cc1468da177	2563	/**
<>	161:2cc1468da177	2564	* @brief Configure USB clock source
<>	161:2cc1468da177	2565	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
<>	161:2cc1468da177	2566	* @param USBxSource This parameter can be one of the following values:
<>	161:2cc1468da177	2567	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<>	161:2cc1468da177	2568	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2569	* @retval None
<>	161:2cc1468da177	2570	*/
<>	161:2cc1468da177	2571	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
<>	161:2cc1468da177	2572	{
<>	161:2cc1468da177	2573	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
<>	161:2cc1468da177	2574	}
<>	161:2cc1468da177	2575
<>	161:2cc1468da177	2576	#if defined(CEC)
<>	161:2cc1468da177	2577	/**
<>	161:2cc1468da177	2578	* @brief Configure CEC clock source
<>	161:2cc1468da177	2579	* @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
<>	161:2cc1468da177	2580	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	2581	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
<>	161:2cc1468da177	2582	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
<>	161:2cc1468da177	2583	* @retval None
<>	161:2cc1468da177	2584	*/
<>	161:2cc1468da177	2585	__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
<>	161:2cc1468da177	2586	{
<>	161:2cc1468da177	2587	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
<>	161:2cc1468da177	2588	}
<>	161:2cc1468da177	2589	#endif /* CEC */
<>	161:2cc1468da177	2590
<>	161:2cc1468da177	2591	/**
<>	161:2cc1468da177	2592	* @brief Configure I2S clock source
<>	161:2cc1468da177	2593	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
<>	161:2cc1468da177	2594	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	2595	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
<>	161:2cc1468da177	2596	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
<>	161:2cc1468da177	2597	* @retval None
<>	161:2cc1468da177	2598	*/
<>	161:2cc1468da177	2599	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
<>	161:2cc1468da177	2600	{
<>	161:2cc1468da177	2601	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
<>	161:2cc1468da177	2602	}
<>	161:2cc1468da177	2603
<>	161:2cc1468da177	2604	#if defined(DSI)
<>	161:2cc1468da177	2605	/**
<>	161:2cc1468da177	2606	* @brief Configure DSI clock source
<>	161:2cc1468da177	2607	* @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource
<>	161:2cc1468da177	2608	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	2609	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
<>	161:2cc1468da177	2610	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
<>	161:2cc1468da177	2611	* @retval None
<>	161:2cc1468da177	2612	*/
<>	161:2cc1468da177	2613	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
<>	161:2cc1468da177	2614	{
<>	161:2cc1468da177	2615	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
<>	161:2cc1468da177	2616	}
<>	161:2cc1468da177	2617	#endif /* DSI */
<>	161:2cc1468da177	2618
<>	161:2cc1468da177	2619	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	2620	/**
<>	161:2cc1468da177	2621	* @brief Configure DFSDM Audio clock source
<>	161:2cc1468da177	2622	* @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
<>	161:2cc1468da177	2623	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	2624	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
<>	161:2cc1468da177	2625	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
<>	161:2cc1468da177	2626	* @retval None
<>	161:2cc1468da177	2627	*/
<>	161:2cc1468da177	2628	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
<>	161:2cc1468da177	2629	{
<>	161:2cc1468da177	2630	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
<>	161:2cc1468da177	2631	}
<>	161:2cc1468da177	2632
<>	161:2cc1468da177	2633	/**
<>	161:2cc1468da177	2634	* @brief Configure DFSDM Kernel clock source
<>	161:2cc1468da177	2635	* @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource
<>	161:2cc1468da177	2636	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	2637	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
<>	161:2cc1468da177	2638	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2639	* @retval None
<>	161:2cc1468da177	2640	*/
<>	161:2cc1468da177	2641	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
<>	161:2cc1468da177	2642	{
<>	161:2cc1468da177	2643	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
<>	161:2cc1468da177	2644	}
<>	161:2cc1468da177	2645	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	2646
<>	161:2cc1468da177	2647	/**
<>	161:2cc1468da177	2648	* @brief Get USARTx clock source
<>	161:2cc1468da177	2649	* @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n
<>	161:2cc1468da177	2650	* DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n
<>	161:2cc1468da177	2651	* DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n
<>	161:2cc1468da177	2652	* DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource
<>	161:2cc1468da177	2653	* @param USARTx This parameter can be one of the following values:
<>	161:2cc1468da177	2654	* @arg @ref LL_RCC_USART1_CLKSOURCE
<>	161:2cc1468da177	2655	* @arg @ref LL_RCC_USART2_CLKSOURCE
<>	161:2cc1468da177	2656	* @arg @ref LL_RCC_USART3_CLKSOURCE
<>	161:2cc1468da177	2657	* @arg @ref LL_RCC_USART6_CLKSOURCE
<>	161:2cc1468da177	2658	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2659	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
<>	161:2cc1468da177	2660	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2661	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
<>	161:2cc1468da177	2662	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
<>	161:2cc1468da177	2663	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2664	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2665	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
<>	161:2cc1468da177	2666	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
<>	161:2cc1468da177	2667	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2668	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2669	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
<>	161:2cc1468da177	2670	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
<>	161:2cc1468da177	2671	* @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
<>	161:2cc1468da177	2672	* @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2673	* @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
<>	161:2cc1468da177	2674	* @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
<>	161:2cc1468da177	2675	*/
<>	161:2cc1468da177	2676	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
<>	161:2cc1468da177	2677	{
<>	161:2cc1468da177	2678	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) \| (USARTx << 16U));
<>	161:2cc1468da177	2679	}
<>	161:2cc1468da177	2680
<>	161:2cc1468da177	2681	/**
<>	161:2cc1468da177	2682	* @brief Get UARTx clock source
<>	161:2cc1468da177	2683	* @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n
<>	161:2cc1468da177	2684	* DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n
<>	161:2cc1468da177	2685	* DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n
<>	161:2cc1468da177	2686	* DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource
<>	161:2cc1468da177	2687	* @param UARTx This parameter can be one of the following values:
<>	161:2cc1468da177	2688	* @arg @ref LL_RCC_UART4_CLKSOURCE
<>	161:2cc1468da177	2689	* @arg @ref LL_RCC_UART5_CLKSOURCE
<>	161:2cc1468da177	2690	* @arg @ref LL_RCC_UART7_CLKSOURCE
<>	161:2cc1468da177	2691	* @arg @ref LL_RCC_UART8_CLKSOURCE
<>	161:2cc1468da177	2692	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2693	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2694	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2695	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
<>	161:2cc1468da177	2696	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
<>	161:2cc1468da177	2697	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2698	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2699	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
<>	161:2cc1468da177	2700	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
<>	161:2cc1468da177	2701	* @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2702	* @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2703	* @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
<>	161:2cc1468da177	2704	* @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
<>	161:2cc1468da177	2705	* @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2706	* @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2707	* @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
<>	161:2cc1468da177	2708	* @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
<>	161:2cc1468da177	2709	*/
<>	161:2cc1468da177	2710	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
<>	161:2cc1468da177	2711	{
<>	161:2cc1468da177	2712	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) \| (UARTx << 16U));
<>	161:2cc1468da177	2713	}
<>	161:2cc1468da177	2714
<>	161:2cc1468da177	2715	/**
<>	161:2cc1468da177	2716	* @brief Get I2Cx clock source
<>	161:2cc1468da177	2717	* @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n
<>	161:2cc1468da177	2718	* DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n
<>	161:2cc1468da177	2719	* DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n
<>	161:2cc1468da177	2720	* DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource
<>	161:2cc1468da177	2721	* @param I2Cx This parameter can be one of the following values:
<>	161:2cc1468da177	2722	* @arg @ref LL_RCC_I2C1_CLKSOURCE
<>	161:2cc1468da177	2723	* @arg @ref LL_RCC_I2C2_CLKSOURCE
<>	161:2cc1468da177	2724	* @arg @ref LL_RCC_I2C3_CLKSOURCE
<>	161:2cc1468da177	2725	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
<>	161:2cc1468da177	2726	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2727	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2728	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2729	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
<>	161:2cc1468da177	2730	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2731	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2732	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
<>	161:2cc1468da177	2733	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2734	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2735	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
<>	161:2cc1468da177	2736	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
<>	161:2cc1468da177	2737	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
<>	161:2cc1468da177	2738	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
<>	161:2cc1468da177	2739	*
<>	161:2cc1468da177	2740	* (*) value not defined in all devices.
<>	161:2cc1468da177	2741	*/
<>	161:2cc1468da177	2742	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
<>	161:2cc1468da177	2743	{
<>	161:2cc1468da177	2744	return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) \| I2Cx);
<>	161:2cc1468da177	2745	}
<>	161:2cc1468da177	2746
<>	161:2cc1468da177	2747	/**
<>	161:2cc1468da177	2748	* @brief Get LPTIMx clock source
<>	161:2cc1468da177	2749	* @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
<>	161:2cc1468da177	2750	* @param LPTIMx This parameter can be one of the following values:
<>	161:2cc1468da177	2751	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
<>	161:2cc1468da177	2752	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2753	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
<>	161:2cc1468da177	2754	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
<>	161:2cc1468da177	2755	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
<>	161:2cc1468da177	2756	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
<>	161:2cc1468da177	2757	*/
<>	161:2cc1468da177	2758	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
<>	161:2cc1468da177	2759	{
<>	161:2cc1468da177	2760	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
<>	161:2cc1468da177	2761	}
<>	161:2cc1468da177	2762
<>	161:2cc1468da177	2763	/**
<>	161:2cc1468da177	2764	* @brief Get SAIx clock source
<>	161:2cc1468da177	2765	* @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n
<>	161:2cc1468da177	2766	* DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource
<>	161:2cc1468da177	2767	* @param SAIx This parameter can be one of the following values:
<>	161:2cc1468da177	2768	* @arg @ref LL_RCC_SAI1_CLKSOURCE
<>	161:2cc1468da177	2769	* @arg @ref LL_RCC_SAI2_CLKSOURCE
<>	161:2cc1468da177	2770	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2771	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2772	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
<>	161:2cc1468da177	2773	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
<>	161:2cc1468da177	2774	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
<>	161:2cc1468da177	2775	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2776	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
<>	161:2cc1468da177	2777	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
<>	161:2cc1468da177	2778	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
<>	161:2cc1468da177	2779	*
<>	161:2cc1468da177	2780	* (*) value not defined in all devices.
<>	161:2cc1468da177	2781	*/
<>	161:2cc1468da177	2782	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
<>	161:2cc1468da177	2783	{
<>	161:2cc1468da177	2784	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U \| SAIx);
<>	161:2cc1468da177	2785	}
<>	161:2cc1468da177	2786
<>	161:2cc1468da177	2787	/**
<>	161:2cc1468da177	2788	* @brief Get SDMMCx clock source
<>	161:2cc1468da177	2789	* @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n
<>	161:2cc1468da177	2790	* DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource
<>	161:2cc1468da177	2791	* @param SDMMCx This parameter can be one of the following values:
<>	161:2cc1468da177	2792	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
<>	161:2cc1468da177	2793	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
<>	161:2cc1468da177	2794	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2795	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
<>	161:2cc1468da177	2796	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2797	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
<>	161:2cc1468da177	2798	* @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
<>	161:2cc1468da177	2799	*
<>	161:2cc1468da177	2800	* (*) value not defined in all devices.
<>	161:2cc1468da177	2801	*/
<>	161:2cc1468da177	2802	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
<>	161:2cc1468da177	2803	{
<>	161:2cc1468da177	2804	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U \| SDMMCx);
<>	161:2cc1468da177	2805	}
<>	161:2cc1468da177	2806
<>	161:2cc1468da177	2807	/**
<>	161:2cc1468da177	2808	* @brief Get 48Mhz domain clock source
<>	161:2cc1468da177	2809	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
<>	161:2cc1468da177	2810	* @param CK48Mx This parameter can be one of the following values:
<>	161:2cc1468da177	2811	* @arg @ref LL_RCC_CK48M_CLKSOURCE
<>	161:2cc1468da177	2812	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2813	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
<>	161:2cc1468da177	2814	* @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2815	*/
<>	161:2cc1468da177	2816	__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
<>	161:2cc1468da177	2817	{
<>	161:2cc1468da177	2818	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
<>	161:2cc1468da177	2819	}
<>	161:2cc1468da177	2820
<>	161:2cc1468da177	2821	/**
<>	161:2cc1468da177	2822	* @brief Get RNGx clock source
<>	161:2cc1468da177	2823	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
<>	161:2cc1468da177	2824	* @param RNGx This parameter can be one of the following values:
<>	161:2cc1468da177	2825	* @arg @ref LL_RCC_RNG_CLKSOURCE
<>	161:2cc1468da177	2826	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2827	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
<>	161:2cc1468da177	2828	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2829	*/
<>	161:2cc1468da177	2830	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
<>	161:2cc1468da177	2831	{
<>	161:2cc1468da177	2832	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
<>	161:2cc1468da177	2833	}
<>	161:2cc1468da177	2834
<>	161:2cc1468da177	2835	/**
<>	161:2cc1468da177	2836	* @brief Get USBx clock source
<>	161:2cc1468da177	2837	* @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
<>	161:2cc1468da177	2838	* @param USBx This parameter can be one of the following values:
<>	161:2cc1468da177	2839	* @arg @ref LL_RCC_USB_CLKSOURCE
<>	161:2cc1468da177	2840	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2841	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
<>	161:2cc1468da177	2842	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
<>	161:2cc1468da177	2843	*/
<>	161:2cc1468da177	2844	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
<>	161:2cc1468da177	2845	{
<>	161:2cc1468da177	2846	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
<>	161:2cc1468da177	2847	}
<>	161:2cc1468da177	2848
<>	161:2cc1468da177	2849	#if defined(CEC)
<>	161:2cc1468da177	2850	/**
<>	161:2cc1468da177	2851	* @brief Get CEC Clock Source
<>	161:2cc1468da177	2852	* @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
<>	161:2cc1468da177	2853	* @param CECx This parameter can be one of the following values:
<>	161:2cc1468da177	2854	* @arg @ref LL_RCC_CEC_CLKSOURCE
<>	161:2cc1468da177	2855	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2856	* @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
<>	161:2cc1468da177	2857	* @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
<>	161:2cc1468da177	2858	*/
<>	161:2cc1468da177	2859	__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
<>	161:2cc1468da177	2860	{
<>	161:2cc1468da177	2861	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
<>	161:2cc1468da177	2862	}
<>	161:2cc1468da177	2863	#endif /* CEC */
<>	161:2cc1468da177	2864
<>	161:2cc1468da177	2865	/**
<>	161:2cc1468da177	2866	* @brief Get I2S Clock Source
<>	161:2cc1468da177	2867	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
<>	161:2cc1468da177	2868	* @param I2Sx This parameter can be one of the following values:
<>	161:2cc1468da177	2869	* @arg @ref LL_RCC_I2S1_CLKSOURCE
<>	161:2cc1468da177	2870	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2871	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
<>	161:2cc1468da177	2872	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
<>	161:2cc1468da177	2873	*/
<>	161:2cc1468da177	2874	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
<>	161:2cc1468da177	2875	{
<>	161:2cc1468da177	2876	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
<>	161:2cc1468da177	2877	}
<>	161:2cc1468da177	2878
<>	161:2cc1468da177	2879	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	2880	/**
<>	161:2cc1468da177	2881	* @brief Get DFSDM Audio Clock Source
<>	161:2cc1468da177	2882	* @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
<>	161:2cc1468da177	2883	* @param DFSDMx This parameter can be one of the following values:
<>	161:2cc1468da177	2884	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
<>	161:2cc1468da177	2885	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2886	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
<>	161:2cc1468da177	2887	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
<>	161:2cc1468da177	2888	*/
<>	161:2cc1468da177	2889	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
<>	161:2cc1468da177	2890	{
<>	161:2cc1468da177	2891	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
<>	161:2cc1468da177	2892	}
<>	161:2cc1468da177	2893
<>	161:2cc1468da177	2894	/**
<>	161:2cc1468da177	2895	* @brief Get DFSDM Audio Clock Source
<>	161:2cc1468da177	2896	* @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource
<>	161:2cc1468da177	2897	* @param DFSDMx This parameter can be one of the following values:
<>	161:2cc1468da177	2898	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
<>	161:2cc1468da177	2899	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2900	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
<>	161:2cc1468da177	2901	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
<>	161:2cc1468da177	2902	*/
<>	161:2cc1468da177	2903	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
<>	161:2cc1468da177	2904	{
<>	161:2cc1468da177	2905	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
<>	161:2cc1468da177	2906	}
<>	161:2cc1468da177	2907	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	2908
<>	161:2cc1468da177	2909	#if defined(DSI)
<>	161:2cc1468da177	2910	/**
<>	161:2cc1468da177	2911	* @brief Get DSI Clock Source
<>	161:2cc1468da177	2912	* @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource
<>	161:2cc1468da177	2913	* @param DSIx This parameter can be one of the following values:
<>	161:2cc1468da177	2914	* @arg @ref LL_RCC_DSI_CLKSOURCE
<>	161:2cc1468da177	2915	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2916	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
<>	161:2cc1468da177	2917	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
<>	161:2cc1468da177	2918	*/
<>	161:2cc1468da177	2919	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
<>	161:2cc1468da177	2920	{
<>	161:2cc1468da177	2921	return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
<>	161:2cc1468da177	2922	}
<>	161:2cc1468da177	2923	#endif /* DSI */
<>	161:2cc1468da177	2924
<>	161:2cc1468da177	2925	/**
<>	161:2cc1468da177	2926	* @}
<>	161:2cc1468da177	2927	*/
<>	161:2cc1468da177	2928
<>	161:2cc1468da177	2929	/** @defgroup RCC_LL_EF_RTC RTC
<>	161:2cc1468da177	2930	* @{
<>	161:2cc1468da177	2931	*/
<>	161:2cc1468da177	2932
<>	161:2cc1468da177	2933	/**
<>	161:2cc1468da177	2934	* @brief Set RTC Clock Source
<>	161:2cc1468da177	2935	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
<>	161:2cc1468da177	2936	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
<>	161:2cc1468da177	2937	* set). The BDRST bit can be used to reset them.
<>	161:2cc1468da177	2938	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
<>	161:2cc1468da177	2939	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	2940	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	161:2cc1468da177	2941	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	161:2cc1468da177	2942	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	161:2cc1468da177	2943	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
<>	161:2cc1468da177	2944	* @retval None
<>	161:2cc1468da177	2945	*/
<>	161:2cc1468da177	2946	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
<>	161:2cc1468da177	2947	{
<>	161:2cc1468da177	2948	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
<>	161:2cc1468da177	2949	}
<>	161:2cc1468da177	2950
<>	161:2cc1468da177	2951	/**
<>	161:2cc1468da177	2952	* @brief Get RTC Clock Source
<>	161:2cc1468da177	2953	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
<>	161:2cc1468da177	2954	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2955	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	161:2cc1468da177	2956	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	161:2cc1468da177	2957	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	161:2cc1468da177	2958	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
<>	161:2cc1468da177	2959	*/
<>	161:2cc1468da177	2960	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
<>	161:2cc1468da177	2961	{
<>	161:2cc1468da177	2962	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
<>	161:2cc1468da177	2963	}
<>	161:2cc1468da177	2964
<>	161:2cc1468da177	2965	/**
<>	161:2cc1468da177	2966	* @brief Enable RTC
<>	161:2cc1468da177	2967	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
<>	161:2cc1468da177	2968	* @retval None
<>	161:2cc1468da177	2969	*/
<>	161:2cc1468da177	2970	__STATIC_INLINE void LL_RCC_EnableRTC(void)
<>	161:2cc1468da177	2971	{
<>	161:2cc1468da177	2972	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	161:2cc1468da177	2973	}
<>	161:2cc1468da177	2974
<>	161:2cc1468da177	2975	/**
<>	161:2cc1468da177	2976	* @brief Disable RTC
<>	161:2cc1468da177	2977	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
<>	161:2cc1468da177	2978	* @retval None
<>	161:2cc1468da177	2979	*/
<>	161:2cc1468da177	2980	__STATIC_INLINE void LL_RCC_DisableRTC(void)
<>	161:2cc1468da177	2981	{
<>	161:2cc1468da177	2982	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	161:2cc1468da177	2983	}
<>	161:2cc1468da177	2984
<>	161:2cc1468da177	2985	/**
<>	161:2cc1468da177	2986	* @brief Check if RTC has been enabled or not
<>	161:2cc1468da177	2987	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
<>	161:2cc1468da177	2988	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2989	*/
<>	161:2cc1468da177	2990	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
<>	161:2cc1468da177	2991	{
<>	161:2cc1468da177	2992	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
<>	161:2cc1468da177	2993	}
<>	161:2cc1468da177	2994
<>	161:2cc1468da177	2995	/**
<>	161:2cc1468da177	2996	* @brief Force the Backup domain reset
<>	161:2cc1468da177	2997	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
<>	161:2cc1468da177	2998	* @retval None
<>	161:2cc1468da177	2999	*/
<>	161:2cc1468da177	3000	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
<>	161:2cc1468da177	3001	{
<>	161:2cc1468da177	3002	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	161:2cc1468da177	3003	}
<>	161:2cc1468da177	3004
<>	161:2cc1468da177	3005	/**
<>	161:2cc1468da177	3006	* @brief Release the Backup domain reset
<>	161:2cc1468da177	3007	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
<>	161:2cc1468da177	3008	* @retval None
<>	161:2cc1468da177	3009	*/
<>	161:2cc1468da177	3010	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
<>	161:2cc1468da177	3011	{
<>	161:2cc1468da177	3012	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	161:2cc1468da177	3013	}
<>	161:2cc1468da177	3014
<>	161:2cc1468da177	3015	/**
<>	161:2cc1468da177	3016	* @brief Set HSE Prescalers for RTC Clock
<>	161:2cc1468da177	3017	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
<>	161:2cc1468da177	3018	* @param Prescaler This parameter can be one of the following values:
<>	161:2cc1468da177	3019	* @arg @ref LL_RCC_RTC_NOCLOCK
<>	161:2cc1468da177	3020	* @arg @ref LL_RCC_RTC_HSE_DIV_2
<>	161:2cc1468da177	3021	* @arg @ref LL_RCC_RTC_HSE_DIV_3
<>	161:2cc1468da177	3022	* @arg @ref LL_RCC_RTC_HSE_DIV_4
<>	161:2cc1468da177	3023	* @arg @ref LL_RCC_RTC_HSE_DIV_5
<>	161:2cc1468da177	3024	* @arg @ref LL_RCC_RTC_HSE_DIV_6
<>	161:2cc1468da177	3025	* @arg @ref LL_RCC_RTC_HSE_DIV_7
<>	161:2cc1468da177	3026	* @arg @ref LL_RCC_RTC_HSE_DIV_8
<>	161:2cc1468da177	3027	* @arg @ref LL_RCC_RTC_HSE_DIV_9
<>	161:2cc1468da177	3028	* @arg @ref LL_RCC_RTC_HSE_DIV_10
<>	161:2cc1468da177	3029	* @arg @ref LL_RCC_RTC_HSE_DIV_11
<>	161:2cc1468da177	3030	* @arg @ref LL_RCC_RTC_HSE_DIV_12
<>	161:2cc1468da177	3031	* @arg @ref LL_RCC_RTC_HSE_DIV_13
<>	161:2cc1468da177	3032	* @arg @ref LL_RCC_RTC_HSE_DIV_14
<>	161:2cc1468da177	3033	* @arg @ref LL_RCC_RTC_HSE_DIV_15
<>	161:2cc1468da177	3034	* @arg @ref LL_RCC_RTC_HSE_DIV_16
<>	161:2cc1468da177	3035	* @arg @ref LL_RCC_RTC_HSE_DIV_17
<>	161:2cc1468da177	3036	* @arg @ref LL_RCC_RTC_HSE_DIV_18
<>	161:2cc1468da177	3037	* @arg @ref LL_RCC_RTC_HSE_DIV_19
<>	161:2cc1468da177	3038	* @arg @ref LL_RCC_RTC_HSE_DIV_20
<>	161:2cc1468da177	3039	* @arg @ref LL_RCC_RTC_HSE_DIV_21
<>	161:2cc1468da177	3040	* @arg @ref LL_RCC_RTC_HSE_DIV_22
<>	161:2cc1468da177	3041	* @arg @ref LL_RCC_RTC_HSE_DIV_23
<>	161:2cc1468da177	3042	* @arg @ref LL_RCC_RTC_HSE_DIV_24
<>	161:2cc1468da177	3043	* @arg @ref LL_RCC_RTC_HSE_DIV_25
<>	161:2cc1468da177	3044	* @arg @ref LL_RCC_RTC_HSE_DIV_26
<>	161:2cc1468da177	3045	* @arg @ref LL_RCC_RTC_HSE_DIV_27
<>	161:2cc1468da177	3046	* @arg @ref LL_RCC_RTC_HSE_DIV_28
<>	161:2cc1468da177	3047	* @arg @ref LL_RCC_RTC_HSE_DIV_29
<>	161:2cc1468da177	3048	* @arg @ref LL_RCC_RTC_HSE_DIV_30
<>	161:2cc1468da177	3049	* @arg @ref LL_RCC_RTC_HSE_DIV_31
<>	161:2cc1468da177	3050	* @retval None
<>	161:2cc1468da177	3051	*/
<>	161:2cc1468da177	3052	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
<>	161:2cc1468da177	3053	{
<>	161:2cc1468da177	3054	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
<>	161:2cc1468da177	3055	}
<>	161:2cc1468da177	3056
<>	161:2cc1468da177	3057	/**
<>	161:2cc1468da177	3058	* @brief Get HSE Prescalers for RTC Clock
<>	161:2cc1468da177	3059	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
<>	161:2cc1468da177	3060	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3061	* @arg @ref LL_RCC_RTC_NOCLOCK
<>	161:2cc1468da177	3062	* @arg @ref LL_RCC_RTC_HSE_DIV_2
<>	161:2cc1468da177	3063	* @arg @ref LL_RCC_RTC_HSE_DIV_3
<>	161:2cc1468da177	3064	* @arg @ref LL_RCC_RTC_HSE_DIV_4
<>	161:2cc1468da177	3065	* @arg @ref LL_RCC_RTC_HSE_DIV_5
<>	161:2cc1468da177	3066	* @arg @ref LL_RCC_RTC_HSE_DIV_6
<>	161:2cc1468da177	3067	* @arg @ref LL_RCC_RTC_HSE_DIV_7
<>	161:2cc1468da177	3068	* @arg @ref LL_RCC_RTC_HSE_DIV_8
<>	161:2cc1468da177	3069	* @arg @ref LL_RCC_RTC_HSE_DIV_9
<>	161:2cc1468da177	3070	* @arg @ref LL_RCC_RTC_HSE_DIV_10
<>	161:2cc1468da177	3071	* @arg @ref LL_RCC_RTC_HSE_DIV_11
<>	161:2cc1468da177	3072	* @arg @ref LL_RCC_RTC_HSE_DIV_12
<>	161:2cc1468da177	3073	* @arg @ref LL_RCC_RTC_HSE_DIV_13
<>	161:2cc1468da177	3074	* @arg @ref LL_RCC_RTC_HSE_DIV_14
<>	161:2cc1468da177	3075	* @arg @ref LL_RCC_RTC_HSE_DIV_15
<>	161:2cc1468da177	3076	* @arg @ref LL_RCC_RTC_HSE_DIV_16
<>	161:2cc1468da177	3077	* @arg @ref LL_RCC_RTC_HSE_DIV_17
<>	161:2cc1468da177	3078	* @arg @ref LL_RCC_RTC_HSE_DIV_18
<>	161:2cc1468da177	3079	* @arg @ref LL_RCC_RTC_HSE_DIV_19
<>	161:2cc1468da177	3080	* @arg @ref LL_RCC_RTC_HSE_DIV_20
<>	161:2cc1468da177	3081	* @arg @ref LL_RCC_RTC_HSE_DIV_21
<>	161:2cc1468da177	3082	* @arg @ref LL_RCC_RTC_HSE_DIV_22
<>	161:2cc1468da177	3083	* @arg @ref LL_RCC_RTC_HSE_DIV_23
<>	161:2cc1468da177	3084	* @arg @ref LL_RCC_RTC_HSE_DIV_24
<>	161:2cc1468da177	3085	* @arg @ref LL_RCC_RTC_HSE_DIV_25
<>	161:2cc1468da177	3086	* @arg @ref LL_RCC_RTC_HSE_DIV_26
<>	161:2cc1468da177	3087	* @arg @ref LL_RCC_RTC_HSE_DIV_27
<>	161:2cc1468da177	3088	* @arg @ref LL_RCC_RTC_HSE_DIV_28
<>	161:2cc1468da177	3089	* @arg @ref LL_RCC_RTC_HSE_DIV_29
<>	161:2cc1468da177	3090	* @arg @ref LL_RCC_RTC_HSE_DIV_30
<>	161:2cc1468da177	3091	* @arg @ref LL_RCC_RTC_HSE_DIV_31
<>	161:2cc1468da177	3092	*/
<>	161:2cc1468da177	3093	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
<>	161:2cc1468da177	3094	{
<>	161:2cc1468da177	3095	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
<>	161:2cc1468da177	3096	}
<>	161:2cc1468da177	3097
<>	161:2cc1468da177	3098	/**
<>	161:2cc1468da177	3099	* @}
<>	161:2cc1468da177	3100	*/
<>	161:2cc1468da177	3101
<>	161:2cc1468da177	3102	/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
<>	161:2cc1468da177	3103	* @{
<>	161:2cc1468da177	3104	*/
<>	161:2cc1468da177	3105
<>	161:2cc1468da177	3106	/**
<>	161:2cc1468da177	3107	* @brief Set Timers Clock Prescalers
<>	161:2cc1468da177	3108	* @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler
<>	161:2cc1468da177	3109	* @param Prescaler This parameter can be one of the following values:
<>	161:2cc1468da177	3110	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
<>	161:2cc1468da177	3111	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
<>	161:2cc1468da177	3112	* @retval None
<>	161:2cc1468da177	3113	*/
<>	161:2cc1468da177	3114	__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
<>	161:2cc1468da177	3115	{
<>	161:2cc1468da177	3116	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
<>	161:2cc1468da177	3117	}
<>	161:2cc1468da177	3118
<>	161:2cc1468da177	3119	/**
<>	161:2cc1468da177	3120	* @brief Get Timers Clock Prescalers
<>	161:2cc1468da177	3121	* @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler
<>	161:2cc1468da177	3122	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3123	* @arg @ref LL_RCC_TIM_PRESCALER_TWICE
<>	161:2cc1468da177	3124	* @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
<>	161:2cc1468da177	3125	*/
<>	161:2cc1468da177	3126	__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
<>	161:2cc1468da177	3127	{
<>	161:2cc1468da177	3128	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
<>	161:2cc1468da177	3129	}
<>	161:2cc1468da177	3130
<>	161:2cc1468da177	3131	/**
<>	161:2cc1468da177	3132	* @}
<>	161:2cc1468da177	3133	*/
<>	161:2cc1468da177	3134
<>	161:2cc1468da177	3135	/** @defgroup RCC_LL_EF_PLL PLL
<>	161:2cc1468da177	3136	* @{
<>	161:2cc1468da177	3137	*/
<>	161:2cc1468da177	3138
<>	161:2cc1468da177	3139	/**
<>	161:2cc1468da177	3140	* @brief Enable PLL
<>	161:2cc1468da177	3141	* @rmtoll CR PLLON LL_RCC_PLL_Enable
<>	161:2cc1468da177	3142	* @retval None
<>	161:2cc1468da177	3143	*/
<>	161:2cc1468da177	3144	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
<>	161:2cc1468da177	3145	{
<>	161:2cc1468da177	3146	SET_BIT(RCC->CR, RCC_CR_PLLON);
<>	161:2cc1468da177	3147	}
<>	161:2cc1468da177	3148
<>	161:2cc1468da177	3149	/**
<>	161:2cc1468da177	3150	* @brief Disable PLL
<>	161:2cc1468da177	3151	* @note Cannot be disabled if the PLL clock is used as the system clock
<>	161:2cc1468da177	3152	* @rmtoll CR PLLON LL_RCC_PLL_Disable
<>	161:2cc1468da177	3153	* @retval None
<>	161:2cc1468da177	3154	*/
<>	161:2cc1468da177	3155	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
<>	161:2cc1468da177	3156	{
<>	161:2cc1468da177	3157	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<>	161:2cc1468da177	3158	}
<>	161:2cc1468da177	3159
<>	161:2cc1468da177	3160	/**
<>	161:2cc1468da177	3161	* @brief Check if PLL Ready
<>	161:2cc1468da177	3162	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
<>	161:2cc1468da177	3163	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3164	*/
<>	161:2cc1468da177	3165	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
<>	161:2cc1468da177	3166	{
<>	161:2cc1468da177	3167	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
<>	161:2cc1468da177	3168	}
<>	161:2cc1468da177	3169
<>	161:2cc1468da177	3170	/**
<>	161:2cc1468da177	3171	* @brief Configure PLL used for SYSCLK Domain
<>	161:2cc1468da177	3172	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	3173	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	3174	* @note PLLN/PLLP can be written only when PLL is disabled
<>	161:2cc1468da177	3175	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<>	161:2cc1468da177	3176	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
<>	161:2cc1468da177	3177	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
<>	161:2cc1468da177	3178	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
<>	161:2cc1468da177	3179	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3180	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	3181	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	3182	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	3183	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	3184	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	3185	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	3186	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	3187	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	3188	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	3189	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	3190	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	3191	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	3192	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	3193	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	3194	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	3195	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	3196	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	3197	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	3198	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	3199	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	3200	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	3201	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	3202	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	3203	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	3204	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	3205	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	3206	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	3207	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	3208	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	3209	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	3210	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	3211	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	3212	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	3213	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	3214	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	3215	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	3216	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	3217	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	3218	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	3219	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	3220	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	3221	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	3222	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	3223	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	3224	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	3225	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	3226	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	3227	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	3228	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	3229	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	3230	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	3231	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	3232	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	3233	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	3234	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	3235	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	3236	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	3237	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	3238	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	3239	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	3240	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	3241	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	3242	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	3243	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	3244	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	3245	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	3246	* @param PLLP This parameter can be one of the following values:
<>	161:2cc1468da177	3247	* @arg @ref LL_RCC_PLLP_DIV_2
<>	161:2cc1468da177	3248	* @arg @ref LL_RCC_PLLP_DIV_4
<>	161:2cc1468da177	3249	* @arg @ref LL_RCC_PLLP_DIV_6
<>	161:2cc1468da177	3250	* @arg @ref LL_RCC_PLLP_DIV_8
<>	161:2cc1468da177	3251	* @retval None
<>	161:2cc1468da177	3252	*/
<>	161:2cc1468da177	3253	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
<>	161:2cc1468da177	3254	{
<>	161:2cc1468da177	3255	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
<>	161:2cc1468da177	3256	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
<>	161:2cc1468da177	3257	}
<>	161:2cc1468da177	3258
<>	161:2cc1468da177	3259	/**
<>	161:2cc1468da177	3260	* @brief Configure PLL used for 48Mhz domain clock
<>	161:2cc1468da177	3261	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	3262	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	3263	* @note PLLN/PLLQ can be written only when PLL is disabled
<>	161:2cc1468da177	3264	* @note This can be selected for USB, RNG, SDMMC1
<>	161:2cc1468da177	3265	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
<>	161:2cc1468da177	3266	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
<>	161:2cc1468da177	3267	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
<>	161:2cc1468da177	3268	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
<>	161:2cc1468da177	3269	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3270	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	3271	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	3272	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	3273	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	3274	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	3275	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	3276	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	3277	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	3278	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	3279	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	3280	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	3281	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	3282	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	3283	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	3284	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	3285	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	3286	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	3287	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	3288	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	3289	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	3290	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	3291	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	3292	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	3293	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	3294	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	3295	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	3296	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	3297	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	3298	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	3299	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	3300	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	3301	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	3302	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	3303	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	3304	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	3305	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	3306	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	3307	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	3308	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	3309	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	3310	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	3311	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	3312	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	3313	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	3314	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	3315	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	3316	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	3317	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	3318	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	3319	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	3320	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	3321	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	3322	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	3323	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	3324	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	3325	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	3326	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	3327	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	3328	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	3329	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	3330	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	3331	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	3332	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	3333	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	3334	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	3335	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	3336	* @param PLLQ This parameter can be one of the following values:
<>	161:2cc1468da177	3337	* @arg @ref LL_RCC_PLLQ_DIV_2
<>	161:2cc1468da177	3338	* @arg @ref LL_RCC_PLLQ_DIV_3
<>	161:2cc1468da177	3339	* @arg @ref LL_RCC_PLLQ_DIV_4
<>	161:2cc1468da177	3340	* @arg @ref LL_RCC_PLLQ_DIV_5
<>	161:2cc1468da177	3341	* @arg @ref LL_RCC_PLLQ_DIV_6
<>	161:2cc1468da177	3342	* @arg @ref LL_RCC_PLLQ_DIV_7
<>	161:2cc1468da177	3343	* @arg @ref LL_RCC_PLLQ_DIV_8
<>	161:2cc1468da177	3344	* @arg @ref LL_RCC_PLLQ_DIV_9
<>	161:2cc1468da177	3345	* @arg @ref LL_RCC_PLLQ_DIV_10
<>	161:2cc1468da177	3346	* @arg @ref LL_RCC_PLLQ_DIV_11
<>	161:2cc1468da177	3347	* @arg @ref LL_RCC_PLLQ_DIV_12
<>	161:2cc1468da177	3348	* @arg @ref LL_RCC_PLLQ_DIV_13
<>	161:2cc1468da177	3349	* @arg @ref LL_RCC_PLLQ_DIV_14
<>	161:2cc1468da177	3350	* @arg @ref LL_RCC_PLLQ_DIV_15
<>	161:2cc1468da177	3351	* @retval None
<>	161:2cc1468da177	3352	*/
<>	161:2cc1468da177	3353	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
<>	161:2cc1468da177	3354	{
<>	161:2cc1468da177	3355	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
<>	161:2cc1468da177	3356	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
<>	161:2cc1468da177	3357	}
<>	161:2cc1468da177	3358
<>	161:2cc1468da177	3359	#if defined(DSI)
<>	161:2cc1468da177	3360	/**
<>	161:2cc1468da177	3361	* @brief Configure PLL used for DSI clock
<>	161:2cc1468da177	3362	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	3363	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	3364	* @note PLLN/PLLR can be written only when PLL is disabled
<>	161:2cc1468da177	3365	* @note This can be selected for DSI
<>	161:2cc1468da177	3366	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
<>	161:2cc1468da177	3367	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
<>	161:2cc1468da177	3368	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
<>	161:2cc1468da177	3369	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
<>	161:2cc1468da177	3370	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3371	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	3372	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	3373	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	3374	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	3375	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	3376	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	3377	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	3378	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	3379	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	3380	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	3381	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	3382	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	3383	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	3384	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	3385	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	3386	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	3387	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	3388	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	3389	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	3390	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	3391	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	3392	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	3393	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	3394	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	3395	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	3396	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	3397	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	3398	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	3399	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	3400	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	3401	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	3402	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	3403	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	3404	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	3405	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	3406	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	3407	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	3408	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	3409	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	3410	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	3411	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	3412	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	3413	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	3414	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	3415	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	3416	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	3417	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	3418	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	3419	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	3420	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	3421	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	3422	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	3423	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	3424	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	3425	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	3426	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	3427	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	3428	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	3429	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	3430	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	3431	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	3432	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	3433	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	3434	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	3435	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	3436	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	3437	* @param PLLR This parameter can be one of the following values:
<>	161:2cc1468da177	3438	* @arg @ref LL_RCC_PLLR_DIV_2
<>	161:2cc1468da177	3439	* @arg @ref LL_RCC_PLLR_DIV_3
<>	161:2cc1468da177	3440	* @arg @ref LL_RCC_PLLR_DIV_4
<>	161:2cc1468da177	3441	* @arg @ref LL_RCC_PLLR_DIV_5
<>	161:2cc1468da177	3442	* @arg @ref LL_RCC_PLLR_DIV_6
<>	161:2cc1468da177	3443	* @arg @ref LL_RCC_PLLR_DIV_7
<>	161:2cc1468da177	3444	* @retval None
<>	161:2cc1468da177	3445	*/
<>	161:2cc1468da177	3446	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
<>	161:2cc1468da177	3447	{
<>	161:2cc1468da177	3448	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
<>	161:2cc1468da177	3449	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
<>	161:2cc1468da177	3450	}
<>	161:2cc1468da177	3451	#endif /* DSI */
<>	161:2cc1468da177	3452
<>	161:2cc1468da177	3453	/**
<>	161:2cc1468da177	3454	* @brief Get Main PLL multiplication factor for VCO
<>	161:2cc1468da177	3455	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
<>	161:2cc1468da177	3456	* @retval Between 50 and 432
<>	161:2cc1468da177	3457	*/
<>	161:2cc1468da177	3458	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
<>	161:2cc1468da177	3459	{
<>	161:2cc1468da177	3460	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
<>	161:2cc1468da177	3461	}
<>	161:2cc1468da177	3462
<>	161:2cc1468da177	3463	/**
<>	161:2cc1468da177	3464	* @brief Get Main PLL division factor for PLLP
<>	161:2cc1468da177	3465	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
<>	161:2cc1468da177	3466	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3467	* @arg @ref LL_RCC_PLLP_DIV_2
<>	161:2cc1468da177	3468	* @arg @ref LL_RCC_PLLP_DIV_4
<>	161:2cc1468da177	3469	* @arg @ref LL_RCC_PLLP_DIV_6
<>	161:2cc1468da177	3470	* @arg @ref LL_RCC_PLLP_DIV_8
<>	161:2cc1468da177	3471	*/
<>	161:2cc1468da177	3472	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
<>	161:2cc1468da177	3473	{
<>	161:2cc1468da177	3474	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
<>	161:2cc1468da177	3475	}
<>	161:2cc1468da177	3476
<>	161:2cc1468da177	3477	/**
<>	161:2cc1468da177	3478	* @brief Get Main PLL division factor for PLLQ
<>	161:2cc1468da177	3479	* @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
<>	161:2cc1468da177	3480	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
<>	161:2cc1468da177	3481	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3482	* @arg @ref LL_RCC_PLLQ_DIV_2
<>	161:2cc1468da177	3483	* @arg @ref LL_RCC_PLLQ_DIV_3
<>	161:2cc1468da177	3484	* @arg @ref LL_RCC_PLLQ_DIV_4
<>	161:2cc1468da177	3485	* @arg @ref LL_RCC_PLLQ_DIV_5
<>	161:2cc1468da177	3486	* @arg @ref LL_RCC_PLLQ_DIV_6
<>	161:2cc1468da177	3487	* @arg @ref LL_RCC_PLLQ_DIV_7
<>	161:2cc1468da177	3488	* @arg @ref LL_RCC_PLLQ_DIV_8
<>	161:2cc1468da177	3489	* @arg @ref LL_RCC_PLLQ_DIV_9
<>	161:2cc1468da177	3490	* @arg @ref LL_RCC_PLLQ_DIV_10
<>	161:2cc1468da177	3491	* @arg @ref LL_RCC_PLLQ_DIV_11
<>	161:2cc1468da177	3492	* @arg @ref LL_RCC_PLLQ_DIV_12
<>	161:2cc1468da177	3493	* @arg @ref LL_RCC_PLLQ_DIV_13
<>	161:2cc1468da177	3494	* @arg @ref LL_RCC_PLLQ_DIV_14
<>	161:2cc1468da177	3495	* @arg @ref LL_RCC_PLLQ_DIV_15
<>	161:2cc1468da177	3496	*/
<>	161:2cc1468da177	3497	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
<>	161:2cc1468da177	3498	{
<>	161:2cc1468da177	3499	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
<>	161:2cc1468da177	3500	}
<>	161:2cc1468da177	3501
<>	161:2cc1468da177	3502	#if defined(RCC_PLLCFGR_PLLR)
<>	161:2cc1468da177	3503	/**
<>	161:2cc1468da177	3504	* @brief Get Main PLL division factor for PLLR
<>	161:2cc1468da177	3505	* @note used for PLLCLK (system clock)
<>	161:2cc1468da177	3506	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
<>	161:2cc1468da177	3507	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3508	* @arg @ref LL_RCC_PLLR_DIV_2
<>	161:2cc1468da177	3509	* @arg @ref LL_RCC_PLLR_DIV_3
<>	161:2cc1468da177	3510	* @arg @ref LL_RCC_PLLR_DIV_4
<>	161:2cc1468da177	3511	* @arg @ref LL_RCC_PLLR_DIV_5
<>	161:2cc1468da177	3512	* @arg @ref LL_RCC_PLLR_DIV_6
<>	161:2cc1468da177	3513	* @arg @ref LL_RCC_PLLR_DIV_7
<>	161:2cc1468da177	3514	*/
<>	161:2cc1468da177	3515	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
<>	161:2cc1468da177	3516	{
<>	161:2cc1468da177	3517	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
<>	161:2cc1468da177	3518	}
<>	161:2cc1468da177	3519	#endif /* RCC_PLLCFGR_PLLR */
<>	161:2cc1468da177	3520
<>	161:2cc1468da177	3521	/**
<>	161:2cc1468da177	3522	* @brief Get the oscillator used as PLL clock source.
<>	161:2cc1468da177	3523	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
<>	161:2cc1468da177	3524	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3525	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	3526	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	3527	*/
<>	161:2cc1468da177	3528	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
<>	161:2cc1468da177	3529	{
<>	161:2cc1468da177	3530	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
<>	161:2cc1468da177	3531	}
<>	161:2cc1468da177	3532
<>	161:2cc1468da177	3533	/**
<>	161:2cc1468da177	3534	* @brief Get Division factor for the main PLL and other PLL
<>	161:2cc1468da177	3535	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
<>	161:2cc1468da177	3536	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3537	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	3538	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	3539	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	3540	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	3541	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	3542	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	3543	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	3544	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	3545	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	3546	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	3547	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	3548	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	3549	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	3550	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	3551	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	3552	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	3553	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	3554	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	3555	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	3556	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	3557	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	3558	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	3559	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	3560	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	3561	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	3562	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	3563	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	3564	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	3565	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	3566	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	3567	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	3568	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	3569	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	3570	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	3571	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	3572	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	3573	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	3574	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	3575	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	3576	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	3577	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	3578	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	3579	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	3580	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	3581	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	3582	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	3583	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	3584	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	3585	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	3586	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	3587	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	3588	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	3589	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	3590	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	3591	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	3592	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	3593	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	3594	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	3595	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	3596	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	3597	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	3598	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	3599	*/
<>	161:2cc1468da177	3600	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
<>	161:2cc1468da177	3601	{
<>	161:2cc1468da177	3602	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
<>	161:2cc1468da177	3603	}
<>	161:2cc1468da177	3604
<>	161:2cc1468da177	3605	/**
<>	161:2cc1468da177	3606	* @brief Configure Spread Spectrum used for PLL
<>	161:2cc1468da177	3607	* @note These bits must be written before enabling PLL
<>	161:2cc1468da177	3608	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
<>	161:2cc1468da177	3609	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
<>	161:2cc1468da177	3610	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
<>	161:2cc1468da177	3611	* @param Mod Between Min_Data=0 and Max_Data=8191
<>	161:2cc1468da177	3612	* @param Inc Between Min_Data=0 and Max_Data=32767
<>	161:2cc1468da177	3613	* @param Sel This parameter can be one of the following values:
<>	161:2cc1468da177	3614	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
<>	161:2cc1468da177	3615	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
<>	161:2cc1468da177	3616	* @retval None
<>	161:2cc1468da177	3617	*/
<>	161:2cc1468da177	3618	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
<>	161:2cc1468da177	3619	{
<>	161:2cc1468da177	3620	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
<>	161:2cc1468da177	3621	}
<>	161:2cc1468da177	3622
<>	161:2cc1468da177	3623	/**
<>	161:2cc1468da177	3624	* @brief Get Spread Spectrum Modulation Period for PLL
<>	161:2cc1468da177	3625	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
<>	161:2cc1468da177	3626	* @retval Between Min_Data=0 and Max_Data=8191
<>	161:2cc1468da177	3627	*/
<>	161:2cc1468da177	3628	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
<>	161:2cc1468da177	3629	{
<>	161:2cc1468da177	3630	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
<>	161:2cc1468da177	3631	}
<>	161:2cc1468da177	3632
<>	161:2cc1468da177	3633	/**
<>	161:2cc1468da177	3634	* @brief Get Spread Spectrum Incrementation Step for PLL
<>	161:2cc1468da177	3635	* @note Must be written before enabling PLL
<>	161:2cc1468da177	3636	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
<>	161:2cc1468da177	3637	* @retval Between Min_Data=0 and Max_Data=32767
<>	161:2cc1468da177	3638	*/
<>	161:2cc1468da177	3639	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
<>	161:2cc1468da177	3640	{
<>	161:2cc1468da177	3641	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
<>	161:2cc1468da177	3642	}
<>	161:2cc1468da177	3643
<>	161:2cc1468da177	3644	/**
<>	161:2cc1468da177	3645	* @brief Get Spread Spectrum Selection for PLL
<>	161:2cc1468da177	3646	* @note Must be written before enabling PLL
<>	161:2cc1468da177	3647	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
<>	161:2cc1468da177	3648	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3649	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
<>	161:2cc1468da177	3650	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
<>	161:2cc1468da177	3651	*/
<>	161:2cc1468da177	3652	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
<>	161:2cc1468da177	3653	{
<>	161:2cc1468da177	3654	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
<>	161:2cc1468da177	3655	}
<>	161:2cc1468da177	3656
<>	161:2cc1468da177	3657	/**
<>	161:2cc1468da177	3658	* @brief Enable Spread Spectrum for PLL.
<>	161:2cc1468da177	3659	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
<>	161:2cc1468da177	3660	* @retval None
<>	161:2cc1468da177	3661	*/
<>	161:2cc1468da177	3662	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
<>	161:2cc1468da177	3663	{
<>	161:2cc1468da177	3664	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
<>	161:2cc1468da177	3665	}
<>	161:2cc1468da177	3666
<>	161:2cc1468da177	3667	/**
<>	161:2cc1468da177	3668	* @brief Disable Spread Spectrum for PLL.
<>	161:2cc1468da177	3669	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
<>	161:2cc1468da177	3670	* @retval None
<>	161:2cc1468da177	3671	*/
<>	161:2cc1468da177	3672	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
<>	161:2cc1468da177	3673	{
<>	161:2cc1468da177	3674	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
<>	161:2cc1468da177	3675	}
<>	161:2cc1468da177	3676
<>	161:2cc1468da177	3677	/**
<>	161:2cc1468da177	3678	* @}
<>	161:2cc1468da177	3679	*/
<>	161:2cc1468da177	3680
<>	161:2cc1468da177	3681	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
<>	161:2cc1468da177	3682	* @{
<>	161:2cc1468da177	3683	*/
<>	161:2cc1468da177	3684
<>	161:2cc1468da177	3685	/**
<>	161:2cc1468da177	3686	* @brief Enable PLLI2S
<>	161:2cc1468da177	3687	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
<>	161:2cc1468da177	3688	* @retval None
<>	161:2cc1468da177	3689	*/
<>	161:2cc1468da177	3690	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
<>	161:2cc1468da177	3691	{
<>	161:2cc1468da177	3692	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
<>	161:2cc1468da177	3693	}
<>	161:2cc1468da177	3694
<>	161:2cc1468da177	3695	/**
<>	161:2cc1468da177	3696	* @brief Disable PLLI2S
<>	161:2cc1468da177	3697	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
<>	161:2cc1468da177	3698	* @retval None
<>	161:2cc1468da177	3699	*/
<>	161:2cc1468da177	3700	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
<>	161:2cc1468da177	3701	{
<>	161:2cc1468da177	3702	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
<>	161:2cc1468da177	3703	}
<>	161:2cc1468da177	3704
<>	161:2cc1468da177	3705	/**
<>	161:2cc1468da177	3706	* @brief Check if PLLI2S Ready
<>	161:2cc1468da177	3707	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
<>	161:2cc1468da177	3708	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	3709	*/
<>	161:2cc1468da177	3710	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
<>	161:2cc1468da177	3711	{
<>	161:2cc1468da177	3712	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
<>	161:2cc1468da177	3713	}
<>	161:2cc1468da177	3714
<>	161:2cc1468da177	3715	/**
<>	161:2cc1468da177	3716	* @brief Configure PLLI2S used for SAI1 and SAI2 domain clock
<>	161:2cc1468da177	3717	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	3718	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	3719	* @note PLLN/PLLQ can be written only when PLLI2S is disabled
<>	161:2cc1468da177	3720	* @note This can be selected for SAI1 and SAI2
<>	161:2cc1468da177	3721	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
<>	161:2cc1468da177	3722	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
<>	161:2cc1468da177	3723	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
<>	161:2cc1468da177	3724	* PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
<>	161:2cc1468da177	3725	* DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI
<>	161:2cc1468da177	3726	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3727	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	3728	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	3729	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	3730	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	3731	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	3732	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	3733	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	3734	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	3735	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	3736	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	3737	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	3738	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	3739	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	3740	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	3741	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	3742	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	3743	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	3744	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	3745	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	3746	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	3747	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	3748	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	3749	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	3750	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	3751	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	3752	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	3753	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	3754	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	3755	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	3756	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	3757	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	3758	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	3759	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	3760	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	3761	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	3762	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	3763	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	3764	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	3765	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	3766	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	3767	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	3768	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	3769	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	3770	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	3771	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	3772	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	3773	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	3774	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	3775	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	3776	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	3777	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	3778	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	3779	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	3780	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	3781	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	3782	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	3783	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	3784	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	3785	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	3786	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	3787	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	3788	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	3789	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	3790	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	3791	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	3792	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	3793	* @param PLLQ This parameter can be one of the following values:
<>	161:2cc1468da177	3794	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
<>	161:2cc1468da177	3795	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
<>	161:2cc1468da177	3796	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
<>	161:2cc1468da177	3797	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
<>	161:2cc1468da177	3798	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
<>	161:2cc1468da177	3799	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
<>	161:2cc1468da177	3800	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
<>	161:2cc1468da177	3801	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
<>	161:2cc1468da177	3802	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
<>	161:2cc1468da177	3803	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
<>	161:2cc1468da177	3804	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
<>	161:2cc1468da177	3805	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
<>	161:2cc1468da177	3806	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
<>	161:2cc1468da177	3807	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
<>	161:2cc1468da177	3808	* @param PLLDIVQ This parameter can be one of the following values:
<>	161:2cc1468da177	3809	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
<>	161:2cc1468da177	3810	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
<>	161:2cc1468da177	3811	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
<>	161:2cc1468da177	3812	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
<>	161:2cc1468da177	3813	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
<>	161:2cc1468da177	3814	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
<>	161:2cc1468da177	3815	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
<>	161:2cc1468da177	3816	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
<>	161:2cc1468da177	3817	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
<>	161:2cc1468da177	3818	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
<>	161:2cc1468da177	3819	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
<>	161:2cc1468da177	3820	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
<>	161:2cc1468da177	3821	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
<>	161:2cc1468da177	3822	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
<>	161:2cc1468da177	3823	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
<>	161:2cc1468da177	3824	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
<>	161:2cc1468da177	3825	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
<>	161:2cc1468da177	3826	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
<>	161:2cc1468da177	3827	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
<>	161:2cc1468da177	3828	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
<>	161:2cc1468da177	3829	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
<>	161:2cc1468da177	3830	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
<>	161:2cc1468da177	3831	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
<>	161:2cc1468da177	3832	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
<>	161:2cc1468da177	3833	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
<>	161:2cc1468da177	3834	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
<>	161:2cc1468da177	3835	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
<>	161:2cc1468da177	3836	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
<>	161:2cc1468da177	3837	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
<>	161:2cc1468da177	3838	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
<>	161:2cc1468da177	3839	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
<>	161:2cc1468da177	3840	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
<>	161:2cc1468da177	3841	* @retval None
<>	161:2cc1468da177	3842	*/
<>	161:2cc1468da177	3843	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
<>	161:2cc1468da177	3844	{
<>	161:2cc1468da177	3845	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
<>	161:2cc1468da177	3846	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLQ);
<>	161:2cc1468da177	3847	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
<>	161:2cc1468da177	3848	}
<>	161:2cc1468da177	3849
<>	161:2cc1468da177	3850	#if defined(SPDIFRX)
<>	161:2cc1468da177	3851	/**
<>	161:2cc1468da177	3852	* @brief Configure PLLI2S used for SPDIFRX domain clock
<>	161:2cc1468da177	3853	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	3854	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	3855	* @note PLLN/PLLP can be written only when PLLI2S is disabled
<>	161:2cc1468da177	3856	* @note This can be selected for SPDIFRX
<>	161:2cc1468da177	3857	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
<>	161:2cc1468da177	3858	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
<>	161:2cc1468da177	3859	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
<>	161:2cc1468da177	3860	* PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
<>	161:2cc1468da177	3861	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3862	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	3863	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	3864	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	3865	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	3866	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	3867	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	3868	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	3869	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	3870	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	3871	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	3872	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	3873	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	3874	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	3875	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	3876	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	3877	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	3878	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	3879	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	3880	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	3881	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	3882	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	3883	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	3884	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	3885	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	3886	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	3887	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	3888	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	3889	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	3890	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	3891	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	3892	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	3893	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	3894	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	3895	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	3896	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	3897	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	3898	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	3899	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	3900	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	3901	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	3902	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	3903	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	3904	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	3905	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	3906	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	3907	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	3908	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	3909	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	3910	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	3911	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	3912	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	3913	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	3914	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	3915	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	3916	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	3917	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	3918	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	3919	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	3920	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	3921	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	3922	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	3923	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	3924	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	3925	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	3926	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	3927	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	3928	* @param PLLP This parameter can be one of the following values:
<>	161:2cc1468da177	3929	* @arg @ref LL_RCC_PLLI2SP_DIV_2
<>	161:2cc1468da177	3930	* @arg @ref LL_RCC_PLLI2SP_DIV_4
<>	161:2cc1468da177	3931	* @arg @ref LL_RCC_PLLI2SP_DIV_6
<>	161:2cc1468da177	3932	* @arg @ref LL_RCC_PLLI2SP_DIV_8
<>	161:2cc1468da177	3933	* @retval None
<>	161:2cc1468da177	3934	*/
<>	161:2cc1468da177	3935	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
<>	161:2cc1468da177	3936	{
<>	161:2cc1468da177	3937	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
<>	161:2cc1468da177	3938	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLP);
<>	161:2cc1468da177	3939	}
<>	161:2cc1468da177	3940	#endif /* SPDIFRX */
<>	161:2cc1468da177	3941
<>	161:2cc1468da177	3942	/**
<>	161:2cc1468da177	3943	* @brief Configure PLLI2S used for I2S1 domain clock
<>	161:2cc1468da177	3944	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	3945	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	3946	* @note PLLN/PLLR can be written only when PLLI2S is disabled
<>	161:2cc1468da177	3947	* @note This can be selected for I2S
<>	161:2cc1468da177	3948	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
<>	161:2cc1468da177	3949	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
<>	161:2cc1468da177	3950	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
<>	161:2cc1468da177	3951	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
<>	161:2cc1468da177	3952	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	3953	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	3954	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	3955	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	3956	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	3957	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	3958	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	3959	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	3960	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	3961	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	3962	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	3963	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	3964	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	3965	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	3966	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	3967	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	3968	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	3969	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	3970	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	3971	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	3972	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	3973	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	3974	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	3975	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	3976	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	3977	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	3978	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	3979	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	3980	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	3981	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	3982	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	3983	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	3984	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	3985	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	3986	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	3987	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	3988	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	3989	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	3990	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	3991	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	3992	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	3993	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	3994	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	3995	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	3996	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	3997	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	3998	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	3999	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	4000	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	4001	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	4002	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	4003	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	4004	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	4005	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	4006	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	4007	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	4008	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	4009	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	4010	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	4011	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	4012	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	4013	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	4014	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	4015	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	4016	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	4017	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	4018	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	4019	* @param PLLR This parameter can be one of the following values:
<>	161:2cc1468da177	4020	* @arg @ref LL_RCC_PLLI2SR_DIV_2
<>	161:2cc1468da177	4021	* @arg @ref LL_RCC_PLLI2SR_DIV_3
<>	161:2cc1468da177	4022	* @arg @ref LL_RCC_PLLI2SR_DIV_4
<>	161:2cc1468da177	4023	* @arg @ref LL_RCC_PLLI2SR_DIV_5
<>	161:2cc1468da177	4024	* @arg @ref LL_RCC_PLLI2SR_DIV_6
<>	161:2cc1468da177	4025	* @arg @ref LL_RCC_PLLI2SR_DIV_7
<>	161:2cc1468da177	4026	* @retval None
<>	161:2cc1468da177	4027	*/
<>	161:2cc1468da177	4028	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
<>	161:2cc1468da177	4029	{
<>	161:2cc1468da177	4030	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
<>	161:2cc1468da177	4031	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
<>	161:2cc1468da177	4032	}
<>	161:2cc1468da177	4033
<>	161:2cc1468da177	4034	/**
<>	161:2cc1468da177	4035	* @brief Get I2SPLL multiplication factor for VCO
<>	161:2cc1468da177	4036	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
<>	161:2cc1468da177	4037	* @retval Between 50 and 432
<>	161:2cc1468da177	4038	*/
<>	161:2cc1468da177	4039	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
<>	161:2cc1468da177	4040	{
<>	161:2cc1468da177	4041	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
<>	161:2cc1468da177	4042	}
<>	161:2cc1468da177	4043
<>	161:2cc1468da177	4044	/**
<>	161:2cc1468da177	4045	* @brief Get I2SPLL division factor for PLLI2SQ
<>	161:2cc1468da177	4046	* @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
<>	161:2cc1468da177	4047	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4048	* @arg @ref LL_RCC_PLLI2SQ_DIV_2
<>	161:2cc1468da177	4049	* @arg @ref LL_RCC_PLLI2SQ_DIV_3
<>	161:2cc1468da177	4050	* @arg @ref LL_RCC_PLLI2SQ_DIV_4
<>	161:2cc1468da177	4051	* @arg @ref LL_RCC_PLLI2SQ_DIV_5
<>	161:2cc1468da177	4052	* @arg @ref LL_RCC_PLLI2SQ_DIV_6
<>	161:2cc1468da177	4053	* @arg @ref LL_RCC_PLLI2SQ_DIV_7
<>	161:2cc1468da177	4054	* @arg @ref LL_RCC_PLLI2SQ_DIV_8
<>	161:2cc1468da177	4055	* @arg @ref LL_RCC_PLLI2SQ_DIV_9
<>	161:2cc1468da177	4056	* @arg @ref LL_RCC_PLLI2SQ_DIV_10
<>	161:2cc1468da177	4057	* @arg @ref LL_RCC_PLLI2SQ_DIV_11
<>	161:2cc1468da177	4058	* @arg @ref LL_RCC_PLLI2SQ_DIV_12
<>	161:2cc1468da177	4059	* @arg @ref LL_RCC_PLLI2SQ_DIV_13
<>	161:2cc1468da177	4060	* @arg @ref LL_RCC_PLLI2SQ_DIV_14
<>	161:2cc1468da177	4061	* @arg @ref LL_RCC_PLLI2SQ_DIV_15
<>	161:2cc1468da177	4062	*/
<>	161:2cc1468da177	4063	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
<>	161:2cc1468da177	4064	{
<>	161:2cc1468da177	4065	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
<>	161:2cc1468da177	4066	}
<>	161:2cc1468da177	4067
<>	161:2cc1468da177	4068	/**
<>	161:2cc1468da177	4069	* @brief Get I2SPLL division factor for PLLI2SR
<>	161:2cc1468da177	4070	* @note used for PLLI2SCLK (I2S clock)
<>	161:2cc1468da177	4071	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
<>	161:2cc1468da177	4072	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4073	* @arg @ref LL_RCC_PLLI2SR_DIV_2
<>	161:2cc1468da177	4074	* @arg @ref LL_RCC_PLLI2SR_DIV_3
<>	161:2cc1468da177	4075	* @arg @ref LL_RCC_PLLI2SR_DIV_4
<>	161:2cc1468da177	4076	* @arg @ref LL_RCC_PLLI2SR_DIV_5
<>	161:2cc1468da177	4077	* @arg @ref LL_RCC_PLLI2SR_DIV_6
<>	161:2cc1468da177	4078	* @arg @ref LL_RCC_PLLI2SR_DIV_7
<>	161:2cc1468da177	4079	*/
<>	161:2cc1468da177	4080	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
<>	161:2cc1468da177	4081	{
<>	161:2cc1468da177	4082	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
<>	161:2cc1468da177	4083	}
<>	161:2cc1468da177	4084
<>	161:2cc1468da177	4085	#if defined(RCC_PLLI2SCFGR_PLLI2SP)
<>	161:2cc1468da177	4086	/**
<>	161:2cc1468da177	4087	* @brief Get I2SPLL division factor for PLLI2SP
<>	161:2cc1468da177	4088	* @note used for PLLSPDIFRXCLK (SPDIFRX clock)
<>	161:2cc1468da177	4089	* @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
<>	161:2cc1468da177	4090	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4091	* @arg @ref LL_RCC_PLLI2SP_DIV_2
<>	161:2cc1468da177	4092	* @arg @ref LL_RCC_PLLI2SP_DIV_4
<>	161:2cc1468da177	4093	* @arg @ref LL_RCC_PLLI2SP_DIV_6
<>	161:2cc1468da177	4094	* @arg @ref LL_RCC_PLLI2SP_DIV_8
<>	161:2cc1468da177	4095	*/
<>	161:2cc1468da177	4096	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
<>	161:2cc1468da177	4097	{
<>	161:2cc1468da177	4098	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
<>	161:2cc1468da177	4099	}
<>	161:2cc1468da177	4100	#endif /* RCC_PLLI2SCFGR_PLLI2SP */
<>	161:2cc1468da177	4101
<>	161:2cc1468da177	4102	/**
<>	161:2cc1468da177	4103	* @brief Get I2SPLL division factor for PLLI2SDIVQ
<>	161:2cc1468da177	4104	* @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
<>	161:2cc1468da177	4105	* @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
<>	161:2cc1468da177	4106	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4107	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
<>	161:2cc1468da177	4108	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
<>	161:2cc1468da177	4109	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
<>	161:2cc1468da177	4110	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
<>	161:2cc1468da177	4111	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
<>	161:2cc1468da177	4112	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
<>	161:2cc1468da177	4113	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
<>	161:2cc1468da177	4114	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
<>	161:2cc1468da177	4115	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
<>	161:2cc1468da177	4116	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
<>	161:2cc1468da177	4117	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
<>	161:2cc1468da177	4118	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
<>	161:2cc1468da177	4119	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
<>	161:2cc1468da177	4120	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
<>	161:2cc1468da177	4121	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
<>	161:2cc1468da177	4122	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
<>	161:2cc1468da177	4123	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
<>	161:2cc1468da177	4124	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
<>	161:2cc1468da177	4125	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
<>	161:2cc1468da177	4126	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
<>	161:2cc1468da177	4127	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
<>	161:2cc1468da177	4128	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
<>	161:2cc1468da177	4129	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
<>	161:2cc1468da177	4130	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
<>	161:2cc1468da177	4131	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
<>	161:2cc1468da177	4132	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
<>	161:2cc1468da177	4133	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
<>	161:2cc1468da177	4134	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
<>	161:2cc1468da177	4135	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
<>	161:2cc1468da177	4136	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
<>	161:2cc1468da177	4137	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
<>	161:2cc1468da177	4138	* @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
<>	161:2cc1468da177	4139	*/
<>	161:2cc1468da177	4140	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
<>	161:2cc1468da177	4141	{
<>	161:2cc1468da177	4142	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
<>	161:2cc1468da177	4143	}
<>	161:2cc1468da177	4144
<>	161:2cc1468da177	4145	/**
<>	161:2cc1468da177	4146	* @}
<>	161:2cc1468da177	4147	*/
<>	161:2cc1468da177	4148
<>	161:2cc1468da177	4149	/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
<>	161:2cc1468da177	4150	* @{
<>	161:2cc1468da177	4151	*/
<>	161:2cc1468da177	4152
<>	161:2cc1468da177	4153	/**
<>	161:2cc1468da177	4154	* @brief Enable PLLSAI
<>	161:2cc1468da177	4155	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
<>	161:2cc1468da177	4156	* @retval None
<>	161:2cc1468da177	4157	*/
<>	161:2cc1468da177	4158	__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
<>	161:2cc1468da177	4159	{
<>	161:2cc1468da177	4160	SET_BIT(RCC->CR, RCC_CR_PLLSAION);
<>	161:2cc1468da177	4161	}
<>	161:2cc1468da177	4162
<>	161:2cc1468da177	4163	/**
<>	161:2cc1468da177	4164	* @brief Disable PLLSAI
<>	161:2cc1468da177	4165	* @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
<>	161:2cc1468da177	4166	* @retval None
<>	161:2cc1468da177	4167	*/
<>	161:2cc1468da177	4168	__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
<>	161:2cc1468da177	4169	{
<>	161:2cc1468da177	4170	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
<>	161:2cc1468da177	4171	}
<>	161:2cc1468da177	4172
<>	161:2cc1468da177	4173	/**
<>	161:2cc1468da177	4174	* @brief Check if PLLSAI Ready
<>	161:2cc1468da177	4175	* @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
<>	161:2cc1468da177	4176	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4177	*/
<>	161:2cc1468da177	4178	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
<>	161:2cc1468da177	4179	{
<>	161:2cc1468da177	4180	return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
<>	161:2cc1468da177	4181	}
<>	161:2cc1468da177	4182
<>	161:2cc1468da177	4183	/**
<>	161:2cc1468da177	4184	* @brief Configure PLLSAI used for SAI1 and SAI2 domain clock
<>	161:2cc1468da177	4185	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	4186	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	4187	* @note PLLN/PLLQ can be written only when PLLSAI is disabled
<>	161:2cc1468da177	4188	* @note This can be selected for SAI1 and SAI2
<>	161:2cc1468da177	4189	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
<>	161:2cc1468da177	4190	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
<>	161:2cc1468da177	4191	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
<>	161:2cc1468da177	4192	* PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
<>	161:2cc1468da177	4193	* DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
<>	161:2cc1468da177	4194	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	4195	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	4196	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	4197	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	4198	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	4199	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	4200	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	4201	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	4202	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	4203	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	4204	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	4205	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	4206	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	4207	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	4208	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	4209	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	4210	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	4211	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	4212	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	4213	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	4214	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	4215	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	4216	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	4217	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	4218	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	4219	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	4220	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	4221	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	4222	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	4223	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	4224	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	4225	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	4226	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	4227	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	4228	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	4229	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	4230	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	4231	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	4232	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	4233	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	4234	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	4235	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	4236	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	4237	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	4238	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	4239	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	4240	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	4241	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	4242	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	4243	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	4244	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	4245	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	4246	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	4247	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	4248	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	4249	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	4250	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	4251	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	4252	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	4253	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	4254	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	4255	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	4256	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	4257	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	4258	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	4259	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	4260	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	4261	* @param PLLQ This parameter can be one of the following values:
<>	161:2cc1468da177	4262	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
<>	161:2cc1468da177	4263	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
<>	161:2cc1468da177	4264	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
<>	161:2cc1468da177	4265	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
<>	161:2cc1468da177	4266	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
<>	161:2cc1468da177	4267	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
<>	161:2cc1468da177	4268	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
<>	161:2cc1468da177	4269	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
<>	161:2cc1468da177	4270	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
<>	161:2cc1468da177	4271	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
<>	161:2cc1468da177	4272	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
<>	161:2cc1468da177	4273	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
<>	161:2cc1468da177	4274	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
<>	161:2cc1468da177	4275	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
<>	161:2cc1468da177	4276	* @param PLLDIVQ This parameter can be one of the following values:
<>	161:2cc1468da177	4277	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
<>	161:2cc1468da177	4278	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
<>	161:2cc1468da177	4279	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
<>	161:2cc1468da177	4280	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
<>	161:2cc1468da177	4281	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
<>	161:2cc1468da177	4282	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
<>	161:2cc1468da177	4283	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
<>	161:2cc1468da177	4284	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
<>	161:2cc1468da177	4285	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
<>	161:2cc1468da177	4286	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
<>	161:2cc1468da177	4287	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
<>	161:2cc1468da177	4288	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
<>	161:2cc1468da177	4289	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
<>	161:2cc1468da177	4290	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
<>	161:2cc1468da177	4291	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
<>	161:2cc1468da177	4292	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
<>	161:2cc1468da177	4293	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
<>	161:2cc1468da177	4294	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
<>	161:2cc1468da177	4295	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
<>	161:2cc1468da177	4296	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
<>	161:2cc1468da177	4297	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
<>	161:2cc1468da177	4298	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
<>	161:2cc1468da177	4299	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
<>	161:2cc1468da177	4300	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
<>	161:2cc1468da177	4301	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
<>	161:2cc1468da177	4302	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
<>	161:2cc1468da177	4303	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
<>	161:2cc1468da177	4304	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
<>	161:2cc1468da177	4305	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
<>	161:2cc1468da177	4306	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
<>	161:2cc1468da177	4307	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
<>	161:2cc1468da177	4308	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
<>	161:2cc1468da177	4309	* @retval None
<>	161:2cc1468da177	4310	*/
<>	161:2cc1468da177	4311	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
<>	161:2cc1468da177	4312	{
<>	161:2cc1468da177	4313	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
<>	161:2cc1468da177	4314	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLQ);
<>	161:2cc1468da177	4315	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ);
<>	161:2cc1468da177	4316	}
<>	161:2cc1468da177	4317
<>	161:2cc1468da177	4318	/**
<>	161:2cc1468da177	4319	* @brief Configure PLLSAI used for 48Mhz domain clock
<>	161:2cc1468da177	4320	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	4321	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	4322	* @note PLLN/PLLP can be written only when PLLSAI is disabled
<>	161:2cc1468da177	4323	* @note This can be selected for USB, RNG, SDMMC1
<>	161:2cc1468da177	4324	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
<>	161:2cc1468da177	4325	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
<>	161:2cc1468da177	4326	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
<>	161:2cc1468da177	4327	* PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
<>	161:2cc1468da177	4328	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	4329	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	4330	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	4331	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	4332	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	4333	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	4334	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	4335	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	4336	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	4337	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	4338	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	4339	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	4340	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	4341	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	4342	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	4343	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	4344	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	4345	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	4346	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	4347	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	4348	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	4349	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	4350	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	4351	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	4352	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	4353	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	4354	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	4355	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	4356	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	4357	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	4358	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	4359	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	4360	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	4361	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	4362	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	4363	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	4364	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	4365	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	4366	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	4367	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	4368	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	4369	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	4370	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	4371	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	4372	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	4373	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	4374	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	4375	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	4376	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	4377	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	4378	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	4379	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	4380	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	4381	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	4382	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	4383	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	4384	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	4385	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	4386	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	4387	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	4388	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	4389	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	4390	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	4391	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	4392	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	4393	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	4394	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	4395	* @param PLLP This parameter can be one of the following values:
<>	161:2cc1468da177	4396	* @arg @ref LL_RCC_PLLSAIP_DIV_2
<>	161:2cc1468da177	4397	* @arg @ref LL_RCC_PLLSAIP_DIV_4
<>	161:2cc1468da177	4398	* @arg @ref LL_RCC_PLLSAIP_DIV_6
<>	161:2cc1468da177	4399	* @arg @ref LL_RCC_PLLSAIP_DIV_8
<>	161:2cc1468da177	4400	* @retval None
<>	161:2cc1468da177	4401	*/
<>	161:2cc1468da177	4402	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
<>	161:2cc1468da177	4403	{
<>	161:2cc1468da177	4404	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
<>	161:2cc1468da177	4405	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLP);
<>	161:2cc1468da177	4406	}
<>	161:2cc1468da177	4407
<>	161:2cc1468da177	4408	#if defined(LTDC)
<>	161:2cc1468da177	4409	/**
<>	161:2cc1468da177	4410	* @brief Configure PLLSAI used for LTDC domain clock
<>	161:2cc1468da177	4411	* @note PLL Source and PLLM Divider can be written only when PLL,
<>	161:2cc1468da177	4412	* PLLI2S and PLLSAI are disabled
<>	161:2cc1468da177	4413	* @note PLLN/PLLR can be written only when PLLSAI is disabled
<>	161:2cc1468da177	4414	* @note This can be selected for LTDC
<>	161:2cc1468da177	4415	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
<>	161:2cc1468da177	4416	* PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
<>	161:2cc1468da177	4417	* PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
<>	161:2cc1468da177	4418	* PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
<>	161:2cc1468da177	4419	* DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
<>	161:2cc1468da177	4420	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	4421	* @arg @ref LL_RCC_PLLSOURCE_HSI
<>	161:2cc1468da177	4422	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	161:2cc1468da177	4423	* @param PLLM This parameter can be one of the following values:
<>	161:2cc1468da177	4424	* @arg @ref LL_RCC_PLLM_DIV_2
<>	161:2cc1468da177	4425	* @arg @ref LL_RCC_PLLM_DIV_3
<>	161:2cc1468da177	4426	* @arg @ref LL_RCC_PLLM_DIV_4
<>	161:2cc1468da177	4427	* @arg @ref LL_RCC_PLLM_DIV_5
<>	161:2cc1468da177	4428	* @arg @ref LL_RCC_PLLM_DIV_6
<>	161:2cc1468da177	4429	* @arg @ref LL_RCC_PLLM_DIV_7
<>	161:2cc1468da177	4430	* @arg @ref LL_RCC_PLLM_DIV_8
<>	161:2cc1468da177	4431	* @arg @ref LL_RCC_PLLM_DIV_9
<>	161:2cc1468da177	4432	* @arg @ref LL_RCC_PLLM_DIV_10
<>	161:2cc1468da177	4433	* @arg @ref LL_RCC_PLLM_DIV_11
<>	161:2cc1468da177	4434	* @arg @ref LL_RCC_PLLM_DIV_12
<>	161:2cc1468da177	4435	* @arg @ref LL_RCC_PLLM_DIV_13
<>	161:2cc1468da177	4436	* @arg @ref LL_RCC_PLLM_DIV_14
<>	161:2cc1468da177	4437	* @arg @ref LL_RCC_PLLM_DIV_15
<>	161:2cc1468da177	4438	* @arg @ref LL_RCC_PLLM_DIV_16
<>	161:2cc1468da177	4439	* @arg @ref LL_RCC_PLLM_DIV_17
<>	161:2cc1468da177	4440	* @arg @ref LL_RCC_PLLM_DIV_18
<>	161:2cc1468da177	4441	* @arg @ref LL_RCC_PLLM_DIV_19
<>	161:2cc1468da177	4442	* @arg @ref LL_RCC_PLLM_DIV_20
<>	161:2cc1468da177	4443	* @arg @ref LL_RCC_PLLM_DIV_21
<>	161:2cc1468da177	4444	* @arg @ref LL_RCC_PLLM_DIV_22
<>	161:2cc1468da177	4445	* @arg @ref LL_RCC_PLLM_DIV_23
<>	161:2cc1468da177	4446	* @arg @ref LL_RCC_PLLM_DIV_24
<>	161:2cc1468da177	4447	* @arg @ref LL_RCC_PLLM_DIV_25
<>	161:2cc1468da177	4448	* @arg @ref LL_RCC_PLLM_DIV_26
<>	161:2cc1468da177	4449	* @arg @ref LL_RCC_PLLM_DIV_27
<>	161:2cc1468da177	4450	* @arg @ref LL_RCC_PLLM_DIV_28
<>	161:2cc1468da177	4451	* @arg @ref LL_RCC_PLLM_DIV_29
<>	161:2cc1468da177	4452	* @arg @ref LL_RCC_PLLM_DIV_30
<>	161:2cc1468da177	4453	* @arg @ref LL_RCC_PLLM_DIV_31
<>	161:2cc1468da177	4454	* @arg @ref LL_RCC_PLLM_DIV_32
<>	161:2cc1468da177	4455	* @arg @ref LL_RCC_PLLM_DIV_33
<>	161:2cc1468da177	4456	* @arg @ref LL_RCC_PLLM_DIV_34
<>	161:2cc1468da177	4457	* @arg @ref LL_RCC_PLLM_DIV_35
<>	161:2cc1468da177	4458	* @arg @ref LL_RCC_PLLM_DIV_36
<>	161:2cc1468da177	4459	* @arg @ref LL_RCC_PLLM_DIV_37
<>	161:2cc1468da177	4460	* @arg @ref LL_RCC_PLLM_DIV_38
<>	161:2cc1468da177	4461	* @arg @ref LL_RCC_PLLM_DIV_39
<>	161:2cc1468da177	4462	* @arg @ref LL_RCC_PLLM_DIV_40
<>	161:2cc1468da177	4463	* @arg @ref LL_RCC_PLLM_DIV_41
<>	161:2cc1468da177	4464	* @arg @ref LL_RCC_PLLM_DIV_42
<>	161:2cc1468da177	4465	* @arg @ref LL_RCC_PLLM_DIV_43
<>	161:2cc1468da177	4466	* @arg @ref LL_RCC_PLLM_DIV_44
<>	161:2cc1468da177	4467	* @arg @ref LL_RCC_PLLM_DIV_45
<>	161:2cc1468da177	4468	* @arg @ref LL_RCC_PLLM_DIV_46
<>	161:2cc1468da177	4469	* @arg @ref LL_RCC_PLLM_DIV_47
<>	161:2cc1468da177	4470	* @arg @ref LL_RCC_PLLM_DIV_48
<>	161:2cc1468da177	4471	* @arg @ref LL_RCC_PLLM_DIV_49
<>	161:2cc1468da177	4472	* @arg @ref LL_RCC_PLLM_DIV_50
<>	161:2cc1468da177	4473	* @arg @ref LL_RCC_PLLM_DIV_51
<>	161:2cc1468da177	4474	* @arg @ref LL_RCC_PLLM_DIV_52
<>	161:2cc1468da177	4475	* @arg @ref LL_RCC_PLLM_DIV_53
<>	161:2cc1468da177	4476	* @arg @ref LL_RCC_PLLM_DIV_54
<>	161:2cc1468da177	4477	* @arg @ref LL_RCC_PLLM_DIV_55
<>	161:2cc1468da177	4478	* @arg @ref LL_RCC_PLLM_DIV_56
<>	161:2cc1468da177	4479	* @arg @ref LL_RCC_PLLM_DIV_57
<>	161:2cc1468da177	4480	* @arg @ref LL_RCC_PLLM_DIV_58
<>	161:2cc1468da177	4481	* @arg @ref LL_RCC_PLLM_DIV_59
<>	161:2cc1468da177	4482	* @arg @ref LL_RCC_PLLM_DIV_60
<>	161:2cc1468da177	4483	* @arg @ref LL_RCC_PLLM_DIV_61
<>	161:2cc1468da177	4484	* @arg @ref LL_RCC_PLLM_DIV_62
<>	161:2cc1468da177	4485	* @arg @ref LL_RCC_PLLM_DIV_63
<>	161:2cc1468da177	4486	* @param PLLN Between 50 and 432
<>	161:2cc1468da177	4487	* @param PLLR This parameter can be one of the following values:
<>	161:2cc1468da177	4488	* @arg @ref LL_RCC_PLLSAIR_DIV_2
<>	161:2cc1468da177	4489	* @arg @ref LL_RCC_PLLSAIR_DIV_3
<>	161:2cc1468da177	4490	* @arg @ref LL_RCC_PLLSAIR_DIV_4
<>	161:2cc1468da177	4491	* @arg @ref LL_RCC_PLLSAIR_DIV_5
<>	161:2cc1468da177	4492	* @arg @ref LL_RCC_PLLSAIR_DIV_6
<>	161:2cc1468da177	4493	* @arg @ref LL_RCC_PLLSAIR_DIV_7
<>	161:2cc1468da177	4494	* @param PLLDIVR This parameter can be one of the following values:
<>	161:2cc1468da177	4495	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
<>	161:2cc1468da177	4496	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
<>	161:2cc1468da177	4497	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
<>	161:2cc1468da177	4498	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
<>	161:2cc1468da177	4499	* @retval None
<>	161:2cc1468da177	4500	*/
<>	161:2cc1468da177	4501	__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
<>	161:2cc1468da177	4502	{
<>	161:2cc1468da177	4503	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
<>	161:2cc1468da177	4504	MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN \| RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos \| PLLR);
<>	161:2cc1468da177	4505	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR);
<>	161:2cc1468da177	4506	}
<>	161:2cc1468da177	4507	#endif /* LTDC */
<>	161:2cc1468da177	4508
<>	161:2cc1468da177	4509	/**
<>	161:2cc1468da177	4510	* @brief Get SAIPLL multiplication factor for VCO
<>	161:2cc1468da177	4511	* @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
<>	161:2cc1468da177	4512	* @retval Between 50 and 432
<>	161:2cc1468da177	4513	*/
<>	161:2cc1468da177	4514	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
<>	161:2cc1468da177	4515	{
<>	161:2cc1468da177	4516	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
<>	161:2cc1468da177	4517	}
<>	161:2cc1468da177	4518
<>	161:2cc1468da177	4519	/**
<>	161:2cc1468da177	4520	* @brief Get SAIPLL division factor for PLLSAIQ
<>	161:2cc1468da177	4521	* @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
<>	161:2cc1468da177	4522	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4523	* @arg @ref LL_RCC_PLLSAIQ_DIV_2
<>	161:2cc1468da177	4524	* @arg @ref LL_RCC_PLLSAIQ_DIV_3
<>	161:2cc1468da177	4525	* @arg @ref LL_RCC_PLLSAIQ_DIV_4
<>	161:2cc1468da177	4526	* @arg @ref LL_RCC_PLLSAIQ_DIV_5
<>	161:2cc1468da177	4527	* @arg @ref LL_RCC_PLLSAIQ_DIV_6
<>	161:2cc1468da177	4528	* @arg @ref LL_RCC_PLLSAIQ_DIV_7
<>	161:2cc1468da177	4529	* @arg @ref LL_RCC_PLLSAIQ_DIV_8
<>	161:2cc1468da177	4530	* @arg @ref LL_RCC_PLLSAIQ_DIV_9
<>	161:2cc1468da177	4531	* @arg @ref LL_RCC_PLLSAIQ_DIV_10
<>	161:2cc1468da177	4532	* @arg @ref LL_RCC_PLLSAIQ_DIV_11
<>	161:2cc1468da177	4533	* @arg @ref LL_RCC_PLLSAIQ_DIV_12
<>	161:2cc1468da177	4534	* @arg @ref LL_RCC_PLLSAIQ_DIV_13
<>	161:2cc1468da177	4535	* @arg @ref LL_RCC_PLLSAIQ_DIV_14
<>	161:2cc1468da177	4536	* @arg @ref LL_RCC_PLLSAIQ_DIV_15
<>	161:2cc1468da177	4537	*/
<>	161:2cc1468da177	4538	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
<>	161:2cc1468da177	4539	{
<>	161:2cc1468da177	4540	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
<>	161:2cc1468da177	4541	}
<>	161:2cc1468da177	4542
<>	161:2cc1468da177	4543	#if defined(RCC_PLLSAICFGR_PLLSAIR)
<>	161:2cc1468da177	4544	/**
<>	161:2cc1468da177	4545	* @brief Get SAIPLL division factor for PLLSAIR
<>	161:2cc1468da177	4546	* @note used for PLLSAICLK (SAI clock)
<>	161:2cc1468da177	4547	* @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
<>	161:2cc1468da177	4548	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4549	* @arg @ref LL_RCC_PLLSAIR_DIV_2
<>	161:2cc1468da177	4550	* @arg @ref LL_RCC_PLLSAIR_DIV_3
<>	161:2cc1468da177	4551	* @arg @ref LL_RCC_PLLSAIR_DIV_4
<>	161:2cc1468da177	4552	* @arg @ref LL_RCC_PLLSAIR_DIV_5
<>	161:2cc1468da177	4553	* @arg @ref LL_RCC_PLLSAIR_DIV_6
<>	161:2cc1468da177	4554	* @arg @ref LL_RCC_PLLSAIR_DIV_7
<>	161:2cc1468da177	4555	*/
<>	161:2cc1468da177	4556	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
<>	161:2cc1468da177	4557	{
<>	161:2cc1468da177	4558	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
<>	161:2cc1468da177	4559	}
<>	161:2cc1468da177	4560	#endif /* RCC_PLLSAICFGR_PLLSAIR */
<>	161:2cc1468da177	4561
<>	161:2cc1468da177	4562	/**
<>	161:2cc1468da177	4563	* @brief Get SAIPLL division factor for PLLSAIP
<>	161:2cc1468da177	4564	* @note used for PLL48MCLK (48M domain clock)
<>	161:2cc1468da177	4565	* @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
<>	161:2cc1468da177	4566	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4567	* @arg @ref LL_RCC_PLLSAIP_DIV_2
<>	161:2cc1468da177	4568	* @arg @ref LL_RCC_PLLSAIP_DIV_4
<>	161:2cc1468da177	4569	* @arg @ref LL_RCC_PLLSAIP_DIV_6
<>	161:2cc1468da177	4570	* @arg @ref LL_RCC_PLLSAIP_DIV_8
<>	161:2cc1468da177	4571	*/
<>	161:2cc1468da177	4572	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
<>	161:2cc1468da177	4573	{
<>	161:2cc1468da177	4574	return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
<>	161:2cc1468da177	4575	}
<>	161:2cc1468da177	4576
<>	161:2cc1468da177	4577	/**
<>	161:2cc1468da177	4578	* @brief Get SAIPLL division factor for PLLSAIDIVQ
<>	161:2cc1468da177	4579	* @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
<>	161:2cc1468da177	4580	* @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
<>	161:2cc1468da177	4581	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4582	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
<>	161:2cc1468da177	4583	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
<>	161:2cc1468da177	4584	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
<>	161:2cc1468da177	4585	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
<>	161:2cc1468da177	4586	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
<>	161:2cc1468da177	4587	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
<>	161:2cc1468da177	4588	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
<>	161:2cc1468da177	4589	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
<>	161:2cc1468da177	4590	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
<>	161:2cc1468da177	4591	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
<>	161:2cc1468da177	4592	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
<>	161:2cc1468da177	4593	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
<>	161:2cc1468da177	4594	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
<>	161:2cc1468da177	4595	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
<>	161:2cc1468da177	4596	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
<>	161:2cc1468da177	4597	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
<>	161:2cc1468da177	4598	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
<>	161:2cc1468da177	4599	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
<>	161:2cc1468da177	4600	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
<>	161:2cc1468da177	4601	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
<>	161:2cc1468da177	4602	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
<>	161:2cc1468da177	4603	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
<>	161:2cc1468da177	4604	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
<>	161:2cc1468da177	4605	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
<>	161:2cc1468da177	4606	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
<>	161:2cc1468da177	4607	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
<>	161:2cc1468da177	4608	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
<>	161:2cc1468da177	4609	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
<>	161:2cc1468da177	4610	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
<>	161:2cc1468da177	4611	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
<>	161:2cc1468da177	4612	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
<>	161:2cc1468da177	4613	* @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
<>	161:2cc1468da177	4614	*/
<>	161:2cc1468da177	4615	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
<>	161:2cc1468da177	4616	{
<>	161:2cc1468da177	4617	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ));
<>	161:2cc1468da177	4618	}
<>	161:2cc1468da177	4619
<>	161:2cc1468da177	4620	#if defined(RCC_DCKCFGR1_PLLSAIDIVR)
<>	161:2cc1468da177	4621	/**
<>	161:2cc1468da177	4622	* @brief Get SAIPLL division factor for PLLSAIDIVR
<>	161:2cc1468da177	4623	* @note used for LTDC domain clock
<>	161:2cc1468da177	4624	* @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
<>	161:2cc1468da177	4625	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	4626	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
<>	161:2cc1468da177	4627	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
<>	161:2cc1468da177	4628	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
<>	161:2cc1468da177	4629	* @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
<>	161:2cc1468da177	4630	*/
<>	161:2cc1468da177	4631	__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
<>	161:2cc1468da177	4632	{
<>	161:2cc1468da177	4633	return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR));
<>	161:2cc1468da177	4634	}
<>	161:2cc1468da177	4635	#endif /* RCC_DCKCFGR1_PLLSAIDIVR */
<>	161:2cc1468da177	4636
<>	161:2cc1468da177	4637	/**
<>	161:2cc1468da177	4638	* @}
<>	161:2cc1468da177	4639	*/
<>	161:2cc1468da177	4640
<>	161:2cc1468da177	4641	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
<>	161:2cc1468da177	4642	* @{
<>	161:2cc1468da177	4643	*/
<>	161:2cc1468da177	4644
<>	161:2cc1468da177	4645	/**
<>	161:2cc1468da177	4646	* @brief Clear LSI ready interrupt flag
<>	161:2cc1468da177	4647	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
<>	161:2cc1468da177	4648	* @retval None
<>	161:2cc1468da177	4649	*/
<>	161:2cc1468da177	4650	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
<>	161:2cc1468da177	4651	{
<>	161:2cc1468da177	4652	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
<>	161:2cc1468da177	4653	}
<>	161:2cc1468da177	4654
<>	161:2cc1468da177	4655	/**
<>	161:2cc1468da177	4656	* @brief Clear LSE ready interrupt flag
<>	161:2cc1468da177	4657	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
<>	161:2cc1468da177	4658	* @retval None
<>	161:2cc1468da177	4659	*/
<>	161:2cc1468da177	4660	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
<>	161:2cc1468da177	4661	{
<>	161:2cc1468da177	4662	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
<>	161:2cc1468da177	4663	}
<>	161:2cc1468da177	4664
<>	161:2cc1468da177	4665	/**
<>	161:2cc1468da177	4666	* @brief Clear HSI ready interrupt flag
<>	161:2cc1468da177	4667	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
<>	161:2cc1468da177	4668	* @retval None
<>	161:2cc1468da177	4669	*/
<>	161:2cc1468da177	4670	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
<>	161:2cc1468da177	4671	{
<>	161:2cc1468da177	4672	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
<>	161:2cc1468da177	4673	}
<>	161:2cc1468da177	4674
<>	161:2cc1468da177	4675	/**
<>	161:2cc1468da177	4676	* @brief Clear HSE ready interrupt flag
<>	161:2cc1468da177	4677	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
<>	161:2cc1468da177	4678	* @retval None
<>	161:2cc1468da177	4679	*/
<>	161:2cc1468da177	4680	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
<>	161:2cc1468da177	4681	{
<>	161:2cc1468da177	4682	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
<>	161:2cc1468da177	4683	}
<>	161:2cc1468da177	4684
<>	161:2cc1468da177	4685	/**
<>	161:2cc1468da177	4686	* @brief Clear PLL ready interrupt flag
<>	161:2cc1468da177	4687	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
<>	161:2cc1468da177	4688	* @retval None
<>	161:2cc1468da177	4689	*/
<>	161:2cc1468da177	4690	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
<>	161:2cc1468da177	4691	{
<>	161:2cc1468da177	4692	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
<>	161:2cc1468da177	4693	}
<>	161:2cc1468da177	4694
<>	161:2cc1468da177	4695	/**
<>	161:2cc1468da177	4696	* @brief Clear PLLI2S ready interrupt flag
<>	161:2cc1468da177	4697	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
<>	161:2cc1468da177	4698	* @retval None
<>	161:2cc1468da177	4699	*/
<>	161:2cc1468da177	4700	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
<>	161:2cc1468da177	4701	{
<>	161:2cc1468da177	4702	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
<>	161:2cc1468da177	4703	}
<>	161:2cc1468da177	4704
<>	161:2cc1468da177	4705	/**
<>	161:2cc1468da177	4706	* @brief Clear PLLSAI ready interrupt flag
<>	161:2cc1468da177	4707	* @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
<>	161:2cc1468da177	4708	* @retval None
<>	161:2cc1468da177	4709	*/
<>	161:2cc1468da177	4710	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
<>	161:2cc1468da177	4711	{
<>	161:2cc1468da177	4712	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
<>	161:2cc1468da177	4713	}
<>	161:2cc1468da177	4714
<>	161:2cc1468da177	4715	/**
<>	161:2cc1468da177	4716	* @brief Clear Clock security system interrupt flag
<>	161:2cc1468da177	4717	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
<>	161:2cc1468da177	4718	* @retval None
<>	161:2cc1468da177	4719	*/
<>	161:2cc1468da177	4720	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
<>	161:2cc1468da177	4721	{
<>	161:2cc1468da177	4722	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
<>	161:2cc1468da177	4723	}
<>	161:2cc1468da177	4724
<>	161:2cc1468da177	4725	/**
<>	161:2cc1468da177	4726	* @brief Check if LSI ready interrupt occurred or not
<>	161:2cc1468da177	4727	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
<>	161:2cc1468da177	4728	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4729	*/
<>	161:2cc1468da177	4730	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
<>	161:2cc1468da177	4731	{
<>	161:2cc1468da177	4732	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
<>	161:2cc1468da177	4733	}
<>	161:2cc1468da177	4734
<>	161:2cc1468da177	4735	/**
<>	161:2cc1468da177	4736	* @brief Check if LSE ready interrupt occurred or not
<>	161:2cc1468da177	4737	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
<>	161:2cc1468da177	4738	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4739	*/
<>	161:2cc1468da177	4740	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
<>	161:2cc1468da177	4741	{
<>	161:2cc1468da177	4742	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
<>	161:2cc1468da177	4743	}
<>	161:2cc1468da177	4744
<>	161:2cc1468da177	4745	/**
<>	161:2cc1468da177	4746	* @brief Check if HSI ready interrupt occurred or not
<>	161:2cc1468da177	4747	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
<>	161:2cc1468da177	4748	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4749	*/
<>	161:2cc1468da177	4750	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
<>	161:2cc1468da177	4751	{
<>	161:2cc1468da177	4752	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
<>	161:2cc1468da177	4753	}
<>	161:2cc1468da177	4754
<>	161:2cc1468da177	4755	/**
<>	161:2cc1468da177	4756	* @brief Check if HSE ready interrupt occurred or not
<>	161:2cc1468da177	4757	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
<>	161:2cc1468da177	4758	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4759	*/
<>	161:2cc1468da177	4760	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
<>	161:2cc1468da177	4761	{
<>	161:2cc1468da177	4762	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
<>	161:2cc1468da177	4763	}
<>	161:2cc1468da177	4764
<>	161:2cc1468da177	4765	/**
<>	161:2cc1468da177	4766	* @brief Check if PLL ready interrupt occurred or not
<>	161:2cc1468da177	4767	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
<>	161:2cc1468da177	4768	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4769	*/
<>	161:2cc1468da177	4770	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
<>	161:2cc1468da177	4771	{
<>	161:2cc1468da177	4772	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
<>	161:2cc1468da177	4773	}
<>	161:2cc1468da177	4774
<>	161:2cc1468da177	4775	/**
<>	161:2cc1468da177	4776	* @brief Check if PLLI2S ready interrupt occurred or not
<>	161:2cc1468da177	4777	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
<>	161:2cc1468da177	4778	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4779	*/
<>	161:2cc1468da177	4780	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
<>	161:2cc1468da177	4781	{
<>	161:2cc1468da177	4782	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
<>	161:2cc1468da177	4783	}
<>	161:2cc1468da177	4784
<>	161:2cc1468da177	4785	/**
<>	161:2cc1468da177	4786	* @brief Check if PLLSAI ready interrupt occurred or not
<>	161:2cc1468da177	4787	* @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
<>	161:2cc1468da177	4788	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4789	*/
<>	161:2cc1468da177	4790	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
<>	161:2cc1468da177	4791	{
<>	161:2cc1468da177	4792	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
<>	161:2cc1468da177	4793	}
<>	161:2cc1468da177	4794
<>	161:2cc1468da177	4795	/**
<>	161:2cc1468da177	4796	* @brief Check if Clock security system interrupt occurred or not
<>	161:2cc1468da177	4797	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
<>	161:2cc1468da177	4798	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4799	*/
<>	161:2cc1468da177	4800	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
<>	161:2cc1468da177	4801	{
<>	161:2cc1468da177	4802	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
<>	161:2cc1468da177	4803	}
<>	161:2cc1468da177	4804
<>	161:2cc1468da177	4805	/**
<>	161:2cc1468da177	4806	* @brief Check if RCC flag Independent Watchdog reset is set or not.
<>	161:2cc1468da177	4807	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
<>	161:2cc1468da177	4808	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4809	*/
<>	161:2cc1468da177	4810	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
<>	161:2cc1468da177	4811	{
<>	161:2cc1468da177	4812	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
<>	161:2cc1468da177	4813	}
<>	161:2cc1468da177	4814
<>	161:2cc1468da177	4815	/**
<>	161:2cc1468da177	4816	* @brief Check if RCC flag Low Power reset is set or not.
<>	161:2cc1468da177	4817	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
<>	161:2cc1468da177	4818	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4819	*/
<>	161:2cc1468da177	4820	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
<>	161:2cc1468da177	4821	{
<>	161:2cc1468da177	4822	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
<>	161:2cc1468da177	4823	}
<>	161:2cc1468da177	4824
<>	161:2cc1468da177	4825	/**
<>	161:2cc1468da177	4826	* @brief Check if RCC flag Pin reset is set or not.
<>	161:2cc1468da177	4827	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
<>	161:2cc1468da177	4828	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4829	*/
<>	161:2cc1468da177	4830	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
<>	161:2cc1468da177	4831	{
<>	161:2cc1468da177	4832	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
<>	161:2cc1468da177	4833	}
<>	161:2cc1468da177	4834
<>	161:2cc1468da177	4835	/**
<>	161:2cc1468da177	4836	* @brief Check if RCC flag POR/PDR reset is set or not.
<>	161:2cc1468da177	4837	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
<>	161:2cc1468da177	4838	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4839	*/
<>	161:2cc1468da177	4840	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
<>	161:2cc1468da177	4841	{
<>	161:2cc1468da177	4842	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
<>	161:2cc1468da177	4843	}
<>	161:2cc1468da177	4844
<>	161:2cc1468da177	4845	/**
<>	161:2cc1468da177	4846	* @brief Check if RCC flag Software reset is set or not.
<>	161:2cc1468da177	4847	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
<>	161:2cc1468da177	4848	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4849	*/
<>	161:2cc1468da177	4850	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
<>	161:2cc1468da177	4851	{
<>	161:2cc1468da177	4852	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
<>	161:2cc1468da177	4853	}
<>	161:2cc1468da177	4854
<>	161:2cc1468da177	4855	/**
<>	161:2cc1468da177	4856	* @brief Check if RCC flag Window Watchdog reset is set or not.
<>	161:2cc1468da177	4857	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
<>	161:2cc1468da177	4858	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4859	*/
<>	161:2cc1468da177	4860	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
<>	161:2cc1468da177	4861	{
<>	161:2cc1468da177	4862	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
<>	161:2cc1468da177	4863	}
<>	161:2cc1468da177	4864
<>	161:2cc1468da177	4865	/**
<>	161:2cc1468da177	4866	* @brief Check if RCC flag BOR reset is set or not.
<>	161:2cc1468da177	4867	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
<>	161:2cc1468da177	4868	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4869	*/
<>	161:2cc1468da177	4870	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
<>	161:2cc1468da177	4871	{
<>	161:2cc1468da177	4872	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
<>	161:2cc1468da177	4873	}
<>	161:2cc1468da177	4874
<>	161:2cc1468da177	4875	/**
<>	161:2cc1468da177	4876	* @brief Set RMVF bit to clear the reset flags.
<>	161:2cc1468da177	4877	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
<>	161:2cc1468da177	4878	* @retval None
<>	161:2cc1468da177	4879	*/
<>	161:2cc1468da177	4880	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
<>	161:2cc1468da177	4881	{
<>	161:2cc1468da177	4882	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<>	161:2cc1468da177	4883	}
<>	161:2cc1468da177	4884
<>	161:2cc1468da177	4885	/**
<>	161:2cc1468da177	4886	* @}
<>	161:2cc1468da177	4887	*/
<>	161:2cc1468da177	4888
<>	161:2cc1468da177	4889	/** @defgroup RCC_LL_EF_IT_Management IT Management
<>	161:2cc1468da177	4890	* @{
<>	161:2cc1468da177	4891	*/
<>	161:2cc1468da177	4892
<>	161:2cc1468da177	4893	/**
<>	161:2cc1468da177	4894	* @brief Enable LSI ready interrupt
<>	161:2cc1468da177	4895	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
<>	161:2cc1468da177	4896	* @retval None
<>	161:2cc1468da177	4897	*/
<>	161:2cc1468da177	4898	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
<>	161:2cc1468da177	4899	{
<>	161:2cc1468da177	4900	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	161:2cc1468da177	4901	}
<>	161:2cc1468da177	4902
<>	161:2cc1468da177	4903	/**
<>	161:2cc1468da177	4904	* @brief Enable LSE ready interrupt
<>	161:2cc1468da177	4905	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
<>	161:2cc1468da177	4906	* @retval None
<>	161:2cc1468da177	4907	*/
<>	161:2cc1468da177	4908	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
<>	161:2cc1468da177	4909	{
<>	161:2cc1468da177	4910	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	161:2cc1468da177	4911	}
<>	161:2cc1468da177	4912
<>	161:2cc1468da177	4913	/**
<>	161:2cc1468da177	4914	* @brief Enable HSI ready interrupt
<>	161:2cc1468da177	4915	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
<>	161:2cc1468da177	4916	* @retval None
<>	161:2cc1468da177	4917	*/
<>	161:2cc1468da177	4918	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
<>	161:2cc1468da177	4919	{
<>	161:2cc1468da177	4920	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	161:2cc1468da177	4921	}
<>	161:2cc1468da177	4922
<>	161:2cc1468da177	4923	/**
<>	161:2cc1468da177	4924	* @brief Enable HSE ready interrupt
<>	161:2cc1468da177	4925	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
<>	161:2cc1468da177	4926	* @retval None
<>	161:2cc1468da177	4927	*/
<>	161:2cc1468da177	4928	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
<>	161:2cc1468da177	4929	{
<>	161:2cc1468da177	4930	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	161:2cc1468da177	4931	}
<>	161:2cc1468da177	4932
<>	161:2cc1468da177	4933	/**
<>	161:2cc1468da177	4934	* @brief Enable PLL ready interrupt
<>	161:2cc1468da177	4935	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
<>	161:2cc1468da177	4936	* @retval None
<>	161:2cc1468da177	4937	*/
<>	161:2cc1468da177	4938	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
<>	161:2cc1468da177	4939	{
<>	161:2cc1468da177	4940	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	161:2cc1468da177	4941	}
<>	161:2cc1468da177	4942
<>	161:2cc1468da177	4943	/**
<>	161:2cc1468da177	4944	* @brief Enable PLLI2S ready interrupt
<>	161:2cc1468da177	4945	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
<>	161:2cc1468da177	4946	* @retval None
<>	161:2cc1468da177	4947	*/
<>	161:2cc1468da177	4948	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
<>	161:2cc1468da177	4949	{
<>	161:2cc1468da177	4950	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
<>	161:2cc1468da177	4951	}
<>	161:2cc1468da177	4952
<>	161:2cc1468da177	4953	/**
<>	161:2cc1468da177	4954	* @brief Enable PLLSAI ready interrupt
<>	161:2cc1468da177	4955	* @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
<>	161:2cc1468da177	4956	* @retval None
<>	161:2cc1468da177	4957	*/
<>	161:2cc1468da177	4958	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
<>	161:2cc1468da177	4959	{
<>	161:2cc1468da177	4960	SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
<>	161:2cc1468da177	4961	}
<>	161:2cc1468da177	4962
<>	161:2cc1468da177	4963	/**
<>	161:2cc1468da177	4964	* @brief Disable LSI ready interrupt
<>	161:2cc1468da177	4965	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
<>	161:2cc1468da177	4966	* @retval None
<>	161:2cc1468da177	4967	*/
<>	161:2cc1468da177	4968	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
<>	161:2cc1468da177	4969	{
<>	161:2cc1468da177	4970	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	161:2cc1468da177	4971	}
<>	161:2cc1468da177	4972
<>	161:2cc1468da177	4973	/**
<>	161:2cc1468da177	4974	* @brief Disable LSE ready interrupt
<>	161:2cc1468da177	4975	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
<>	161:2cc1468da177	4976	* @retval None
<>	161:2cc1468da177	4977	*/
<>	161:2cc1468da177	4978	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
<>	161:2cc1468da177	4979	{
<>	161:2cc1468da177	4980	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	161:2cc1468da177	4981	}
<>	161:2cc1468da177	4982
<>	161:2cc1468da177	4983	/**
<>	161:2cc1468da177	4984	* @brief Disable HSI ready interrupt
<>	161:2cc1468da177	4985	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
<>	161:2cc1468da177	4986	* @retval None
<>	161:2cc1468da177	4987	*/
<>	161:2cc1468da177	4988	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
<>	161:2cc1468da177	4989	{
<>	161:2cc1468da177	4990	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	161:2cc1468da177	4991	}
<>	161:2cc1468da177	4992
<>	161:2cc1468da177	4993	/**
<>	161:2cc1468da177	4994	* @brief Disable HSE ready interrupt
<>	161:2cc1468da177	4995	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
<>	161:2cc1468da177	4996	* @retval None
<>	161:2cc1468da177	4997	*/
<>	161:2cc1468da177	4998	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
<>	161:2cc1468da177	4999	{
<>	161:2cc1468da177	5000	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	161:2cc1468da177	5001	}
<>	161:2cc1468da177	5002
<>	161:2cc1468da177	5003	/**
<>	161:2cc1468da177	5004	* @brief Disable PLL ready interrupt
<>	161:2cc1468da177	5005	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
<>	161:2cc1468da177	5006	* @retval None
<>	161:2cc1468da177	5007	*/
<>	161:2cc1468da177	5008	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
<>	161:2cc1468da177	5009	{
<>	161:2cc1468da177	5010	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	161:2cc1468da177	5011	}
<>	161:2cc1468da177	5012
<>	161:2cc1468da177	5013	/**
<>	161:2cc1468da177	5014	* @brief Disable PLLI2S ready interrupt
<>	161:2cc1468da177	5015	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
<>	161:2cc1468da177	5016	* @retval None
<>	161:2cc1468da177	5017	*/
<>	161:2cc1468da177	5018	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
<>	161:2cc1468da177	5019	{
<>	161:2cc1468da177	5020	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
<>	161:2cc1468da177	5021	}
<>	161:2cc1468da177	5022
<>	161:2cc1468da177	5023	/**
<>	161:2cc1468da177	5024	* @brief Disable PLLSAI ready interrupt
<>	161:2cc1468da177	5025	* @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
<>	161:2cc1468da177	5026	* @retval None
<>	161:2cc1468da177	5027	*/
<>	161:2cc1468da177	5028	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
<>	161:2cc1468da177	5029	{
<>	161:2cc1468da177	5030	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
<>	161:2cc1468da177	5031	}
<>	161:2cc1468da177	5032
<>	161:2cc1468da177	5033	/**
<>	161:2cc1468da177	5034	* @brief Checks if LSI ready interrupt source is enabled or disabled.
<>	161:2cc1468da177	5035	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
<>	161:2cc1468da177	5036	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	5037	*/
<>	161:2cc1468da177	5038	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
<>	161:2cc1468da177	5039	{
<>	161:2cc1468da177	5040	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
<>	161:2cc1468da177	5041	}
<>	161:2cc1468da177	5042
<>	161:2cc1468da177	5043	/**
<>	161:2cc1468da177	5044	* @brief Checks if LSE ready interrupt source is enabled or disabled.
<>	161:2cc1468da177	5045	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
<>	161:2cc1468da177	5046	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	5047	*/
<>	161:2cc1468da177	5048	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
<>	161:2cc1468da177	5049	{
<>	161:2cc1468da177	5050	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
<>	161:2cc1468da177	5051	}
<>	161:2cc1468da177	5052
<>	161:2cc1468da177	5053	/**
<>	161:2cc1468da177	5054	* @brief Checks if HSI ready interrupt source is enabled or disabled.
<>	161:2cc1468da177	5055	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
<>	161:2cc1468da177	5056	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	5057	*/
<>	161:2cc1468da177	5058	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
<>	161:2cc1468da177	5059	{
<>	161:2cc1468da177	5060	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
<>	161:2cc1468da177	5061	}
<>	161:2cc1468da177	5062
<>	161:2cc1468da177	5063	/**
<>	161:2cc1468da177	5064	* @brief Checks if HSE ready interrupt source is enabled or disabled.
<>	161:2cc1468da177	5065	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
<>	161:2cc1468da177	5066	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	5067	*/
<>	161:2cc1468da177	5068	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
<>	161:2cc1468da177	5069	{
<>	161:2cc1468da177	5070	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
<>	161:2cc1468da177	5071	}
<>	161:2cc1468da177	5072
<>	161:2cc1468da177	5073	/**
<>	161:2cc1468da177	5074	* @brief Checks if PLL ready interrupt source is enabled or disabled.
<>	161:2cc1468da177	5075	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
<>	161:2cc1468da177	5076	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	5077	*/
<>	161:2cc1468da177	5078	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
<>	161:2cc1468da177	5079	{
<>	161:2cc1468da177	5080	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
<>	161:2cc1468da177	5081	}
<>	161:2cc1468da177	5082
<>	161:2cc1468da177	5083	/**
<>	161:2cc1468da177	5084	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
<>	161:2cc1468da177	5085	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
<>	161:2cc1468da177	5086	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	5087	*/
<>	161:2cc1468da177	5088	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
<>	161:2cc1468da177	5089	{
<>	161:2cc1468da177	5090	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
<>	161:2cc1468da177	5091	}
<>	161:2cc1468da177	5092
<>	161:2cc1468da177	5093	/**
<>	161:2cc1468da177	5094	* @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
<>	161:2cc1468da177	5095	* @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
<>	161:2cc1468da177	5096	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	5097	*/
<>	161:2cc1468da177	5098	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
<>	161:2cc1468da177	5099	{
<>	161:2cc1468da177	5100	return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
<>	161:2cc1468da177	5101	}
<>	161:2cc1468da177	5102
<>	161:2cc1468da177	5103	/**
<>	161:2cc1468da177	5104	* @}
<>	161:2cc1468da177	5105	*/
<>	161:2cc1468da177	5106
<>	161:2cc1468da177	5107	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	5108	/** @defgroup RCC_LL_EF_Init De-initialization function
<>	161:2cc1468da177	5109	* @{
<>	161:2cc1468da177	5110	*/
<>	161:2cc1468da177	5111	ErrorStatus LL_RCC_DeInit(void);
<>	161:2cc1468da177	5112	/**
<>	161:2cc1468da177	5113	* @}
<>	161:2cc1468da177	5114	*/
<>	161:2cc1468da177	5115
<>	161:2cc1468da177	5116	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
<>	161:2cc1468da177	5117	* @{
<>	161:2cc1468da177	5118	*/
<>	161:2cc1468da177	5119	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
<>	161:2cc1468da177	5120	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
<>	161:2cc1468da177	5121	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
<>	161:2cc1468da177	5122	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
<>	161:2cc1468da177	5123	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
<>	161:2cc1468da177	5124	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
<>	161:2cc1468da177	5125	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
<>	161:2cc1468da177	5126	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
<>	161:2cc1468da177	5127	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
<>	161:2cc1468da177	5128	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	5129	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
<>	161:2cc1468da177	5130	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
<>	161:2cc1468da177	5131	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	5132	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
<>	161:2cc1468da177	5133	#if defined(CEC)
<>	161:2cc1468da177	5134	uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
<>	161:2cc1468da177	5135	#endif /* CEC */
<>	161:2cc1468da177	5136	#if defined(LTDC)
<>	161:2cc1468da177	5137	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
<>	161:2cc1468da177	5138	#endif /* LTDC */
<>	161:2cc1468da177	5139	#if defined(SPDIFRX)
<>	161:2cc1468da177	5140	uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
<>	161:2cc1468da177	5141	#endif /* SPDIFRX */
<>	161:2cc1468da177	5142	#if defined(DSI)
<>	161:2cc1468da177	5143	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
<>	161:2cc1468da177	5144	#endif /* DSI */
<>	161:2cc1468da177	5145	/**
<>	161:2cc1468da177	5146	* @}
<>	161:2cc1468da177	5147	*/
<>	161:2cc1468da177	5148	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	5149
<>	161:2cc1468da177	5150	/**
<>	161:2cc1468da177	5151	* @}
<>	161:2cc1468da177	5152	*/
<>	161:2cc1468da177	5153
<>	161:2cc1468da177	5154	/**
<>	161:2cc1468da177	5155	* @}
<>	161:2cc1468da177	5156	*/
<>	161:2cc1468da177	5157
<>	161:2cc1468da177	5158	#endif /* defined(RCC) */
<>	161:2cc1468da177	5159
<>	161:2cc1468da177	5160	/**
<>	161:2cc1468da177	5161	* @}
<>	161:2cc1468da177	5162	*/
<>	161:2cc1468da177	5163
<>	161:2cc1468da177	5164	#ifdef __cplusplus
<>	161:2cc1468da177	5165	}
<>	161:2cc1468da177	5166	#endif
<>	161:2cc1468da177	5167
<>	161:2cc1468da177	5168	#endif /* __STM32F7xx_LL_RCC_H */
<>	161:2cc1468da177	5169
<>	161:2cc1468da177	5170	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/