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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_lptim.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief Header file of LPTIM LL module.
<>	161:2cc1468da177	8	******************************************************************************
<>	161:2cc1468da177	9	* @attention
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	12	*
<>	161:2cc1468da177	13	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	14	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	18	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	19	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	21	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	22	* without specific prior written permission.
<>	161:2cc1468da177	23	*
<>	161:2cc1468da177	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	34	*
<>	161:2cc1468da177	35	******************************************************************************
<>	161:2cc1468da177	36	*/
<>	161:2cc1468da177	37
<>	161:2cc1468da177	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	39	#ifndef __STM32F7xx_LL_LPTIM_H
<>	161:2cc1468da177	40	#define __STM32F7xx_LL_LPTIM_H
<>	161:2cc1468da177	41
<>	161:2cc1468da177	42	#ifdef __cplusplus
<>	161:2cc1468da177	43	extern "C" {
<>	161:2cc1468da177	44	#endif
<>	161:2cc1468da177	45
<>	161:2cc1468da177	46	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	47	#include "stm32f7xx.h"
<>	161:2cc1468da177	48
<>	161:2cc1468da177	49	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	50	* @{
<>	161:2cc1468da177	51	*/
<>	161:2cc1468da177	52	#if defined (LPTIM1)
<>	161:2cc1468da177	53
<>	161:2cc1468da177	54	/** @defgroup LPTIM_LL LPTIM
<>	161:2cc1468da177	55	* @{
<>	161:2cc1468da177	56	*/
<>	161:2cc1468da177	57
<>	161:2cc1468da177	58	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	59	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	60
<>	161:2cc1468da177	61	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	62
<>	161:2cc1468da177	63	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	64	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	65	/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
<>	161:2cc1468da177	66	* @{
<>	161:2cc1468da177	67	*/
<>	161:2cc1468da177	68	/**
<>	161:2cc1468da177	69	* @}
<>	161:2cc1468da177	70	*/
<>	161:2cc1468da177	71	#endif /USE_FULL_LL_DRIVER/
<>	161:2cc1468da177	72
<>	161:2cc1468da177	73	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	74	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	75	/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
<>	161:2cc1468da177	76	* @{
<>	161:2cc1468da177	77	*/
<>	161:2cc1468da177	78
<>	161:2cc1468da177	79	/**
<>	161:2cc1468da177	80	* @brief LPTIM Init structure definition
<>	161:2cc1468da177	81	*/
<>	161:2cc1468da177	82	typedef struct
<>	161:2cc1468da177	83	{
<>	161:2cc1468da177	84	uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
<>	161:2cc1468da177	85	This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
<>	161:2cc1468da177	86
<>	161:2cc1468da177	87	This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
<>	161:2cc1468da177	88
<>	161:2cc1468da177	89	uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
<>	161:2cc1468da177	90	This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
<>	161:2cc1468da177	91
<>	161:2cc1468da177	92	This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
<>	161:2cc1468da177	93
<>	161:2cc1468da177	94	uint32_t Waveform; /*!< Specifies the waveform shape.
<>	161:2cc1468da177	95	This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
<>	161:2cc1468da177	96
<>	161:2cc1468da177	97	This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
<>	161:2cc1468da177	98
<>	161:2cc1468da177	99	uint32_t Polarity; /*!< Specifies waveform polarity.
<>	161:2cc1468da177	100	This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
<>	161:2cc1468da177	101
<>	161:2cc1468da177	102	This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
<>	161:2cc1468da177	103	} LL_LPTIM_InitTypeDef;
<>	161:2cc1468da177	104
<>	161:2cc1468da177	105	/**
<>	161:2cc1468da177	106	* @}
<>	161:2cc1468da177	107	*/
<>	161:2cc1468da177	108	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	109
<>	161:2cc1468da177	110	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	111	/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
<>	161:2cc1468da177	112	* @{
<>	161:2cc1468da177	113	*/
<>	161:2cc1468da177	114
<>	161:2cc1468da177	115	/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
<>	161:2cc1468da177	116	* @brief Flags defines which can be used with LL_LPTIM_ReadReg function
<>	161:2cc1468da177	117	* @{
<>	161:2cc1468da177	118	*/
<>	161:2cc1468da177	119	#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /!< Compare match /
<>	161:2cc1468da177	120	#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /!< Autoreload match /
<>	161:2cc1468da177	121	#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /!< External trigger edge event /
<>	161:2cc1468da177	122	#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /!< Compare register update OK /
<>	161:2cc1468da177	123	#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /!< Autoreload register update OK /
<>	161:2cc1468da177	124	#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /!< Counter direction change down to up /
<>	161:2cc1468da177	125	#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /!< Counter direction change up to down /
<>	161:2cc1468da177	126	/**
<>	161:2cc1468da177	127	* @}
<>	161:2cc1468da177	128	*/
<>	161:2cc1468da177	129
<>	161:2cc1468da177	130	/** @defgroup LPTIM_LL_EC_IT IT Defines
<>	161:2cc1468da177	131	* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
<>	161:2cc1468da177	132	* @{
<>	161:2cc1468da177	133	*/
<>	161:2cc1468da177	134	#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /!< Compare match Interrupt Enable /
<>	161:2cc1468da177	135	#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /!< Autoreload match Interrupt Enable /
<>	161:2cc1468da177	136	#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /!< External trigger valid edge Interrupt Enable /
<>	161:2cc1468da177	137	#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /!< Compare register update OK Interrupt Enable /
<>	161:2cc1468da177	138	#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /!< Autoreload register update OK Interrupt Enable /
<>	161:2cc1468da177	139	#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /!< Direction change to UP Interrupt Enable /
<>	161:2cc1468da177	140	#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /!< Direction change to down Interrupt Enable /
<>	161:2cc1468da177	141	/**
<>	161:2cc1468da177	142	* @}
<>	161:2cc1468da177	143	*/
<>	161:2cc1468da177	144
<>	161:2cc1468da177	145	/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
<>	161:2cc1468da177	146	* @{
<>	161:2cc1468da177	147	*/
<>	161:2cc1468da177	148	#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /!<LP Timer starts in continuous mode/
<>	161:2cc1468da177	149	#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /!<LP Tilmer starts in single mode/
<>	161:2cc1468da177	150	/**
<>	161:2cc1468da177	151	* @}
<>	161:2cc1468da177	152	*/
<>	161:2cc1468da177	153
<>	161:2cc1468da177	154	/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
<>	161:2cc1468da177	155	* @{
<>	161:2cc1468da177	156	*/
<>	161:2cc1468da177	157	#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /!<Preload is disabled: registers are updated after each APB bus write access/
<>	161:2cc1468da177	158	#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /!<preload is enabled: registers are updated at the end of the current LPTIM period/
<>	161:2cc1468da177	159	/**
<>	161:2cc1468da177	160	* @}
<>	161:2cc1468da177	161	*/
<>	161:2cc1468da177	162
<>	161:2cc1468da177	163	/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
<>	161:2cc1468da177	164	* @{
<>	161:2cc1468da177	165	*/
<>	161:2cc1468da177	166	#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /!<The counter is incremented following each internal clock pulse/
<>	161:2cc1468da177	167	#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /!<The counter is incremented following each valid clock pulse on the LPTIM external Input1/
<>	161:2cc1468da177	168	/**
<>	161:2cc1468da177	169	* @}
<>	161:2cc1468da177	170	*/
<>	161:2cc1468da177	171
<>	161:2cc1468da177	172	/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
<>	161:2cc1468da177	173	* @{
<>	161:2cc1468da177	174	*/
<>	161:2cc1468da177	175	#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE/
<>	161:2cc1468da177	176	#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /!<LPTIM generates a Set Once waveform/
<>	161:2cc1468da177	177	/**
<>	161:2cc1468da177	178	* @}
<>	161:2cc1468da177	179	*/
<>	161:2cc1468da177	180
<>	161:2cc1468da177	181	/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
<>	161:2cc1468da177	182	* @{
<>	161:2cc1468da177	183	*/
<>	161:2cc1468da177	184	#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers/
<>	161:2cc1468da177	185	#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers/
<>	161:2cc1468da177	186	/**
<>	161:2cc1468da177	187	* @}
<>	161:2cc1468da177	188	*/
<>	161:2cc1468da177	189
<>	161:2cc1468da177	190	/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
<>	161:2cc1468da177	191	* @{
<>	161:2cc1468da177	192	*/
<>	161:2cc1468da177	193	#define LL_LPTIM_PRESCALER_DIV1 0x00000000U /!<Prescaler division factor is set to 1/
<>	161:2cc1468da177	194	#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /!<Prescaler division factor is set to 2/
<>	161:2cc1468da177	195	#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /!<Prescaler division factor is set to 4/
<>	161:2cc1468da177	196	#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 \| LPTIM_CFGR_PRESC_0) /!<Prescaler division factor is set to 8/
<>	161:2cc1468da177	197	#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /!<Prescaler division factor is set to 16/
<>	161:2cc1468da177	198	#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 \| LPTIM_CFGR_PRESC_0) /!<Prescaler division factor is set to 32/
<>	161:2cc1468da177	199	#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 \| LPTIM_CFGR_PRESC_1) /!<Prescaler division factor is set to 64/
<>	161:2cc1468da177	200	#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /!<Prescaler division factor is set to 128/
<>	161:2cc1468da177	201	/**
<>	161:2cc1468da177	202	* @}
<>	161:2cc1468da177	203	*/
<>	161:2cc1468da177	204
<>	161:2cc1468da177	205	/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
<>	161:2cc1468da177	206	* @{
<>	161:2cc1468da177	207	*/
<>	161:2cc1468da177	208	#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /!<External input trigger is connected to TIMx_ETR input/
<>	161:2cc1468da177	209	#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /!<External input trigger is connected to RTC Alarm A/
<>	161:2cc1468da177	210	#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /!<External input trigger is connected to RTC Alarm B/
<>	161:2cc1468da177	211	#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 \| LPTIM_CFGR_TRIGSEL_0) /!<External input trigger is connected to RTC Tamper 1/
<>	161:2cc1468da177	212	#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /!<External input trigger is connected to RTC Tamper 2/
<>	161:2cc1468da177	213	#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 \| LPTIM_CFGR_TRIGSEL_0) /!<External input trigger is connected to RTC Tamper 3/
<>	161:2cc1468da177	214	#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 \| LPTIM_CFGR_TRIGSEL_1) /!<External input trigger is connected to COMP1 output/
<>	161:2cc1468da177	215	#define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /!<External input trigger is connected to COMP2 output/
<>	161:2cc1468da177	216	/**
<>	161:2cc1468da177	217	* @}
<>	161:2cc1468da177	218	*/
<>	161:2cc1468da177	219
<>	161:2cc1468da177	220	/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
<>	161:2cc1468da177	221	* @{
<>	161:2cc1468da177	222	*/
<>	161:2cc1468da177	223	#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /!<Any trigger active level change is considered as a valid trigger/
<>	161:2cc1468da177	224	#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger/
<>	161:2cc1468da177	225	#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger/
<>	161:2cc1468da177	226	#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger/
<>	161:2cc1468da177	227	/**
<>	161:2cc1468da177	228	* @}
<>	161:2cc1468da177	229	*/
<>	161:2cc1468da177	230
<>	161:2cc1468da177	231	/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
<>	161:2cc1468da177	232	* @{
<>	161:2cc1468da177	233	*/
<>	161:2cc1468da177	234	#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /!<LPTIM counter starts when a rising edge is detected/
<>	161:2cc1468da177	235	#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /!<LPTIM counter starts when a falling edge is detected/
<>	161:2cc1468da177	236	#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /!<LPTIM counter starts when a rising or a falling edge is detected/
<>	161:2cc1468da177	237	/**
<>	161:2cc1468da177	238	* @}
<>	161:2cc1468da177	239	*/
<>	161:2cc1468da177	240
<>	161:2cc1468da177	241	/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
<>	161:2cc1468da177	242	* @{
<>	161:2cc1468da177	243	*/
<>	161:2cc1468da177	244	#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)/
<>	161:2cc1468da177	245	#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /!<LPTIM is clocked by an external clock source through the LPTIM external Input1/
<>	161:2cc1468da177	246	/**
<>	161:2cc1468da177	247	* @}
<>	161:2cc1468da177	248	*/
<>	161:2cc1468da177	249
<>	161:2cc1468da177	250	/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
<>	161:2cc1468da177	251	* @{
<>	161:2cc1468da177	252	*/
<>	161:2cc1468da177	253	#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /!<Any external clock signal level change is considered as a valid transition/
<>	161:2cc1468da177	254	#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition/
<>	161:2cc1468da177	255	#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition/
<>	161:2cc1468da177	256	#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition/
<>	161:2cc1468da177	257	/**
<>	161:2cc1468da177	258	* @}
<>	161:2cc1468da177	259	*/
<>	161:2cc1468da177	260
<>	161:2cc1468da177	261	/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
<>	161:2cc1468da177	262	* @{
<>	161:2cc1468da177	263	*/
<>	161:2cc1468da177	264	#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /!< The rising edge is the active edge used for counting/
<>	161:2cc1468da177	265	#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /!< The falling edge is the active edge used for counting/
<>	161:2cc1468da177	266	#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /!< Both edges are active edges/
<>	161:2cc1468da177	267	/**
<>	161:2cc1468da177	268	* @}
<>	161:2cc1468da177	269	*/
<>	161:2cc1468da177	270
<>	161:2cc1468da177	271	/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
<>	161:2cc1468da177	272	* @{
<>	161:2cc1468da177	273	*/
<>	161:2cc1468da177	274	#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /!< The rising edge is the active edge used for counting/
<>	161:2cc1468da177	275	#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /!< The falling edge is the active edge used for counting/
<>	161:2cc1468da177	276	#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /!< Both edges are active edges/
<>	161:2cc1468da177	277	/**
<>	161:2cc1468da177	278	* @}
<>	161:2cc1468da177	279	*/
<>	161:2cc1468da177	280
<>	161:2cc1468da177	281
<>	161:2cc1468da177	282	/**
<>	161:2cc1468da177	283	* @}
<>	161:2cc1468da177	284	*/
<>	161:2cc1468da177	285
<>	161:2cc1468da177	286	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	287	/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
<>	161:2cc1468da177	288	* @{
<>	161:2cc1468da177	289	*/
<>	161:2cc1468da177	290
<>	161:2cc1468da177	291	/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
<>	161:2cc1468da177	292	* @{
<>	161:2cc1468da177	293	*/
<>	161:2cc1468da177	294
<>	161:2cc1468da177	295	/**
<>	161:2cc1468da177	296	* @brief Write a value in LPTIM register
<>	161:2cc1468da177	297	* @param __INSTANCE__ LPTIM Instance
<>	161:2cc1468da177	298	* @param __REG__ Register to be written
<>	161:2cc1468da177	299	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	300	* @retval None
<>	161:2cc1468da177	301	*/
<>	161:2cc1468da177	302	#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	161:2cc1468da177	303
<>	161:2cc1468da177	304	/**
<>	161:2cc1468da177	305	* @brief Read a value in LPTIM register
<>	161:2cc1468da177	306	* @param __INSTANCE__ LPTIM Instance
<>	161:2cc1468da177	307	* @param __REG__ Register to be read
<>	161:2cc1468da177	308	* @retval Register value
<>	161:2cc1468da177	309	*/
<>	161:2cc1468da177	310	#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	161:2cc1468da177	311	/**
<>	161:2cc1468da177	312	* @}
<>	161:2cc1468da177	313	*/
<>	161:2cc1468da177	314
<>	161:2cc1468da177	315	/**
<>	161:2cc1468da177	316	* @}
<>	161:2cc1468da177	317	*/
<>	161:2cc1468da177	318
<>	161:2cc1468da177	319
<>	161:2cc1468da177	320	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	321	/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
<>	161:2cc1468da177	322	* @{
<>	161:2cc1468da177	323	*/
<>	161:2cc1468da177	324
<>	161:2cc1468da177	325	/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
<>	161:2cc1468da177	326	* @{
<>	161:2cc1468da177	327	*/
<>	161:2cc1468da177	328
<>	161:2cc1468da177	329	/**
<>	161:2cc1468da177	330	* @brief Enable the LPTIM instance
<>	161:2cc1468da177	331	* @note After setting the ENABLE bit, a delay of two counter clock is needed
<>	161:2cc1468da177	332	* before the LPTIM instance is actually enabled.
<>	161:2cc1468da177	333	* @rmtoll CR ENABLE LL_LPTIM_Enable
<>	161:2cc1468da177	334	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	335	* @retval None
<>	161:2cc1468da177	336	*/
<>	161:2cc1468da177	337	__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	338	{
<>	161:2cc1468da177	339	SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
<>	161:2cc1468da177	340	}
<>	161:2cc1468da177	341
<>	161:2cc1468da177	342	/**
<>	161:2cc1468da177	343	* @brief Disable the LPTIM instance
<>	161:2cc1468da177	344	* @rmtoll CR ENABLE LL_LPTIM_Disable
<>	161:2cc1468da177	345	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	346	* @retval None
<>	161:2cc1468da177	347	*/
<>	161:2cc1468da177	348	__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	349	{
<>	161:2cc1468da177	350	CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
<>	161:2cc1468da177	351	}
<>	161:2cc1468da177	352
<>	161:2cc1468da177	353	/**
<>	161:2cc1468da177	354	* @brief Indicates whether the LPTIM instance is enabled.
<>	161:2cc1468da177	355	* @rmtoll CR ENABLE LL_LPTIM_IsEnabled
<>	161:2cc1468da177	356	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	357	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	358	*/
<>	161:2cc1468da177	359	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	360	{
<>	161:2cc1468da177	361	return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
<>	161:2cc1468da177	362	}
<>	161:2cc1468da177	363
<>	161:2cc1468da177	364	/**
<>	161:2cc1468da177	365	* @brief Starts the LPTIM counter in the desired mode.
<>	161:2cc1468da177	366	* @note LPTIM instance must be enabled before starting the counter.
<>	161:2cc1468da177	367	* @note It is possible to change on the fly from One Shot mode to
<>	161:2cc1468da177	368	* Continuous mode.
<>	161:2cc1468da177	369	* @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
<>	161:2cc1468da177	370	* CR SNGSTRT LL_LPTIM_StartCounter
<>	161:2cc1468da177	371	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	372	* @param OperatingMode This parameter can be one of the following values:
<>	161:2cc1468da177	373	* @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
<>	161:2cc1468da177	374	* @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
<>	161:2cc1468da177	375	* @retval None
<>	161:2cc1468da177	376	*/
<>	161:2cc1468da177	377	__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
<>	161:2cc1468da177	378	{
<>	161:2cc1468da177	379	MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT \| LPTIM_CR_SNGSTRT, OperatingMode);
<>	161:2cc1468da177	380	}
<>	161:2cc1468da177	381
<>	161:2cc1468da177	382
<>	161:2cc1468da177	383	/**
<>	161:2cc1468da177	384	* @brief Set the LPTIM registers update mode (enable/disable register preload)
<>	161:2cc1468da177	385	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	386	* @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
<>	161:2cc1468da177	387	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	388	* @param UpdateMode This parameter can be one of the following values:
<>	161:2cc1468da177	389	* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
<>	161:2cc1468da177	390	* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
<>	161:2cc1468da177	391	* @retval None
<>	161:2cc1468da177	392	*/
<>	161:2cc1468da177	393	__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
<>	161:2cc1468da177	394	{
<>	161:2cc1468da177	395	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
<>	161:2cc1468da177	396	}
<>	161:2cc1468da177	397
<>	161:2cc1468da177	398	/**
<>	161:2cc1468da177	399	* @brief Get the LPTIM registers update mode
<>	161:2cc1468da177	400	* @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
<>	161:2cc1468da177	401	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	402	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	403	* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
<>	161:2cc1468da177	404	* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
<>	161:2cc1468da177	405	*/
<>	161:2cc1468da177	406	__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	407	{
<>	161:2cc1468da177	408	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
<>	161:2cc1468da177	409	}
<>	161:2cc1468da177	410
<>	161:2cc1468da177	411	/**
<>	161:2cc1468da177	412	* @brief Set the auto reload value
<>	161:2cc1468da177	413	* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
<>	161:2cc1468da177	414	* @note After a write to the LPTIMx_ARR register a new write operation to the
<>	161:2cc1468da177	415	* same register can only be performed when the previous write operation
<>	161:2cc1468da177	416	* is completed. Any successive write before the ARROK flag be set, will
<>	161:2cc1468da177	417	* lead to unpredictable results.
<>	161:2cc1468da177	418	* @note autoreload value be strictly greater than the compare value.
<>	161:2cc1468da177	419	* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
<>	161:2cc1468da177	420	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	421	* @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	161:2cc1468da177	422	* @retval None
<>	161:2cc1468da177	423	*/
<>	161:2cc1468da177	424	__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
<>	161:2cc1468da177	425	{
<>	161:2cc1468da177	426	MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
<>	161:2cc1468da177	427	}
<>	161:2cc1468da177	428
<>	161:2cc1468da177	429	/**
<>	161:2cc1468da177	430	* @brief Get actual auto reload value
<>	161:2cc1468da177	431	* @rmtoll ARR ARR LL_LPTIM_GetAutoReload
<>	161:2cc1468da177	432	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	433	* @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	161:2cc1468da177	434	*/
<>	161:2cc1468da177	435	__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	436	{
<>	161:2cc1468da177	437	return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
<>	161:2cc1468da177	438	}
<>	161:2cc1468da177	439
<>	161:2cc1468da177	440	/**
<>	161:2cc1468da177	441	* @brief Set the compare value
<>	161:2cc1468da177	442	* @note After a write to the LPTIMx_CMP register a new write operation to the
<>	161:2cc1468da177	443	* same register can only be performed when the previous write operation
<>	161:2cc1468da177	444	* is completed. Any successive write before the CMPOK flag be set, will
<>	161:2cc1468da177	445	* lead to unpredictable results.
<>	161:2cc1468da177	446	* @rmtoll CMP CMP LL_LPTIM_SetCompare
<>	161:2cc1468da177	447	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	448	* @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	161:2cc1468da177	449	* @retval None
<>	161:2cc1468da177	450	*/
<>	161:2cc1468da177	451	__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
<>	161:2cc1468da177	452	{
<>	161:2cc1468da177	453	MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
<>	161:2cc1468da177	454	}
<>	161:2cc1468da177	455
<>	161:2cc1468da177	456	/**
<>	161:2cc1468da177	457	* @brief Get actual compare value
<>	161:2cc1468da177	458	* @rmtoll CMP CMP LL_LPTIM_GetCompare
<>	161:2cc1468da177	459	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	460	* @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
<>	161:2cc1468da177	461	*/
<>	161:2cc1468da177	462	__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	463	{
<>	161:2cc1468da177	464	return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
<>	161:2cc1468da177	465	}
<>	161:2cc1468da177	466
<>	161:2cc1468da177	467	/**
<>	161:2cc1468da177	468	* @brief Get actual counter value
<>	161:2cc1468da177	469	* @note When the LPTIM instance is running with an asynchronous clock, reading
<>	161:2cc1468da177	470	* the LPTIMx_CNT register may return unreliable values. So in this case
<>	161:2cc1468da177	471	* it is necessary to perform two consecutive read accesses and verify
<>	161:2cc1468da177	472	* that the two returned values are identical.
<>	161:2cc1468da177	473	* @rmtoll CNT CNT LL_LPTIM_GetCounter
<>	161:2cc1468da177	474	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	475	* @retval Counter value
<>	161:2cc1468da177	476	*/
<>	161:2cc1468da177	477	__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	478	{
<>	161:2cc1468da177	479	return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
<>	161:2cc1468da177	480	}
<>	161:2cc1468da177	481
<>	161:2cc1468da177	482	/**
<>	161:2cc1468da177	483	* @brief Set the counter mode (selection of the LPTIM counter clock source).
<>	161:2cc1468da177	484	* @note The counter mode can be set only when the LPTIM instance is disabled.
<>	161:2cc1468da177	485	* @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
<>	161:2cc1468da177	486	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	487	* @param CounterMode This parameter can be one of the following values:
<>	161:2cc1468da177	488	* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
<>	161:2cc1468da177	489	* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
<>	161:2cc1468da177	490	* @retval None
<>	161:2cc1468da177	491	*/
<>	161:2cc1468da177	492	__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
<>	161:2cc1468da177	493	{
<>	161:2cc1468da177	494	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
<>	161:2cc1468da177	495	}
<>	161:2cc1468da177	496
<>	161:2cc1468da177	497	/**
<>	161:2cc1468da177	498	* @brief Get the counter mode
<>	161:2cc1468da177	499	* @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
<>	161:2cc1468da177	500	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	501	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	502	* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
<>	161:2cc1468da177	503	* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
<>	161:2cc1468da177	504	*/
<>	161:2cc1468da177	505	__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	506	{
<>	161:2cc1468da177	507	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
<>	161:2cc1468da177	508	}
<>	161:2cc1468da177	509
<>	161:2cc1468da177	510	/**
<>	161:2cc1468da177	511	* @brief Configure the LPTIM instance output (LPTIMx_OUT)
<>	161:2cc1468da177	512	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	513	* @note Regarding the LPTIM output polarity the change takes effect
<>	161:2cc1468da177	514	* immediately, so the output default value will change immediately after
<>	161:2cc1468da177	515	* the polarity is re-configured, even before the timer is enabled.
<>	161:2cc1468da177	516	* @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
<>	161:2cc1468da177	517	* CFGR WAVPOL LL_LPTIM_ConfigOutput
<>	161:2cc1468da177	518	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	519	* @param Waveform This parameter can be one of the following values:
<>	161:2cc1468da177	520	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
<>	161:2cc1468da177	521	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
<>	161:2cc1468da177	522	* @param Polarity This parameter can be one of the following values:
<>	161:2cc1468da177	523	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
<>	161:2cc1468da177	524	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
<>	161:2cc1468da177	525	* @retval None
<>	161:2cc1468da177	526	*/
<>	161:2cc1468da177	527	__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
<>	161:2cc1468da177	528	{
<>	161:2cc1468da177	529	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE \| LPTIM_CFGR_WAVPOL, Waveform \| Polarity);
<>	161:2cc1468da177	530	}
<>	161:2cc1468da177	531
<>	161:2cc1468da177	532	/**
<>	161:2cc1468da177	533	* @brief Set waveform shape
<>	161:2cc1468da177	534	* @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
<>	161:2cc1468da177	535	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	536	* @param Waveform This parameter can be one of the following values:
<>	161:2cc1468da177	537	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
<>	161:2cc1468da177	538	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
<>	161:2cc1468da177	539	* @retval None
<>	161:2cc1468da177	540	*/
<>	161:2cc1468da177	541	__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
<>	161:2cc1468da177	542	{
<>	161:2cc1468da177	543	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
<>	161:2cc1468da177	544	}
<>	161:2cc1468da177	545
<>	161:2cc1468da177	546	/**
<>	161:2cc1468da177	547	* @brief Get actual waveform shape
<>	161:2cc1468da177	548	* @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
<>	161:2cc1468da177	549	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	550	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	551	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
<>	161:2cc1468da177	552	* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
<>	161:2cc1468da177	553	*/
<>	161:2cc1468da177	554	__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	555	{
<>	161:2cc1468da177	556	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
<>	161:2cc1468da177	557	}
<>	161:2cc1468da177	558
<>	161:2cc1468da177	559	/**
<>	161:2cc1468da177	560	* @brief Set output polarity
<>	161:2cc1468da177	561	* @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
<>	161:2cc1468da177	562	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	563	* @param Polarity This parameter can be one of the following values:
<>	161:2cc1468da177	564	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
<>	161:2cc1468da177	565	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
<>	161:2cc1468da177	566	* @retval None
<>	161:2cc1468da177	567	*/
<>	161:2cc1468da177	568	__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
<>	161:2cc1468da177	569	{
<>	161:2cc1468da177	570	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
<>	161:2cc1468da177	571	}
<>	161:2cc1468da177	572
<>	161:2cc1468da177	573	/**
<>	161:2cc1468da177	574	* @brief Get actual output polarity
<>	161:2cc1468da177	575	* @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
<>	161:2cc1468da177	576	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	577	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	578	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
<>	161:2cc1468da177	579	* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
<>	161:2cc1468da177	580	*/
<>	161:2cc1468da177	581	__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	582	{
<>	161:2cc1468da177	583	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
<>	161:2cc1468da177	584	}
<>	161:2cc1468da177	585
<>	161:2cc1468da177	586	/**
<>	161:2cc1468da177	587	* @brief Set actual prescaler division ratio.
<>	161:2cc1468da177	588	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	589	* @note When the LPTIM is configured to be clocked by an internal clock source
<>	161:2cc1468da177	590	* and the LPTIM counter is configured to be updated by active edges
<>	161:2cc1468da177	591	* detected on the LPTIM external Input1, the internal clock provided to
<>	161:2cc1468da177	592	* the LPTIM must be not be prescaled.
<>	161:2cc1468da177	593	* @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
<>	161:2cc1468da177	594	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	595	* @param Prescaler This parameter can be one of the following values:
<>	161:2cc1468da177	596	* @arg @ref LL_LPTIM_PRESCALER_DIV1
<>	161:2cc1468da177	597	* @arg @ref LL_LPTIM_PRESCALER_DIV2
<>	161:2cc1468da177	598	* @arg @ref LL_LPTIM_PRESCALER_DIV4
<>	161:2cc1468da177	599	* @arg @ref LL_LPTIM_PRESCALER_DIV8
<>	161:2cc1468da177	600	* @arg @ref LL_LPTIM_PRESCALER_DIV16
<>	161:2cc1468da177	601	* @arg @ref LL_LPTIM_PRESCALER_DIV32
<>	161:2cc1468da177	602	* @arg @ref LL_LPTIM_PRESCALER_DIV64
<>	161:2cc1468da177	603	* @arg @ref LL_LPTIM_PRESCALER_DIV128
<>	161:2cc1468da177	604	* @retval None
<>	161:2cc1468da177	605	*/
<>	161:2cc1468da177	606	__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
<>	161:2cc1468da177	607	{
<>	161:2cc1468da177	608	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
<>	161:2cc1468da177	609	}
<>	161:2cc1468da177	610
<>	161:2cc1468da177	611	/**
<>	161:2cc1468da177	612	* @brief Get actual prescaler division ratio.
<>	161:2cc1468da177	613	* @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
<>	161:2cc1468da177	614	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	615	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	616	* @arg @ref LL_LPTIM_PRESCALER_DIV1
<>	161:2cc1468da177	617	* @arg @ref LL_LPTIM_PRESCALER_DIV2
<>	161:2cc1468da177	618	* @arg @ref LL_LPTIM_PRESCALER_DIV4
<>	161:2cc1468da177	619	* @arg @ref LL_LPTIM_PRESCALER_DIV8
<>	161:2cc1468da177	620	* @arg @ref LL_LPTIM_PRESCALER_DIV16
<>	161:2cc1468da177	621	* @arg @ref LL_LPTIM_PRESCALER_DIV32
<>	161:2cc1468da177	622	* @arg @ref LL_LPTIM_PRESCALER_DIV64
<>	161:2cc1468da177	623	* @arg @ref LL_LPTIM_PRESCALER_DIV128
<>	161:2cc1468da177	624	*/
<>	161:2cc1468da177	625	__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	626	{
<>	161:2cc1468da177	627	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
<>	161:2cc1468da177	628	}
<>	161:2cc1468da177	629
<>	161:2cc1468da177	630
<>	161:2cc1468da177	631	/**
<>	161:2cc1468da177	632	* @}
<>	161:2cc1468da177	633	*/
<>	161:2cc1468da177	634
<>	161:2cc1468da177	635	/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
<>	161:2cc1468da177	636	* @{
<>	161:2cc1468da177	637	*/
<>	161:2cc1468da177	638
<>	161:2cc1468da177	639	/**
<>	161:2cc1468da177	640	* @brief Enable the timeout function
<>	161:2cc1468da177	641	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	642	* @note The first trigger event will start the timer, any successive trigger
<>	161:2cc1468da177	643	* event will reset the counter and the timer will restart.
<>	161:2cc1468da177	644	* @note The timeout value corresponds to the compare value; if no trigger
<>	161:2cc1468da177	645	* occurs within the expected time frame, the MCU is waked-up by the
<>	161:2cc1468da177	646	* compare match event.
<>	161:2cc1468da177	647	* @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
<>	161:2cc1468da177	648	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	649	* @retval None
<>	161:2cc1468da177	650	*/
<>	161:2cc1468da177	651	__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	652	{
<>	161:2cc1468da177	653	SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
<>	161:2cc1468da177	654	}
<>	161:2cc1468da177	655
<>	161:2cc1468da177	656	/**
<>	161:2cc1468da177	657	* @brief Disable the timeout function
<>	161:2cc1468da177	658	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	659	* @note A trigger event arriving when the timer is already started will be
<>	161:2cc1468da177	660	* ignored.
<>	161:2cc1468da177	661	* @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
<>	161:2cc1468da177	662	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	663	* @retval None
<>	161:2cc1468da177	664	*/
<>	161:2cc1468da177	665	__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	666	{
<>	161:2cc1468da177	667	CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
<>	161:2cc1468da177	668	}
<>	161:2cc1468da177	669
<>	161:2cc1468da177	670	/**
<>	161:2cc1468da177	671	* @brief Indicate whether the timeout function is enabled.
<>	161:2cc1468da177	672	* @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
<>	161:2cc1468da177	673	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	674	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	675	*/
<>	161:2cc1468da177	676	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	677	{
<>	161:2cc1468da177	678	return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
<>	161:2cc1468da177	679	}
<>	161:2cc1468da177	680
<>	161:2cc1468da177	681	/**
<>	161:2cc1468da177	682	* @brief Start the LPTIM counter
<>	161:2cc1468da177	683	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	684	* @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
<>	161:2cc1468da177	685	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	686	* @retval None
<>	161:2cc1468da177	687	*/
<>	161:2cc1468da177	688	__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	689	{
<>	161:2cc1468da177	690	CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
<>	161:2cc1468da177	691	}
<>	161:2cc1468da177	692
<>	161:2cc1468da177	693	/**
<>	161:2cc1468da177	694	* @brief Configure the external trigger used as a trigger event for the LPTIM.
<>	161:2cc1468da177	695	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	696	* @note An internal clock source must be present when a digital filter is
<>	161:2cc1468da177	697	* required for the trigger.
<>	161:2cc1468da177	698	* @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
<>	161:2cc1468da177	699	* CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
<>	161:2cc1468da177	700	* CFGR TRIGEN LL_LPTIM_ConfigTrigger
<>	161:2cc1468da177	701	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	702	* @param Source This parameter can be one of the following values:
<>	161:2cc1468da177	703	* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
<>	161:2cc1468da177	704	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
<>	161:2cc1468da177	705	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
<>	161:2cc1468da177	706	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
<>	161:2cc1468da177	707	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
<>	161:2cc1468da177	708	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
<>	161:2cc1468da177	709	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
<>	161:2cc1468da177	710	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
<>	161:2cc1468da177	711	* @param Filter This parameter can be one of the following values:
<>	161:2cc1468da177	712	* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
<>	161:2cc1468da177	713	* @arg @ref LL_LPTIM_TRIG_FILTER_2
<>	161:2cc1468da177	714	* @arg @ref LL_LPTIM_TRIG_FILTER_4
<>	161:2cc1468da177	715	* @arg @ref LL_LPTIM_TRIG_FILTER_8
<>	161:2cc1468da177	716	* @param Polarity This parameter can be one of the following values:
<>	161:2cc1468da177	717	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
<>	161:2cc1468da177	718	* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
<>	161:2cc1468da177	719	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
<>	161:2cc1468da177	720	* @retval None
<>	161:2cc1468da177	721	*/
<>	161:2cc1468da177	722	__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
<>	161:2cc1468da177	723	{
<>	161:2cc1468da177	724	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL \| LPTIM_CFGR_TRGFLT \| LPTIM_CFGR_TRIGEN, Source \| Filter \| Polarity);
<>	161:2cc1468da177	725	}
<>	161:2cc1468da177	726
<>	161:2cc1468da177	727	/**
<>	161:2cc1468da177	728	* @brief Get actual external trigger source.
<>	161:2cc1468da177	729	* @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
<>	161:2cc1468da177	730	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	731	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	732	* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
<>	161:2cc1468da177	733	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
<>	161:2cc1468da177	734	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
<>	161:2cc1468da177	735	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
<>	161:2cc1468da177	736	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
<>	161:2cc1468da177	737	* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
<>	161:2cc1468da177	738	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
<>	161:2cc1468da177	739	* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
<>	161:2cc1468da177	740	*/
<>	161:2cc1468da177	741	__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	742	{
<>	161:2cc1468da177	743	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
<>	161:2cc1468da177	744	}
<>	161:2cc1468da177	745
<>	161:2cc1468da177	746	/**
<>	161:2cc1468da177	747	* @brief Get actual external trigger filter.
<>	161:2cc1468da177	748	* @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
<>	161:2cc1468da177	749	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	750	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	751	* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
<>	161:2cc1468da177	752	* @arg @ref LL_LPTIM_TRIG_FILTER_2
<>	161:2cc1468da177	753	* @arg @ref LL_LPTIM_TRIG_FILTER_4
<>	161:2cc1468da177	754	* @arg @ref LL_LPTIM_TRIG_FILTER_8
<>	161:2cc1468da177	755	*/
<>	161:2cc1468da177	756	__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	757	{
<>	161:2cc1468da177	758	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
<>	161:2cc1468da177	759	}
<>	161:2cc1468da177	760
<>	161:2cc1468da177	761	/**
<>	161:2cc1468da177	762	* @brief Get actual external trigger polarity.
<>	161:2cc1468da177	763	* @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
<>	161:2cc1468da177	764	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	765	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	766	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
<>	161:2cc1468da177	767	* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
<>	161:2cc1468da177	768	* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
<>	161:2cc1468da177	769	*/
<>	161:2cc1468da177	770	__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	771	{
<>	161:2cc1468da177	772	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
<>	161:2cc1468da177	773	}
<>	161:2cc1468da177	774
<>	161:2cc1468da177	775	/**
<>	161:2cc1468da177	776	* @}
<>	161:2cc1468da177	777	*/
<>	161:2cc1468da177	778
<>	161:2cc1468da177	779	/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
<>	161:2cc1468da177	780	* @{
<>	161:2cc1468da177	781	*/
<>	161:2cc1468da177	782
<>	161:2cc1468da177	783	/**
<>	161:2cc1468da177	784	* @brief Set the source of the clock used by the LPTIM instance.
<>	161:2cc1468da177	785	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	786	* @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
<>	161:2cc1468da177	787	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	788	* @param ClockSource This parameter can be one of the following values:
<>	161:2cc1468da177	789	* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
<>	161:2cc1468da177	790	* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
<>	161:2cc1468da177	791	* @retval None
<>	161:2cc1468da177	792	*/
<>	161:2cc1468da177	793	__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
<>	161:2cc1468da177	794	{
<>	161:2cc1468da177	795	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
<>	161:2cc1468da177	796	}
<>	161:2cc1468da177	797
<>	161:2cc1468da177	798	/**
<>	161:2cc1468da177	799	* @brief Get actual LPTIM instance clock source.
<>	161:2cc1468da177	800	* @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
<>	161:2cc1468da177	801	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	802	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	803	* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
<>	161:2cc1468da177	804	* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
<>	161:2cc1468da177	805	*/
<>	161:2cc1468da177	806	__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	807	{
<>	161:2cc1468da177	808	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
<>	161:2cc1468da177	809	}
<>	161:2cc1468da177	810
<>	161:2cc1468da177	811	/**
<>	161:2cc1468da177	812	* @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
<>	161:2cc1468da177	813	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	814	* @note When both external clock signal edges are considered active ones,
<>	161:2cc1468da177	815	* the LPTIM must also be clocked by an internal clock source with a
<>	161:2cc1468da177	816	* frequency equal to at least four times the external clock frequency.
<>	161:2cc1468da177	817	* @note An internal clock source must be present when a digital filter is
<>	161:2cc1468da177	818	* required for external clock.
<>	161:2cc1468da177	819	* @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
<>	161:2cc1468da177	820	* CFGR CKPOL LL_LPTIM_ConfigClock
<>	161:2cc1468da177	821	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	822	* @param ClockFilter This parameter can be one of the following values:
<>	161:2cc1468da177	823	* @arg @ref LL_LPTIM_CLK_FILTER_NONE
<>	161:2cc1468da177	824	* @arg @ref LL_LPTIM_CLK_FILTER_2
<>	161:2cc1468da177	825	* @arg @ref LL_LPTIM_CLK_FILTER_4
<>	161:2cc1468da177	826	* @arg @ref LL_LPTIM_CLK_FILTER_8
<>	161:2cc1468da177	827	* @param ClockPolarity This parameter can be one of the following values:
<>	161:2cc1468da177	828	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
<>	161:2cc1468da177	829	* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
<>	161:2cc1468da177	830	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
<>	161:2cc1468da177	831	* @retval None
<>	161:2cc1468da177	832	*/
<>	161:2cc1468da177	833	__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
<>	161:2cc1468da177	834	{
<>	161:2cc1468da177	835	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT \| LPTIM_CFGR_CKPOL, ClockFilter \| ClockPolarity);
<>	161:2cc1468da177	836	}
<>	161:2cc1468da177	837
<>	161:2cc1468da177	838	/**
<>	161:2cc1468da177	839	* @brief Get actual clock polarity
<>	161:2cc1468da177	840	* @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
<>	161:2cc1468da177	841	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	842	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	843	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
<>	161:2cc1468da177	844	* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
<>	161:2cc1468da177	845	* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
<>	161:2cc1468da177	846	*/
<>	161:2cc1468da177	847	__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	848	{
<>	161:2cc1468da177	849	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
<>	161:2cc1468da177	850	}
<>	161:2cc1468da177	851
<>	161:2cc1468da177	852	/**
<>	161:2cc1468da177	853	* @brief Get actual clock digital filter
<>	161:2cc1468da177	854	* @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
<>	161:2cc1468da177	855	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	856	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	857	* @arg @ref LL_LPTIM_CLK_FILTER_NONE
<>	161:2cc1468da177	858	* @arg @ref LL_LPTIM_CLK_FILTER_2
<>	161:2cc1468da177	859	* @arg @ref LL_LPTIM_CLK_FILTER_4
<>	161:2cc1468da177	860	* @arg @ref LL_LPTIM_CLK_FILTER_8
<>	161:2cc1468da177	861	*/
<>	161:2cc1468da177	862	__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	863	{
<>	161:2cc1468da177	864	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
<>	161:2cc1468da177	865	}
<>	161:2cc1468da177	866
<>	161:2cc1468da177	867	/**
<>	161:2cc1468da177	868	* @}
<>	161:2cc1468da177	869	*/
<>	161:2cc1468da177	870
<>	161:2cc1468da177	871	/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
<>	161:2cc1468da177	872	* @{
<>	161:2cc1468da177	873	*/
<>	161:2cc1468da177	874
<>	161:2cc1468da177	875	/**
<>	161:2cc1468da177	876	* @brief Configure the encoder mode.
<>	161:2cc1468da177	877	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	878	* @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
<>	161:2cc1468da177	879	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	880	* @param EncoderMode This parameter can be one of the following values:
<>	161:2cc1468da177	881	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
<>	161:2cc1468da177	882	* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
<>	161:2cc1468da177	883	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
<>	161:2cc1468da177	884	* @retval None
<>	161:2cc1468da177	885	*/
<>	161:2cc1468da177	886	__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
<>	161:2cc1468da177	887	{
<>	161:2cc1468da177	888	MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
<>	161:2cc1468da177	889	}
<>	161:2cc1468da177	890
<>	161:2cc1468da177	891	/**
<>	161:2cc1468da177	892	* @brief Get actual encoder mode.
<>	161:2cc1468da177	893	* @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
<>	161:2cc1468da177	894	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	895	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	896	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
<>	161:2cc1468da177	897	* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
<>	161:2cc1468da177	898	* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
<>	161:2cc1468da177	899	*/
<>	161:2cc1468da177	900	__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	901	{
<>	161:2cc1468da177	902	return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
<>	161:2cc1468da177	903	}
<>	161:2cc1468da177	904
<>	161:2cc1468da177	905	/**
<>	161:2cc1468da177	906	* @brief Enable the encoder mode
<>	161:2cc1468da177	907	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	908	* @note In this mode the LPTIM instance must be clocked by an internal clock
<>	161:2cc1468da177	909	* source. Also, the prescaler division ratio must be equal to 1.
<>	161:2cc1468da177	910	* @note LPTIM instance must be configured in continuous mode prior enabling
<>	161:2cc1468da177	911	* the encoder mode.
<>	161:2cc1468da177	912	* @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
<>	161:2cc1468da177	913	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	914	* @retval None
<>	161:2cc1468da177	915	*/
<>	161:2cc1468da177	916	__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	917	{
<>	161:2cc1468da177	918	SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
<>	161:2cc1468da177	919	}
<>	161:2cc1468da177	920
<>	161:2cc1468da177	921	/**
<>	161:2cc1468da177	922	* @brief Disable the encoder mode
<>	161:2cc1468da177	923	* @note This function must be called when the LPTIM instance is disabled.
<>	161:2cc1468da177	924	* @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
<>	161:2cc1468da177	925	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	926	* @retval None
<>	161:2cc1468da177	927	*/
<>	161:2cc1468da177	928	__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	929	{
<>	161:2cc1468da177	930	CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
<>	161:2cc1468da177	931	}
<>	161:2cc1468da177	932
<>	161:2cc1468da177	933	/**
<>	161:2cc1468da177	934	* @brief Indicates whether the LPTIM operates in encoder mode.
<>	161:2cc1468da177	935	* @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
<>	161:2cc1468da177	936	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	937	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	938	*/
<>	161:2cc1468da177	939	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	940	{
<>	161:2cc1468da177	941	return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
<>	161:2cc1468da177	942	}
<>	161:2cc1468da177	943
<>	161:2cc1468da177	944	/**
<>	161:2cc1468da177	945	* @}
<>	161:2cc1468da177	946	*/
<>	161:2cc1468da177	947
<>	161:2cc1468da177	948	/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
<>	161:2cc1468da177	949	* @{
<>	161:2cc1468da177	950	*/
<>	161:2cc1468da177	951
<>	161:2cc1468da177	952	/**
<>	161:2cc1468da177	953	* @brief Clear the compare match flag (CMPMCF)
<>	161:2cc1468da177	954	* @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
<>	161:2cc1468da177	955	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	956	* @retval None
<>	161:2cc1468da177	957	*/
<>	161:2cc1468da177	958	__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	959	{
<>	161:2cc1468da177	960	SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
<>	161:2cc1468da177	961	}
<>	161:2cc1468da177	962
<>	161:2cc1468da177	963	/**
<>	161:2cc1468da177	964	* @brief Inform application whether a compare match interrupt has occurred.
<>	161:2cc1468da177	965	* @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
<>	161:2cc1468da177	966	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	967	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	968	*/
<>	161:2cc1468da177	969	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	970	{
<>	161:2cc1468da177	971	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
<>	161:2cc1468da177	972	}
<>	161:2cc1468da177	973
<>	161:2cc1468da177	974	/**
<>	161:2cc1468da177	975	* @brief Clear the autoreload match flag (ARRMCF)
<>	161:2cc1468da177	976	* @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
<>	161:2cc1468da177	977	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	978	* @retval None
<>	161:2cc1468da177	979	*/
<>	161:2cc1468da177	980	__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	981	{
<>	161:2cc1468da177	982	SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
<>	161:2cc1468da177	983	}
<>	161:2cc1468da177	984
<>	161:2cc1468da177	985	/**
<>	161:2cc1468da177	986	* @brief Inform application whether a autoreload match interrupt has occured.
<>	161:2cc1468da177	987	* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
<>	161:2cc1468da177	988	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	989	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	990	*/
<>	161:2cc1468da177	991	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	992	{
<>	161:2cc1468da177	993	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
<>	161:2cc1468da177	994	}
<>	161:2cc1468da177	995
<>	161:2cc1468da177	996	/**
<>	161:2cc1468da177	997	* @brief Clear the external trigger valid edge flag(EXTTRIGCF).
<>	161:2cc1468da177	998	* @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
<>	161:2cc1468da177	999	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1000	* @retval None
<>	161:2cc1468da177	1001	*/
<>	161:2cc1468da177	1002	__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1003	{
<>	161:2cc1468da177	1004	SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
<>	161:2cc1468da177	1005	}
<>	161:2cc1468da177	1006
<>	161:2cc1468da177	1007	/**
<>	161:2cc1468da177	1008	* @brief Inform application whether a valid edge on the selected external trigger input has occurred.
<>	161:2cc1468da177	1009	* @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
<>	161:2cc1468da177	1010	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1011	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1012	*/
<>	161:2cc1468da177	1013	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1014	{
<>	161:2cc1468da177	1015	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
<>	161:2cc1468da177	1016	}
<>	161:2cc1468da177	1017
<>	161:2cc1468da177	1018	/**
<>	161:2cc1468da177	1019	* @brief Clear the compare register update interrupt flag (CMPOKCF).
<>	161:2cc1468da177	1020	* @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
<>	161:2cc1468da177	1021	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1022	* @retval None
<>	161:2cc1468da177	1023	*/
<>	161:2cc1468da177	1024	__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1025	{
<>	161:2cc1468da177	1026	SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
<>	161:2cc1468da177	1027	}
<>	161:2cc1468da177	1028
<>	161:2cc1468da177	1029	/**
<>	161:2cc1468da177	1030	* @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
<>	161:2cc1468da177	1031	* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
<>	161:2cc1468da177	1032	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1033	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1034	*/
<>	161:2cc1468da177	1035	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1036	{
<>	161:2cc1468da177	1037	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
<>	161:2cc1468da177	1038	}
<>	161:2cc1468da177	1039
<>	161:2cc1468da177	1040	/**
<>	161:2cc1468da177	1041	* @brief Clear the autoreload register update interrupt flag (ARROKCF).
<>	161:2cc1468da177	1042	* @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
<>	161:2cc1468da177	1043	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1044	* @retval None
<>	161:2cc1468da177	1045	*/
<>	161:2cc1468da177	1046	__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1047	{
<>	161:2cc1468da177	1048	SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
<>	161:2cc1468da177	1049	}
<>	161:2cc1468da177	1050
<>	161:2cc1468da177	1051	/**
<>	161:2cc1468da177	1052	* @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
<>	161:2cc1468da177	1053	* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
<>	161:2cc1468da177	1054	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1055	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1056	*/
<>	161:2cc1468da177	1057	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1058	{
<>	161:2cc1468da177	1059	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
<>	161:2cc1468da177	1060	}
<>	161:2cc1468da177	1061
<>	161:2cc1468da177	1062	/**
<>	161:2cc1468da177	1063	* @brief Clear the counter direction change to up interrupt flag (UPCF).
<>	161:2cc1468da177	1064	* @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
<>	161:2cc1468da177	1065	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1066	* @retval None
<>	161:2cc1468da177	1067	*/
<>	161:2cc1468da177	1068	__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1069	{
<>	161:2cc1468da177	1070	SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
<>	161:2cc1468da177	1071	}
<>	161:2cc1468da177	1072
<>	161:2cc1468da177	1073	/**
<>	161:2cc1468da177	1074	* @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
<>	161:2cc1468da177	1075	* @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
<>	161:2cc1468da177	1076	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1077	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1078	*/
<>	161:2cc1468da177	1079	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1080	{
<>	161:2cc1468da177	1081	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
<>	161:2cc1468da177	1082	}
<>	161:2cc1468da177	1083
<>	161:2cc1468da177	1084	/**
<>	161:2cc1468da177	1085	* @brief Clear the counter direction change to down interrupt flag (DOWNCF).
<>	161:2cc1468da177	1086	* @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
<>	161:2cc1468da177	1087	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1088	* @retval None
<>	161:2cc1468da177	1089	*/
<>	161:2cc1468da177	1090	__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1091	{
<>	161:2cc1468da177	1092	SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
<>	161:2cc1468da177	1093	}
<>	161:2cc1468da177	1094
<>	161:2cc1468da177	1095	/**
<>	161:2cc1468da177	1096	* @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
<>	161:2cc1468da177	1097	* @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
<>	161:2cc1468da177	1098	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1099	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1100	*/
<>	161:2cc1468da177	1101	__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1102	{
<>	161:2cc1468da177	1103	return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
<>	161:2cc1468da177	1104	}
<>	161:2cc1468da177	1105
<>	161:2cc1468da177	1106	/**
<>	161:2cc1468da177	1107	* @}
<>	161:2cc1468da177	1108	*/
<>	161:2cc1468da177	1109
<>	161:2cc1468da177	1110	/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
<>	161:2cc1468da177	1111	* @{
<>	161:2cc1468da177	1112	*/
<>	161:2cc1468da177	1113
<>	161:2cc1468da177	1114	/**
<>	161:2cc1468da177	1115	* @brief Enable compare match interrupt (CMPMIE).
<>	161:2cc1468da177	1116	* @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
<>	161:2cc1468da177	1117	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1118	* @retval None
<>	161:2cc1468da177	1119	*/
<>	161:2cc1468da177	1120	__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1121	{
<>	161:2cc1468da177	1122	SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
<>	161:2cc1468da177	1123	}
<>	161:2cc1468da177	1124
<>	161:2cc1468da177	1125	/**
<>	161:2cc1468da177	1126	* @brief Disable compare match interrupt (CMPMIE).
<>	161:2cc1468da177	1127	* @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
<>	161:2cc1468da177	1128	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1129	* @retval None
<>	161:2cc1468da177	1130	*/
<>	161:2cc1468da177	1131	__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1132	{
<>	161:2cc1468da177	1133	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
<>	161:2cc1468da177	1134	}
<>	161:2cc1468da177	1135
<>	161:2cc1468da177	1136	/**
<>	161:2cc1468da177	1137	* @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
<>	161:2cc1468da177	1138	* @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
<>	161:2cc1468da177	1139	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1140	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1141	*/
<>	161:2cc1468da177	1142	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1143	{
<>	161:2cc1468da177	1144	return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
<>	161:2cc1468da177	1145	}
<>	161:2cc1468da177	1146
<>	161:2cc1468da177	1147	/**
<>	161:2cc1468da177	1148	* @brief Enable autoreload match interrupt (ARRMIE).
<>	161:2cc1468da177	1149	* @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
<>	161:2cc1468da177	1150	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1151	* @retval None
<>	161:2cc1468da177	1152	*/
<>	161:2cc1468da177	1153	__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1154	{
<>	161:2cc1468da177	1155	SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
<>	161:2cc1468da177	1156	}
<>	161:2cc1468da177	1157
<>	161:2cc1468da177	1158	/**
<>	161:2cc1468da177	1159	* @brief Disable autoreload match interrupt (ARRMIE).
<>	161:2cc1468da177	1160	* @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
<>	161:2cc1468da177	1161	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1162	* @retval None
<>	161:2cc1468da177	1163	*/
<>	161:2cc1468da177	1164	__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1165	{
<>	161:2cc1468da177	1166	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
<>	161:2cc1468da177	1167	}
<>	161:2cc1468da177	1168
<>	161:2cc1468da177	1169	/**
<>	161:2cc1468da177	1170	* @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
<>	161:2cc1468da177	1171	* @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
<>	161:2cc1468da177	1172	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1173	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1174	*/
<>	161:2cc1468da177	1175	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1176	{
<>	161:2cc1468da177	1177	return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
<>	161:2cc1468da177	1178	}
<>	161:2cc1468da177	1179
<>	161:2cc1468da177	1180	/**
<>	161:2cc1468da177	1181	* @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
<>	161:2cc1468da177	1182	* @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
<>	161:2cc1468da177	1183	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1184	* @retval None
<>	161:2cc1468da177	1185	*/
<>	161:2cc1468da177	1186	__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1187	{
<>	161:2cc1468da177	1188	SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
<>	161:2cc1468da177	1189	}
<>	161:2cc1468da177	1190
<>	161:2cc1468da177	1191	/**
<>	161:2cc1468da177	1192	* @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
<>	161:2cc1468da177	1193	* @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
<>	161:2cc1468da177	1194	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1195	* @retval None
<>	161:2cc1468da177	1196	*/
<>	161:2cc1468da177	1197	__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1198	{
<>	161:2cc1468da177	1199	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
<>	161:2cc1468da177	1200	}
<>	161:2cc1468da177	1201
<>	161:2cc1468da177	1202	/**
<>	161:2cc1468da177	1203	* @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
<>	161:2cc1468da177	1204	* @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
<>	161:2cc1468da177	1205	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1206	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1207	*/
<>	161:2cc1468da177	1208	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1209	{
<>	161:2cc1468da177	1210	return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
<>	161:2cc1468da177	1211	}
<>	161:2cc1468da177	1212
<>	161:2cc1468da177	1213	/**
<>	161:2cc1468da177	1214	* @brief Enable compare register write completed interrupt (CMPOKIE).
<>	161:2cc1468da177	1215	* @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
<>	161:2cc1468da177	1216	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1217	* @retval None
<>	161:2cc1468da177	1218	*/
<>	161:2cc1468da177	1219	__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1220	{
<>	161:2cc1468da177	1221	SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
<>	161:2cc1468da177	1222	}
<>	161:2cc1468da177	1223
<>	161:2cc1468da177	1224	/**
<>	161:2cc1468da177	1225	* @brief Disable compare register write completed interrupt (CMPOKIE).
<>	161:2cc1468da177	1226	* @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
<>	161:2cc1468da177	1227	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1228	* @retval None
<>	161:2cc1468da177	1229	*/
<>	161:2cc1468da177	1230	__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1231	{
<>	161:2cc1468da177	1232	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
<>	161:2cc1468da177	1233	}
<>	161:2cc1468da177	1234
<>	161:2cc1468da177	1235	/**
<>	161:2cc1468da177	1236	* @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
<>	161:2cc1468da177	1237	* @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
<>	161:2cc1468da177	1238	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1239	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1240	*/
<>	161:2cc1468da177	1241	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1242	{
<>	161:2cc1468da177	1243	return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
<>	161:2cc1468da177	1244	}
<>	161:2cc1468da177	1245
<>	161:2cc1468da177	1246	/**
<>	161:2cc1468da177	1247	* @brief Enable autoreload register write completed interrupt (ARROKIE).
<>	161:2cc1468da177	1248	* @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
<>	161:2cc1468da177	1249	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1250	* @retval None
<>	161:2cc1468da177	1251	*/
<>	161:2cc1468da177	1252	__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1253	{
<>	161:2cc1468da177	1254	SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
<>	161:2cc1468da177	1255	}
<>	161:2cc1468da177	1256
<>	161:2cc1468da177	1257	/**
<>	161:2cc1468da177	1258	* @brief Disable autoreload register write completed interrupt (ARROKIE).
<>	161:2cc1468da177	1259	* @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
<>	161:2cc1468da177	1260	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1261	* @retval None
<>	161:2cc1468da177	1262	*/
<>	161:2cc1468da177	1263	__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1264	{
<>	161:2cc1468da177	1265	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
<>	161:2cc1468da177	1266	}
<>	161:2cc1468da177	1267
<>	161:2cc1468da177	1268	/**
<>	161:2cc1468da177	1269	* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
<>	161:2cc1468da177	1270	* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
<>	161:2cc1468da177	1271	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1272	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1273	*/
<>	161:2cc1468da177	1274	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1275	{
<>	161:2cc1468da177	1276	return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
<>	161:2cc1468da177	1277	}
<>	161:2cc1468da177	1278
<>	161:2cc1468da177	1279	/**
<>	161:2cc1468da177	1280	* @brief Enable direction change to up interrupt (UPIE).
<>	161:2cc1468da177	1281	* @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
<>	161:2cc1468da177	1282	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1283	* @retval None
<>	161:2cc1468da177	1284	*/
<>	161:2cc1468da177	1285	__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1286	{
<>	161:2cc1468da177	1287	SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
<>	161:2cc1468da177	1288	}
<>	161:2cc1468da177	1289
<>	161:2cc1468da177	1290	/**
<>	161:2cc1468da177	1291	* @brief Disable direction change to up interrupt (UPIE).
<>	161:2cc1468da177	1292	* @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
<>	161:2cc1468da177	1293	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1294	* @retval None
<>	161:2cc1468da177	1295	*/
<>	161:2cc1468da177	1296	__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1297	{
<>	161:2cc1468da177	1298	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
<>	161:2cc1468da177	1299	}
<>	161:2cc1468da177	1300
<>	161:2cc1468da177	1301	/**
<>	161:2cc1468da177	1302	* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
<>	161:2cc1468da177	1303	* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
<>	161:2cc1468da177	1304	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1305	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1306	*/
<>	161:2cc1468da177	1307	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1308	{
<>	161:2cc1468da177	1309	return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
<>	161:2cc1468da177	1310	}
<>	161:2cc1468da177	1311
<>	161:2cc1468da177	1312	/**
<>	161:2cc1468da177	1313	* @brief Enable direction change to down interrupt (DOWNIE).
<>	161:2cc1468da177	1314	* @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
<>	161:2cc1468da177	1315	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1316	* @retval None
<>	161:2cc1468da177	1317	*/
<>	161:2cc1468da177	1318	__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1319	{
<>	161:2cc1468da177	1320	SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
<>	161:2cc1468da177	1321	}
<>	161:2cc1468da177	1322
<>	161:2cc1468da177	1323	/**
<>	161:2cc1468da177	1324	* @brief Disable direction change to down interrupt (DOWNIE).
<>	161:2cc1468da177	1325	* @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
<>	161:2cc1468da177	1326	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1327	* @retval None
<>	161:2cc1468da177	1328	*/
<>	161:2cc1468da177	1329	__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1330	{
<>	161:2cc1468da177	1331	CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
<>	161:2cc1468da177	1332	}
<>	161:2cc1468da177	1333
<>	161:2cc1468da177	1334	/**
<>	161:2cc1468da177	1335	* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
<>	161:2cc1468da177	1336	* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
<>	161:2cc1468da177	1337	* @param LPTIMx Low-Power Timer instance
<>	161:2cc1468da177	1338	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1339	*/
<>	161:2cc1468da177	1340	__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
<>	161:2cc1468da177	1341	{
<>	161:2cc1468da177	1342	return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
<>	161:2cc1468da177	1343	}
<>	161:2cc1468da177	1344
<>	161:2cc1468da177	1345	/**
<>	161:2cc1468da177	1346	* @}
<>	161:2cc1468da177	1347	*/
<>	161:2cc1468da177	1348
<>	161:2cc1468da177	1349	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	1350	/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
<>	161:2cc1468da177	1351	* @{
<>	161:2cc1468da177	1352	*/
<>	161:2cc1468da177	1353
<>	161:2cc1468da177	1354	ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
<>	161:2cc1468da177	1355	void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
<>	161:2cc1468da177	1356	ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef LPTIMx, LL_LPTIM_InitTypeDef LPTIM_InitStruct);
<>	161:2cc1468da177	1357	/**
<>	161:2cc1468da177	1358	* @}
<>	161:2cc1468da177	1359	*/
<>	161:2cc1468da177	1360	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	1361
<>	161:2cc1468da177	1362	/**
<>	161:2cc1468da177	1363	* @}
<>	161:2cc1468da177	1364	*/
<>	161:2cc1468da177	1365
<>	161:2cc1468da177	1366	/**
<>	161:2cc1468da177	1367	* @}
<>	161:2cc1468da177	1368	*/
<>	161:2cc1468da177	1369
<>	161:2cc1468da177	1370	#endif /* LPTIM1 */
<>	161:2cc1468da177	1371
<>	161:2cc1468da177	1372	/**
<>	161:2cc1468da177	1373	* @}
<>	161:2cc1468da177	1374	*/
<>	161:2cc1468da177	1375
<>	161:2cc1468da177	1376	#ifdef __cplusplus
<>	161:2cc1468da177	1377	}
<>	161:2cc1468da177	1378	#endif
<>	161:2cc1468da177	1379
<>	161:2cc1468da177	1380	#endif /* __STM32F7xx_LL_LPTIM_H */
<>	161:2cc1468da177	1381
<>	161:2cc1468da177	1382	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/