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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_dma2d.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief Header file of DMA2D LL module.
<>	161:2cc1468da177	8	******************************************************************************
<>	161:2cc1468da177	9	* @attention
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	12	*
<>	161:2cc1468da177	13	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	14	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	18	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	19	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	21	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	22	* without specific prior written permission.
<>	161:2cc1468da177	23	*
<>	161:2cc1468da177	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	34	*
<>	161:2cc1468da177	35	******************************************************************************
<>	161:2cc1468da177	36	*/
<>	161:2cc1468da177	37
<>	161:2cc1468da177	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	39	#ifndef __STM32F7xx_LL_DMA2D_H
<>	161:2cc1468da177	40	#define __STM32F7xx_LL_DMA2D_H
<>	161:2cc1468da177	41
<>	161:2cc1468da177	42	#ifdef __cplusplus
<>	161:2cc1468da177	43	extern "C" {
<>	161:2cc1468da177	44	#endif
<>	161:2cc1468da177	45
<>	161:2cc1468da177	46	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	47	#include "stm32f7xx.h"
<>	161:2cc1468da177	48
<>	161:2cc1468da177	49	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	50	* @{
<>	161:2cc1468da177	51	*/
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	#if defined (DMA2D)
<>	161:2cc1468da177	54
<>	161:2cc1468da177	55	/** @defgroup DMA2D_LL DMA2D
<>	161:2cc1468da177	56	* @{
<>	161:2cc1468da177	57	*/
<>	161:2cc1468da177	58
<>	161:2cc1468da177	59	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	60	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	61	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	62	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	63	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	64	/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
<>	161:2cc1468da177	65	* @{
<>	161:2cc1468da177	66	*/
<>	161:2cc1468da177	67
<>	161:2cc1468da177	68	/**
<>	161:2cc1468da177	69	* @}
<>	161:2cc1468da177	70	*/
<>	161:2cc1468da177	71	#endif /USE_FULL_LL_DRIVER/
<>	161:2cc1468da177	72
<>	161:2cc1468da177	73	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	74	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	75	/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
<>	161:2cc1468da177	76	* @{
<>	161:2cc1468da177	77	*/
<>	161:2cc1468da177	78
<>	161:2cc1468da177	79	/**
<>	161:2cc1468da177	80	* @brief LL DMA2D Init Structure Definition
<>	161:2cc1468da177	81	*/
<>	161:2cc1468da177	82	typedef struct
<>	161:2cc1468da177	83	{
<>	161:2cc1468da177	84	uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
<>	161:2cc1468da177	85	- This parameter can be one value of @ref DMA2D_LL_EC_MODE.
<>	161:2cc1468da177	86
<>	161:2cc1468da177	87	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
<>	161:2cc1468da177	88
<>	161:2cc1468da177	89	uint32_t ColorMode; /*!< Specifies the color format of the output image.
<>	161:2cc1468da177	90	- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
<>	161:2cc1468da177	91
<>	161:2cc1468da177	92	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
<>	161:2cc1468da177	93
<>	161:2cc1468da177	94	uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
<>	161:2cc1468da177	95	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	96	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
<>	161:2cc1468da177	97	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
<>	161:2cc1468da177	98	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
<>	161:2cc1468da177	99	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	100
<>	161:2cc1468da177	101	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	102	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	103
<>	161:2cc1468da177	104	uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
<>	161:2cc1468da177	105	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	106	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
<>	161:2cc1468da177	107	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
<>	161:2cc1468da177	108	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
<>	161:2cc1468da177	109	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	110
<>	161:2cc1468da177	111	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	112	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	113
<>	161:2cc1468da177	114	uint32_t OutputRed; /*!< Specifies the Red value of the output image.
<>	161:2cc1468da177	115	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	116	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
<>	161:2cc1468da177	117	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
<>	161:2cc1468da177	118	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
<>	161:2cc1468da177	119	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	120
<>	161:2cc1468da177	121	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	122	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	123
<>	161:2cc1468da177	124	uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
<>	161:2cc1468da177	125	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	126	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
<>	161:2cc1468da177	127	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	128	- This parameter is not considered if RGB888 or RGB565 color mode is selected.
<>	161:2cc1468da177	129
<>	161:2cc1468da177	130	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	131	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	132
<>	161:2cc1468da177	133	uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
<>	161:2cc1468da177	134	- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
<>	161:2cc1468da177	135
<>	161:2cc1468da177	136	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
<>	161:2cc1468da177	137
<>	161:2cc1468da177	138	uint32_t LineOffset; /*!< Specifies the output line offset value.
<>	161:2cc1468da177	139	- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
<>	161:2cc1468da177	140
<>	161:2cc1468da177	141	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
<>	161:2cc1468da177	142
<>	161:2cc1468da177	143	uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
<>	161:2cc1468da177	144	- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
<>	161:2cc1468da177	145
<>	161:2cc1468da177	146	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
<>	161:2cc1468da177	147
<>	161:2cc1468da177	148	uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
<>	161:2cc1468da177	149	- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
<>	161:2cc1468da177	150
<>	161:2cc1468da177	151	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
<>	161:2cc1468da177	152
<>	161:2cc1468da177	153	#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
<>	161:2cc1468da177	154	uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
<>	161:2cc1468da177	155	- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
<>	161:2cc1468da177	156
<>	161:2cc1468da177	157	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
<>	161:2cc1468da177	158
<>	161:2cc1468da177	159	uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
<>	161:2cc1468da177	160	- This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
<>	161:2cc1468da177	161
<>	161:2cc1468da177	162	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
<>	161:2cc1468da177	163	#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
<>	161:2cc1468da177	164
<>	161:2cc1468da177	165	} LL_DMA2D_InitTypeDef;
<>	161:2cc1468da177	166
<>	161:2cc1468da177	167	/**
<>	161:2cc1468da177	168	* @brief LL DMA2D Layer Configuration Structure Definition
<>	161:2cc1468da177	169	*/
<>	161:2cc1468da177	170	typedef struct
<>	161:2cc1468da177	171	{
<>	161:2cc1468da177	172	uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
<>	161:2cc1468da177	173	- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
<>	161:2cc1468da177	174
<>	161:2cc1468da177	175	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	176	- @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
<>	161:2cc1468da177	177	- @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
<>	161:2cc1468da177	178
<>	161:2cc1468da177	179	uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
<>	161:2cc1468da177	180	- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
<>	161:2cc1468da177	181
<>	161:2cc1468da177	182	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	183	- @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
<>	161:2cc1468da177	184	- @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
<>	161:2cc1468da177	185
<>	161:2cc1468da177	186	uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
<>	161:2cc1468da177	187	- This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
<>	161:2cc1468da177	188
<>	161:2cc1468da177	189	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	190	- @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
<>	161:2cc1468da177	191	- @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
<>	161:2cc1468da177	192
<>	161:2cc1468da177	193	uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
<>	161:2cc1468da177	194	- This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
<>	161:2cc1468da177	195
<>	161:2cc1468da177	196	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	197	- @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
<>	161:2cc1468da177	198	- @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
<>	161:2cc1468da177	199
<>	161:2cc1468da177	200	uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
<>	161:2cc1468da177	201	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	161:2cc1468da177	202
<>	161:2cc1468da177	203	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	204	- @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
<>	161:2cc1468da177	205	- @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
<>	161:2cc1468da177	206
<>	161:2cc1468da177	207	uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
<>	161:2cc1468da177	208	- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
<>	161:2cc1468da177	209
<>	161:2cc1468da177	210	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	211	- @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
<>	161:2cc1468da177	212	- @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
<>	161:2cc1468da177	213
<>	161:2cc1468da177	214	uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
<>	161:2cc1468da177	215	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	161:2cc1468da177	216
<>	161:2cc1468da177	217	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	218	- @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
<>	161:2cc1468da177	219	- @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
<>	161:2cc1468da177	220
<>	161:2cc1468da177	221	uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
<>	161:2cc1468da177	222	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	161:2cc1468da177	223
<>	161:2cc1468da177	224	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	225	- @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
<>	161:2cc1468da177	226	- @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
<>	161:2cc1468da177	227
<>	161:2cc1468da177	228	uint32_t Green; /*!< Specifies the foreground or background Green color value.
<>	161:2cc1468da177	229	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	161:2cc1468da177	230
<>	161:2cc1468da177	231	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	232	- @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
<>	161:2cc1468da177	233	- @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
<>	161:2cc1468da177	234
<>	161:2cc1468da177	235	uint32_t Red; /*!< Specifies the foreground or background Red color value.
<>	161:2cc1468da177	236	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	161:2cc1468da177	237
<>	161:2cc1468da177	238	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	239	- @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
<>	161:2cc1468da177	240	- @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
<>	161:2cc1468da177	241
<>	161:2cc1468da177	242	uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
<>	161:2cc1468da177	243	- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
<>	161:2cc1468da177	244
<>	161:2cc1468da177	245	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	246	- @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
<>	161:2cc1468da177	247	- @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
<>	161:2cc1468da177	248
<>	161:2cc1468da177	249	#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
<>	161:2cc1468da177	250	uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
<>	161:2cc1468da177	251	- This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
<>	161:2cc1468da177	252
<>	161:2cc1468da177	253	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	254	- @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
<>	161:2cc1468da177	255	- @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
<>	161:2cc1468da177	256
<>	161:2cc1468da177	257	uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
<>	161:2cc1468da177	258	This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
<>	161:2cc1468da177	259
<>	161:2cc1468da177	260	This parameter can be modified afterwards using unitary functions
<>	161:2cc1468da177	261	- @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
<>	161:2cc1468da177	262	- @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
<>	161:2cc1468da177	263	#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
<>	161:2cc1468da177	264
<>	161:2cc1468da177	265	} LL_DMA2D_LayerCfgTypeDef;
<>	161:2cc1468da177	266
<>	161:2cc1468da177	267	/**
<>	161:2cc1468da177	268	* @brief LL DMA2D Output Color Structure Definition
<>	161:2cc1468da177	269	*/
<>	161:2cc1468da177	270	typedef struct
<>	161:2cc1468da177	271	{
<>	161:2cc1468da177	272	uint32_t ColorMode; /*!< Specifies the color format of the output image.
<>	161:2cc1468da177	273	- This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
<>	161:2cc1468da177	274
<>	161:2cc1468da177	275	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
<>	161:2cc1468da177	276
<>	161:2cc1468da177	277	uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
<>	161:2cc1468da177	278	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	279	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
<>	161:2cc1468da177	280	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
<>	161:2cc1468da177	281	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
<>	161:2cc1468da177	282	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	283
<>	161:2cc1468da177	284	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	285	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	286
<>	161:2cc1468da177	287	uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
<>	161:2cc1468da177	288	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	289	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
<>	161:2cc1468da177	290	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
<>	161:2cc1468da177	291	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
<>	161:2cc1468da177	292	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	293
<>	161:2cc1468da177	294	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	295	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	296
<>	161:2cc1468da177	297	uint32_t OutputRed; /*!< Specifies the Red value of the output image.
<>	161:2cc1468da177	298	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	299	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
<>	161:2cc1468da177	300	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
<>	161:2cc1468da177	301	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
<>	161:2cc1468da177	302	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	303
<>	161:2cc1468da177	304	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	305	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	306
<>	161:2cc1468da177	307	uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
<>	161:2cc1468da177	308	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
<>	161:2cc1468da177	309	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
<>	161:2cc1468da177	310	- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
<>	161:2cc1468da177	311	- This parameter is not considered if RGB888 or RGB565 color mode is selected.
<>	161:2cc1468da177	312
<>	161:2cc1468da177	313	This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
<>	161:2cc1468da177	314	function @ref LL_DMA2D_ConfigOutputColor(). */
<>	161:2cc1468da177	315
<>	161:2cc1468da177	316	} LL_DMA2D_ColorTypeDef;
<>	161:2cc1468da177	317
<>	161:2cc1468da177	318	/**
<>	161:2cc1468da177	319	* @}
<>	161:2cc1468da177	320	*/
<>	161:2cc1468da177	321	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	322
<>	161:2cc1468da177	323	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	324	/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
<>	161:2cc1468da177	325	* @{
<>	161:2cc1468da177	326	*/
<>	161:2cc1468da177	327
<>	161:2cc1468da177	328	/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
<>	161:2cc1468da177	329	* @brief Flags defines which can be used with LL_DMA2D_ReadReg function
<>	161:2cc1468da177	330	* @{
<>	161:2cc1468da177	331	*/
<>	161:2cc1468da177	332	#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /!< Configuration Error Interrupt Flag /
<>	161:2cc1468da177	333	#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /!< CLUT Transfer Complete Interrupt Flag /
<>	161:2cc1468da177	334	#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /!< CLUT Access Error Interrupt Flag /
<>	161:2cc1468da177	335	#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /!< Transfer Watermark Interrupt Flag /
<>	161:2cc1468da177	336	#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /!< Transfer Complete Interrupt Flag /
<>	161:2cc1468da177	337	#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /!< Transfer Error Interrupt Flag /
<>	161:2cc1468da177	338	/**
<>	161:2cc1468da177	339	* @}
<>	161:2cc1468da177	340	*/
<>	161:2cc1468da177	341
<>	161:2cc1468da177	342	/** @defgroup DMA2D_LL_EC_IT IT Defines
<>	161:2cc1468da177	343	* @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
<>	161:2cc1468da177	344	* @{
<>	161:2cc1468da177	345	*/
<>	161:2cc1468da177	346	#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /!< Configuration Error Interrupt /
<>	161:2cc1468da177	347	#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /!< CLUT Transfer Complete Interrupt /
<>	161:2cc1468da177	348	#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /!< CLUT Access Error Interrupt /
<>	161:2cc1468da177	349	#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /!< Transfer Watermark Interrupt /
<>	161:2cc1468da177	350	#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /!< Transfer Complete Interrupt /
<>	161:2cc1468da177	351	#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /!< Transfer Error Interrupt /
<>	161:2cc1468da177	352	/**
<>	161:2cc1468da177	353	* @}
<>	161:2cc1468da177	354	*/
<>	161:2cc1468da177	355
<>	161:2cc1468da177	356	/** @defgroup DMA2D_LL_EC_MODE Mode
<>	161:2cc1468da177	357	* @{
<>	161:2cc1468da177	358	*/
<>	161:2cc1468da177	359	#define LL_DMA2D_MODE_M2M 0x00000000U /!< DMA2D memory to memory transfer mode /
<>	161:2cc1468da177	360	#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /!< DMA2D memory to memory with pixel format conversion transfer mode /
<>	161:2cc1468da177	361	#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /!< DMA2D memory to memory with blending transfer mode /
<>	161:2cc1468da177	362	#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /!< DMA2D register to memory transfer mode /
<>	161:2cc1468da177	363	/**
<>	161:2cc1468da177	364	* @}
<>	161:2cc1468da177	365	*/
<>	161:2cc1468da177	366
<>	161:2cc1468da177	367	/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
<>	161:2cc1468da177	368	* @{
<>	161:2cc1468da177	369	*/
<>	161:2cc1468da177	370	#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /!< ARGB8888 /
<>	161:2cc1468da177	371	#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /!< RGB888 /
<>	161:2cc1468da177	372	#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /!< RGB565 /
<>	161:2cc1468da177	373	#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0\|DMA2D_OPFCCR_CM_1) /!< ARGB1555 /
<>	161:2cc1468da177	374	#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /!< ARGB4444 /
<>	161:2cc1468da177	375	/**
<>	161:2cc1468da177	376	* @}
<>	161:2cc1468da177	377	*/
<>	161:2cc1468da177	378
<>	161:2cc1468da177	379	/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
<>	161:2cc1468da177	380	* @{
<>	161:2cc1468da177	381	*/
<>	161:2cc1468da177	382	#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /!< ARGB8888 /
<>	161:2cc1468da177	383	#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /!< RGB888 /
<>	161:2cc1468da177	384	#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /!< RGB565 /
<>	161:2cc1468da177	385	#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0\|DMA2D_FGPFCCR_CM_1) /!< ARGB1555 /
<>	161:2cc1468da177	386	#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /!< ARGB4444 /
<>	161:2cc1468da177	387	#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0\|DMA2D_FGPFCCR_CM_2) /!< L8 /
<>	161:2cc1468da177	388	#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1\|DMA2D_FGPFCCR_CM_2) /!< AL44 /
<>	161:2cc1468da177	389	#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0\|DMA2D_FGPFCCR_CM_1\|DMA2D_FGPFCCR_CM_2) /!< AL88 /
<>	161:2cc1468da177	390	#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /!< L4 /
<>	161:2cc1468da177	391	#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0\|DMA2D_FGPFCCR_CM_3) /!< A8 /
<>	161:2cc1468da177	392	#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1\|DMA2D_FGPFCCR_CM_3) /!< A4 /
<>	161:2cc1468da177	393	/**
<>	161:2cc1468da177	394	* @}
<>	161:2cc1468da177	395	*/
<>	161:2cc1468da177	396
<>	161:2cc1468da177	397	/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
<>	161:2cc1468da177	398	* @{
<>	161:2cc1468da177	399	*/
<>	161:2cc1468da177	400	#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /!< No modification of the alpha channel value /
<>	161:2cc1468da177	401	#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /!< Replace original alpha channel value by programmed alpha value /
<>	161:2cc1468da177	402	#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
<>	161:2cc1468da177	403	with original alpha channel value */
<>	161:2cc1468da177	404	/**
<>	161:2cc1468da177	405	* @}
<>	161:2cc1468da177	406	*/
<>	161:2cc1468da177	407
<>	161:2cc1468da177	408	#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
<>	161:2cc1468da177	409	/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
<>	161:2cc1468da177	410	* @{
<>	161:2cc1468da177	411	*/
<>	161:2cc1468da177	412	#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /!< RGB or ARGB /
<>	161:2cc1468da177	413	#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /!< BGR or ABGR /
<>	161:2cc1468da177	414	/**
<>	161:2cc1468da177	415	* @}
<>	161:2cc1468da177	416	*/
<>	161:2cc1468da177	417
<>	161:2cc1468da177	418	/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
<>	161:2cc1468da177	419	* @{
<>	161:2cc1468da177	420	*/
<>	161:2cc1468da177	421	#define LL_DMA2D_ALPHA_REGULAR 0x00000000U /!< Regular alpha /
<>	161:2cc1468da177	422	#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /!< Inverted alpha /
<>	161:2cc1468da177	423	/**
<>	161:2cc1468da177	424	* @}
<>	161:2cc1468da177	425	*/
<>	161:2cc1468da177	426
<>	161:2cc1468da177	427	#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
<>	161:2cc1468da177	428	/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
<>	161:2cc1468da177	429	* @{
<>	161:2cc1468da177	430	*/
<>	161:2cc1468da177	431	#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /!< ARGB8888 /
<>	161:2cc1468da177	432	#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /!< RGB888 /
<>	161:2cc1468da177	433	/**
<>	161:2cc1468da177	434	* @}
<>	161:2cc1468da177	435	*/
<>	161:2cc1468da177	436
<>	161:2cc1468da177	437	/**
<>	161:2cc1468da177	438	* @}
<>	161:2cc1468da177	439	*/
<>	161:2cc1468da177	440
<>	161:2cc1468da177	441	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	442	/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
<>	161:2cc1468da177	443	* @{
<>	161:2cc1468da177	444	*/
<>	161:2cc1468da177	445
<>	161:2cc1468da177	446	/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
<>	161:2cc1468da177	447	* @{
<>	161:2cc1468da177	448	*/
<>	161:2cc1468da177	449
<>	161:2cc1468da177	450	/**
<>	161:2cc1468da177	451	* @brief Write a value in DMA2D register.
<>	161:2cc1468da177	452	* @param __INSTANCE__ DMA2D Instance
<>	161:2cc1468da177	453	* @param __REG__ Register to be written
<>	161:2cc1468da177	454	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	455	* @retval None
<>	161:2cc1468da177	456	*/
<>	161:2cc1468da177	457	#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	161:2cc1468da177	458
<>	161:2cc1468da177	459	/**
<>	161:2cc1468da177	460	* @brief Read a value in DMA2D register.
<>	161:2cc1468da177	461	* @param __INSTANCE__ DMA2D Instance
<>	161:2cc1468da177	462	* @param __REG__ Register to be read
<>	161:2cc1468da177	463	* @retval Register value
<>	161:2cc1468da177	464	*/
<>	161:2cc1468da177	465	#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	161:2cc1468da177	466	/**
<>	161:2cc1468da177	467	* @}
<>	161:2cc1468da177	468	*/
<>	161:2cc1468da177	469
<>	161:2cc1468da177	470	/**
<>	161:2cc1468da177	471	* @}
<>	161:2cc1468da177	472	*/
<>	161:2cc1468da177	473
<>	161:2cc1468da177	474	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	475	/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
<>	161:2cc1468da177	476	* @{
<>	161:2cc1468da177	477	*/
<>	161:2cc1468da177	478
<>	161:2cc1468da177	479	/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
<>	161:2cc1468da177	480	* @{
<>	161:2cc1468da177	481	*/
<>	161:2cc1468da177	482
<>	161:2cc1468da177	483	/**
<>	161:2cc1468da177	484	* @brief Start a DMA2D transfer.
<>	161:2cc1468da177	485	* @rmtoll CR START LL_DMA2D_Start
<>	161:2cc1468da177	486	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	487	* @retval None
<>	161:2cc1468da177	488	*/
<>	161:2cc1468da177	489	__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	490	{
<>	161:2cc1468da177	491	SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
<>	161:2cc1468da177	492	}
<>	161:2cc1468da177	493
<>	161:2cc1468da177	494	/**
<>	161:2cc1468da177	495	* @brief Indicate if a DMA2D transfer is ongoing.
<>	161:2cc1468da177	496	* @rmtoll CR START LL_DMA2D_IsTransferOngoing
<>	161:2cc1468da177	497	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	498	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	499	*/
<>	161:2cc1468da177	500	__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	501	{
<>	161:2cc1468da177	502	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START));
<>	161:2cc1468da177	503	}
<>	161:2cc1468da177	504
<>	161:2cc1468da177	505	/**
<>	161:2cc1468da177	506	* @brief Suspend DMA2D transfer.
<>	161:2cc1468da177	507	* @note This API can be used to suspend automatic foreground or background CLUT loading.
<>	161:2cc1468da177	508	* @rmtoll CR SUSP LL_DMA2D_Suspend
<>	161:2cc1468da177	509	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	510	* @retval None
<>	161:2cc1468da177	511	*/
<>	161:2cc1468da177	512	__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	513	{
<>	161:2cc1468da177	514	MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP \| DMA2D_CR_START, DMA2D_CR_SUSP);
<>	161:2cc1468da177	515	}
<>	161:2cc1468da177	516
<>	161:2cc1468da177	517	/**
<>	161:2cc1468da177	518	* @brief Resume DMA2D transfer.
<>	161:2cc1468da177	519	* @note This API can be used to resume automatic foreground or background CLUT loading.
<>	161:2cc1468da177	520	* @rmtoll CR SUSP LL_DMA2D_Resume
<>	161:2cc1468da177	521	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	522	* @retval None
<>	161:2cc1468da177	523	*/
<>	161:2cc1468da177	524	__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	525	{
<>	161:2cc1468da177	526	CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP \| DMA2D_CR_START);
<>	161:2cc1468da177	527	}
<>	161:2cc1468da177	528
<>	161:2cc1468da177	529	/**
<>	161:2cc1468da177	530	* @brief Indicate if DMA2D transfer is suspended.
<>	161:2cc1468da177	531	* @note This API can be used to indicate whether or not automatic foreground or
<>	161:2cc1468da177	532	* background CLUT loading is suspended.
<>	161:2cc1468da177	533	* @rmtoll CR SUSP LL_DMA2D_IsSuspended
<>	161:2cc1468da177	534	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	535	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	536	*/
<>	161:2cc1468da177	537	__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	538	{
<>	161:2cc1468da177	539	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP));
<>	161:2cc1468da177	540	}
<>	161:2cc1468da177	541
<>	161:2cc1468da177	542	/**
<>	161:2cc1468da177	543	* @brief Abort DMA2D transfer.
<>	161:2cc1468da177	544	* @note This API can be used to abort automatic foreground or background CLUT loading.
<>	161:2cc1468da177	545	* @rmtoll CR ABORT LL_DMA2D_Abort
<>	161:2cc1468da177	546	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	547	* @retval None
<>	161:2cc1468da177	548	*/
<>	161:2cc1468da177	549	__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	550	{
<>	161:2cc1468da177	551	MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT \| DMA2D_CR_START, DMA2D_CR_ABORT);
<>	161:2cc1468da177	552	}
<>	161:2cc1468da177	553
<>	161:2cc1468da177	554	/**
<>	161:2cc1468da177	555	* @brief Indicate if DMA2D transfer is aborted.
<>	161:2cc1468da177	556	* @note This API can be used to indicate whether or not automatic foreground or
<>	161:2cc1468da177	557	* background CLUT loading is aborted.
<>	161:2cc1468da177	558	* @rmtoll CR ABORT LL_DMA2D_IsAborted
<>	161:2cc1468da177	559	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	560	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	561	*/
<>	161:2cc1468da177	562	__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	563	{
<>	161:2cc1468da177	564	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT));
<>	161:2cc1468da177	565	}
<>	161:2cc1468da177	566
<>	161:2cc1468da177	567	/**
<>	161:2cc1468da177	568	* @brief Set DMA2D mode.
<>	161:2cc1468da177	569	* @rmtoll CR MODE LL_DMA2D_SetMode
<>	161:2cc1468da177	570	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	571	* @param Mode This parameter can be one of the following values:
<>	161:2cc1468da177	572	* @arg @ref LL_DMA2D_MODE_M2M
<>	161:2cc1468da177	573	* @arg @ref LL_DMA2D_MODE_M2M_PFC
<>	161:2cc1468da177	574	* @arg @ref LL_DMA2D_MODE_M2M_BLEND
<>	161:2cc1468da177	575	* @arg @ref LL_DMA2D_MODE_R2M
<>	161:2cc1468da177	576	* @retval None
<>	161:2cc1468da177	577	*/
<>	161:2cc1468da177	578	__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
<>	161:2cc1468da177	579	{
<>	161:2cc1468da177	580	MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
<>	161:2cc1468da177	581	}
<>	161:2cc1468da177	582
<>	161:2cc1468da177	583	/**
<>	161:2cc1468da177	584	* @brief Return DMA2D mode
<>	161:2cc1468da177	585	* @rmtoll CR MODE LL_DMA2D_GetMode
<>	161:2cc1468da177	586	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	587	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	588	* @arg @ref LL_DMA2D_MODE_M2M
<>	161:2cc1468da177	589	* @arg @ref LL_DMA2D_MODE_M2M_PFC
<>	161:2cc1468da177	590	* @arg @ref LL_DMA2D_MODE_M2M_BLEND
<>	161:2cc1468da177	591	* @arg @ref LL_DMA2D_MODE_R2M
<>	161:2cc1468da177	592	*/
<>	161:2cc1468da177	593	__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	594	{
<>	161:2cc1468da177	595	return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
<>	161:2cc1468da177	596	}
<>	161:2cc1468da177	597
<>	161:2cc1468da177	598	/**
<>	161:2cc1468da177	599	* @brief Set DMA2D output color mode.
<>	161:2cc1468da177	600	* @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
<>	161:2cc1468da177	601	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	602	* @param ColorMode This parameter can be one of the following values:
<>	161:2cc1468da177	603	* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
<>	161:2cc1468da177	604	* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
<>	161:2cc1468da177	605	* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
<>	161:2cc1468da177	606	* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
<>	161:2cc1468da177	607	* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
<>	161:2cc1468da177	608	* @retval None
<>	161:2cc1468da177	609	*/
<>	161:2cc1468da177	610	__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
<>	161:2cc1468da177	611	{
<>	161:2cc1468da177	612	MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
<>	161:2cc1468da177	613	}
<>	161:2cc1468da177	614
<>	161:2cc1468da177	615	/**
<>	161:2cc1468da177	616	* @brief Return DMA2D output color mode.
<>	161:2cc1468da177	617	* @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
<>	161:2cc1468da177	618	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	619	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	620	* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
<>	161:2cc1468da177	621	* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
<>	161:2cc1468da177	622	* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
<>	161:2cc1468da177	623	* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
<>	161:2cc1468da177	624	* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
<>	161:2cc1468da177	625	*/
<>	161:2cc1468da177	626	__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	627	{
<>	161:2cc1468da177	628	return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
<>	161:2cc1468da177	629	}
<>	161:2cc1468da177	630
<>	161:2cc1468da177	631	#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
<>	161:2cc1468da177	632	/**
<>	161:2cc1468da177	633	* @brief Set DMA2D output Red Blue swap mode.
<>	161:2cc1468da177	634	* @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
<>	161:2cc1468da177	635	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	636	* @param RBSwapMode This parameter can be one of the following values:
<>	161:2cc1468da177	637	* @arg @ref LL_DMA2D_RB_MODE_REGULAR
<>	161:2cc1468da177	638	* @arg @ref LL_DMA2D_RB_MODE_SWAP
<>	161:2cc1468da177	639	* @retval None
<>	161:2cc1468da177	640	*/
<>	161:2cc1468da177	641	__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
<>	161:2cc1468da177	642	{
<>	161:2cc1468da177	643	MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
<>	161:2cc1468da177	644	}
<>	161:2cc1468da177	645
<>	161:2cc1468da177	646	/**
<>	161:2cc1468da177	647	* @brief Return DMA2D output Red Blue swap mode.
<>	161:2cc1468da177	648	* @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
<>	161:2cc1468da177	649	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	650	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	651	* @arg @ref LL_DMA2D_RB_MODE_REGULAR
<>	161:2cc1468da177	652	* @arg @ref LL_DMA2D_RB_MODE_SWAP
<>	161:2cc1468da177	653	*/
<>	161:2cc1468da177	654	__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	655	{
<>	161:2cc1468da177	656	return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
<>	161:2cc1468da177	657	}
<>	161:2cc1468da177	658
<>	161:2cc1468da177	659	/**
<>	161:2cc1468da177	660	* @brief Set DMA2D output alpha inversion mode.
<>	161:2cc1468da177	661	* @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
<>	161:2cc1468da177	662	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	663	* @param AlphaInversionMode This parameter can be one of the following values:
<>	161:2cc1468da177	664	* @arg @ref LL_DMA2D_ALPHA_REGULAR
<>	161:2cc1468da177	665	* @arg @ref LL_DMA2D_ALPHA_INVERTED
<>	161:2cc1468da177	666	* @retval None
<>	161:2cc1468da177	667	*/
<>	161:2cc1468da177	668	__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
<>	161:2cc1468da177	669	{
<>	161:2cc1468da177	670	MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
<>	161:2cc1468da177	671	}
<>	161:2cc1468da177	672
<>	161:2cc1468da177	673	/**
<>	161:2cc1468da177	674	* @brief Return DMA2D output alpha inversion mode.
<>	161:2cc1468da177	675	* @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
<>	161:2cc1468da177	676	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	677	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	678	* @arg @ref LL_DMA2D_ALPHA_REGULAR
<>	161:2cc1468da177	679	* @arg @ref LL_DMA2D_ALPHA_INVERTED
<>	161:2cc1468da177	680	*/
<>	161:2cc1468da177	681	__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	682	{
<>	161:2cc1468da177	683	return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
<>	161:2cc1468da177	684	}
<>	161:2cc1468da177	685
<>	161:2cc1468da177	686	#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
<>	161:2cc1468da177	687
<>	161:2cc1468da177	688	/**
<>	161:2cc1468da177	689	* @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
<>	161:2cc1468da177	690	* @rmtoll OOR LO LL_DMA2D_SetLineOffset
<>	161:2cc1468da177	691	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	692	* @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
<>	161:2cc1468da177	693	* @retval None
<>	161:2cc1468da177	694	*/
<>	161:2cc1468da177	695	__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
<>	161:2cc1468da177	696	{
<>	161:2cc1468da177	697	MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
<>	161:2cc1468da177	698	}
<>	161:2cc1468da177	699
<>	161:2cc1468da177	700	/**
<>	161:2cc1468da177	701	* @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
<>	161:2cc1468da177	702	* @rmtoll OOR LO LL_DMA2D_GetLineOffset
<>	161:2cc1468da177	703	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	704	* @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
<>	161:2cc1468da177	705	*/
<>	161:2cc1468da177	706	__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	707	{
<>	161:2cc1468da177	708	return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
<>	161:2cc1468da177	709	}
<>	161:2cc1468da177	710
<>	161:2cc1468da177	711	/**
<>	161:2cc1468da177	712	* @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
<>	161:2cc1468da177	713	* @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
<>	161:2cc1468da177	714	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	715	* @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
<>	161:2cc1468da177	716	* @retval None
<>	161:2cc1468da177	717	*/
<>	161:2cc1468da177	718	__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
<>	161:2cc1468da177	719	{
<>	161:2cc1468da177	720	MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
<>	161:2cc1468da177	721	}
<>	161:2cc1468da177	722
<>	161:2cc1468da177	723	/**
<>	161:2cc1468da177	724	* @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
<>	161:2cc1468da177	725	* @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
<>	161:2cc1468da177	726	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	727	* @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
<>	161:2cc1468da177	728	*/
<>	161:2cc1468da177	729	__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	730	{
<>	161:2cc1468da177	731	return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
<>	161:2cc1468da177	732	}
<>	161:2cc1468da177	733
<>	161:2cc1468da177	734	/**
<>	161:2cc1468da177	735	* @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
<>	161:2cc1468da177	736	* @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
<>	161:2cc1468da177	737	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	738	* @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
<>	161:2cc1468da177	739	* @retval None
<>	161:2cc1468da177	740	*/
<>	161:2cc1468da177	741	__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
<>	161:2cc1468da177	742	{
<>	161:2cc1468da177	743	MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
<>	161:2cc1468da177	744	}
<>	161:2cc1468da177	745
<>	161:2cc1468da177	746	/**
<>	161:2cc1468da177	747	* @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
<>	161:2cc1468da177	748	* @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
<>	161:2cc1468da177	749	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	750	* @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
<>	161:2cc1468da177	751	*/
<>	161:2cc1468da177	752	__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	753	{
<>	161:2cc1468da177	754	return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
<>	161:2cc1468da177	755	}
<>	161:2cc1468da177	756
<>	161:2cc1468da177	757	/**
<>	161:2cc1468da177	758	* @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	759	* @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
<>	161:2cc1468da177	760	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	761	* @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	762	* @retval None
<>	161:2cc1468da177	763	*/
<>	161:2cc1468da177	764	__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
<>	161:2cc1468da177	765	{
<>	161:2cc1468da177	766	LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
<>	161:2cc1468da177	767	}
<>	161:2cc1468da177	768
<>	161:2cc1468da177	769	/**
<>	161:2cc1468da177	770	* @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	771	* @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
<>	161:2cc1468da177	772	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	773	* @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	774	*/
<>	161:2cc1468da177	775	__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	776	{
<>	161:2cc1468da177	777	return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
<>	161:2cc1468da177	778	}
<>	161:2cc1468da177	779
<>	161:2cc1468da177	780	/**
<>	161:2cc1468da177	781	* @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	782	* @note Output color format depends on output color mode, ARGB8888, RGB888,
<>	161:2cc1468da177	783	* RGB565, ARGB1555 or ARGB4444.
<>	161:2cc1468da177	784	* @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
<>	161:2cc1468da177	785	* with respect to color mode is not done by the user code.
<>	161:2cc1468da177	786	* @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
<>	161:2cc1468da177	787	* OCOLR GREEN LL_DMA2D_SetOutputColor\n
<>	161:2cc1468da177	788	* OCOLR RED LL_DMA2D_SetOutputColor\n
<>	161:2cc1468da177	789	* OCOLR ALPHA LL_DMA2D_SetOutputColor
<>	161:2cc1468da177	790	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	791	* @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	792	* @retval None
<>	161:2cc1468da177	793	*/
<>	161:2cc1468da177	794	__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
<>	161:2cc1468da177	795	{
<>	161:2cc1468da177	796	MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 \| DMA2D_OCOLR_GREEN_1 \| DMA2D_OCOLR_RED_1 \| DMA2D_OCOLR_ALPHA_1), \
<>	161:2cc1468da177	797	OutputColor);
<>	161:2cc1468da177	798	}
<>	161:2cc1468da177	799
<>	161:2cc1468da177	800	/**
<>	161:2cc1468da177	801	* @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	802	* @note Alpha channel and red, green, blue color values must be retrieved from the returned
<>	161:2cc1468da177	803	* value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
<>	161:2cc1468da177	804	* as set by @ref LL_DMA2D_SetOutputColorMode.
<>	161:2cc1468da177	805	* @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
<>	161:2cc1468da177	806	* OCOLR GREEN LL_DMA2D_GetOutputColor\n
<>	161:2cc1468da177	807	* OCOLR RED LL_DMA2D_GetOutputColor\n
<>	161:2cc1468da177	808	* OCOLR ALPHA LL_DMA2D_GetOutputColor
<>	161:2cc1468da177	809	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	810	* @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	811	*/
<>	161:2cc1468da177	812	__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	813	{
<>	161:2cc1468da177	814	return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
<>	161:2cc1468da177	815	(DMA2D_OCOLR_BLUE_1 \| DMA2D_OCOLR_GREEN_1 \| DMA2D_OCOLR_RED_1 \| DMA2D_OCOLR_ALPHA_1)));
<>	161:2cc1468da177	816	}
<>	161:2cc1468da177	817
<>	161:2cc1468da177	818	/**
<>	161:2cc1468da177	819	* @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
<>	161:2cc1468da177	820	* @rmtoll LWR LW LL_DMA2D_SetLineWatermark
<>	161:2cc1468da177	821	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	822	* @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
<>	161:2cc1468da177	823	* @retval None
<>	161:2cc1468da177	824	*/
<>	161:2cc1468da177	825	__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
<>	161:2cc1468da177	826	{
<>	161:2cc1468da177	827	MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
<>	161:2cc1468da177	828	}
<>	161:2cc1468da177	829
<>	161:2cc1468da177	830	/**
<>	161:2cc1468da177	831	* @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
<>	161:2cc1468da177	832	* @rmtoll LWR LW LL_DMA2D_GetLineWatermark
<>	161:2cc1468da177	833	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	834	* @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
<>	161:2cc1468da177	835	*/
<>	161:2cc1468da177	836	__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	837	{
<>	161:2cc1468da177	838	return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
<>	161:2cc1468da177	839	}
<>	161:2cc1468da177	840
<>	161:2cc1468da177	841	/**
<>	161:2cc1468da177	842	* @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	843	* @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
<>	161:2cc1468da177	844	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	845	* @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	846	* @retval None
<>	161:2cc1468da177	847	*/
<>	161:2cc1468da177	848	__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
<>	161:2cc1468da177	849	{
<>	161:2cc1468da177	850	MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
<>	161:2cc1468da177	851	}
<>	161:2cc1468da177	852
<>	161:2cc1468da177	853	/**
<>	161:2cc1468da177	854	* @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	855	* @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
<>	161:2cc1468da177	856	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	857	* @retval Dead time value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	858	*/
<>	161:2cc1468da177	859	__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	860	{
<>	161:2cc1468da177	861	return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
<>	161:2cc1468da177	862	}
<>	161:2cc1468da177	863
<>	161:2cc1468da177	864	/**
<>	161:2cc1468da177	865	* @brief Enable DMA2D dead time functionality.
<>	161:2cc1468da177	866	* @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
<>	161:2cc1468da177	867	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	868	* @retval None
<>	161:2cc1468da177	869	*/
<>	161:2cc1468da177	870	__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	871	{
<>	161:2cc1468da177	872	SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
<>	161:2cc1468da177	873	}
<>	161:2cc1468da177	874
<>	161:2cc1468da177	875	/**
<>	161:2cc1468da177	876	* @brief Disable DMA2D dead time functionality.
<>	161:2cc1468da177	877	* @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
<>	161:2cc1468da177	878	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	879	* @retval None
<>	161:2cc1468da177	880	*/
<>	161:2cc1468da177	881	__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	882	{
<>	161:2cc1468da177	883	CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
<>	161:2cc1468da177	884	}
<>	161:2cc1468da177	885
<>	161:2cc1468da177	886	/**
<>	161:2cc1468da177	887	* @brief Indicate if DMA2D dead time functionality is enabled.
<>	161:2cc1468da177	888	* @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
<>	161:2cc1468da177	889	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	890	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	891	*/
<>	161:2cc1468da177	892	__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	893	{
<>	161:2cc1468da177	894	return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN));
<>	161:2cc1468da177	895	}
<>	161:2cc1468da177	896
<>	161:2cc1468da177	897	/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
<>	161:2cc1468da177	898	* @{
<>	161:2cc1468da177	899	*/
<>	161:2cc1468da177	900
<>	161:2cc1468da177	901	/**
<>	161:2cc1468da177	902	* @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	903	* @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
<>	161:2cc1468da177	904	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	905	* @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	906	* @retval None
<>	161:2cc1468da177	907	*/
<>	161:2cc1468da177	908	__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
<>	161:2cc1468da177	909	{
<>	161:2cc1468da177	910	LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
<>	161:2cc1468da177	911	}
<>	161:2cc1468da177	912
<>	161:2cc1468da177	913	/**
<>	161:2cc1468da177	914	* @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	915	* @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
<>	161:2cc1468da177	916	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	917	* @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	918	*/
<>	161:2cc1468da177	919	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	920	{
<>	161:2cc1468da177	921	return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
<>	161:2cc1468da177	922	}
<>	161:2cc1468da177	923
<>	161:2cc1468da177	924	/**
<>	161:2cc1468da177	925	* @brief Enable DMA2D foreground CLUT loading.
<>	161:2cc1468da177	926	* @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
<>	161:2cc1468da177	927	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	928	* @retval None
<>	161:2cc1468da177	929	*/
<>	161:2cc1468da177	930	__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	931	{
<>	161:2cc1468da177	932	SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
<>	161:2cc1468da177	933	}
<>	161:2cc1468da177	934
<>	161:2cc1468da177	935	/**
<>	161:2cc1468da177	936	* @brief Indicate if DMA2D foreground CLUT loading is enabled.
<>	161:2cc1468da177	937	* @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
<>	161:2cc1468da177	938	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	939	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	940	*/
<>	161:2cc1468da177	941	__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	942	{
<>	161:2cc1468da177	943	return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START));
<>	161:2cc1468da177	944	}
<>	161:2cc1468da177	945
<>	161:2cc1468da177	946	/**
<>	161:2cc1468da177	947	* @brief Set DMA2D foreground color mode.
<>	161:2cc1468da177	948	* @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
<>	161:2cc1468da177	949	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	950	* @param ColorMode This parameter can be one of the following values:
<>	161:2cc1468da177	951	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
<>	161:2cc1468da177	952	* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
<>	161:2cc1468da177	953	* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
<>	161:2cc1468da177	954	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
<>	161:2cc1468da177	955	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
<>	161:2cc1468da177	956	* @arg @ref LL_DMA2D_INPUT_MODE_L8
<>	161:2cc1468da177	957	* @arg @ref LL_DMA2D_INPUT_MODE_AL44
<>	161:2cc1468da177	958	* @arg @ref LL_DMA2D_INPUT_MODE_AL88
<>	161:2cc1468da177	959	* @arg @ref LL_DMA2D_INPUT_MODE_L4
<>	161:2cc1468da177	960	* @arg @ref LL_DMA2D_INPUT_MODE_A8
<>	161:2cc1468da177	961	* @arg @ref LL_DMA2D_INPUT_MODE_A4
<>	161:2cc1468da177	962	* @retval None
<>	161:2cc1468da177	963	*/
<>	161:2cc1468da177	964	__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
<>	161:2cc1468da177	965	{
<>	161:2cc1468da177	966	MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
<>	161:2cc1468da177	967	}
<>	161:2cc1468da177	968
<>	161:2cc1468da177	969	/**
<>	161:2cc1468da177	970	* @brief Return DMA2D foreground color mode.
<>	161:2cc1468da177	971	* @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
<>	161:2cc1468da177	972	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	973	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	974	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
<>	161:2cc1468da177	975	* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
<>	161:2cc1468da177	976	* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
<>	161:2cc1468da177	977	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
<>	161:2cc1468da177	978	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
<>	161:2cc1468da177	979	* @arg @ref LL_DMA2D_INPUT_MODE_L8
<>	161:2cc1468da177	980	* @arg @ref LL_DMA2D_INPUT_MODE_AL44
<>	161:2cc1468da177	981	* @arg @ref LL_DMA2D_INPUT_MODE_AL88
<>	161:2cc1468da177	982	* @arg @ref LL_DMA2D_INPUT_MODE_L4
<>	161:2cc1468da177	983	* @arg @ref LL_DMA2D_INPUT_MODE_A8
<>	161:2cc1468da177	984	* @arg @ref LL_DMA2D_INPUT_MODE_A4
<>	161:2cc1468da177	985	*/
<>	161:2cc1468da177	986	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	987	{
<>	161:2cc1468da177	988	return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
<>	161:2cc1468da177	989	}
<>	161:2cc1468da177	990
<>	161:2cc1468da177	991	/**
<>	161:2cc1468da177	992	* @brief Set DMA2D foreground alpha mode.
<>	161:2cc1468da177	993	* @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
<>	161:2cc1468da177	994	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	995	* @param AphaMode This parameter can be one of the following values:
<>	161:2cc1468da177	996	* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
<>	161:2cc1468da177	997	* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
<>	161:2cc1468da177	998	* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
<>	161:2cc1468da177	999	* @retval None
<>	161:2cc1468da177	1000	*/
<>	161:2cc1468da177	1001	__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
<>	161:2cc1468da177	1002	{
<>	161:2cc1468da177	1003	MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
<>	161:2cc1468da177	1004	}
<>	161:2cc1468da177	1005
<>	161:2cc1468da177	1006	/**
<>	161:2cc1468da177	1007	* @brief Return DMA2D foreground alpha mode.
<>	161:2cc1468da177	1008	* @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
<>	161:2cc1468da177	1009	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1010	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1011	* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
<>	161:2cc1468da177	1012	* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
<>	161:2cc1468da177	1013	* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
<>	161:2cc1468da177	1014	*/
<>	161:2cc1468da177	1015	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1016	{
<>	161:2cc1468da177	1017	return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
<>	161:2cc1468da177	1018	}
<>	161:2cc1468da177	1019
<>	161:2cc1468da177	1020	/**
<>	161:2cc1468da177	1021	* @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1022	* @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
<>	161:2cc1468da177	1023	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1024	* @param Alpha Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1025	* @retval None
<>	161:2cc1468da177	1026	*/
<>	161:2cc1468da177	1027	__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
<>	161:2cc1468da177	1028	{
<>	161:2cc1468da177	1029	MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
<>	161:2cc1468da177	1030	}
<>	161:2cc1468da177	1031
<>	161:2cc1468da177	1032	/**
<>	161:2cc1468da177	1033	* @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1034	* @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
<>	161:2cc1468da177	1035	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1036	* @retval Alpha value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1037	*/
<>	161:2cc1468da177	1038	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1039	{
<>	161:2cc1468da177	1040	return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
<>	161:2cc1468da177	1041	}
<>	161:2cc1468da177	1042
<>	161:2cc1468da177	1043	#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
<>	161:2cc1468da177	1044	/**
<>	161:2cc1468da177	1045	* @brief Set DMA2D foreground Red Blue swap mode.
<>	161:2cc1468da177	1046	* @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
<>	161:2cc1468da177	1047	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1048	* @param RBSwapMode This parameter can be one of the following values:
<>	161:2cc1468da177	1049	* @arg @ref LL_DMA2D_RB_MODE_REGULAR
<>	161:2cc1468da177	1050	* @arg @ref LL_DMA2D_RB_MODE_SWAP
<>	161:2cc1468da177	1051	* @retval None
<>	161:2cc1468da177	1052	*/
<>	161:2cc1468da177	1053	__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
<>	161:2cc1468da177	1054	{
<>	161:2cc1468da177	1055	MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
<>	161:2cc1468da177	1056	}
<>	161:2cc1468da177	1057
<>	161:2cc1468da177	1058	/**
<>	161:2cc1468da177	1059	* @brief Return DMA2D foreground Red Blue swap mode.
<>	161:2cc1468da177	1060	* @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
<>	161:2cc1468da177	1061	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1062	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1063	* @arg @ref LL_DMA2D_RB_MODE_REGULAR
<>	161:2cc1468da177	1064	* @arg @ref LL_DMA2D_RB_MODE_SWAP
<>	161:2cc1468da177	1065	*/
<>	161:2cc1468da177	1066	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1067	{
<>	161:2cc1468da177	1068	return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
<>	161:2cc1468da177	1069	}
<>	161:2cc1468da177	1070
<>	161:2cc1468da177	1071	/**
<>	161:2cc1468da177	1072	* @brief Set DMA2D foreground alpha inversion mode.
<>	161:2cc1468da177	1073	* @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
<>	161:2cc1468da177	1074	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1075	* @param AlphaInversionMode This parameter can be one of the following values:
<>	161:2cc1468da177	1076	* @arg @ref LL_DMA2D_ALPHA_REGULAR
<>	161:2cc1468da177	1077	* @arg @ref LL_DMA2D_ALPHA_INVERTED
<>	161:2cc1468da177	1078	* @retval None
<>	161:2cc1468da177	1079	*/
<>	161:2cc1468da177	1080	__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
<>	161:2cc1468da177	1081	{
<>	161:2cc1468da177	1082	MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
<>	161:2cc1468da177	1083	}
<>	161:2cc1468da177	1084
<>	161:2cc1468da177	1085	/**
<>	161:2cc1468da177	1086	* @brief Return DMA2D foreground alpha inversion mode.
<>	161:2cc1468da177	1087	* @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
<>	161:2cc1468da177	1088	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1089	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1090	* @arg @ref LL_DMA2D_ALPHA_REGULAR
<>	161:2cc1468da177	1091	* @arg @ref LL_DMA2D_ALPHA_INVERTED
<>	161:2cc1468da177	1092	*/
<>	161:2cc1468da177	1093	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1094	{
<>	161:2cc1468da177	1095	return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
<>	161:2cc1468da177	1096	}
<>	161:2cc1468da177	1097
<>	161:2cc1468da177	1098	#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
<>	161:2cc1468da177	1099
<>	161:2cc1468da177	1100	/**
<>	161:2cc1468da177	1101	* @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
<>	161:2cc1468da177	1102	* @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
<>	161:2cc1468da177	1103	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1104	* @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
<>	161:2cc1468da177	1105	* @retval None
<>	161:2cc1468da177	1106	*/
<>	161:2cc1468da177	1107	__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
<>	161:2cc1468da177	1108	{
<>	161:2cc1468da177	1109	MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
<>	161:2cc1468da177	1110	}
<>	161:2cc1468da177	1111
<>	161:2cc1468da177	1112	/**
<>	161:2cc1468da177	1113	* @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
<>	161:2cc1468da177	1114	* @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
<>	161:2cc1468da177	1115	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1116	* @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
<>	161:2cc1468da177	1117	*/
<>	161:2cc1468da177	1118	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1119	{
<>	161:2cc1468da177	1120	return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
<>	161:2cc1468da177	1121	}
<>	161:2cc1468da177	1122
<>	161:2cc1468da177	1123	/**
<>	161:2cc1468da177	1124	* @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
<>	161:2cc1468da177	1125	* @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
<>	161:2cc1468da177	1126	* @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
<>	161:2cc1468da177	1127	* @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
<>	161:2cc1468da177	1128	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1129	* @param Red Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1130	* @param Green Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1131	* @param Blue Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1132	* @retval None
<>	161:2cc1468da177	1133	*/
<>	161:2cc1468da177	1134	__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
<>	161:2cc1468da177	1135	{
<>	161:2cc1468da177	1136	MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED \| DMA2D_FGCOLR_GREEN \| DMA2D_FGCOLR_BLUE), \
<>	161:2cc1468da177	1137	((Red << DMA2D_FGCOLR_RED_Pos) \| (Green << DMA2D_FGCOLR_GREEN_Pos) \| Blue));
<>	161:2cc1468da177	1138	}
<>	161:2cc1468da177	1139
<>	161:2cc1468da177	1140	/**
<>	161:2cc1468da177	1141	* @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1142	* @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
<>	161:2cc1468da177	1143	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1144	* @param Red Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1145	* @retval None
<>	161:2cc1468da177	1146	*/
<>	161:2cc1468da177	1147	__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
<>	161:2cc1468da177	1148	{
<>	161:2cc1468da177	1149	MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
<>	161:2cc1468da177	1150	}
<>	161:2cc1468da177	1151
<>	161:2cc1468da177	1152	/**
<>	161:2cc1468da177	1153	* @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1154	* @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
<>	161:2cc1468da177	1155	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1156	* @retval Red color value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1157	*/
<>	161:2cc1468da177	1158	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1159	{
<>	161:2cc1468da177	1160	return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
<>	161:2cc1468da177	1161	}
<>	161:2cc1468da177	1162
<>	161:2cc1468da177	1163	/**
<>	161:2cc1468da177	1164	* @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1165	* @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
<>	161:2cc1468da177	1166	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1167	* @param Green Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1168	* @retval None
<>	161:2cc1468da177	1169	*/
<>	161:2cc1468da177	1170	__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
<>	161:2cc1468da177	1171	{
<>	161:2cc1468da177	1172	MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
<>	161:2cc1468da177	1173	}
<>	161:2cc1468da177	1174
<>	161:2cc1468da177	1175	/**
<>	161:2cc1468da177	1176	* @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1177	* @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
<>	161:2cc1468da177	1178	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1179	* @retval Green color value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1180	*/
<>	161:2cc1468da177	1181	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1182	{
<>	161:2cc1468da177	1183	return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
<>	161:2cc1468da177	1184	}
<>	161:2cc1468da177	1185
<>	161:2cc1468da177	1186	/**
<>	161:2cc1468da177	1187	* @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1188	* @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
<>	161:2cc1468da177	1189	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1190	* @param Blue Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1191	* @retval None
<>	161:2cc1468da177	1192	*/
<>	161:2cc1468da177	1193	__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
<>	161:2cc1468da177	1194	{
<>	161:2cc1468da177	1195	MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
<>	161:2cc1468da177	1196	}
<>	161:2cc1468da177	1197
<>	161:2cc1468da177	1198	/**
<>	161:2cc1468da177	1199	* @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1200	* @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
<>	161:2cc1468da177	1201	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1202	* @retval Blue color value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1203	*/
<>	161:2cc1468da177	1204	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1205	{
<>	161:2cc1468da177	1206	return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
<>	161:2cc1468da177	1207	}
<>	161:2cc1468da177	1208
<>	161:2cc1468da177	1209	/**
<>	161:2cc1468da177	1210	* @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	1211	* @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
<>	161:2cc1468da177	1212	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1213	* @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	1214	* @retval None
<>	161:2cc1468da177	1215	*/
<>	161:2cc1468da177	1216	__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
<>	161:2cc1468da177	1217	{
<>	161:2cc1468da177	1218	LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
<>	161:2cc1468da177	1219	}
<>	161:2cc1468da177	1220
<>	161:2cc1468da177	1221	/**
<>	161:2cc1468da177	1222	* @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	1223	* @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
<>	161:2cc1468da177	1224	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1225	* @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	1226	*/
<>	161:2cc1468da177	1227	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1228	{
<>	161:2cc1468da177	1229	return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
<>	161:2cc1468da177	1230	}
<>	161:2cc1468da177	1231
<>	161:2cc1468da177	1232	/**
<>	161:2cc1468da177	1233	* @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1234	* @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
<>	161:2cc1468da177	1235	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1236	* @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1237	* @retval None
<>	161:2cc1468da177	1238	*/
<>	161:2cc1468da177	1239	__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
<>	161:2cc1468da177	1240	{
<>	161:2cc1468da177	1241	MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
<>	161:2cc1468da177	1242	}
<>	161:2cc1468da177	1243
<>	161:2cc1468da177	1244	/**
<>	161:2cc1468da177	1245	* @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1246	* @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
<>	161:2cc1468da177	1247	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1248	* @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1249	*/
<>	161:2cc1468da177	1250	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1251	{
<>	161:2cc1468da177	1252	return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
<>	161:2cc1468da177	1253	}
<>	161:2cc1468da177	1254
<>	161:2cc1468da177	1255	/**
<>	161:2cc1468da177	1256	* @brief Set DMA2D foreground CLUT color mode.
<>	161:2cc1468da177	1257	* @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
<>	161:2cc1468da177	1258	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1259	* @param CLUTColorMode This parameter can be one of the following values:
<>	161:2cc1468da177	1260	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
<>	161:2cc1468da177	1261	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
<>	161:2cc1468da177	1262	* @retval None
<>	161:2cc1468da177	1263	*/
<>	161:2cc1468da177	1264	__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
<>	161:2cc1468da177	1265	{
<>	161:2cc1468da177	1266	MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
<>	161:2cc1468da177	1267	}
<>	161:2cc1468da177	1268
<>	161:2cc1468da177	1269	/**
<>	161:2cc1468da177	1270	* @brief Return DMA2D foreground CLUT color mode.
<>	161:2cc1468da177	1271	* @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
<>	161:2cc1468da177	1272	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1273	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1274	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
<>	161:2cc1468da177	1275	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
<>	161:2cc1468da177	1276	*/
<>	161:2cc1468da177	1277	__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1278	{
<>	161:2cc1468da177	1279	return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
<>	161:2cc1468da177	1280	}
<>	161:2cc1468da177	1281
<>	161:2cc1468da177	1282	/**
<>	161:2cc1468da177	1283	* @}
<>	161:2cc1468da177	1284	*/
<>	161:2cc1468da177	1285
<>	161:2cc1468da177	1286	/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
<>	161:2cc1468da177	1287	* @{
<>	161:2cc1468da177	1288	*/
<>	161:2cc1468da177	1289
<>	161:2cc1468da177	1290	/**
<>	161:2cc1468da177	1291	* @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	1292	* @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
<>	161:2cc1468da177	1293	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1294	* @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	1295	* @retval None
<>	161:2cc1468da177	1296	*/
<>	161:2cc1468da177	1297	__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
<>	161:2cc1468da177	1298	{
<>	161:2cc1468da177	1299	LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
<>	161:2cc1468da177	1300	}
<>	161:2cc1468da177	1301
<>	161:2cc1468da177	1302	/**
<>	161:2cc1468da177	1303	* @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	1304	* @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
<>	161:2cc1468da177	1305	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1306	* @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	1307	*/
<>	161:2cc1468da177	1308	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1309	{
<>	161:2cc1468da177	1310	return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
<>	161:2cc1468da177	1311	}
<>	161:2cc1468da177	1312
<>	161:2cc1468da177	1313	/**
<>	161:2cc1468da177	1314	* @brief Enable DMA2D background CLUT loading.
<>	161:2cc1468da177	1315	* @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
<>	161:2cc1468da177	1316	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1317	* @retval None
<>	161:2cc1468da177	1318	*/
<>	161:2cc1468da177	1319	__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1320	{
<>	161:2cc1468da177	1321	SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
<>	161:2cc1468da177	1322	}
<>	161:2cc1468da177	1323
<>	161:2cc1468da177	1324	/**
<>	161:2cc1468da177	1325	* @brief Indicate if DMA2D background CLUT loading is enabled.
<>	161:2cc1468da177	1326	* @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
<>	161:2cc1468da177	1327	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1328	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1329	*/
<>	161:2cc1468da177	1330	__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1331	{
<>	161:2cc1468da177	1332	return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START));
<>	161:2cc1468da177	1333	}
<>	161:2cc1468da177	1334
<>	161:2cc1468da177	1335	/**
<>	161:2cc1468da177	1336	* @brief Set DMA2D background color mode.
<>	161:2cc1468da177	1337	* @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
<>	161:2cc1468da177	1338	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1339	* @param ColorMode This parameter can be one of the following values:
<>	161:2cc1468da177	1340	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
<>	161:2cc1468da177	1341	* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
<>	161:2cc1468da177	1342	* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
<>	161:2cc1468da177	1343	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
<>	161:2cc1468da177	1344	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
<>	161:2cc1468da177	1345	* @arg @ref LL_DMA2D_INPUT_MODE_L8
<>	161:2cc1468da177	1346	* @arg @ref LL_DMA2D_INPUT_MODE_AL44
<>	161:2cc1468da177	1347	* @arg @ref LL_DMA2D_INPUT_MODE_AL88
<>	161:2cc1468da177	1348	* @arg @ref LL_DMA2D_INPUT_MODE_L4
<>	161:2cc1468da177	1349	* @arg @ref LL_DMA2D_INPUT_MODE_A8
<>	161:2cc1468da177	1350	* @arg @ref LL_DMA2D_INPUT_MODE_A4
<>	161:2cc1468da177	1351	* @retval None
<>	161:2cc1468da177	1352	*/
<>	161:2cc1468da177	1353	__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
<>	161:2cc1468da177	1354	{
<>	161:2cc1468da177	1355	MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
<>	161:2cc1468da177	1356	}
<>	161:2cc1468da177	1357
<>	161:2cc1468da177	1358	/**
<>	161:2cc1468da177	1359	* @brief Return DMA2D background color mode.
<>	161:2cc1468da177	1360	* @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
<>	161:2cc1468da177	1361	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1362	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1363	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
<>	161:2cc1468da177	1364	* @arg @ref LL_DMA2D_INPUT_MODE_RGB888
<>	161:2cc1468da177	1365	* @arg @ref LL_DMA2D_INPUT_MODE_RGB565
<>	161:2cc1468da177	1366	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
<>	161:2cc1468da177	1367	* @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
<>	161:2cc1468da177	1368	* @arg @ref LL_DMA2D_INPUT_MODE_L8
<>	161:2cc1468da177	1369	* @arg @ref LL_DMA2D_INPUT_MODE_AL44
<>	161:2cc1468da177	1370	* @arg @ref LL_DMA2D_INPUT_MODE_AL88
<>	161:2cc1468da177	1371	* @arg @ref LL_DMA2D_INPUT_MODE_L4
<>	161:2cc1468da177	1372	* @arg @ref LL_DMA2D_INPUT_MODE_A8
<>	161:2cc1468da177	1373	* @arg @ref LL_DMA2D_INPUT_MODE_A4
<>	161:2cc1468da177	1374	*/
<>	161:2cc1468da177	1375	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1376	{
<>	161:2cc1468da177	1377	return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
<>	161:2cc1468da177	1378	}
<>	161:2cc1468da177	1379
<>	161:2cc1468da177	1380	/**
<>	161:2cc1468da177	1381	* @brief Set DMA2D background alpha mode.
<>	161:2cc1468da177	1382	* @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
<>	161:2cc1468da177	1383	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1384	* @param AphaMode This parameter can be one of the following values:
<>	161:2cc1468da177	1385	* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
<>	161:2cc1468da177	1386	* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
<>	161:2cc1468da177	1387	* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
<>	161:2cc1468da177	1388	* @retval None
<>	161:2cc1468da177	1389	*/
<>	161:2cc1468da177	1390	__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
<>	161:2cc1468da177	1391	{
<>	161:2cc1468da177	1392	MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
<>	161:2cc1468da177	1393	}
<>	161:2cc1468da177	1394
<>	161:2cc1468da177	1395	/**
<>	161:2cc1468da177	1396	* @brief Return DMA2D background alpha mode.
<>	161:2cc1468da177	1397	* @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
<>	161:2cc1468da177	1398	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1399	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1400	* @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
<>	161:2cc1468da177	1401	* @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
<>	161:2cc1468da177	1402	* @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
<>	161:2cc1468da177	1403	*/
<>	161:2cc1468da177	1404	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1405	{
<>	161:2cc1468da177	1406	return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
<>	161:2cc1468da177	1407	}
<>	161:2cc1468da177	1408
<>	161:2cc1468da177	1409	/**
<>	161:2cc1468da177	1410	* @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1411	* @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
<>	161:2cc1468da177	1412	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1413	* @param Alpha Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1414	* @retval None
<>	161:2cc1468da177	1415	*/
<>	161:2cc1468da177	1416	__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
<>	161:2cc1468da177	1417	{
<>	161:2cc1468da177	1418	MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
<>	161:2cc1468da177	1419	}
<>	161:2cc1468da177	1420
<>	161:2cc1468da177	1421	/**
<>	161:2cc1468da177	1422	* @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1423	* @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
<>	161:2cc1468da177	1424	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1425	* @retval Alpha value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1426	*/
<>	161:2cc1468da177	1427	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1428	{
<>	161:2cc1468da177	1429	return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
<>	161:2cc1468da177	1430	}
<>	161:2cc1468da177	1431
<>	161:2cc1468da177	1432	#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
<>	161:2cc1468da177	1433	/**
<>	161:2cc1468da177	1434	* @brief Set DMA2D background Red Blue swap mode.
<>	161:2cc1468da177	1435	* @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
<>	161:2cc1468da177	1436	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1437	* @param RBSwapMode This parameter can be one of the following values:
<>	161:2cc1468da177	1438	* @arg @ref LL_DMA2D_RB_MODE_REGULAR
<>	161:2cc1468da177	1439	* @arg @ref LL_DMA2D_RB_MODE_SWAP
<>	161:2cc1468da177	1440	* @retval None
<>	161:2cc1468da177	1441	*/
<>	161:2cc1468da177	1442	__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
<>	161:2cc1468da177	1443	{
<>	161:2cc1468da177	1444	MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
<>	161:2cc1468da177	1445	}
<>	161:2cc1468da177	1446
<>	161:2cc1468da177	1447	/**
<>	161:2cc1468da177	1448	* @brief Return DMA2D background Red Blue swap mode.
<>	161:2cc1468da177	1449	* @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
<>	161:2cc1468da177	1450	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1451	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1452	* @arg @ref LL_DMA2D_RB_MODE_REGULAR
<>	161:2cc1468da177	1453	* @arg @ref LL_DMA2D_RB_MODE_SWAP
<>	161:2cc1468da177	1454	*/
<>	161:2cc1468da177	1455	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1456	{
<>	161:2cc1468da177	1457	return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
<>	161:2cc1468da177	1458	}
<>	161:2cc1468da177	1459
<>	161:2cc1468da177	1460	/**
<>	161:2cc1468da177	1461	* @brief Set DMA2D background alpha inversion mode.
<>	161:2cc1468da177	1462	* @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
<>	161:2cc1468da177	1463	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1464	* @param AlphaInversionMode This parameter can be one of the following values:
<>	161:2cc1468da177	1465	* @arg @ref LL_DMA2D_ALPHA_REGULAR
<>	161:2cc1468da177	1466	* @arg @ref LL_DMA2D_ALPHA_INVERTED
<>	161:2cc1468da177	1467	* @retval None
<>	161:2cc1468da177	1468	*/
<>	161:2cc1468da177	1469	__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
<>	161:2cc1468da177	1470	{
<>	161:2cc1468da177	1471	MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
<>	161:2cc1468da177	1472	}
<>	161:2cc1468da177	1473
<>	161:2cc1468da177	1474	/**
<>	161:2cc1468da177	1475	* @brief Return DMA2D background alpha inversion mode.
<>	161:2cc1468da177	1476	* @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
<>	161:2cc1468da177	1477	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1478	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1479	* @arg @ref LL_DMA2D_ALPHA_REGULAR
<>	161:2cc1468da177	1480	* @arg @ref LL_DMA2D_ALPHA_INVERTED
<>	161:2cc1468da177	1481	*/
<>	161:2cc1468da177	1482	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1483	{
<>	161:2cc1468da177	1484	return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
<>	161:2cc1468da177	1485	}
<>	161:2cc1468da177	1486
<>	161:2cc1468da177	1487	#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
<>	161:2cc1468da177	1488
<>	161:2cc1468da177	1489	/**
<>	161:2cc1468da177	1490	* @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
<>	161:2cc1468da177	1491	* @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
<>	161:2cc1468da177	1492	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1493	* @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
<>	161:2cc1468da177	1494	* @retval None
<>	161:2cc1468da177	1495	*/
<>	161:2cc1468da177	1496	__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
<>	161:2cc1468da177	1497	{
<>	161:2cc1468da177	1498	MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
<>	161:2cc1468da177	1499	}
<>	161:2cc1468da177	1500
<>	161:2cc1468da177	1501	/**
<>	161:2cc1468da177	1502	* @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
<>	161:2cc1468da177	1503	* @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
<>	161:2cc1468da177	1504	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1505	* @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
<>	161:2cc1468da177	1506	*/
<>	161:2cc1468da177	1507	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1508	{
<>	161:2cc1468da177	1509	return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
<>	161:2cc1468da177	1510	}
<>	161:2cc1468da177	1511
<>	161:2cc1468da177	1512	/**
<>	161:2cc1468da177	1513	* @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
<>	161:2cc1468da177	1514	* @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
<>	161:2cc1468da177	1515	* @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
<>	161:2cc1468da177	1516	* @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
<>	161:2cc1468da177	1517	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1518	* @param Red Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1519	* @param Green Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1520	* @param Blue Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1521	* @retval None
<>	161:2cc1468da177	1522	*/
<>	161:2cc1468da177	1523	__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
<>	161:2cc1468da177	1524	{
<>	161:2cc1468da177	1525	MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED \| DMA2D_BGCOLR_GREEN \| DMA2D_BGCOLR_BLUE), \
<>	161:2cc1468da177	1526	((Red << DMA2D_BGCOLR_RED_Pos) \| (Green << DMA2D_BGCOLR_GREEN_Pos) \| Blue));
<>	161:2cc1468da177	1527	}
<>	161:2cc1468da177	1528
<>	161:2cc1468da177	1529	/**
<>	161:2cc1468da177	1530	* @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1531	* @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
<>	161:2cc1468da177	1532	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1533	* @param Red Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1534	* @retval None
<>	161:2cc1468da177	1535	*/
<>	161:2cc1468da177	1536	__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
<>	161:2cc1468da177	1537	{
<>	161:2cc1468da177	1538	MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
<>	161:2cc1468da177	1539	}
<>	161:2cc1468da177	1540
<>	161:2cc1468da177	1541	/**
<>	161:2cc1468da177	1542	* @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1543	* @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
<>	161:2cc1468da177	1544	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1545	* @retval Red color value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1546	*/
<>	161:2cc1468da177	1547	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1548	{
<>	161:2cc1468da177	1549	return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
<>	161:2cc1468da177	1550	}
<>	161:2cc1468da177	1551
<>	161:2cc1468da177	1552	/**
<>	161:2cc1468da177	1553	* @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1554	* @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
<>	161:2cc1468da177	1555	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1556	* @param Green Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1557	* @retval None
<>	161:2cc1468da177	1558	*/
<>	161:2cc1468da177	1559	__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
<>	161:2cc1468da177	1560	{
<>	161:2cc1468da177	1561	MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
<>	161:2cc1468da177	1562	}
<>	161:2cc1468da177	1563
<>	161:2cc1468da177	1564	/**
<>	161:2cc1468da177	1565	* @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1566	* @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
<>	161:2cc1468da177	1567	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1568	* @retval Green color value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1569	*/
<>	161:2cc1468da177	1570	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1571	{
<>	161:2cc1468da177	1572	return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
<>	161:2cc1468da177	1573	}
<>	161:2cc1468da177	1574
<>	161:2cc1468da177	1575	/**
<>	161:2cc1468da177	1576	* @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1577	* @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
<>	161:2cc1468da177	1578	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1579	* @param Blue Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1580	* @retval None
<>	161:2cc1468da177	1581	*/
<>	161:2cc1468da177	1582	__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
<>	161:2cc1468da177	1583	{
<>	161:2cc1468da177	1584	MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
<>	161:2cc1468da177	1585	}
<>	161:2cc1468da177	1586
<>	161:2cc1468da177	1587	/**
<>	161:2cc1468da177	1588	* @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1589	* @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
<>	161:2cc1468da177	1590	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1591	* @retval Blue color value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1592	*/
<>	161:2cc1468da177	1593	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1594	{
<>	161:2cc1468da177	1595	return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
<>	161:2cc1468da177	1596	}
<>	161:2cc1468da177	1597
<>	161:2cc1468da177	1598	/**
<>	161:2cc1468da177	1599	* @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	1600	* @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
<>	161:2cc1468da177	1601	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1602	* @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	1603	* @retval None
<>	161:2cc1468da177	1604	*/
<>	161:2cc1468da177	1605	__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
<>	161:2cc1468da177	1606	{
<>	161:2cc1468da177	1607	LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
<>	161:2cc1468da177	1608	}
<>	161:2cc1468da177	1609
<>	161:2cc1468da177	1610	/**
<>	161:2cc1468da177	1611	* @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
<>	161:2cc1468da177	1612	* @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
<>	161:2cc1468da177	1613	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1614	* @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	1615	*/
<>	161:2cc1468da177	1616	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1617	{
<>	161:2cc1468da177	1618	return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
<>	161:2cc1468da177	1619	}
<>	161:2cc1468da177	1620
<>	161:2cc1468da177	1621	/**
<>	161:2cc1468da177	1622	* @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1623	* @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
<>	161:2cc1468da177	1624	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1625	* @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1626	* @retval None
<>	161:2cc1468da177	1627	*/
<>	161:2cc1468da177	1628	__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
<>	161:2cc1468da177	1629	{
<>	161:2cc1468da177	1630	MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
<>	161:2cc1468da177	1631	}
<>	161:2cc1468da177	1632
<>	161:2cc1468da177	1633	/**
<>	161:2cc1468da177	1634	* @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
<>	161:2cc1468da177	1635	* @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
<>	161:2cc1468da177	1636	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1637	* @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
<>	161:2cc1468da177	1638	*/
<>	161:2cc1468da177	1639	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1640	{
<>	161:2cc1468da177	1641	return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
<>	161:2cc1468da177	1642	}
<>	161:2cc1468da177	1643
<>	161:2cc1468da177	1644	/**
<>	161:2cc1468da177	1645	* @brief Set DMA2D background CLUT color mode.
<>	161:2cc1468da177	1646	* @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
<>	161:2cc1468da177	1647	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1648	* @param CLUTColorMode This parameter can be one of the following values:
<>	161:2cc1468da177	1649	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
<>	161:2cc1468da177	1650	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
<>	161:2cc1468da177	1651	* @retval None
<>	161:2cc1468da177	1652	*/
<>	161:2cc1468da177	1653	__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
<>	161:2cc1468da177	1654	{
<>	161:2cc1468da177	1655	MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
<>	161:2cc1468da177	1656	}
<>	161:2cc1468da177	1657
<>	161:2cc1468da177	1658	/**
<>	161:2cc1468da177	1659	* @brief Return DMA2D background CLUT color mode.
<>	161:2cc1468da177	1660	* @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
<>	161:2cc1468da177	1661	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1662	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1663	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
<>	161:2cc1468da177	1664	* @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
<>	161:2cc1468da177	1665	*/
<>	161:2cc1468da177	1666	__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1667	{
<>	161:2cc1468da177	1668	return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
<>	161:2cc1468da177	1669	}
<>	161:2cc1468da177	1670
<>	161:2cc1468da177	1671	/**
<>	161:2cc1468da177	1672	* @}
<>	161:2cc1468da177	1673	*/
<>	161:2cc1468da177	1674
<>	161:2cc1468da177	1675	/**
<>	161:2cc1468da177	1676	* @}
<>	161:2cc1468da177	1677	*/
<>	161:2cc1468da177	1678
<>	161:2cc1468da177	1679
<>	161:2cc1468da177	1680	/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
<>	161:2cc1468da177	1681	* @{
<>	161:2cc1468da177	1682	*/
<>	161:2cc1468da177	1683
<>	161:2cc1468da177	1684	/**
<>	161:2cc1468da177	1685	* @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
<>	161:2cc1468da177	1686	* @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
<>	161:2cc1468da177	1687	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1688	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1689	*/
<>	161:2cc1468da177	1690	__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1691	{
<>	161:2cc1468da177	1692	return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF));
<>	161:2cc1468da177	1693	}
<>	161:2cc1468da177	1694
<>	161:2cc1468da177	1695	/**
<>	161:2cc1468da177	1696	* @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
<>	161:2cc1468da177	1697	* @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
<>	161:2cc1468da177	1698	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1699	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1700	*/
<>	161:2cc1468da177	1701	__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1702	{
<>	161:2cc1468da177	1703	return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF));
<>	161:2cc1468da177	1704	}
<>	161:2cc1468da177	1705
<>	161:2cc1468da177	1706	/**
<>	161:2cc1468da177	1707	* @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
<>	161:2cc1468da177	1708	* @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
<>	161:2cc1468da177	1709	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1710	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1711	*/
<>	161:2cc1468da177	1712	__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1713	{
<>	161:2cc1468da177	1714	return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF));
<>	161:2cc1468da177	1715	}
<>	161:2cc1468da177	1716
<>	161:2cc1468da177	1717	/**
<>	161:2cc1468da177	1718	* @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
<>	161:2cc1468da177	1719	* @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
<>	161:2cc1468da177	1720	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1721	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1722	*/
<>	161:2cc1468da177	1723	__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1724	{
<>	161:2cc1468da177	1725	return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF));
<>	161:2cc1468da177	1726	}
<>	161:2cc1468da177	1727
<>	161:2cc1468da177	1728	/**
<>	161:2cc1468da177	1729	* @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
<>	161:2cc1468da177	1730	* @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
<>	161:2cc1468da177	1731	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1732	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1733	*/
<>	161:2cc1468da177	1734	__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1735	{
<>	161:2cc1468da177	1736	return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF));
<>	161:2cc1468da177	1737	}
<>	161:2cc1468da177	1738
<>	161:2cc1468da177	1739	/**
<>	161:2cc1468da177	1740	* @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
<>	161:2cc1468da177	1741	* @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
<>	161:2cc1468da177	1742	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1743	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1744	*/
<>	161:2cc1468da177	1745	__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1746	{
<>	161:2cc1468da177	1747	return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF));
<>	161:2cc1468da177	1748	}
<>	161:2cc1468da177	1749
<>	161:2cc1468da177	1750	/**
<>	161:2cc1468da177	1751	* @brief Clear DMA2D Configuration Error Interrupt Flag
<>	161:2cc1468da177	1752	* @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
<>	161:2cc1468da177	1753	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1754	* @retval None
<>	161:2cc1468da177	1755	*/
<>	161:2cc1468da177	1756	__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1757	{
<>	161:2cc1468da177	1758	WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
<>	161:2cc1468da177	1759	}
<>	161:2cc1468da177	1760
<>	161:2cc1468da177	1761	/**
<>	161:2cc1468da177	1762	* @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
<>	161:2cc1468da177	1763	* @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
<>	161:2cc1468da177	1764	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1765	* @retval None
<>	161:2cc1468da177	1766	*/
<>	161:2cc1468da177	1767	__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1768	{
<>	161:2cc1468da177	1769	WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
<>	161:2cc1468da177	1770	}
<>	161:2cc1468da177	1771
<>	161:2cc1468da177	1772	/**
<>	161:2cc1468da177	1773	* @brief Clear DMA2D CLUT Access Error Interrupt Flag
<>	161:2cc1468da177	1774	* @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
<>	161:2cc1468da177	1775	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1776	* @retval None
<>	161:2cc1468da177	1777	*/
<>	161:2cc1468da177	1778	__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1779	{
<>	161:2cc1468da177	1780	WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
<>	161:2cc1468da177	1781	}
<>	161:2cc1468da177	1782
<>	161:2cc1468da177	1783	/**
<>	161:2cc1468da177	1784	* @brief Clear DMA2D Transfer Watermark Interrupt Flag
<>	161:2cc1468da177	1785	* @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
<>	161:2cc1468da177	1786	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1787	* @retval None
<>	161:2cc1468da177	1788	*/
<>	161:2cc1468da177	1789	__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1790	{
<>	161:2cc1468da177	1791	WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
<>	161:2cc1468da177	1792	}
<>	161:2cc1468da177	1793
<>	161:2cc1468da177	1794	/**
<>	161:2cc1468da177	1795	* @brief Clear DMA2D Transfer Complete Interrupt Flag
<>	161:2cc1468da177	1796	* @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
<>	161:2cc1468da177	1797	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1798	* @retval None
<>	161:2cc1468da177	1799	*/
<>	161:2cc1468da177	1800	__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1801	{
<>	161:2cc1468da177	1802	WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
<>	161:2cc1468da177	1803	}
<>	161:2cc1468da177	1804
<>	161:2cc1468da177	1805	/**
<>	161:2cc1468da177	1806	* @brief Clear DMA2D Transfer Error Interrupt Flag
<>	161:2cc1468da177	1807	* @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
<>	161:2cc1468da177	1808	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1809	* @retval None
<>	161:2cc1468da177	1810	*/
<>	161:2cc1468da177	1811	__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1812	{
<>	161:2cc1468da177	1813	WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
<>	161:2cc1468da177	1814	}
<>	161:2cc1468da177	1815
<>	161:2cc1468da177	1816	/**
<>	161:2cc1468da177	1817	* @}
<>	161:2cc1468da177	1818	*/
<>	161:2cc1468da177	1819
<>	161:2cc1468da177	1820	/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
<>	161:2cc1468da177	1821	* @{
<>	161:2cc1468da177	1822	*/
<>	161:2cc1468da177	1823
<>	161:2cc1468da177	1824	/**
<>	161:2cc1468da177	1825	* @brief Enable Configuration Error Interrupt
<>	161:2cc1468da177	1826	* @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
<>	161:2cc1468da177	1827	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1828	* @retval None
<>	161:2cc1468da177	1829	*/
<>	161:2cc1468da177	1830	__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1831	{
<>	161:2cc1468da177	1832	SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
<>	161:2cc1468da177	1833	}
<>	161:2cc1468da177	1834
<>	161:2cc1468da177	1835	/**
<>	161:2cc1468da177	1836	* @brief Enable CLUT Transfer Complete Interrupt
<>	161:2cc1468da177	1837	* @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
<>	161:2cc1468da177	1838	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1839	* @retval None
<>	161:2cc1468da177	1840	*/
<>	161:2cc1468da177	1841	__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1842	{
<>	161:2cc1468da177	1843	SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
<>	161:2cc1468da177	1844	}
<>	161:2cc1468da177	1845
<>	161:2cc1468da177	1846	/**
<>	161:2cc1468da177	1847	* @brief Enable CLUT Access Error Interrupt
<>	161:2cc1468da177	1848	* @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
<>	161:2cc1468da177	1849	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1850	* @retval None
<>	161:2cc1468da177	1851	*/
<>	161:2cc1468da177	1852	__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1853	{
<>	161:2cc1468da177	1854	SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
<>	161:2cc1468da177	1855	}
<>	161:2cc1468da177	1856
<>	161:2cc1468da177	1857	/**
<>	161:2cc1468da177	1858	* @brief Enable Transfer Watermark Interrupt
<>	161:2cc1468da177	1859	* @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
<>	161:2cc1468da177	1860	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1861	* @retval None
<>	161:2cc1468da177	1862	*/
<>	161:2cc1468da177	1863	__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1864	{
<>	161:2cc1468da177	1865	SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
<>	161:2cc1468da177	1866	}
<>	161:2cc1468da177	1867
<>	161:2cc1468da177	1868	/**
<>	161:2cc1468da177	1869	* @brief Enable Transfer Complete Interrupt
<>	161:2cc1468da177	1870	* @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
<>	161:2cc1468da177	1871	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1872	* @retval None
<>	161:2cc1468da177	1873	*/
<>	161:2cc1468da177	1874	__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1875	{
<>	161:2cc1468da177	1876	SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
<>	161:2cc1468da177	1877	}
<>	161:2cc1468da177	1878
<>	161:2cc1468da177	1879	/**
<>	161:2cc1468da177	1880	* @brief Enable Transfer Error Interrupt
<>	161:2cc1468da177	1881	* @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
<>	161:2cc1468da177	1882	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1883	* @retval None
<>	161:2cc1468da177	1884	*/
<>	161:2cc1468da177	1885	__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1886	{
<>	161:2cc1468da177	1887	SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
<>	161:2cc1468da177	1888	}
<>	161:2cc1468da177	1889
<>	161:2cc1468da177	1890	/**
<>	161:2cc1468da177	1891	* @brief Disable Configuration Error Interrupt
<>	161:2cc1468da177	1892	* @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
<>	161:2cc1468da177	1893	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1894	* @retval None
<>	161:2cc1468da177	1895	*/
<>	161:2cc1468da177	1896	__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1897	{
<>	161:2cc1468da177	1898	CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
<>	161:2cc1468da177	1899	}
<>	161:2cc1468da177	1900
<>	161:2cc1468da177	1901	/**
<>	161:2cc1468da177	1902	* @brief Disable CLUT Transfer Complete Interrupt
<>	161:2cc1468da177	1903	* @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
<>	161:2cc1468da177	1904	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1905	* @retval None
<>	161:2cc1468da177	1906	*/
<>	161:2cc1468da177	1907	__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1908	{
<>	161:2cc1468da177	1909	CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
<>	161:2cc1468da177	1910	}
<>	161:2cc1468da177	1911
<>	161:2cc1468da177	1912	/**
<>	161:2cc1468da177	1913	* @brief Disable CLUT Access Error Interrupt
<>	161:2cc1468da177	1914	* @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
<>	161:2cc1468da177	1915	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1916	* @retval None
<>	161:2cc1468da177	1917	*/
<>	161:2cc1468da177	1918	__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1919	{
<>	161:2cc1468da177	1920	CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
<>	161:2cc1468da177	1921	}
<>	161:2cc1468da177	1922
<>	161:2cc1468da177	1923	/**
<>	161:2cc1468da177	1924	* @brief Disable Transfer Watermark Interrupt
<>	161:2cc1468da177	1925	* @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
<>	161:2cc1468da177	1926	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1927	* @retval None
<>	161:2cc1468da177	1928	*/
<>	161:2cc1468da177	1929	__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1930	{
<>	161:2cc1468da177	1931	CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
<>	161:2cc1468da177	1932	}
<>	161:2cc1468da177	1933
<>	161:2cc1468da177	1934	/**
<>	161:2cc1468da177	1935	* @brief Disable Transfer Complete Interrupt
<>	161:2cc1468da177	1936	* @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
<>	161:2cc1468da177	1937	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1938	* @retval None
<>	161:2cc1468da177	1939	*/
<>	161:2cc1468da177	1940	__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1941	{
<>	161:2cc1468da177	1942	CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
<>	161:2cc1468da177	1943	}
<>	161:2cc1468da177	1944
<>	161:2cc1468da177	1945	/**
<>	161:2cc1468da177	1946	* @brief Disable Transfer Error Interrupt
<>	161:2cc1468da177	1947	* @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
<>	161:2cc1468da177	1948	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1949	* @retval None
<>	161:2cc1468da177	1950	*/
<>	161:2cc1468da177	1951	__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1952	{
<>	161:2cc1468da177	1953	CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
<>	161:2cc1468da177	1954	}
<>	161:2cc1468da177	1955
<>	161:2cc1468da177	1956	/**
<>	161:2cc1468da177	1957	* @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
<>	161:2cc1468da177	1958	* @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
<>	161:2cc1468da177	1959	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1960	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1961	*/
<>	161:2cc1468da177	1962	__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1963	{
<>	161:2cc1468da177	1964	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE));
<>	161:2cc1468da177	1965	}
<>	161:2cc1468da177	1966
<>	161:2cc1468da177	1967	/**
<>	161:2cc1468da177	1968	* @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
<>	161:2cc1468da177	1969	* @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
<>	161:2cc1468da177	1970	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1971	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1972	*/
<>	161:2cc1468da177	1973	__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1974	{
<>	161:2cc1468da177	1975	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE));
<>	161:2cc1468da177	1976	}
<>	161:2cc1468da177	1977
<>	161:2cc1468da177	1978	/**
<>	161:2cc1468da177	1979	* @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
<>	161:2cc1468da177	1980	* @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
<>	161:2cc1468da177	1981	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1982	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1983	*/
<>	161:2cc1468da177	1984	__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1985	{
<>	161:2cc1468da177	1986	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE));
<>	161:2cc1468da177	1987	}
<>	161:2cc1468da177	1988
<>	161:2cc1468da177	1989	/**
<>	161:2cc1468da177	1990	* @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
<>	161:2cc1468da177	1991	* @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
<>	161:2cc1468da177	1992	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	1993	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1994	*/
<>	161:2cc1468da177	1995	__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	1996	{
<>	161:2cc1468da177	1997	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE));
<>	161:2cc1468da177	1998	}
<>	161:2cc1468da177	1999
<>	161:2cc1468da177	2000	/**
<>	161:2cc1468da177	2001	* @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
<>	161:2cc1468da177	2002	* @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
<>	161:2cc1468da177	2003	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	2004	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2005	*/
<>	161:2cc1468da177	2006	__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	2007	{
<>	161:2cc1468da177	2008	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE));
<>	161:2cc1468da177	2009	}
<>	161:2cc1468da177	2010
<>	161:2cc1468da177	2011	/**
<>	161:2cc1468da177	2012	* @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
<>	161:2cc1468da177	2013	* @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
<>	161:2cc1468da177	2014	* @param DMA2Dx DMA2D Instance
<>	161:2cc1468da177	2015	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2016	*/
<>	161:2cc1468da177	2017	__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
<>	161:2cc1468da177	2018	{
<>	161:2cc1468da177	2019	return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE));
<>	161:2cc1468da177	2020	}
<>	161:2cc1468da177	2021
<>	161:2cc1468da177	2022
<>	161:2cc1468da177	2023
<>	161:2cc1468da177	2024	/**
<>	161:2cc1468da177	2025	* @}
<>	161:2cc1468da177	2026	*/
<>	161:2cc1468da177	2027
<>	161:2cc1468da177	2028	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	2029	/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
<>	161:2cc1468da177	2030	* @{
<>	161:2cc1468da177	2031	*/
<>	161:2cc1468da177	2032
<>	161:2cc1468da177	2033	ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
<>	161:2cc1468da177	2034	ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef DMA2Dx, LL_DMA2D_InitTypeDef DMA2D_InitStruct);
<>	161:2cc1468da177	2035	void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
<>	161:2cc1468da177	2036	void LL_DMA2D_ConfigLayer(DMA2D_TypeDef DMA2Dx, LL_DMA2D_LayerCfgTypeDef DMA2D_LayerCfg, uint32_t LayerIdx);
<>	161:2cc1468da177	2037	void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
<>	161:2cc1468da177	2038	void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef DMA2Dx, LL_DMA2D_ColorTypeDef DMA2D_ColorStruct);
<>	161:2cc1468da177	2039	uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
<>	161:2cc1468da177	2040	uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
<>	161:2cc1468da177	2041	uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
<>	161:2cc1468da177	2042	uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
<>	161:2cc1468da177	2043	void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
<>	161:2cc1468da177	2044
<>	161:2cc1468da177	2045	/**
<>	161:2cc1468da177	2046	* @}
<>	161:2cc1468da177	2047	*/
<>	161:2cc1468da177	2048	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	2049
<>	161:2cc1468da177	2050	/**
<>	161:2cc1468da177	2051	* @}
<>	161:2cc1468da177	2052	*/
<>	161:2cc1468da177	2053
<>	161:2cc1468da177	2054	/**
<>	161:2cc1468da177	2055	* @}
<>	161:2cc1468da177	2056	*/
<>	161:2cc1468da177	2057
<>	161:2cc1468da177	2058	#endif /* defined (DMA2D) */
<>	161:2cc1468da177	2059
<>	161:2cc1468da177	2060	/**
<>	161:2cc1468da177	2061	* @}
<>	161:2cc1468da177	2062	*/
<>	161:2cc1468da177	2063
<>	161:2cc1468da177	2064	#ifdef __cplusplus
<>	161:2cc1468da177	2065	}
<>	161:2cc1468da177	2066	#endif
<>	161:2cc1468da177	2067
<>	161:2cc1468da177	2068	#endif /* __STM32F7xx_LL_DMA2D_H */
<>	161:2cc1468da177	2069
<>	161:2cc1468da177	2070	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/