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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_adc.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief Header file of ADC LL module.
<>	161:2cc1468da177	8	******************************************************************************
<>	161:2cc1468da177	9	* @attention
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	12	*
<>	161:2cc1468da177	13	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	14	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	18	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	19	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	21	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	22	* without specific prior written permission.
<>	161:2cc1468da177	23	*
<>	161:2cc1468da177	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	34	*
<>	161:2cc1468da177	35	******************************************************************************
<>	161:2cc1468da177	36	*/
<>	161:2cc1468da177	37
<>	161:2cc1468da177	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	39	#ifndef __STM32F7xx_LL_ADC_H
<>	161:2cc1468da177	40	#define __STM32F7xx_LL_ADC_H
<>	161:2cc1468da177	41
<>	161:2cc1468da177	42	#ifdef __cplusplus
<>	161:2cc1468da177	43	extern "C" {
<>	161:2cc1468da177	44	#endif
<>	161:2cc1468da177	45
<>	161:2cc1468da177	46	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	47	#include "stm32f7xx.h"
<>	161:2cc1468da177	48
<>	161:2cc1468da177	49	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	50	* @{
<>	161:2cc1468da177	51	*/
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	#if defined (ADC1) \|\| defined (ADC2) \|\| defined (ADC3)
<>	161:2cc1468da177	54
<>	161:2cc1468da177	55	/** @defgroup ADC_LL ADC
<>	161:2cc1468da177	56	* @{
<>	161:2cc1468da177	57	*/
<>	161:2cc1468da177	58
<>	161:2cc1468da177	59	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	60	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	61
<>	161:2cc1468da177	62	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	63	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
<>	161:2cc1468da177	64	* @{
<>	161:2cc1468da177	65	*/
<>	161:2cc1468da177	66
<>	161:2cc1468da177	67	/* Internal mask for ADC group regular sequencer: */
<>	161:2cc1468da177	68	/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
<>	161:2cc1468da177	69	/* - sequencer register offset */
<>	161:2cc1468da177	70	/* - sequencer rank bits position into the selected register */
<>	161:2cc1468da177	71
<>	161:2cc1468da177	72	/* Internal register offset for ADC group regular sequencer configuration */
<>	161:2cc1468da177	73	/* (offset placed into a spare area of literal definition) */
<>	161:2cc1468da177	74	#define ADC_SQR1_REGOFFSET (0x00000000U)
<>	161:2cc1468da177	75	#define ADC_SQR2_REGOFFSET (0x00000100U)
<>	161:2cc1468da177	76	#define ADC_SQR3_REGOFFSET (0x00000200U)
<>	161:2cc1468da177	77	#define ADC_SQR4_REGOFFSET (0x00000300U)
<>	161:2cc1468da177	78
<>	161:2cc1468da177	79	#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET \| ADC_SQR2_REGOFFSET \| ADC_SQR3_REGOFFSET \| ADC_SQR4_REGOFFSET)
<>	161:2cc1468da177	80	#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	161:2cc1468da177	81
<>	161:2cc1468da177	82	/* Definition of ADC group regular sequencer bits information to be inserted */
<>	161:2cc1468da177	83	/* into ADC group regular sequencer ranks literals definition. */
<>	161:2cc1468da177	84	#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
<>	161:2cc1468da177	85	#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
<>	161:2cc1468da177	86	#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
<>	161:2cc1468da177	87	#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
<>	161:2cc1468da177	88	#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
<>	161:2cc1468da177	89	#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
<>	161:2cc1468da177	90	#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
<>	161:2cc1468da177	91	#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
<>	161:2cc1468da177	92	#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
<>	161:2cc1468da177	93	#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
<>	161:2cc1468da177	94	#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
<>	161:2cc1468da177	95	#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
<>	161:2cc1468da177	96	#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
<>	161:2cc1468da177	97	#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
<>	161:2cc1468da177	98	#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
<>	161:2cc1468da177	99	#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
<>	161:2cc1468da177	100
<>	161:2cc1468da177	101
<>	161:2cc1468da177	102
<>	161:2cc1468da177	103	/* Internal mask for ADC group injected sequencer: */
<>	161:2cc1468da177	104	/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
<>	161:2cc1468da177	105	/* - data register offset */
<>	161:2cc1468da177	106	/* - offset register offset */
<>	161:2cc1468da177	107	/* - sequencer rank bits position into the selected register */
<>	161:2cc1468da177	108
<>	161:2cc1468da177	109	/* Internal register offset for ADC group injected data register */
<>	161:2cc1468da177	110	/* (offset placed into a spare area of literal definition) */
<>	161:2cc1468da177	111	#define ADC_JDR1_REGOFFSET (0x00000000U)
<>	161:2cc1468da177	112	#define ADC_JDR2_REGOFFSET (0x00000100U)
<>	161:2cc1468da177	113	#define ADC_JDR3_REGOFFSET (0x00000200U)
<>	161:2cc1468da177	114	#define ADC_JDR4_REGOFFSET (0x00000300U)
<>	161:2cc1468da177	115
<>	161:2cc1468da177	116	/* Internal register offset for ADC group injected offset configuration */
<>	161:2cc1468da177	117	/* (offset placed into a spare area of literal definition) */
<>	161:2cc1468da177	118	#define ADC_JOFR1_REGOFFSET (0x00000000U)
<>	161:2cc1468da177	119	#define ADC_JOFR2_REGOFFSET (0x00001000U)
<>	161:2cc1468da177	120	#define ADC_JOFR3_REGOFFSET (0x00002000U)
<>	161:2cc1468da177	121	#define ADC_JOFR4_REGOFFSET (0x00003000U)
<>	161:2cc1468da177	122
<>	161:2cc1468da177	123	#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET \| ADC_JDR2_REGOFFSET \| ADC_JDR3_REGOFFSET \| ADC_JDR4_REGOFFSET)
<>	161:2cc1468da177	124	#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_JOFR4_REGOFFSET)
<>	161:2cc1468da177	125	#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
<>	161:2cc1468da177	126
<>	161:2cc1468da177	127	/* Definition of ADC group injected sequencer bits information to be inserted */
<>	161:2cc1468da177	128	/* into ADC group injected sequencer ranks literals definition. */
<>	161:2cc1468da177	129	#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
<>	161:2cc1468da177	130	#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
<>	161:2cc1468da177	131	#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
<>	161:2cc1468da177	132	#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
<>	161:2cc1468da177	133
<>	161:2cc1468da177	134
<>	161:2cc1468da177	135
<>	161:2cc1468da177	136	/* Internal mask for ADC group regular trigger: */
<>	161:2cc1468da177	137	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
<>	161:2cc1468da177	138	/* - regular trigger source */
<>	161:2cc1468da177	139	/* - regular trigger edge */
<>	161:2cc1468da177	140	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	161:2cc1468da177	141
<>	161:2cc1468da177	142	/* Mask containing trigger source masks for each of possible */
<>	161:2cc1468da177	143	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	161:2cc1468da177	144	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	161:2cc1468da177	145	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) \| \
<>	161:2cc1468da177	146	((ADC_CR2_EXTSEL) >> (4U * 1U)) \| \
<>	161:2cc1468da177	147	((ADC_CR2_EXTSEL) >> (4U * 2U)) \| \
<>	161:2cc1468da177	148	((ADC_CR2_EXTSEL) >> (4U * 3U)) )
<>	161:2cc1468da177	149
<>	161:2cc1468da177	150	/* Mask containing trigger edge masks for each of possible */
<>	161:2cc1468da177	151	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	161:2cc1468da177	152	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	161:2cc1468da177	153	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) \| \
<>	161:2cc1468da177	154	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) \| \
<>	161:2cc1468da177	155	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) \| \
<>	161:2cc1468da177	156	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
<>	161:2cc1468da177	157
<>	161:2cc1468da177	158	/* Definition of ADC group regular trigger bits information. */
<>	161:2cc1468da177	159	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
<>	161:2cc1468da177	160	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
<>	161:2cc1468da177	161
<>	161:2cc1468da177	162
<>	161:2cc1468da177	163
<>	161:2cc1468da177	164	/* Internal mask for ADC group injected trigger: */
<>	161:2cc1468da177	165	/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
<>	161:2cc1468da177	166	/* - injected trigger source */
<>	161:2cc1468da177	167	/* - injected trigger edge */
<>	161:2cc1468da177	168	#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	161:2cc1468da177	169
<>	161:2cc1468da177	170	/* Mask containing trigger source masks for each of possible */
<>	161:2cc1468da177	171	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	161:2cc1468da177	172	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	161:2cc1468da177	173	#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) \| \
<>	161:2cc1468da177	174	((ADC_CR2_JEXTSEL) >> (4U * 1U)) \| \
<>	161:2cc1468da177	175	((ADC_CR2_JEXTSEL) >> (4U * 2U)) \| \
<>	161:2cc1468da177	176	((ADC_CR2_JEXTSEL) >> (4U * 3U)) )
<>	161:2cc1468da177	177
<>	161:2cc1468da177	178	/* Mask containing trigger edge masks for each of possible */
<>	161:2cc1468da177	179	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	161:2cc1468da177	180	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	161:2cc1468da177	181	#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) \| \
<>	161:2cc1468da177	182	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) \| \
<>	161:2cc1468da177	183	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) \| \
<>	161:2cc1468da177	184	((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U)) )
<>	161:2cc1468da177	185
<>	161:2cc1468da177	186	/* Definition of ADC group injected trigger bits information. */
<>	161:2cc1468da177	187	#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
<>	161:2cc1468da177	188	#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
<>	161:2cc1468da177	189
<>	161:2cc1468da177	190
<>	161:2cc1468da177	191
<>	161:2cc1468da177	192
<>	161:2cc1468da177	193
<>	161:2cc1468da177	194
<>	161:2cc1468da177	195	/* Internal mask for ADC channel: */
<>	161:2cc1468da177	196	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
<>	161:2cc1468da177	197	/* - channel identifier defined by number */
<>	161:2cc1468da177	198	/* - channel differentiation between external channels (connected to */
<>	161:2cc1468da177	199	/* GPIO pins) and internal channels (connected to internal paths) */
<>	161:2cc1468da177	200	/* - channel sampling time defined by SMPRx register offset */
<>	161:2cc1468da177	201	/* and SMPx bits positions into SMPRx register */
<>	161:2cc1468da177	202	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
<>	161:2cc1468da177	203	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
<>	161:2cc1468da177	204	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	161:2cc1468da177	205	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
<>	161:2cc1468da177	206	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
<>	161:2cc1468da177	207
<>	161:2cc1468da177	208	/* Channel differentiation between external and internal channels */
<>	161:2cc1468da177	209	#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */
<>	161:2cc1468da177	210	#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x40000000U) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
<>	161:2cc1468da177	211	#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT (0x10000000U) /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
<>	161:2cc1468da177	212	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH \| ADC_CHANNEL_ID_INTERNAL_CH_2 \| ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
<>	161:2cc1468da177	213
<>	161:2cc1468da177	214	/* Internal register offset for ADC channel sampling time configuration */
<>	161:2cc1468da177	215	/* (offset placed into a spare area of literal definition) */
<>	161:2cc1468da177	216	#define ADC_SMPR1_REGOFFSET (0x00000000U)
<>	161:2cc1468da177	217	#define ADC_SMPR2_REGOFFSET (0x02000000U)
<>	161:2cc1468da177	218	#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET \| ADC_SMPR2_REGOFFSET)
<>	161:2cc1468da177	219
<>	161:2cc1468da177	220	#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000U)
<>	161:2cc1468da177	221	#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
<>	161:2cc1468da177	222
<>	161:2cc1468da177	223	/* Definition of channels ID number information to be inserted into */
<>	161:2cc1468da177	224	/* channels literals definition. */
<>	161:2cc1468da177	225	#define ADC_CHANNEL_0_NUMBER (0x00000000U)
<>	161:2cc1468da177	226	#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	227	#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
<>	161:2cc1468da177	228	#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	229	#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
<>	161:2cc1468da177	230	#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	231	#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	161:2cc1468da177	232	#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	233	#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
<>	161:2cc1468da177	234	#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	235	#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 )
<>	161:2cc1468da177	236	#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	237	#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 )
<>	161:2cc1468da177	238	#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	239	#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 )
<>	161:2cc1468da177	240	#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	241	#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
<>	161:2cc1468da177	242	#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0)
<>	161:2cc1468da177	243	#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1 )
<>	161:2cc1468da177	244
<>	161:2cc1468da177	245	/* Definition of channels sampling time information to be inserted into */
<>	161:2cc1468da177	246	/* channels literals definition. */
<>	161:2cc1468da177	247	#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
<>	161:2cc1468da177	248	#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
<>	161:2cc1468da177	249	#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
<>	161:2cc1468da177	250	#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
<>	161:2cc1468da177	251	#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
<>	161:2cc1468da177	252	#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
<>	161:2cc1468da177	253	#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
<>	161:2cc1468da177	254	#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
<>	161:2cc1468da177	255	#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
<>	161:2cc1468da177	256	#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET \| ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
<>	161:2cc1468da177	257	#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET \| (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
<>	161:2cc1468da177	258	#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET \| (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
<>	161:2cc1468da177	259	#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET \| (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
<>	161:2cc1468da177	260	#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET \| (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
<>	161:2cc1468da177	261	#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET \| ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
<>	161:2cc1468da177	262	#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET \| ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
<>	161:2cc1468da177	263	#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET \| ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
<>	161:2cc1468da177	264	#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET \| ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
<>	161:2cc1468da177	265	#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET \| ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
<>	161:2cc1468da177	266
<>	161:2cc1468da177	267
<>	161:2cc1468da177	268	/* Internal mask for ADC analog watchdog: */
<>	161:2cc1468da177	269	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
<>	161:2cc1468da177	270	/* (concatenation of multiple bits used in different analog watchdogs, */
<>	161:2cc1468da177	271	/* (feature of several watchdogs not available on all STM32 families)). */
<>	161:2cc1468da177	272	/* - analog watchdog 1: monitored channel defined by number, */
<>	161:2cc1468da177	273	/* selection of ADC group (ADC groups regular and-or injected). */
<>	161:2cc1468da177	274
<>	161:2cc1468da177	275	/* Internal register offset for ADC analog watchdog channel configuration */
<>	161:2cc1468da177	276	#define ADC_AWD_CR1_REGOFFSET (0x00000000U)
<>	161:2cc1468da177	277
<>	161:2cc1468da177	278	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
<>	161:2cc1468da177	279
<>	161:2cc1468da177	280	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL)
<>	161:2cc1468da177	281	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
<>	161:2cc1468da177	282
<>	161:2cc1468da177	283	/* Internal register offset for ADC analog watchdog threshold configuration */
<>	161:2cc1468da177	284	#define ADC_AWD_TR1_HIGH_REGOFFSET (0x00000000U)
<>	161:2cc1468da177	285	#define ADC_AWD_TR1_LOW_REGOFFSET (0x00000001U)
<>	161:2cc1468da177	286	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET \| ADC_AWD_TR1_LOW_REGOFFSET)
<>	161:2cc1468da177	287
<>	161:2cc1468da177	288
<>	161:2cc1468da177	289	/* ADC registers bits positions */
<>	161:2cc1468da177	290	#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
<>	161:2cc1468da177	291	#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
<>	161:2cc1468da177	292
<>	161:2cc1468da177	293
<>	161:2cc1468da177	294	/* ADC internal channels related definitions */
<>	161:2cc1468da177	295	/* Internal voltage reference VrefInt */
<>	161:2cc1468da177	296	#define VREFINT_CAL_ADDR ((uint16_t) (0x1FF07A4A)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	161:2cc1468da177	297	#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
<>	161:2cc1468da177	298	/* Temperature sensor */
<>	161:2cc1468da177	299	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) (0x1FF07A4C)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	161:2cc1468da177	300	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) (0x1FF07A4E)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	161:2cc1468da177	301	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	161:2cc1468da177	302	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	161:2cc1468da177	303	#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
<>	161:2cc1468da177	304
<>	161:2cc1468da177	305	/**
<>	161:2cc1468da177	306	* @}
<>	161:2cc1468da177	307	*/
<>	161:2cc1468da177	308
<>	161:2cc1468da177	309
<>	161:2cc1468da177	310	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	311	/** @defgroup ADC_LL_Private_Macros ADC Private Macros
<>	161:2cc1468da177	312	* @{
<>	161:2cc1468da177	313	*/
<>	161:2cc1468da177	314
<>	161:2cc1468da177	315	/**
<>	161:2cc1468da177	316	* @brief Driver macro reserved for internal use: isolate bits with the
<>	161:2cc1468da177	317	* selected mask and shift them to the register LSB
<>	161:2cc1468da177	318	* (shift mask on register position bit 0).
<>	161:2cc1468da177	319	* @param __BITS__ Bits in register 32 bits
<>	161:2cc1468da177	320	* @param __MASK__ Mask in register 32 bits
<>	161:2cc1468da177	321	* @retval Bits in register 32 bits
<>	161:2cc1468da177	322	*/
<>	161:2cc1468da177	323	#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
<>	161:2cc1468da177	324	(((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
<>	161:2cc1468da177	325
<>	161:2cc1468da177	326	/**
<>	161:2cc1468da177	327	* @brief Driver macro reserved for internal use: set a pointer to
<>	161:2cc1468da177	328	* a register from a register basis from which an offset
<>	161:2cc1468da177	329	* is applied.
<>	161:2cc1468da177	330	* @param __REG__ Register basis from which the offset is applied.
<>	161:2cc1468da177	331	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
<>	161:2cc1468da177	332	* @retval Pointer to register address
<>	161:2cc1468da177	333	*/
<>	161:2cc1468da177	334	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
<>	161:2cc1468da177	335	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
<>	161:2cc1468da177	336
<>	161:2cc1468da177	337	/**
<>	161:2cc1468da177	338	* @}
<>	161:2cc1468da177	339	*/
<>	161:2cc1468da177	340
<>	161:2cc1468da177	341
<>	161:2cc1468da177	342	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	343	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	344	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
<>	161:2cc1468da177	345	* @{
<>	161:2cc1468da177	346	*/
<>	161:2cc1468da177	347
<>	161:2cc1468da177	348	/**
<>	161:2cc1468da177	349	* @brief Structure definition of some features of ADC common parameters
<>	161:2cc1468da177	350	* and multimode
<>	161:2cc1468da177	351	* (all ADC instances belonging to the same ADC common instance).
<>	161:2cc1468da177	352	* @note The setting of these parameters by function @ref LL_ADC_CommonInit()
<>	161:2cc1468da177	353	* is conditioned to ADC instances state (all ADC instances
<>	161:2cc1468da177	354	* sharing the same ADC common instance):
<>	161:2cc1468da177	355	* All ADC instances sharing the same ADC common instance must be
<>	161:2cc1468da177	356	* disabled.
<>	161:2cc1468da177	357	*/
<>	161:2cc1468da177	358	typedef struct
<>	161:2cc1468da177	359	{
<>	161:2cc1468da177	360	uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
<>	161:2cc1468da177	361	This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
<>	161:2cc1468da177	362
<>	161:2cc1468da177	363	This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
<>	161:2cc1468da177	364
<>	161:2cc1468da177	365	uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
<>	161:2cc1468da177	366	This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
<>	161:2cc1468da177	367
<>	161:2cc1468da177	368	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
<>	161:2cc1468da177	369
<>	161:2cc1468da177	370	uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
<>	161:2cc1468da177	371	This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
<>	161:2cc1468da177	372
<>	161:2cc1468da177	373	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
<>	161:2cc1468da177	374
<>	161:2cc1468da177	375	uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
<>	161:2cc1468da177	376	This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
<>	161:2cc1468da177	377
<>	161:2cc1468da177	378	This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
<>	161:2cc1468da177	379
<>	161:2cc1468da177	380	} LL_ADC_CommonInitTypeDef;
<>	161:2cc1468da177	381
<>	161:2cc1468da177	382	/**
<>	161:2cc1468da177	383	* @brief Structure definition of some features of ADC instance.
<>	161:2cc1468da177	384	* @note These parameters have an impact on ADC scope: ADC instance.
<>	161:2cc1468da177	385	* Affects both group regular and group injected (availability
<>	161:2cc1468da177	386	* of ADC group injected depends on STM32 families).
<>	161:2cc1468da177	387	* Refer to corresponding unitary functions into
<>	161:2cc1468da177	388	* @ref ADC_LL_EF_Configuration_ADC_Instance .
<>	161:2cc1468da177	389	* @note The setting of these parameters by function @ref LL_ADC_Init()
<>	161:2cc1468da177	390	* is conditioned to ADC state:
<>	161:2cc1468da177	391	* ADC instance must be disabled.
<>	161:2cc1468da177	392	* This condition is applied to all ADC features, for efficiency
<>	161:2cc1468da177	393	* and compatibility over all STM32 families. However, the different
<>	161:2cc1468da177	394	* features can be set under different ADC state conditions
<>	161:2cc1468da177	395	* (setting possible with ADC enabled without conversion on going,
<>	161:2cc1468da177	396	* ADC enabled with conversion on going, ...)
<>	161:2cc1468da177	397	* Each feature can be updated afterwards with a unitary function
<>	161:2cc1468da177	398	* and potentially with ADC in a different state than disabled,
<>	161:2cc1468da177	399	* refer to description of each function for setting
<>	161:2cc1468da177	400	* conditioned to ADC state.
<>	161:2cc1468da177	401	*/
<>	161:2cc1468da177	402	typedef struct
<>	161:2cc1468da177	403	{
<>	161:2cc1468da177	404	uint32_t Resolution; /*!< Set ADC resolution.
<>	161:2cc1468da177	405	This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
<>	161:2cc1468da177	406
<>	161:2cc1468da177	407	This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
<>	161:2cc1468da177	408
<>	161:2cc1468da177	409	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
<>	161:2cc1468da177	410	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
<>	161:2cc1468da177	411
<>	161:2cc1468da177	412	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
<>	161:2cc1468da177	413
<>	161:2cc1468da177	414	uint32_t SequencersScanMode; /*!< Set ADC scan selection.
<>	161:2cc1468da177	415	This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
<>	161:2cc1468da177	416
<>	161:2cc1468da177	417	This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
<>	161:2cc1468da177	418
<>	161:2cc1468da177	419	} LL_ADC_InitTypeDef;
<>	161:2cc1468da177	420
<>	161:2cc1468da177	421	/**
<>	161:2cc1468da177	422	* @brief Structure definition of some features of ADC group regular.
<>	161:2cc1468da177	423	* @note These parameters have an impact on ADC scope: ADC group regular.
<>	161:2cc1468da177	424	* Refer to corresponding unitary functions into
<>	161:2cc1468da177	425	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	161:2cc1468da177	426	* (functions with prefix "REG").
<>	161:2cc1468da177	427	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
<>	161:2cc1468da177	428	* is conditioned to ADC state:
<>	161:2cc1468da177	429	* ADC instance must be disabled.
<>	161:2cc1468da177	430	* This condition is applied to all ADC features, for efficiency
<>	161:2cc1468da177	431	* and compatibility over all STM32 families. However, the different
<>	161:2cc1468da177	432	* features can be set under different ADC state conditions
<>	161:2cc1468da177	433	* (setting possible with ADC enabled without conversion on going,
<>	161:2cc1468da177	434	* ADC enabled with conversion on going, ...)
<>	161:2cc1468da177	435	* Each feature can be updated afterwards with a unitary function
<>	161:2cc1468da177	436	* and potentially with ADC in a different state than disabled,
<>	161:2cc1468da177	437	* refer to description of each function for setting
<>	161:2cc1468da177	438	* conditioned to ADC state.
<>	161:2cc1468da177	439	*/
<>	161:2cc1468da177	440	typedef struct
<>	161:2cc1468da177	441	{
<>	161:2cc1468da177	442	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	161:2cc1468da177	443	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
<>	161:2cc1468da177	444	@note On this STM32 serie, setting of external trigger edge is performed
<>	161:2cc1468da177	445	using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	161:2cc1468da177	446
<>	161:2cc1468da177	447	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
<>	161:2cc1468da177	448
<>	161:2cc1468da177	449	uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
<>	161:2cc1468da177	450	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
<>	161:2cc1468da177	451	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
<>	161:2cc1468da177	452
<>	161:2cc1468da177	453	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
<>	161:2cc1468da177	454
<>	161:2cc1468da177	455	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	161:2cc1468da177	456	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
<>	161:2cc1468da177	457	@note This parameter has an effect only if group regular sequencer is enabled
<>	161:2cc1468da177	458	(scan length of 2 ranks or more).
<>	161:2cc1468da177	459
<>	161:2cc1468da177	460	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
<>	161:2cc1468da177	461
<>	161:2cc1468da177	462	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
<>	161:2cc1468da177	463	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
<>	161:2cc1468da177	464	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
<>	161:2cc1468da177	465
<>	161:2cc1468da177	466	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
<>	161:2cc1468da177	467
<>	161:2cc1468da177	468	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
<>	161:2cc1468da177	469	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
<>	161:2cc1468da177	470
<>	161:2cc1468da177	471	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
<>	161:2cc1468da177	472
<>	161:2cc1468da177	473	} LL_ADC_REG_InitTypeDef;
<>	161:2cc1468da177	474
<>	161:2cc1468da177	475	/**
<>	161:2cc1468da177	476	* @brief Structure definition of some features of ADC group injected.
<>	161:2cc1468da177	477	* @note These parameters have an impact on ADC scope: ADC group injected.
<>	161:2cc1468da177	478	* Refer to corresponding unitary functions into
<>	161:2cc1468da177	479	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	161:2cc1468da177	480	* (functions with prefix "INJ").
<>	161:2cc1468da177	481	* @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
<>	161:2cc1468da177	482	* is conditioned to ADC state:
<>	161:2cc1468da177	483	* ADC instance must be disabled.
<>	161:2cc1468da177	484	* This condition is applied to all ADC features, for efficiency
<>	161:2cc1468da177	485	* and compatibility over all STM32 families. However, the different
<>	161:2cc1468da177	486	* features can be set under different ADC state conditions
<>	161:2cc1468da177	487	* (setting possible with ADC enabled without conversion on going,
<>	161:2cc1468da177	488	* ADC enabled with conversion on going, ...)
<>	161:2cc1468da177	489	* Each feature can be updated afterwards with a unitary function
<>	161:2cc1468da177	490	* and potentially with ADC in a different state than disabled,
<>	161:2cc1468da177	491	* refer to description of each function for setting
<>	161:2cc1468da177	492	* conditioned to ADC state.
<>	161:2cc1468da177	493	*/
<>	161:2cc1468da177	494	typedef struct
<>	161:2cc1468da177	495	{
<>	161:2cc1468da177	496	uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	161:2cc1468da177	497	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
<>	161:2cc1468da177	498	@note On this STM32 serie, setting of external trigger edge is performed
<>	161:2cc1468da177	499	using function @ref LL_ADC_INJ_StartConversionExtTrig().
<>	161:2cc1468da177	500
<>	161:2cc1468da177	501	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
<>	161:2cc1468da177	502
<>	161:2cc1468da177	503	uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
<>	161:2cc1468da177	504	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
<>	161:2cc1468da177	505	@note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
<>	161:2cc1468da177	506
<>	161:2cc1468da177	507	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
<>	161:2cc1468da177	508
<>	161:2cc1468da177	509	uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	161:2cc1468da177	510	This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
<>	161:2cc1468da177	511	@note This parameter has an effect only if group injected sequencer is enabled
<>	161:2cc1468da177	512	(scan length of 2 ranks or more).
<>	161:2cc1468da177	513
<>	161:2cc1468da177	514	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
<>	161:2cc1468da177	515
<>	161:2cc1468da177	516	uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
<>	161:2cc1468da177	517	This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
<>	161:2cc1468da177	518	Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
<>	161:2cc1468da177	519
<>	161:2cc1468da177	520	This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
<>	161:2cc1468da177	521
<>	161:2cc1468da177	522	} LL_ADC_INJ_InitTypeDef;
<>	161:2cc1468da177	523
<>	161:2cc1468da177	524	/**
<>	161:2cc1468da177	525	* @}
<>	161:2cc1468da177	526	*/
<>	161:2cc1468da177	527	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	528
<>	161:2cc1468da177	529	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	530	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
<>	161:2cc1468da177	531	* @{
<>	161:2cc1468da177	532	*/
<>	161:2cc1468da177	533
<>	161:2cc1468da177	534	/** @defgroup ADC_LL_EC_FLAG ADC flags
<>	161:2cc1468da177	535	* @brief Flags defines which can be used with LL_ADC_ReadReg function
<>	161:2cc1468da177	536	* @{
<>	161:2cc1468da177	537	*/
<>	161:2cc1468da177	538	#define LL_ADC_FLAG_STRT ADC_SR_STRT /!< ADC flag ADC group regular conversion start /
<>	161:2cc1468da177	539	#define LL_ADC_FLAG_EOCS ADC_SR_EOC /!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	161:2cc1468da177	540	#define LL_ADC_FLAG_OVR ADC_SR_OVR /!< ADC flag ADC group regular overrun /
<>	161:2cc1468da177	541	#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC flag ADC group injected conversion start /
<>	161:2cc1468da177	542	#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	161:2cc1468da177	543	#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /!< ADC flag ADC analog watchdog 1 /
<>	161:2cc1468da177	544	#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	161:2cc1468da177	545	#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	161:2cc1468da177	546	#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	161:2cc1468da177	547	#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /!< ADC flag ADC multimode master group regular overrun /
<>	161:2cc1468da177	548	#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /!< ADC flag ADC multimode slave 1 group regular overrun /
<>	161:2cc1468da177	549	#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /!< ADC flag ADC multimode slave 2 group regular overrun /
<>	161:2cc1468da177	550	#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	161:2cc1468da177	551	#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	161:2cc1468da177	552	#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	161:2cc1468da177	553	#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /!< ADC flag ADC multimode master analog watchdog 1 of the ADC master /
<>	161:2cc1468da177	554	#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /!< ADC flag ADC multimode slave 1 analog watchdog 1 /
<>	161:2cc1468da177	555	#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /!< ADC flag ADC multimode slave 2 analog watchdog 1 /
<>	161:2cc1468da177	556	/**
<>	161:2cc1468da177	557	* @}
<>	161:2cc1468da177	558	*/
<>	161:2cc1468da177	559
<>	161:2cc1468da177	560	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
<>	161:2cc1468da177	561	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
<>	161:2cc1468da177	562	* @{
<>	161:2cc1468da177	563	*/
<>	161:2cc1468da177	564	#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) /
<>	161:2cc1468da177	565	#define LL_ADC_IT_OVR ADC_CR1_OVRIE /!< ADC interruption ADC group regular overrun /
<>	161:2cc1468da177	566	#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) /
<>	161:2cc1468da177	567	#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /!< ADC interruption ADC analog watchdog 1 /
<>	161:2cc1468da177	568	/**
<>	161:2cc1468da177	569	* @}
<>	161:2cc1468da177	570	*/
<>	161:2cc1468da177	571
<>	161:2cc1468da177	572	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
<>	161:2cc1468da177	573	* @{
<>	161:2cc1468da177	574	*/
<>	161:2cc1468da177	575	/* List of ADC registers intended to be used (most commonly) with */
<>	161:2cc1468da177	576	/* DMA transfer. */
<>	161:2cc1468da177	577	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
<>	161:2cc1468da177	578	#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
<>	161:2cc1468da177	579	#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001U) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
<>	161:2cc1468da177	580	/**
<>	161:2cc1468da177	581	* @}
<>	161:2cc1468da177	582	*/
<>	161:2cc1468da177	583
<>	161:2cc1468da177	584	/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
<>	161:2cc1468da177	585	* @{
<>	161:2cc1468da177	586	*/
<>	161:2cc1468da177	587	#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (0x00000000U) /!< ADC synchronous clock derived from AHB clock with prescaler division by 2 /
<>	161:2cc1468da177	588	#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /!< ADC synchronous clock derived from AHB clock with prescaler division by 4 /
<>	161:2cc1468da177	589	#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /!< ADC synchronous clock derived from AHB clock with prescaler division by 6 /
<>	161:2cc1468da177	590	#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 \| ADC_CCR_ADCPRE_0) /!< ADC synchronous clock derived from AHB clock with prescaler division by 8 /
<>	161:2cc1468da177	591	/**
<>	161:2cc1468da177	592	* @}
<>	161:2cc1468da177	593	*/
<>	161:2cc1468da177	594
<>	161:2cc1468da177	595	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
<>	161:2cc1468da177	596	* @{
<>	161:2cc1468da177	597	*/
<>	161:2cc1468da177	598	/* Note: Other measurement paths to internal channels may be available */
<>	161:2cc1468da177	599	/* (connections to other peripherals). */
<>	161:2cc1468da177	600	/* If they are not listed below, they do not require any specific */
<>	161:2cc1468da177	601	/* path enable. In this case, Access to measurement path is done */
<>	161:2cc1468da177	602	/* only by selecting the corresponding ADC internal channel. */
<>	161:2cc1468da177	603	#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U)/!< ADC measurement pathes all disabled /
<>	161:2cc1468da177	604	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /!< ADC measurement path to internal channel VrefInt /
<>	161:2cc1468da177	605	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /!< ADC measurement path to internal channel temperature sensor /
<>	161:2cc1468da177	606	#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /!< ADC measurement path to internal channel Vbat /
<>	161:2cc1468da177	607	/**
<>	161:2cc1468da177	608	* @}
<>	161:2cc1468da177	609	*/
<>	161:2cc1468da177	610
<>	161:2cc1468da177	611	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
<>	161:2cc1468da177	612	* @{
<>	161:2cc1468da177	613	*/
<>	161:2cc1468da177	614	#define LL_ADC_RESOLUTION_12B (0x00000000U) /!< ADC resolution 12 bits /
<>	161:2cc1468da177	615	#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /!< ADC resolution 10 bits /
<>	161:2cc1468da177	616	#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /!< ADC resolution 8 bits /
<>	161:2cc1468da177	617	#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 \| ADC_CR1_RES_0) /!< ADC resolution 6 bits /
<>	161:2cc1468da177	618	/**
<>	161:2cc1468da177	619	* @}
<>	161:2cc1468da177	620	*/
<>	161:2cc1468da177	621
<>	161:2cc1468da177	622	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
<>	161:2cc1468da177	623	* @{
<>	161:2cc1468da177	624	*/
<>	161:2cc1468da177	625	#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U)/!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
<>	161:2cc1468da177	626	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
<>	161:2cc1468da177	627	/**
<>	161:2cc1468da177	628	* @}
<>	161:2cc1468da177	629	*/
<>	161:2cc1468da177	630
<>	161:2cc1468da177	631	/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
<>	161:2cc1468da177	632	* @{
<>	161:2cc1468da177	633	*/
<>	161:2cc1468da177	634	#define LL_ADC_SEQ_SCAN_DISABLE (0x00000000U) /!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank./
<>	161:2cc1468da177	635	#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). /
<>	161:2cc1468da177	636	/**
<>	161:2cc1468da177	637	* @}
<>	161:2cc1468da177	638	*/
<>	161:2cc1468da177	639
<>	161:2cc1468da177	640	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
<>	161:2cc1468da177	641	* @{
<>	161:2cc1468da177	642	*/
<>	161:2cc1468da177	643	#define LL_ADC_GROUP_REGULAR (0x00000001U) /!< ADC group regular (available on all STM32 devices) /
<>	161:2cc1468da177	644	#define LL_ADC_GROUP_INJECTED (0x00000002U) /!< ADC group injected (not available on all STM32 devices)/
<>	161:2cc1468da177	645	#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003U) /!< ADC both groups regular and injected /
<>	161:2cc1468da177	646	/**
<>	161:2cc1468da177	647	* @}
<>	161:2cc1468da177	648	*/
<>	161:2cc1468da177	649
<>	161:2cc1468da177	650	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
<>	161:2cc1468da177	651	* @{
<>	161:2cc1468da177	652	*/
<>	161:2cc1468da177	653	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
<>	161:2cc1468da177	654	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
<>	161:2cc1468da177	655	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
<>	161:2cc1468da177	656	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
<>	161:2cc1468da177	657	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
<>	161:2cc1468da177	658	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
<>	161:2cc1468da177	659	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
<>	161:2cc1468da177	660	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
<>	161:2cc1468da177	661	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
<>	161:2cc1468da177	662	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
<>	161:2cc1468da177	663	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
<>	161:2cc1468da177	664	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
<>	161:2cc1468da177	665	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
<>	161:2cc1468da177	666	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
<>	161:2cc1468da177	667	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
<>	161:2cc1468da177	668	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
<>	161:2cc1468da177	669	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
<>	161:2cc1468da177	670	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
<>	161:2cc1468da177	671	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_SMP) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 /
<>	161:2cc1468da177	672	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. /
<>	161:2cc1468da177	673	#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. /
<>	161:2cc1468da177	674	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. /
<>	161:2cc1468da177	675
<>	161:2cc1468da177	676	/**
<>	161:2cc1468da177	677	* @}
<>	161:2cc1468da177	678	*/
<>	161:2cc1468da177	679
<>	161:2cc1468da177	680	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
<>	161:2cc1468da177	681	* @{
<>	161:2cc1468da177	682	*/
<>	161:2cc1468da177	683	#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /!< ADC group regular conversion trigger internal: SW start. /
<>	161:2cc1468da177	684	#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	685	#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	686	#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	687	#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	688	#define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CR2_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	689	#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	690	#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	691	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	692	#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_EXTSEL_3 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	693	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	694	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	695	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	696	#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	697	#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 \|ADC_CR2_EXTSEL_2\| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	698	#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	699
<>	161:2cc1468da177	700	/**
<>	161:2cc1468da177	701	* @}
<>	161:2cc1468da177	702	*/
<>	161:2cc1468da177	703
<>	161:2cc1468da177	704	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
<>	161:2cc1468da177	705	* @{
<>	161:2cc1468da177	706	*/
<>	161:2cc1468da177	707	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
<>	161:2cc1468da177	708	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
<>	161:2cc1468da177	709	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 \| ADC_CR2_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
<>	161:2cc1468da177	710	/**
<>	161:2cc1468da177	711	* @}
<>	161:2cc1468da177	712	*/
<>	161:2cc1468da177	713
<>	161:2cc1468da177	714	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
<>	161:2cc1468da177	715	* @{
<>	161:2cc1468da177	716	*/
<>	161:2cc1468da177	717	#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /!< ADC conversions are performed in single mode: one conversion per trigger /
<>	161:2cc1468da177	718	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
<>	161:2cc1468da177	719	/**
<>	161:2cc1468da177	720	* @}
<>	161:2cc1468da177	721	*/
<>	161:2cc1468da177	722
<>	161:2cc1468da177	723	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
<>	161:2cc1468da177	724	* @{
<>	161:2cc1468da177	725	*/
<>	161:2cc1468da177	726	#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /!< ADC conversions are not transferred by DMA /
<>	161:2cc1468da177	727	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
<>	161:2cc1468da177	728	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS \| ADC_CR2_DMA) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
<>	161:2cc1468da177	729	/**
<>	161:2cc1468da177	730	* @}
<>	161:2cc1468da177	731	*/
<>	161:2cc1468da177	732
<>	161:2cc1468da177	733	/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
<>	161:2cc1468da177	734	* @{
<>	161:2cc1468da177	735	*/
<>	161:2cc1468da177	736	#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV (0x00000000U) /!< ADC flag EOC (end of unitary conversion) selected /
<>	161:2cc1468da177	737	#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /!< ADC flag EOS (end of sequence conversions) selected /
<>	161:2cc1468da177	738	/**
<>	161:2cc1468da177	739	* @}
<>	161:2cc1468da177	740	*/
<>	161:2cc1468da177	741
<>	161:2cc1468da177	742	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
<>	161:2cc1468da177	743	* @{
<>	161:2cc1468da177	744	*/
<>	161:2cc1468da177	745	#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000U) /!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	161:2cc1468da177	746	#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 2 ranks in the sequence /
<>	161:2cc1468da177	747	#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 3 ranks in the sequence /
<>	161:2cc1468da177	748	#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 4 ranks in the sequence /
<>	161:2cc1468da177	749	#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 5 ranks in the sequence /
<>	161:2cc1468da177	750	#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 6 ranks in the sequence /
<>	161:2cc1468da177	751	#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 7 ranks in the sequence /
<>	161:2cc1468da177	752	#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 8 ranks in the sequence /
<>	161:2cc1468da177	753	#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /!< ADC group regular sequencer enable with 9 ranks in the sequence /
<>	161:2cc1468da177	754	#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 10 ranks in the sequence /
<>	161:2cc1468da177	755	#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 11 ranks in the sequence /
<>	161:2cc1468da177	756	#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 12 ranks in the sequence /
<>	161:2cc1468da177	757	#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 ) /!< ADC group regular sequencer enable with 13 ranks in the sequence /
<>	161:2cc1468da177	758	#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 14 ranks in the sequence /
<>	161:2cc1468da177	759	#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 ) /!< ADC group regular sequencer enable with 15 ranks in the sequence /
<>	161:2cc1468da177	760	#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 \| ADC_SQR1_L_2 \| ADC_SQR1_L_1 \| ADC_SQR1_L_0) /!< ADC group regular sequencer enable with 16 ranks in the sequence /
<>	161:2cc1468da177	761	/**
<>	161:2cc1468da177	762	* @}
<>	161:2cc1468da177	763	*/
<>	161:2cc1468da177	764
<>	161:2cc1468da177	765	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
<>	161:2cc1468da177	766	* @{
<>	161:2cc1468da177	767	*/
<>	161:2cc1468da177	768	#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /!< ADC group regular sequencer discontinuous mode disable /
<>	161:2cc1468da177	769	#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
<>	161:2cc1468da177	770	#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks /
<>	161:2cc1468da177	771	#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks /
<>	161:2cc1468da177	772	#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks /
<>	161:2cc1468da177	773	#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks /
<>	161:2cc1468da177	774	#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks /
<>	161:2cc1468da177	775	#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks /
<>	161:2cc1468da177	776	#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 \| ADC_CR1_DISCNUM_1 \| ADC_CR1_DISCNUM_0 \| ADC_CR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks /
<>	161:2cc1468da177	777	/**
<>	161:2cc1468da177	778	* @}
<>	161:2cc1468da177	779	*/
<>	161:2cc1468da177	780
<>	161:2cc1468da177	781	/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
<>	161:2cc1468da177	782	* @{
<>	161:2cc1468da177	783	*/
<>	161:2cc1468da177	784	#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 1 /
<>	161:2cc1468da177	785	#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 2 /
<>	161:2cc1468da177	786	#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 3 /
<>	161:2cc1468da177	787	#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 4 /
<>	161:2cc1468da177	788	#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 5 /
<>	161:2cc1468da177	789	#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET \| ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 6 /
<>	161:2cc1468da177	790	#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 7 /
<>	161:2cc1468da177	791	#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 8 /
<>	161:2cc1468da177	792	#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 9 /
<>	161:2cc1468da177	793	#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 10 /
<>	161:2cc1468da177	794	#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 11 /
<>	161:2cc1468da177	795	#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET \| ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 12 /
<>	161:2cc1468da177	796	#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 13 /
<>	161:2cc1468da177	797	#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 14 /
<>	161:2cc1468da177	798	#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 15 /
<>	161:2cc1468da177	799	#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET \| ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /!< ADC group regular sequencer rank 16 /
<>	161:2cc1468da177	800	/**
<>	161:2cc1468da177	801	* @}
<>	161:2cc1468da177	802	*/
<>	161:2cc1468da177	803
<>	161:2cc1468da177	804	/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
<>	161:2cc1468da177	805	* @{
<>	161:2cc1468da177	806	*/
<>	161:2cc1468da177	807	#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000U) /!< ADC group injected conversion trigger internal: SW start. /
<>	161:2cc1468da177	808	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	809	#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	810	#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	811	#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	812	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	813	#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	814	#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	815	#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_JEXTSEL_3 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	816	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	817	#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	818	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	819	#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	820	#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	821	#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_CR2_JEXTSEL_3 \| ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
<>	161:2cc1468da177	822
<>	161:2cc1468da177	823	/**
<>	161:2cc1468da177	824	* @}
<>	161:2cc1468da177	825	*/
<>	161:2cc1468da177	826
<>	161:2cc1468da177	827	/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
<>	161:2cc1468da177	828	* @{
<>	161:2cc1468da177	829	*/
<>	161:2cc1468da177	830	#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to rising edge /
<>	161:2cc1468da177	831	#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /!< ADC group injected conversion trigger polarity set to falling edge /
<>	161:2cc1468da177	832	#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 \| ADC_CR2_JEXTEN_0) /!< ADC group injected conversion trigger polarity set to both rising and falling edges /
<>	161:2cc1468da177	833	/**
<>	161:2cc1468da177	834	* @}
<>	161:2cc1468da177	835	*/
<>	161:2cc1468da177	836
<>	161:2cc1468da177	837	/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
<>	161:2cc1468da177	838	* @{
<>	161:2cc1468da177	839	*/
<>	161:2cc1468da177	840	#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000U)/!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. /
<>	161:2cc1468da177	841	#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. /
<>	161:2cc1468da177	842	/**
<>	161:2cc1468da177	843	* @}
<>	161:2cc1468da177	844	*/
<>	161:2cc1468da177	845
<>	161:2cc1468da177	846
<>	161:2cc1468da177	847	/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
<>	161:2cc1468da177	848	* @{
<>	161:2cc1468da177	849	*/
<>	161:2cc1468da177	850	#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000U) /!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) /
<>	161:2cc1468da177	851	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 2 ranks in the sequence /
<>	161:2cc1468da177	852	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /!< ADC group injected sequencer enable with 3 ranks in the sequence /
<>	161:2cc1468da177	853	#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 \| ADC_JSQR_JL_0) /!< ADC group injected sequencer enable with 4 ranks in the sequence /
<>	161:2cc1468da177	854	/**
<>	161:2cc1468da177	855	* @}
<>	161:2cc1468da177	856	*/
<>	161:2cc1468da177	857
<>	161:2cc1468da177	858	/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
<>	161:2cc1468da177	859	* @{
<>	161:2cc1468da177	860	*/
<>	161:2cc1468da177	861	#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000U)/!< ADC group injected sequencer discontinuous mode disable /
<>	161:2cc1468da177	862	#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank /
<>	161:2cc1468da177	863	/**
<>	161:2cc1468da177	864	* @}
<>	161:2cc1468da177	865	*/
<>	161:2cc1468da177	866
<>	161:2cc1468da177	867	/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
<>	161:2cc1468da177	868	* @{
<>	161:2cc1468da177	869	*/
<>	161:2cc1468da177	870	#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET \| ADC_JOFR1_REGOFFSET \| ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 1 /
<>	161:2cc1468da177	871	#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET \| ADC_JOFR2_REGOFFSET \| ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 2 /
<>	161:2cc1468da177	872	#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET \| ADC_JOFR3_REGOFFSET \| ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 3 /
<>	161:2cc1468da177	873	#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET \| ADC_JOFR4_REGOFFSET \| ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /!< ADC group injected sequencer rank 4 /
<>	161:2cc1468da177	874	/**
<>	161:2cc1468da177	875	* @}
<>	161:2cc1468da177	876	*/
<>	161:2cc1468da177	877
<>	161:2cc1468da177	878	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
<>	161:2cc1468da177	879	* @{
<>	161:2cc1468da177	880	*/
<>	161:2cc1468da177	881	#define LL_ADC_SAMPLINGTIME_3CYCLES (0x00000000U) /!< Sampling time 3 ADC clock cycles /
<>	161:2cc1468da177	882	#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /!< Sampling time 15 ADC clock cycles /
<>	161:2cc1468da177	883	#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /!< Sampling time 28 ADC clock cycles /
<>	161:2cc1468da177	884	#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 \| ADC_SMPR1_SMP10_0) /!< Sampling time 56 ADC clock cycles /
<>	161:2cc1468da177	885	#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /!< Sampling time 84 ADC clock cycles /
<>	161:2cc1468da177	886	#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_0) /!< Sampling time 112 ADC clock cycles /
<>	161:2cc1468da177	887	#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_1) /!< Sampling time 144 ADC clock cycles /
<>	161:2cc1468da177	888	#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /!< Sampling time 480 ADC clock cycles /
<>	161:2cc1468da177	889	/**
<>	161:2cc1468da177	890	* @}
<>	161:2cc1468da177	891	*/
<>	161:2cc1468da177	892
<>	161:2cc1468da177	893	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
<>	161:2cc1468da177	894	* @{
<>	161:2cc1468da177	895	*/
<>	161:2cc1468da177	896	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
<>	161:2cc1468da177	897	/**
<>	161:2cc1468da177	898	* @}
<>	161:2cc1468da177	899	*/
<>	161:2cc1468da177	900
<>	161:2cc1468da177	901	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
<>	161:2cc1468da177	902	* @{
<>	161:2cc1468da177	903	*/
<>	161:2cc1468da177	904	#define LL_ADC_AWD_DISABLE (0x00000000U) /!< ADC analog watchdog monitoring disabled /
<>	161:2cc1468da177	905	#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
<>	161:2cc1468da177	906	#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group injected only /
<>	161:2cc1468da177	907	#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN \| ADC_CR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected /
<>	161:2cc1468da177	908	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
<>	161:2cc1468da177	909	#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only /
<>	161:2cc1468da177	910	#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected /
<>	161:2cc1468da177	911	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
<>	161:2cc1468da177	912	#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only /
<>	161:2cc1468da177	913	#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected /
<>	161:2cc1468da177	914	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
<>	161:2cc1468da177	915	#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only /
<>	161:2cc1468da177	916	#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected /
<>	161:2cc1468da177	917	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
<>	161:2cc1468da177	918	#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only /
<>	161:2cc1468da177	919	#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected /
<>	161:2cc1468da177	920	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
<>	161:2cc1468da177	921	#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only /
<>	161:2cc1468da177	922	#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected /
<>	161:2cc1468da177	923	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
<>	161:2cc1468da177	924	#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only /
<>	161:2cc1468da177	925	#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected /
<>	161:2cc1468da177	926	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
<>	161:2cc1468da177	927	#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only /
<>	161:2cc1468da177	928	#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected /
<>	161:2cc1468da177	929	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
<>	161:2cc1468da177	930	#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only /
<>	161:2cc1468da177	931	#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected /
<>	161:2cc1468da177	932	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
<>	161:2cc1468da177	933	#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only /
<>	161:2cc1468da177	934	#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected /
<>	161:2cc1468da177	935	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
<>	161:2cc1468da177	936	#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only /
<>	161:2cc1468da177	937	#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected /
<>	161:2cc1468da177	938	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
<>	161:2cc1468da177	939	#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only /
<>	161:2cc1468da177	940	#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected /
<>	161:2cc1468da177	941	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
<>	161:2cc1468da177	942	#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only /
<>	161:2cc1468da177	943	#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected /
<>	161:2cc1468da177	944	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
<>	161:2cc1468da177	945	#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only /
<>	161:2cc1468da177	946	#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected /
<>	161:2cc1468da177	947	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
<>	161:2cc1468da177	948	#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only /
<>	161:2cc1468da177	949	#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected /
<>	161:2cc1468da177	950	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
<>	161:2cc1468da177	951	#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only /
<>	161:2cc1468da177	952	#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected /
<>	161:2cc1468da177	953	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
<>	161:2cc1468da177	954	#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only /
<>	161:2cc1468da177	955	#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected /
<>	161:2cc1468da177	956	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
<>	161:2cc1468da177	957	#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only /
<>	161:2cc1468da177	958	#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected /
<>	161:2cc1468da177	959	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
<>	161:2cc1468da177	960	#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only /
<>	161:2cc1468da177	961	#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected /
<>	161:2cc1468da177	962	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
<>	161:2cc1468da177	963	#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only /
<>	161:2cc1468da177	964	#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected /
<>	161:2cc1468da177	965	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
<>	161:2cc1468da177	966	#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only /
<>	161:2cc1468da177	967	#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected /
<>	161:2cc1468da177	968	#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only /
<>	161:2cc1468da177	969	#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only /
<>	161:2cc1468da177	970	#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda /
<>	161:2cc1468da177	971	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. /
<>	161:2cc1468da177	972	#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. /
<>	161:2cc1468da177	973	#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. /
<>	161:2cc1468da177	974	/**
<>	161:2cc1468da177	975	* @}
<>	161:2cc1468da177	976	*/
<>	161:2cc1468da177	977
<>	161:2cc1468da177	978	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
<>	161:2cc1468da177	979	* @{
<>	161:2cc1468da177	980	*/
<>	161:2cc1468da177	981	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /!< ADC analog watchdog threshold high /
<>	161:2cc1468da177	982	#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /!< ADC analog watchdog threshold low /
<>	161:2cc1468da177	983	/**
<>	161:2cc1468da177	984	* @}
<>	161:2cc1468da177	985	*/
<>	161:2cc1468da177	986
<>	161:2cc1468da177	987	/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
<>	161:2cc1468da177	988	* @{
<>	161:2cc1468da177	989	*/
<>	161:2cc1468da177	990	#define LL_ADC_MULTI_INDEPENDENT (0x00000000U) /!< ADC dual mode disabled (ADC independent mode) /
<>	161:2cc1468da177	991	#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 ) /!< ADC dual mode enabled: group regular simultaneous /
<>	161:2cc1468da177	992	#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: Combined group regular interleaved /
<>	161:2cc1468da177	993	#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: group injected simultaneous /
<>	161:2cc1468da177	994	#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
<>	161:2cc1468da177	995	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous /
<>	161:2cc1468da177	996	#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger /
<>	161:2cc1468da177	997	#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0) /!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous /
<>	161:2cc1468da177	998	#if defined(ADC3)
<>	161:2cc1468da177	999	#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous /
<>	161:2cc1468da177	1000	#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_1 ) /!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger /
<>	161:2cc1468da177	1001	#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: group injected simultaneous /
<>	161:2cc1468da177	1002	#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 ) /!< ADC triple mode enabled: group regular simultaneous /
<>	161:2cc1468da177	1003	#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_2 \| ADC_CCR_MULTI_1 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: Combined group regular interleaved /
<>	161:2cc1468da177	1004	#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 \| ADC_CCR_MULTI_0) /!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
<>	161:2cc1468da177	1005	#endif
<>	161:2cc1468da177	1006	/**
<>	161:2cc1468da177	1007	* @}
<>	161:2cc1468da177	1008	*/
<>	161:2cc1468da177	1009
<>	161:2cc1468da177	1010	/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
<>	161:2cc1468da177	1011	* @{
<>	161:2cc1468da177	1012	*/
<>	161:2cc1468da177	1013	#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000U) /!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings /
<>	161:2cc1468da177	1014	#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. /
<>	161:2cc1468da177	1015	#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. /
<>	161:2cc1468da177	1016	#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 \| ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. /
<>	161:2cc1468da177	1017	#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS \| ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. /
<>	161:2cc1468da177	1018	#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS \| ADC_CCR_DMA_1 ) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. /
<>	161:2cc1468da177	1019	#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS \| ADC_CCR_DMA_0 \| ADC_CCR_DMA_0) /!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. /
<>	161:2cc1468da177	1020	/**
<>	161:2cc1468da177	1021	* @}
<>	161:2cc1468da177	1022	*/
<>	161:2cc1468da177	1023
<>	161:2cc1468da177	1024	/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
<>	161:2cc1468da177	1025	* @{
<>	161:2cc1468da177	1026	*/
<>	161:2cc1468da177	1027	#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES (0x00000000U) /!< ADC multimode delay between two sampling phases: 5 ADC clock cycles/
<>	161:2cc1468da177	1028	#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 6 ADC clock cycles /
<>	161:2cc1468da177	1029	#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 7 ADC clock cycles /
<>	161:2cc1468da177	1030	#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 8 ADC clock cycles /
<>	161:2cc1468da177	1031	#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /!< ADC multimode delay between two sampling phases: 9 ADC clock cycles /
<>	161:2cc1468da177	1032	#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 10 ADC clock cycles /
<>	161:2cc1468da177	1033	#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 11 ADC clock cycles /
<>	161:2cc1468da177	1034	#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 12 ADC clock cycles /
<>	161:2cc1468da177	1035	#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /!< ADC multimode delay between two sampling phases: 13 ADC clock cycles /
<>	161:2cc1468da177	1036	#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 14 ADC clock cycles /
<>	161:2cc1468da177	1037	#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 15 ADC clock cycles /
<>	161:2cc1468da177	1038	#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 16 ADC clock cycles /
<>	161:2cc1468da177	1039	#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 ) /!< ADC multimode delay between two sampling phases: 17 ADC clock cycles /
<>	161:2cc1468da177	1040	#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 18 ADC clock cycles /
<>	161:2cc1468da177	1041	#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 ) /!< ADC multimode delay between two sampling phases: 19 ADC clock cycles /
<>	161:2cc1468da177	1042	#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0) /!< ADC multimode delay between two sampling phases: 20 ADC clock cycles /
<>	161:2cc1468da177	1043	/**
<>	161:2cc1468da177	1044	* @}
<>	161:2cc1468da177	1045	*/
<>	161:2cc1468da177	1046
<>	161:2cc1468da177	1047	/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
<>	161:2cc1468da177	1048	* @{
<>	161:2cc1468da177	1049	*/
<>	161:2cc1468da177	1050	#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: ADC master /
<>	161:2cc1468da177	1051	#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /!< In multimode, selection among several ADC instances: ADC slave /
<>	161:2cc1468da177	1052	#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV \| ADC_CDR_RDATA_MST) /!< In multimode, selection among several ADC instances: both ADC master and ADC slave /
<>	161:2cc1468da177	1053	/**
<>	161:2cc1468da177	1054	* @}
<>	161:2cc1468da177	1055	*/
<>	161:2cc1468da177	1056
<>	161:2cc1468da177	1057
<>	161:2cc1468da177	1058
<>	161:2cc1468da177	1059	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
<>	161:2cc1468da177	1060	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
<>	161:2cc1468da177	1061	* not timeout values.
<>	161:2cc1468da177	1062	* For details on delays values, refer to descriptions in source code
<>	161:2cc1468da177	1063	* above each literal definition.
<>	161:2cc1468da177	1064	* @{
<>	161:2cc1468da177	1065	*/
<>	161:2cc1468da177	1066
<>	161:2cc1468da177	1067	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<>	161:2cc1468da177	1068	/* not timeout values. */
<>	161:2cc1468da177	1069	/* Timeout values for ADC operations are dependent to device clock */
<>	161:2cc1468da177	1070	/* configuration (system clock versus ADC clock), */
<>	161:2cc1468da177	1071	/* and therefore must be defined in user application. */
<>	161:2cc1468da177	1072	/* Indications for estimation of ADC timeout delays, for this */
<>	161:2cc1468da177	1073	/* STM32 serie: */
<>	161:2cc1468da177	1074	/* - ADC enable time: maximum delay is 2us */
<>	161:2cc1468da177	1075	/* (refer to device datasheet, parameter "tSTAB") */
<>	161:2cc1468da177	1076	/* - ADC conversion time: duration depending on ADC clock and ADC */
<>	161:2cc1468da177	1077	/* configuration. */
<>	161:2cc1468da177	1078	/* (refer to device reference manual, section "Timing") */
<>	161:2cc1468da177	1079
<>	161:2cc1468da177	1080	/* Delay for internal voltage reference stabilization time. */
<>	161:2cc1468da177	1081	/* Delay set to maximum value (refer to device datasheet, */
<>	161:2cc1468da177	1082	/* parameter "tSTART"). */
<>	161:2cc1468da177	1083	/* Unit: us */
<>	161:2cc1468da177	1084	#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /!< Delay for internal voltage reference stabilization time /
<>	161:2cc1468da177	1085
<>	161:2cc1468da177	1086	/* Delay for temperature sensor stabilization time. */
<>	161:2cc1468da177	1087	/* Literal set to maximum value (refer to device datasheet, */
<>	161:2cc1468da177	1088	/* parameter "tSTART"). */
<>	161:2cc1468da177	1089	/* Unit: us */
<>	161:2cc1468da177	1090	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /!< Delay for internal voltage reference stabilization time /
<>	161:2cc1468da177	1091
<>	161:2cc1468da177	1092	/**
<>	161:2cc1468da177	1093	* @}
<>	161:2cc1468da177	1094	*/
<>	161:2cc1468da177	1095
<>	161:2cc1468da177	1096	/**
<>	161:2cc1468da177	1097	* @}
<>	161:2cc1468da177	1098	*/
<>	161:2cc1468da177	1099
<>	161:2cc1468da177	1100
<>	161:2cc1468da177	1101	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	1102	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
<>	161:2cc1468da177	1103	* @{
<>	161:2cc1468da177	1104	*/
<>	161:2cc1468da177	1105
<>	161:2cc1468da177	1106	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
<>	161:2cc1468da177	1107	* @{
<>	161:2cc1468da177	1108	*/
<>	161:2cc1468da177	1109
<>	161:2cc1468da177	1110	/**
<>	161:2cc1468da177	1111	* @brief Write a value in ADC register
<>	161:2cc1468da177	1112	* @param __INSTANCE__ ADC Instance
<>	161:2cc1468da177	1113	* @param __REG__ Register to be written
<>	161:2cc1468da177	1114	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	1115	* @retval None
<>	161:2cc1468da177	1116	*/
<>	161:2cc1468da177	1117	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	161:2cc1468da177	1118
<>	161:2cc1468da177	1119	/**
<>	161:2cc1468da177	1120	* @brief Read a value in ADC register
<>	161:2cc1468da177	1121	* @param __INSTANCE__ ADC Instance
<>	161:2cc1468da177	1122	* @param __REG__ Register to be read
<>	161:2cc1468da177	1123	* @retval Register value
<>	161:2cc1468da177	1124	*/
<>	161:2cc1468da177	1125	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	161:2cc1468da177	1126	/**
<>	161:2cc1468da177	1127	* @}
<>	161:2cc1468da177	1128	*/
<>	161:2cc1468da177	1129
<>	161:2cc1468da177	1130	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
<>	161:2cc1468da177	1131	* @{
<>	161:2cc1468da177	1132	*/
<>	161:2cc1468da177	1133
<>	161:2cc1468da177	1134	/**
<>	161:2cc1468da177	1135	* @brief Helper macro to get ADC channel number in decimal format
<>	161:2cc1468da177	1136	* from literals LL_ADC_CHANNEL_x.
<>	161:2cc1468da177	1137	* @note Example:
<>	161:2cc1468da177	1138	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
<>	161:2cc1468da177	1139	* will return decimal number "4".
<>	161:2cc1468da177	1140	* @note The input can be a value from functions where a channel
<>	161:2cc1468da177	1141	* number is returned, either defined with number
<>	161:2cc1468da177	1142	* or with bitfield (only one bit must be set).
<>	161:2cc1468da177	1143	* @param __CHANNEL__ This parameter can be one of the following values:
<>	161:2cc1468da177	1144	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	1145	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	1146	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	1147	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	1148	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	1149	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	1150	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	1151	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	1152	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	1153	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	1154	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	1155	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	1156	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	1157	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	1158	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	1159	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	1160	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	1161	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	1162	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	1163	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	1164	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	1165	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	1166	*
<>	161:2cc1468da177	1167	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	1168	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	1169	* @retval Value between Min_Data=0 and Max_Data=18
<>	161:2cc1468da177	1170	*/
<>	161:2cc1468da177	1171	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	161:2cc1468da177	1172	(((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<>	161:2cc1468da177	1173
<>	161:2cc1468da177	1174	/**
<>	161:2cc1468da177	1175	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
<>	161:2cc1468da177	1176	* from number in decimal format.
<>	161:2cc1468da177	1177	* @note Example:
<>	161:2cc1468da177	1178	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
<>	161:2cc1468da177	1179	* will return a data equivalent to "LL_ADC_CHANNEL_4".
<>	161:2cc1468da177	1180	* @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
<>	161:2cc1468da177	1181	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1182	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	1183	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	1184	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	1185	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	1186	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	1187	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	1188	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	1189	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	1190	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	1191	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	1192	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	1193	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	1194	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	1195	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	1196	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	1197	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	1198	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	1199	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	1200	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	1201	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	1202	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	1203	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	1204	*
<>	161:2cc1468da177	1205	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	1206	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	161:2cc1468da177	1207	* (1) For ADC channel read back from ADC register,
<>	161:2cc1468da177	1208	* comparison with internal channel parameter to be done
<>	161:2cc1468da177	1209	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	161:2cc1468da177	1210	*/
<>	161:2cc1468da177	1211	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	161:2cc1468da177	1212	(((__DECIMAL_NB__) <= 9U) \
<>	161:2cc1468da177	1213	? ( \
<>	161:2cc1468da177	1214	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	161:2cc1468da177	1215	(ADC_SMPR2_REGOFFSET \| (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	161:2cc1468da177	1216	) \
<>	161:2cc1468da177	1217	: \
<>	161:2cc1468da177	1218	( \
<>	161:2cc1468da177	1219	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	161:2cc1468da177	1220	(ADC_SMPR1_REGOFFSET \| (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
<>	161:2cc1468da177	1221	) \
<>	161:2cc1468da177	1222	)
<>	161:2cc1468da177	1223
<>	161:2cc1468da177	1224	/**
<>	161:2cc1468da177	1225	* @brief Helper macro to determine whether the selected channel
<>	161:2cc1468da177	1226	* corresponds to literal definitions of driver.
<>	161:2cc1468da177	1227	* @note The different literal definitions of ADC channels are:
<>	161:2cc1468da177	1228	* - ADC internal channel:
<>	161:2cc1468da177	1229	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
<>	161:2cc1468da177	1230	* - ADC external channel (channel connected to a GPIO pin):
<>	161:2cc1468da177	1231	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
<>	161:2cc1468da177	1232	* @note The channel parameter must be a value defined from literal
<>	161:2cc1468da177	1233	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	161:2cc1468da177	1234	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	161:2cc1468da177	1235	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
<>	161:2cc1468da177	1236	* must not be a value from functions where a channel number is
<>	161:2cc1468da177	1237	* returned from ADC registers,
<>	161:2cc1468da177	1238	* because internal and external channels share the same channel
<>	161:2cc1468da177	1239	* number in ADC registers. The differentiation is made only with
<>	161:2cc1468da177	1240	* parameters definitions of driver.
<>	161:2cc1468da177	1241	* @param __CHANNEL__ This parameter can be one of the following values:
<>	161:2cc1468da177	1242	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	1243	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	1244	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	1245	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	1246	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	1247	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	1248	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	1249	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	1250	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	1251	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	1252	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	1253	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	1254	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	1255	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	1256	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	1257	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	1258	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	1259	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	1260	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	1261	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	1262	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	1263	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	1264	*
<>	161:2cc1468da177	1265	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	1266	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	1267	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
<>	161:2cc1468da177	1268	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
<>	161:2cc1468da177	1269	*/
<>	161:2cc1468da177	1270	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
<>	161:2cc1468da177	1271	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
<>	161:2cc1468da177	1272
<>	161:2cc1468da177	1273	/**
<>	161:2cc1468da177	1274	* @brief Helper macro to convert a channel defined from parameter
<>	161:2cc1468da177	1275	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	161:2cc1468da177	1276	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	161:2cc1468da177	1277	* to its equivalent parameter definition of a ADC external channel
<>	161:2cc1468da177	1278	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
<>	161:2cc1468da177	1279	* @note The channel parameter can be, additionally to a value
<>	161:2cc1468da177	1280	* defined from parameter definition of a ADC internal channel
<>	161:2cc1468da177	1281	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	161:2cc1468da177	1282	* a value defined from parameter definition of
<>	161:2cc1468da177	1283	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	161:2cc1468da177	1284	* or a value from functions where a channel number is returned
<>	161:2cc1468da177	1285	* from ADC registers.
<>	161:2cc1468da177	1286	* @param __CHANNEL__ This parameter can be one of the following values:
<>	161:2cc1468da177	1287	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	1288	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	1289	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	1290	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	1291	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	1292	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	1293	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	1294	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	1295	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	1296	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	1297	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	1298	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	1299	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	1300	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	1301	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	1302	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	1303	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	1304	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	1305	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	1306	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	1307	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	1308	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	1309	*
<>	161:2cc1468da177	1310	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	1311	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	1312	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1313	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	1314	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	1315	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	1316	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	1317	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	1318	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	1319	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	1320	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	1321	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	1322	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	1323	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	1324	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	1325	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	1326	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	1327	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	1328	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	1329	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	1330	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	1331	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	1332	*/
<>	161:2cc1468da177	1333	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
<>	161:2cc1468da177	1334	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	161:2cc1468da177	1335
<>	161:2cc1468da177	1336	/**
<>	161:2cc1468da177	1337	* @brief Helper macro to determine whether the internal channel
<>	161:2cc1468da177	1338	* selected is available on the ADC instance selected.
<>	161:2cc1468da177	1339	* @note The channel parameter must be a value defined from parameter
<>	161:2cc1468da177	1340	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	161:2cc1468da177	1341	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	161:2cc1468da177	1342	* must not be a value defined from parameter definition of
<>	161:2cc1468da177	1343	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	161:2cc1468da177	1344	* or a value from functions where a channel number is
<>	161:2cc1468da177	1345	* returned from ADC registers,
<>	161:2cc1468da177	1346	* because internal and external channels share the same channel
<>	161:2cc1468da177	1347	* number in ADC registers. The differentiation is made only with
<>	161:2cc1468da177	1348	* parameters definitions of driver.
<>	161:2cc1468da177	1349	* @param __ADC_INSTANCE__ ADC instance
<>	161:2cc1468da177	1350	* @param __CHANNEL__ This parameter can be one of the following values:
<>	161:2cc1468da177	1351	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	1352	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	1353	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	1354	*
<>	161:2cc1468da177	1355	* (1) On STM32F7, parameter available only on ADC instance: ADC1.
<>	161:2cc1468da177	1356	* (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	1357	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
<>	161:2cc1468da177	1358	* Value "1" if the internal channel selected is available on the ADC instance selected.
<>	161:2cc1468da177	1359	*/
<>	161:2cc1468da177	1360	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	161:2cc1468da177	1361	( \
<>	161:2cc1468da177	1362	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	161:2cc1468da177	1363	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
<>	161:2cc1468da177	1364	)
<>	161:2cc1468da177	1365	/**
<>	161:2cc1468da177	1366	* @brief Helper macro to define ADC analog watchdog parameter:
<>	161:2cc1468da177	1367	* define a single channel to monitor with analog watchdog
<>	161:2cc1468da177	1368	* from sequencer channel and groups definition.
<>	161:2cc1468da177	1369	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
<>	161:2cc1468da177	1370	* Example:
<>	161:2cc1468da177	1371	* LL_ADC_SetAnalogWDMonitChannels(
<>	161:2cc1468da177	1372	* ADC1, LL_ADC_AWD1,
<>	161:2cc1468da177	1373	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
<>	161:2cc1468da177	1374	* @param __CHANNEL__ This parameter can be one of the following values:
<>	161:2cc1468da177	1375	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	1376	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	1377	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	1378	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	1379	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	1380	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	1381	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	1382	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	1383	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	1384	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	1385	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	1386	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	1387	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	1388	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	1389	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	1390	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	1391	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	1392	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	1393	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	1394	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	1395	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	1396	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	1397	*
<>	161:2cc1468da177	1398	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	1399	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	161:2cc1468da177	1400	* (1) For ADC channel read back from ADC register,
<>	161:2cc1468da177	1401	* comparison with internal channel parameter to be done
<>	161:2cc1468da177	1402	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	161:2cc1468da177	1403	* @param __GROUP__ This parameter can be one of the following values:
<>	161:2cc1468da177	1404	* @arg @ref LL_ADC_GROUP_REGULAR
<>	161:2cc1468da177	1405	* @arg @ref LL_ADC_GROUP_INJECTED
<>	161:2cc1468da177	1406	* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
<>	161:2cc1468da177	1407	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1408	* @arg @ref LL_ADC_AWD_DISABLE
<>	161:2cc1468da177	1409	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	161:2cc1468da177	1410	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	161:2cc1468da177	1411	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	161:2cc1468da177	1412	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	161:2cc1468da177	1413	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
<>	161:2cc1468da177	1414	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	161:2cc1468da177	1415	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	161:2cc1468da177	1416	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
<>	161:2cc1468da177	1417	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	161:2cc1468da177	1418	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	161:2cc1468da177	1419	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
<>	161:2cc1468da177	1420	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	161:2cc1468da177	1421	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	161:2cc1468da177	1422	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
<>	161:2cc1468da177	1423	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	161:2cc1468da177	1424	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	161:2cc1468da177	1425	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
<>	161:2cc1468da177	1426	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	161:2cc1468da177	1427	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	161:2cc1468da177	1428	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
<>	161:2cc1468da177	1429	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	161:2cc1468da177	1430	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	161:2cc1468da177	1431	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
<>	161:2cc1468da177	1432	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	161:2cc1468da177	1433	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	161:2cc1468da177	1434	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
<>	161:2cc1468da177	1435	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	161:2cc1468da177	1436	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	161:2cc1468da177	1437	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
<>	161:2cc1468da177	1438	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	161:2cc1468da177	1439	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	161:2cc1468da177	1440	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
<>	161:2cc1468da177	1441	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	161:2cc1468da177	1442	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	161:2cc1468da177	1443	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
<>	161:2cc1468da177	1444	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	161:2cc1468da177	1445	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	161:2cc1468da177	1446	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
<>	161:2cc1468da177	1447	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	161:2cc1468da177	1448	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	161:2cc1468da177	1449	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
<>	161:2cc1468da177	1450	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	161:2cc1468da177	1451	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	161:2cc1468da177	1452	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
<>	161:2cc1468da177	1453	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	161:2cc1468da177	1454	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	161:2cc1468da177	1455	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
<>	161:2cc1468da177	1456	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	161:2cc1468da177	1457	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	161:2cc1468da177	1458	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
<>	161:2cc1468da177	1459	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	161:2cc1468da177	1460	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	161:2cc1468da177	1461	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
<>	161:2cc1468da177	1462	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	161:2cc1468da177	1463	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	161:2cc1468da177	1464	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
<>	161:2cc1468da177	1465	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	161:2cc1468da177	1466	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<>	161:2cc1468da177	1467	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
<>	161:2cc1468da177	1468	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	161:2cc1468da177	1469	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
<>	161:2cc1468da177	1470	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
<>	161:2cc1468da177	1471	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
<>	161:2cc1468da177	1472	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
<>	161:2cc1468da177	1473	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
<>	161:2cc1468da177	1474	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
<>	161:2cc1468da177	1475	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<>	161:2cc1468da177	1476	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
<>	161:2cc1468da177	1477	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
<>	161:2cc1468da177	1478	*
<>	161:2cc1468da177	1479	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	1480	* (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	1481	*/
<>	161:2cc1468da177	1482	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
<>	161:2cc1468da177	1483	(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
<>	161:2cc1468da177	1484	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
<>	161:2cc1468da177	1485	: \
<>	161:2cc1468da177	1486	((__GROUP__) == LL_ADC_GROUP_INJECTED) \
<>	161:2cc1468da177	1487	? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL) \
<>	161:2cc1468da177	1488	: \
<>	161:2cc1468da177	1489	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CR1_JAWDEN \| ADC_CR1_AWDEN \| ADC_CR1_AWDSGL) \
<>	161:2cc1468da177	1490	)
<>	161:2cc1468da177	1491
<>	161:2cc1468da177	1492	/**
<>	161:2cc1468da177	1493	* @brief Helper macro to set the value of ADC analog watchdog threshold high
<>	161:2cc1468da177	1494	* or low in function of ADC resolution, when ADC resolution is
<>	161:2cc1468da177	1495	* different of 12 bits.
<>	161:2cc1468da177	1496	* @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
<>	161:2cc1468da177	1497	* Example, with a ADC resolution of 8 bits, to set the value of
<>	161:2cc1468da177	1498	* analog watchdog threshold high (on 8 bits):
<>	161:2cc1468da177	1499	* LL_ADC_SetAnalogWDThresholds
<>	161:2cc1468da177	1500	* (< ADCx param >,
<>	161:2cc1468da177	1501	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
<>	161:2cc1468da177	1502	* );
<>	161:2cc1468da177	1503	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	161:2cc1468da177	1504	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1505	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1506	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1507	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1508	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	1509	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	1510	*/
<>	161:2cc1468da177	1511	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
<>	161:2cc1468da177	1512	((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
<>	161:2cc1468da177	1513
<>	161:2cc1468da177	1514	/**
<>	161:2cc1468da177	1515	* @brief Helper macro to get the value of ADC analog watchdog threshold high
<>	161:2cc1468da177	1516	* or low in function of ADC resolution, when ADC resolution is
<>	161:2cc1468da177	1517	* different of 12 bits.
<>	161:2cc1468da177	1518	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<>	161:2cc1468da177	1519	* Example, with a ADC resolution of 8 bits, to get the value of
<>	161:2cc1468da177	1520	* analog watchdog threshold high (on 8 bits):
<>	161:2cc1468da177	1521	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
<>	161:2cc1468da177	1522	* (LL_ADC_RESOLUTION_8B,
<>	161:2cc1468da177	1523	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
<>	161:2cc1468da177	1524	* );
<>	161:2cc1468da177	1525	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	161:2cc1468da177	1526	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1527	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1528	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1529	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1530	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	1531	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	1532	*/
<>	161:2cc1468da177	1533	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
<>	161:2cc1468da177	1534	((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))
<>	161:2cc1468da177	1535
<>	161:2cc1468da177	1536	/**
<>	161:2cc1468da177	1537	* @brief Helper macro to get the ADC multimode conversion data of ADC master
<>	161:2cc1468da177	1538	* or ADC slave from raw value with both ADC conversion data concatenated.
<>	161:2cc1468da177	1539	* @note This macro is intended to be used when multimode transfer by DMA
<>	161:2cc1468da177	1540	* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
<>	161:2cc1468da177	1541	* In this case the transferred data need to processed with this macro
<>	161:2cc1468da177	1542	* to separate the conversion data of ADC master and ADC slave.
<>	161:2cc1468da177	1543	* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
<>	161:2cc1468da177	1544	* @arg @ref LL_ADC_MULTI_MASTER
<>	161:2cc1468da177	1545	* @arg @ref LL_ADC_MULTI_SLAVE
<>	161:2cc1468da177	1546	* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	1547	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	1548	*/
<>	161:2cc1468da177	1549	#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
<>	161:2cc1468da177	1550	(((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
<>	161:2cc1468da177	1551
<>	161:2cc1468da177	1552	/**
<>	161:2cc1468da177	1553	* @brief Helper macro to select the ADC common instance
<>	161:2cc1468da177	1554	* to which is belonging the selected ADC instance.
<>	161:2cc1468da177	1555	* @note ADC common register instance can be used for:
<>	161:2cc1468da177	1556	* - Set parameters common to several ADC instances
<>	161:2cc1468da177	1557	* - Multimode (for devices with several ADC instances)
<>	161:2cc1468da177	1558	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	161:2cc1468da177	1559	* @param __ADCx__ ADC instance
<>	161:2cc1468da177	1560	* @retval ADC common register instance
<>	161:2cc1468da177	1561	*/
<>	161:2cc1468da177	1562	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
<>	161:2cc1468da177	1563	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	161:2cc1468da177	1564	(ADC123_COMMON)
<>	161:2cc1468da177	1565	#elif defined(ADC1) && defined(ADC2)
<>	161:2cc1468da177	1566	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	161:2cc1468da177	1567	(ADC12_COMMON)
<>	161:2cc1468da177	1568	#else
<>	161:2cc1468da177	1569	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	161:2cc1468da177	1570	(ADC1_COMMON)
<>	161:2cc1468da177	1571	#endif
<>	161:2cc1468da177	1572
<>	161:2cc1468da177	1573	/**
<>	161:2cc1468da177	1574	* @brief Helper macro to check if all ADC instances sharing the same
<>	161:2cc1468da177	1575	* ADC common instance are disabled.
<>	161:2cc1468da177	1576	* @note This check is required by functions with setting conditioned to
<>	161:2cc1468da177	1577	* ADC state:
<>	161:2cc1468da177	1578	* All ADC instances of the ADC common group must be disabled.
<>	161:2cc1468da177	1579	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	161:2cc1468da177	1580	* @note On devices with only 1 ADC common instance, parameter of this macro
<>	161:2cc1468da177	1581	* is useless and can be ignored (parameter kept for compatibility
<>	161:2cc1468da177	1582	* with devices featuring several ADC common instances).
<>	161:2cc1468da177	1583	* @param __ADCXY_COMMON__ ADC common instance
<>	161:2cc1468da177	1584	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	1585	* @retval Value "0" if all ADC instances sharing the same ADC common instance
<>	161:2cc1468da177	1586	* are disabled.
<>	161:2cc1468da177	1587	* Value "1" if at least one ADC instance sharing the same ADC common instance
<>	161:2cc1468da177	1588	* is enabled.
<>	161:2cc1468da177	1589	*/
<>	161:2cc1468da177	1590	#if defined(ADC1) && defined(ADC2) && defined(ADC3)
<>	161:2cc1468da177	1591	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	161:2cc1468da177	1592	(LL_ADC_IsEnabled(ADC1) \| \
<>	161:2cc1468da177	1593	LL_ADC_IsEnabled(ADC2) \| \
<>	161:2cc1468da177	1594	LL_ADC_IsEnabled(ADC3) )
<>	161:2cc1468da177	1595	#elif defined(ADC1) && defined(ADC2)
<>	161:2cc1468da177	1596	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	161:2cc1468da177	1597	(LL_ADC_IsEnabled(ADC1) \| \
<>	161:2cc1468da177	1598	LL_ADC_IsEnabled(ADC2) )
<>	161:2cc1468da177	1599	#else
<>	161:2cc1468da177	1600	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	161:2cc1468da177	1601	(LL_ADC_IsEnabled(ADC1))
<>	161:2cc1468da177	1602	#endif
<>	161:2cc1468da177	1603
<>	161:2cc1468da177	1604	/**
<>	161:2cc1468da177	1605	* @brief Helper macro to define the ADC conversion data full-scale digital
<>	161:2cc1468da177	1606	* value corresponding to the selected ADC resolution.
<>	161:2cc1468da177	1607	* @note ADC conversion data full-scale corresponds to voltage range
<>	161:2cc1468da177	1608	* determined by analog voltage references Vref+ and Vref-
<>	161:2cc1468da177	1609	* (refer to reference manual).
<>	161:2cc1468da177	1610	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	161:2cc1468da177	1611	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1612	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1613	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1614	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1615	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	161:2cc1468da177	1616	*/
<>	161:2cc1468da177	1617	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	161:2cc1468da177	1618	(0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
<>	161:2cc1468da177	1619
<>	161:2cc1468da177	1620	/**
<>	161:2cc1468da177	1621	* @brief Helper macro to convert the ADC conversion data from
<>	161:2cc1468da177	1622	* a resolution to another resolution.
<>	161:2cc1468da177	1623	* @param __DATA__ ADC conversion data to be converted
<>	161:2cc1468da177	1624	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
<>	161:2cc1468da177	1625	* This parameter can be one of the following values:
<>	161:2cc1468da177	1626	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1627	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1628	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1629	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1630	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
<>	161:2cc1468da177	1631	* This parameter can be one of the following values:
<>	161:2cc1468da177	1632	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1633	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1634	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1635	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1636	* @retval ADC conversion data to the requested resolution
<>	161:2cc1468da177	1637	*/
<>	161:2cc1468da177	1638	#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
<>	161:2cc1468da177	1639	(((__DATA__) \
<>	161:2cc1468da177	1640	<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \
<>	161:2cc1468da177	1641	>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \
<>	161:2cc1468da177	1642	)
<>	161:2cc1468da177	1643
<>	161:2cc1468da177	1644	/**
<>	161:2cc1468da177	1645	* @brief Helper macro to calculate the voltage (unit: mVolt)
<>	161:2cc1468da177	1646	* corresponding to a ADC conversion data (unit: digital value).
<>	161:2cc1468da177	1647	* @note Analog reference voltage (Vref+) must be either known from
<>	161:2cc1468da177	1648	* user board environment or can be calculated using ADC measurement
<>	161:2cc1468da177	1649	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	161:2cc1468da177	1650	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	161:2cc1468da177	1651	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
<>	161:2cc1468da177	1652	* (unit: digital value).
<>	161:2cc1468da177	1653	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	161:2cc1468da177	1654	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1655	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1656	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1657	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1658	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	161:2cc1468da177	1659	*/
<>	161:2cc1468da177	1660	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
<>	161:2cc1468da177	1661	__ADC_DATA__,\
<>	161:2cc1468da177	1662	__ADC_RESOLUTION__) \
<>	161:2cc1468da177	1663	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
<>	161:2cc1468da177	1664	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	161:2cc1468da177	1665	)
<>	161:2cc1468da177	1666
<>	161:2cc1468da177	1667	/**
<>	161:2cc1468da177	1668	* @brief Helper macro to calculate analog reference voltage (Vref+)
<>	161:2cc1468da177	1669	* (unit: mVolt) from ADC conversion data of internal voltage
<>	161:2cc1468da177	1670	* reference VrefInt.
<>	161:2cc1468da177	1671	* @note Computation is using VrefInt calibration value
<>	161:2cc1468da177	1672	* stored in system memory for each device during production.
<>	161:2cc1468da177	1673	* @note This voltage depends on user board environment: voltage level
<>	161:2cc1468da177	1674	* connected to pin Vref+.
<>	161:2cc1468da177	1675	* On devices with small package, the pin Vref+ is not present
<>	161:2cc1468da177	1676	* and internally bonded to pin Vdda.
<>	161:2cc1468da177	1677	* @note On this STM32 serie, calibration data of internal voltage reference
<>	161:2cc1468da177	1678	* VrefInt corresponds to a resolution of 12 bits,
<>	161:2cc1468da177	1679	* this is the recommended ADC resolution to convert voltage of
<>	161:2cc1468da177	1680	* internal voltage reference VrefInt.
<>	161:2cc1468da177	1681	* Otherwise, this macro performs the processing to scale
<>	161:2cc1468da177	1682	* ADC conversion data to 12 bits.
<>	161:2cc1468da177	1683	* @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
<>	161:2cc1468da177	1684	* of internal voltage reference VrefInt (unit: digital value).
<>	161:2cc1468da177	1685	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	161:2cc1468da177	1686	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1687	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1688	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1689	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1690	* @retval Analog reference voltage (unit: mV)
<>	161:2cc1468da177	1691	*/
<>	161:2cc1468da177	1692	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
<>	161:2cc1468da177	1693	__ADC_RESOLUTION__) \
<>	161:2cc1468da177	1694	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) \
<>	161:2cc1468da177	1695	/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
<>	161:2cc1468da177	1696	(__ADC_RESOLUTION__), \
<>	161:2cc1468da177	1697	LL_ADC_RESOLUTION_12B) \
<>	161:2cc1468da177	1698	)
<>	161:2cc1468da177	1699
<>	161:2cc1468da177	1700	/**
<>	161:2cc1468da177	1701	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	161:2cc1468da177	1702	* from ADC conversion data of internal temperature sensor.
<>	161:2cc1468da177	1703	* @note Computation is using temperature sensor calibration values
<>	161:2cc1468da177	1704	* stored in system memory for each device during production.
<>	161:2cc1468da177	1705	* @note Calculation formula:
<>	161:2cc1468da177	1706	* Temperature = ((TS_ADC_DATA - TS_CAL1)
<>	161:2cc1468da177	1707	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
<>	161:2cc1468da177	1708	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
<>	161:2cc1468da177	1709	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	161:2cc1468da177	1710	* Avg_Slope = (TS_CAL2 - TS_CAL1)
<>	161:2cc1468da177	1711	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
<>	161:2cc1468da177	1712	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
<>	161:2cc1468da177	1713	* TEMP_DEGC_CAL1 (calibrated in factory)
<>	161:2cc1468da177	1714	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
<>	161:2cc1468da177	1715	* TEMP_DEGC_CAL2 (calibrated in factory)
<>	161:2cc1468da177	1716	* Caution: Calculation relevancy under reserve that calibration
<>	161:2cc1468da177	1717	* parameters are correct (address and data).
<>	161:2cc1468da177	1718	* To calculate temperature using temperature sensor
<>	161:2cc1468da177	1719	* datasheet typical values (generic values less, therefore
<>	161:2cc1468da177	1720	* less accurate than calibrated values),
<>	161:2cc1468da177	1721	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
<>	161:2cc1468da177	1722	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	161:2cc1468da177	1723	* defined as it impacts the ADC LSB equivalent voltage.
<>	161:2cc1468da177	1724	* @note Analog reference voltage (Vref+) must be either known from
<>	161:2cc1468da177	1725	* user board environment or can be calculated using ADC measurement
<>	161:2cc1468da177	1726	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	161:2cc1468da177	1727	* @note On this STM32 serie, calibration data of temperature sensor
<>	161:2cc1468da177	1728	* corresponds to a resolution of 12 bits,
<>	161:2cc1468da177	1729	* this is the recommended ADC resolution to convert voltage of
<>	161:2cc1468da177	1730	* temperature sensor.
<>	161:2cc1468da177	1731	* Otherwise, this macro performs the processing to scale
<>	161:2cc1468da177	1732	* ADC conversion data to 12 bits.
<>	161:2cc1468da177	1733	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	161:2cc1468da177	1734	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
<>	161:2cc1468da177	1735	* temperature sensor (unit: digital value).
<>	161:2cc1468da177	1736	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
<>	161:2cc1468da177	1737	* sensor voltage has been measured.
<>	161:2cc1468da177	1738	* This parameter can be one of the following values:
<>	161:2cc1468da177	1739	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1740	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1741	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1742	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1743	* @retval Temperature (unit: degree Celsius)
<>	161:2cc1468da177	1744	*/
<>	161:2cc1468da177	1745	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
<>	161:2cc1468da177	1746	__TEMPSENSOR_ADC_DATA__,\
<>	161:2cc1468da177	1747	__ADC_RESOLUTION__) \
<>	161:2cc1468da177	1748	(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
<>	161:2cc1468da177	1749	(__ADC_RESOLUTION__), \
<>	161:2cc1468da177	1750	LL_ADC_RESOLUTION_12B) \
<>	161:2cc1468da177	1751	* (__VREFANALOG_VOLTAGE__)) \
<>	161:2cc1468da177	1752	/ TEMPSENSOR_CAL_VREFANALOG) \
<>	161:2cc1468da177	1753	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
<>	161:2cc1468da177	1754	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
<>	161:2cc1468da177	1755	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
<>	161:2cc1468da177	1756	) + TEMPSENSOR_CAL1_TEMP \
<>	161:2cc1468da177	1757	)
<>	161:2cc1468da177	1758
<>	161:2cc1468da177	1759	/**
<>	161:2cc1468da177	1760	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	161:2cc1468da177	1761	* from ADC conversion data of internal temperature sensor.
<>	161:2cc1468da177	1762	* @note Computation is using temperature sensor typical values
<>	161:2cc1468da177	1763	* (refer to device datasheet).
<>	161:2cc1468da177	1764	* @note Calculation formula:
<>	161:2cc1468da177	1765	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
<>	161:2cc1468da177	1766	* / Avg_Slope + CALx_TEMP
<>	161:2cc1468da177	1767	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	161:2cc1468da177	1768	* (unit: digital value)
<>	161:2cc1468da177	1769	* Avg_Slope = temperature sensor slope
<>	161:2cc1468da177	1770	* (unit: uV/Degree Celsius)
<>	161:2cc1468da177	1771	* TS_TYP_CALx_VOLT = temperature sensor digital value at
<>	161:2cc1468da177	1772	* temperature CALx_TEMP (unit: mV)
<>	161:2cc1468da177	1773	* Caution: Calculation relevancy under reserve the temperature sensor
<>	161:2cc1468da177	1774	* of the current device has characteristics in line with
<>	161:2cc1468da177	1775	* datasheet typical values.
<>	161:2cc1468da177	1776	* If temperature sensor calibration values are available on
<>	161:2cc1468da177	1777	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
<>	161:2cc1468da177	1778	* temperature calculation will be more accurate using
<>	161:2cc1468da177	1779	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
<>	161:2cc1468da177	1780	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	161:2cc1468da177	1781	* defined as it impacts the ADC LSB equivalent voltage.
<>	161:2cc1468da177	1782	* @note Analog reference voltage (Vref+) must be either known from
<>	161:2cc1468da177	1783	* user board environment or can be calculated using ADC measurement
<>	161:2cc1468da177	1784	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	161:2cc1468da177	1785	* @note ADC measurement data must correspond to a resolution of 12bits
<>	161:2cc1468da177	1786	* (full scale digital value 4095). If not the case, the data must be
<>	161:2cc1468da177	1787	* preliminarily rescaled to an equivalent resolution of 12 bits.
<>	161:2cc1468da177	1788	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
<>	161:2cc1468da177	1789	* On STM32F7, refer to device datasheet parameter "Avg_Slope".
<>	161:2cc1468da177	1790	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
<>	161:2cc1468da177	1791	* On STM32F4, refer to device datasheet parameter "V25".
<>	161:2cc1468da177	1792	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
<>	161:2cc1468da177	1793	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
<>	161:2cc1468da177	1794	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
<>	161:2cc1468da177	1795	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
<>	161:2cc1468da177	1796	* This parameter can be one of the following values:
<>	161:2cc1468da177	1797	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	1798	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	1799	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	1800	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	1801	* @retval Temperature (unit: degree Celsius)
<>	161:2cc1468da177	1802	*/
<>	161:2cc1468da177	1803	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
<>	161:2cc1468da177	1804	__TEMPSENSOR_TYP_CALX_V__,\
<>	161:2cc1468da177	1805	__TEMPSENSOR_CALX_TEMP__,\
<>	161:2cc1468da177	1806	__VREFANALOG_VOLTAGE__,\
<>	161:2cc1468da177	1807	__TEMPSENSOR_ADC_DATA__,\
<>	161:2cc1468da177	1808	__ADC_RESOLUTION__) \
<>	161:2cc1468da177	1809	((( ( \
<>	161:2cc1468da177	1810	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
<>	161:2cc1468da177	1811	* 1000) \
<>	161:2cc1468da177	1812	- \
<>	161:2cc1468da177	1813	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
<>	161:2cc1468da177	1814	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
<>	161:2cc1468da177	1815	* 1000) \
<>	161:2cc1468da177	1816	) \
<>	161:2cc1468da177	1817	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
<>	161:2cc1468da177	1818	) + (__TEMPSENSOR_CALX_TEMP__) \
<>	161:2cc1468da177	1819	)
<>	161:2cc1468da177	1820
<>	161:2cc1468da177	1821	/**
<>	161:2cc1468da177	1822	* @}
<>	161:2cc1468da177	1823	*/
<>	161:2cc1468da177	1824
<>	161:2cc1468da177	1825	/**
<>	161:2cc1468da177	1826	* @}
<>	161:2cc1468da177	1827	*/
<>	161:2cc1468da177	1828
<>	161:2cc1468da177	1829
<>	161:2cc1468da177	1830	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	1831	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
<>	161:2cc1468da177	1832	* @{
<>	161:2cc1468da177	1833	*/
<>	161:2cc1468da177	1834
<>	161:2cc1468da177	1835	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
<>	161:2cc1468da177	1836	* @{
<>	161:2cc1468da177	1837	*/
<>	161:2cc1468da177	1838	/* Note: LL ADC functions to set DMA transfer are located into sections of */
<>	161:2cc1468da177	1839	/* configuration of ADC instance, groups and multimode (if available): */
<>	161:2cc1468da177	1840	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
<>	161:2cc1468da177	1841
<>	161:2cc1468da177	1842	/**
<>	161:2cc1468da177	1843	* @brief Function to help to configure DMA transfer from ADC: retrieve the
<>	161:2cc1468da177	1844	* ADC register address from ADC instance and a list of ADC registers
<>	161:2cc1468da177	1845	* intended to be used (most commonly) with DMA transfer.
<>	161:2cc1468da177	1846	* @note These ADC registers are data registers:
<>	161:2cc1468da177	1847	* when ADC conversion data is available in ADC data registers,
<>	161:2cc1468da177	1848	* ADC generates a DMA transfer request.
<>	161:2cc1468da177	1849	* @note This macro is intended to be used with LL DMA driver, refer to
<>	161:2cc1468da177	1850	* function "LL_DMA_ConfigAddresses()".
<>	161:2cc1468da177	1851	* Example:
<>	161:2cc1468da177	1852	* LL_DMA_ConfigAddresses(DMA1,
<>	161:2cc1468da177	1853	* LL_DMA_CHANNEL_1,
<>	161:2cc1468da177	1854	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
<>	161:2cc1468da177	1855	* (uint32_t)&< array or variable >,
<>	161:2cc1468da177	1856	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
<>	161:2cc1468da177	1857	* @note For devices with several ADC: in multimode, some devices
<>	161:2cc1468da177	1858	* use a different data register outside of ADC instance scope
<>	161:2cc1468da177	1859	* (common data register). This macro manages this register difference,
<>	161:2cc1468da177	1860	* only ADC instance has to be set as parameter.
<>	161:2cc1468da177	1861	* @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
<>	161:2cc1468da177	1862	* CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
<>	161:2cc1468da177	1863	* CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
<>	161:2cc1468da177	1864	* @param ADCx ADC instance
<>	161:2cc1468da177	1865	* @param Register This parameter can be one of the following values:
<>	161:2cc1468da177	1866	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
<>	161:2cc1468da177	1867	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
<>	161:2cc1468da177	1868	*
<>	161:2cc1468da177	1869	* (1) Available on devices with several ADC instances.
<>	161:2cc1468da177	1870	* @retval ADC register address
<>	161:2cc1468da177	1871	*/
<>	161:2cc1468da177	1872	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
<>	161:2cc1468da177	1873	{
<>	161:2cc1468da177	1874	register uint32_t data_reg_addr = 0U;
<>	161:2cc1468da177	1875
<>	161:2cc1468da177	1876	if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
<>	161:2cc1468da177	1877	{
<>	161:2cc1468da177	1878	/* Retrieve address of register DR */
<>	161:2cc1468da177	1879	data_reg_addr = (uint32_t)&(ADCx->DR);
<>	161:2cc1468da177	1880	}
<>	161:2cc1468da177	1881	else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
<>	161:2cc1468da177	1882	{
<>	161:2cc1468da177	1883	/* Retrieve address of register CDR */
<>	161:2cc1468da177	1884	data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
<>	161:2cc1468da177	1885	}
<>	161:2cc1468da177	1886
<>	161:2cc1468da177	1887	return data_reg_addr;
<>	161:2cc1468da177	1888	}
<>	161:2cc1468da177	1889
<>	161:2cc1468da177	1890	/**
<>	161:2cc1468da177	1891	* @}
<>	161:2cc1468da177	1892	*/
<>	161:2cc1468da177	1893
<>	161:2cc1468da177	1894	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
<>	161:2cc1468da177	1895	* @{
<>	161:2cc1468da177	1896	*/
<>	161:2cc1468da177	1897
<>	161:2cc1468da177	1898	/**
<>	161:2cc1468da177	1899	* @brief Set parameter common to several ADC: Clock source and prescaler.
<>	161:2cc1468da177	1900	* @rmtoll CCR ADCPRE LL_ADC_SetCommonClock
<>	161:2cc1468da177	1901	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	1902	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	1903	* @param CommonClock This parameter can be one of the following values:
<>	161:2cc1468da177	1904	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	161:2cc1468da177	1905	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	161:2cc1468da177	1906	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
<>	161:2cc1468da177	1907	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
<>	161:2cc1468da177	1908	* @retval None
<>	161:2cc1468da177	1909	*/
<>	161:2cc1468da177	1910	__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
<>	161:2cc1468da177	1911	{
<>	161:2cc1468da177	1912	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
<>	161:2cc1468da177	1913	}
<>	161:2cc1468da177	1914
<>	161:2cc1468da177	1915	/**
<>	161:2cc1468da177	1916	* @brief Get parameter common to several ADC: Clock source and prescaler.
<>	161:2cc1468da177	1917	* @rmtoll CCR ADCPRE LL_ADC_GetCommonClock
<>	161:2cc1468da177	1918	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	1919	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	1920	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1921	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	161:2cc1468da177	1922	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	161:2cc1468da177	1923	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6
<>	161:2cc1468da177	1924	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8
<>	161:2cc1468da177	1925	*/
<>	161:2cc1468da177	1926	__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	1927	{
<>	161:2cc1468da177	1928	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
<>	161:2cc1468da177	1929	}
<>	161:2cc1468da177	1930
<>	161:2cc1468da177	1931	/**
<>	161:2cc1468da177	1932	* @brief Set parameter common to several ADC: measurement path to internal
<>	161:2cc1468da177	1933	* channels (VrefInt, temperature sensor, ...).
<>	161:2cc1468da177	1934	* @note One or several values can be selected.
<>	161:2cc1468da177	1935	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	161:2cc1468da177	1936	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	161:2cc1468da177	1937	* @note Stabilization time of measurement path to internal channel:
<>	161:2cc1468da177	1938	* After enabling internal paths, before starting ADC conversion,
<>	161:2cc1468da177	1939	* a delay is required for internal voltage reference and
<>	161:2cc1468da177	1940	* temperature sensor stabilization time.
<>	161:2cc1468da177	1941	* Refer to device datasheet.
<>	161:2cc1468da177	1942	* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
<>	161:2cc1468da177	1943	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
<>	161:2cc1468da177	1944	* @note ADC internal channel sampling time constraint:
<>	161:2cc1468da177	1945	* For ADC conversion of internal channels,
<>	161:2cc1468da177	1946	* a sampling time minimum value is required.
<>	161:2cc1468da177	1947	* Refer to device datasheet.
<>	161:2cc1468da177	1948	* @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n
<>	161:2cc1468da177	1949	* CCR VBATE LL_ADC_SetCommonPathInternalCh
<>	161:2cc1468da177	1950	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	1951	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	1952	* @param PathInternal This parameter can be a combination of the following values:
<>	161:2cc1468da177	1953	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	161:2cc1468da177	1954	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	161:2cc1468da177	1955	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	161:2cc1468da177	1956	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
<>	161:2cc1468da177	1957	* @retval None
<>	161:2cc1468da177	1958	*/
<>	161:2cc1468da177	1959	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
<>	161:2cc1468da177	1960	{
<>	161:2cc1468da177	1961	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE \| ADC_CCR_VBATE, PathInternal);
<>	161:2cc1468da177	1962	}
<>	161:2cc1468da177	1963
<>	161:2cc1468da177	1964	/**
<>	161:2cc1468da177	1965	* @brief Get parameter common to several ADC: measurement path to internal
<>	161:2cc1468da177	1966	* channels (VrefInt, temperature sensor, ...).
<>	161:2cc1468da177	1967	* @note One or several values can be selected.
<>	161:2cc1468da177	1968	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	161:2cc1468da177	1969	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	161:2cc1468da177	1970	* @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n
<>	161:2cc1468da177	1971	* CCR VBATE LL_ADC_GetCommonPathInternalCh
<>	161:2cc1468da177	1972	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	1973	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	1974	* @retval Returned value can be a combination of the following values:
<>	161:2cc1468da177	1975	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	161:2cc1468da177	1976	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	161:2cc1468da177	1977	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	161:2cc1468da177	1978	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
<>	161:2cc1468da177	1979	*/
<>	161:2cc1468da177	1980	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	1981	{
<>	161:2cc1468da177	1982	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE \| ADC_CCR_VBATE));
<>	161:2cc1468da177	1983	}
<>	161:2cc1468da177	1984
<>	161:2cc1468da177	1985	/**
<>	161:2cc1468da177	1986	* @}
<>	161:2cc1468da177	1987	*/
<>	161:2cc1468da177	1988
<>	161:2cc1468da177	1989	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
<>	161:2cc1468da177	1990	* @{
<>	161:2cc1468da177	1991	*/
<>	161:2cc1468da177	1992
<>	161:2cc1468da177	1993	/**
<>	161:2cc1468da177	1994	* @brief Set ADC resolution.
<>	161:2cc1468da177	1995	* Refer to reference manual for alignments formats
<>	161:2cc1468da177	1996	* dependencies to ADC resolutions.
<>	161:2cc1468da177	1997	* @rmtoll CR1 RES LL_ADC_SetResolution
<>	161:2cc1468da177	1998	* @param ADCx ADC instance
<>	161:2cc1468da177	1999	* @param Resolution This parameter can be one of the following values:
<>	161:2cc1468da177	2000	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	2001	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	2002	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	2003	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	2004	* @retval None
<>	161:2cc1468da177	2005	*/
<>	161:2cc1468da177	2006	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
<>	161:2cc1468da177	2007	{
<>	161:2cc1468da177	2008	MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
<>	161:2cc1468da177	2009	}
<>	161:2cc1468da177	2010
<>	161:2cc1468da177	2011	/**
<>	161:2cc1468da177	2012	* @brief Get ADC resolution.
<>	161:2cc1468da177	2013	* Refer to reference manual for alignments formats
<>	161:2cc1468da177	2014	* dependencies to ADC resolutions.
<>	161:2cc1468da177	2015	* @rmtoll CR1 RES LL_ADC_GetResolution
<>	161:2cc1468da177	2016	* @param ADCx ADC instance
<>	161:2cc1468da177	2017	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2018	* @arg @ref LL_ADC_RESOLUTION_12B
<>	161:2cc1468da177	2019	* @arg @ref LL_ADC_RESOLUTION_10B
<>	161:2cc1468da177	2020	* @arg @ref LL_ADC_RESOLUTION_8B
<>	161:2cc1468da177	2021	* @arg @ref LL_ADC_RESOLUTION_6B
<>	161:2cc1468da177	2022	*/
<>	161:2cc1468da177	2023	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2024	{
<>	161:2cc1468da177	2025	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
<>	161:2cc1468da177	2026	}
<>	161:2cc1468da177	2027
<>	161:2cc1468da177	2028	/**
<>	161:2cc1468da177	2029	* @brief Set ADC conversion data alignment.
<>	161:2cc1468da177	2030	* @note Refer to reference manual for alignments formats
<>	161:2cc1468da177	2031	* dependencies to ADC resolutions.
<>	161:2cc1468da177	2032	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
<>	161:2cc1468da177	2033	* @param ADCx ADC instance
<>	161:2cc1468da177	2034	* @param DataAlignment This parameter can be one of the following values:
<>	161:2cc1468da177	2035	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	161:2cc1468da177	2036	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	161:2cc1468da177	2037	* @retval None
<>	161:2cc1468da177	2038	*/
<>	161:2cc1468da177	2039	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
<>	161:2cc1468da177	2040	{
<>	161:2cc1468da177	2041	MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
<>	161:2cc1468da177	2042	}
<>	161:2cc1468da177	2043
<>	161:2cc1468da177	2044	/**
<>	161:2cc1468da177	2045	* @brief Get ADC conversion data alignment.
<>	161:2cc1468da177	2046	* @note Refer to reference manual for alignments formats
<>	161:2cc1468da177	2047	* dependencies to ADC resolutions.
<>	161:2cc1468da177	2048	* @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
<>	161:2cc1468da177	2049	* @param ADCx ADC instance
<>	161:2cc1468da177	2050	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2051	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	161:2cc1468da177	2052	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	161:2cc1468da177	2053	*/
<>	161:2cc1468da177	2054	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2055	{
<>	161:2cc1468da177	2056	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
<>	161:2cc1468da177	2057	}
<>	161:2cc1468da177	2058
<>	161:2cc1468da177	2059	/**
<>	161:2cc1468da177	2060	* @brief Set ADC sequencers scan mode, for all ADC groups
<>	161:2cc1468da177	2061	* (group regular, group injected).
<>	161:2cc1468da177	2062	* @note According to sequencers scan mode :
<>	161:2cc1468da177	2063	* - If disabled: ADC conversion is performed in unitary conversion
<>	161:2cc1468da177	2064	* mode (one channel converted, that defined in rank 1).
<>	161:2cc1468da177	2065	* Configuration of sequencers of all ADC groups
<>	161:2cc1468da177	2066	* (sequencer scan length, ...) is discarded: equivalent to
<>	161:2cc1468da177	2067	* scan length of 1 rank.
<>	161:2cc1468da177	2068	* - If enabled: ADC conversions are performed in sequence conversions
<>	161:2cc1468da177	2069	* mode, according to configuration of sequencers of
<>	161:2cc1468da177	2070	* each ADC group (sequencer scan length, ...).
<>	161:2cc1468da177	2071	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
<>	161:2cc1468da177	2072	* and to function @ref LL_ADC_INJ_SetSequencerLength().
<>	161:2cc1468da177	2073	* @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
<>	161:2cc1468da177	2074	* @param ADCx ADC instance
<>	161:2cc1468da177	2075	* @param ScanMode This parameter can be one of the following values:
<>	161:2cc1468da177	2076	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
<>	161:2cc1468da177	2077	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
<>	161:2cc1468da177	2078	* @retval None
<>	161:2cc1468da177	2079	*/
<>	161:2cc1468da177	2080	__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
<>	161:2cc1468da177	2081	{
<>	161:2cc1468da177	2082	MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
<>	161:2cc1468da177	2083	}
<>	161:2cc1468da177	2084
<>	161:2cc1468da177	2085	/**
<>	161:2cc1468da177	2086	* @brief Get ADC sequencers scan mode, for all ADC groups
<>	161:2cc1468da177	2087	* (group regular, group injected).
<>	161:2cc1468da177	2088	* @note According to sequencers scan mode :
<>	161:2cc1468da177	2089	* - If disabled: ADC conversion is performed in unitary conversion
<>	161:2cc1468da177	2090	* mode (one channel converted, that defined in rank 1).
<>	161:2cc1468da177	2091	* Configuration of sequencers of all ADC groups
<>	161:2cc1468da177	2092	* (sequencer scan length, ...) is discarded: equivalent to
<>	161:2cc1468da177	2093	* scan length of 1 rank.
<>	161:2cc1468da177	2094	* - If enabled: ADC conversions are performed in sequence conversions
<>	161:2cc1468da177	2095	* mode, according to configuration of sequencers of
<>	161:2cc1468da177	2096	* each ADC group (sequencer scan length, ...).
<>	161:2cc1468da177	2097	* Refer to function @ref LL_ADC_REG_SetSequencerLength()
<>	161:2cc1468da177	2098	* and to function @ref LL_ADC_INJ_SetSequencerLength().
<>	161:2cc1468da177	2099	* @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
<>	161:2cc1468da177	2100	* @param ADCx ADC instance
<>	161:2cc1468da177	2101	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2102	* @arg @ref LL_ADC_SEQ_SCAN_DISABLE
<>	161:2cc1468da177	2103	* @arg @ref LL_ADC_SEQ_SCAN_ENABLE
<>	161:2cc1468da177	2104	*/
<>	161:2cc1468da177	2105	__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2106	{
<>	161:2cc1468da177	2107	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
<>	161:2cc1468da177	2108	}
<>	161:2cc1468da177	2109
<>	161:2cc1468da177	2110	/**
<>	161:2cc1468da177	2111	* @}
<>	161:2cc1468da177	2112	*/
<>	161:2cc1468da177	2113
<>	161:2cc1468da177	2114	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
<>	161:2cc1468da177	2115	* @{
<>	161:2cc1468da177	2116	*/
<>	161:2cc1468da177	2117
<>	161:2cc1468da177	2118	/**
<>	161:2cc1468da177	2119	* @brief Set ADC group regular conversion trigger source:
<>	161:2cc1468da177	2120	* internal (SW start) or from external IP (timer event,
<>	161:2cc1468da177	2121	* external interrupt line).
<>	161:2cc1468da177	2122	* @note On this STM32 serie, setting of external trigger edge is performed
<>	161:2cc1468da177	2123	* using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	161:2cc1468da177	2124	* @note Availability of parameters of trigger sources from timer
<>	161:2cc1468da177	2125	* depends on timers availability on the selected device.
<>	161:2cc1468da177	2126	* @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n
<>	161:2cc1468da177	2127	* CR2 EXTEN LL_ADC_REG_SetTriggerSource
<>	161:2cc1468da177	2128	* @param ADCx ADC instance
<>	161:2cc1468da177	2129	* @param TriggerSource This parameter can be one of the following values:
<>	161:2cc1468da177	2130	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	161:2cc1468da177	2131	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
<>	161:2cc1468da177	2132	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
<>	161:2cc1468da177	2133	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
<>	161:2cc1468da177	2134	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	161:2cc1468da177	2135	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
<>	161:2cc1468da177	2136	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	161:2cc1468da177	2137	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
<>	161:2cc1468da177	2138	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
<>	161:2cc1468da177	2139	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
<>	161:2cc1468da177	2140	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	161:2cc1468da177	2141	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
<>	161:2cc1468da177	2142	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	161:2cc1468da177	2143	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	161:2cc1468da177	2144	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	161:2cc1468da177	2145	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	161:2cc1468da177	2146	* @retval None
<>	161:2cc1468da177	2147	*/
<>	161:2cc1468da177	2148	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	161:2cc1468da177	2149	{
<>	161:2cc1468da177	2150	/* Note: On this STM32 serie, ADC group regular external trigger edge */
<>	161:2cc1468da177	2151	/* is used to perform a ADC conversion start. */
<>	161:2cc1468da177	2152	/* This function does not set external trigger edge. */
<>	161:2cc1468da177	2153	/* This feature is set using function */
<>	161:2cc1468da177	2154	/* @ref LL_ADC_REG_StartConversionExtTrig(). */
<>	161:2cc1468da177	2155	MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
<>	161:2cc1468da177	2156	}
<>	161:2cc1468da177	2157
<>	161:2cc1468da177	2158	/**
<>	161:2cc1468da177	2159	* @brief Get ADC group regular conversion trigger source:
<>	161:2cc1468da177	2160	* internal (SW start) or from external IP (timer event,
<>	161:2cc1468da177	2161	* external interrupt line).
<>	161:2cc1468da177	2162	* @note To determine whether group regular trigger source is
<>	161:2cc1468da177	2163	* internal (SW start) or external, without detail
<>	161:2cc1468da177	2164	* of which peripheral is selected as external trigger,
<>	161:2cc1468da177	2165	* (equivalent to
<>	161:2cc1468da177	2166	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
<>	161:2cc1468da177	2167	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
<>	161:2cc1468da177	2168	* @note Availability of parameters of trigger sources from timer
<>	161:2cc1468da177	2169	* depends on timers availability on the selected device.
<>	161:2cc1468da177	2170	* @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n
<>	161:2cc1468da177	2171	* CR2 EXTEN LL_ADC_REG_GetTriggerSource
<>	161:2cc1468da177	2172	* @param ADCx ADC instance
<>	161:2cc1468da177	2173	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2174	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	161:2cc1468da177	2175	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1
<>	161:2cc1468da177	2176	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2
<>	161:2cc1468da177	2177	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
<>	161:2cc1468da177	2178	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2
<>	161:2cc1468da177	2179	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO
<>	161:2cc1468da177	2180	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4
<>	161:2cc1468da177	2181	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4
<>	161:2cc1468da177	2182	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
<>	161:2cc1468da177	2183	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
<>	161:2cc1468da177	2184	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	161:2cc1468da177	2185	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
<>	161:2cc1468da177	2186	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
<>	161:2cc1468da177	2187	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
<>	161:2cc1468da177	2188	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
<>	161:2cc1468da177	2189	* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
<>	161:2cc1468da177	2190	*/
<>	161:2cc1468da177	2191	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2192	{
<>	161:2cc1468da177	2193	register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL \| ADC_CR2_EXTEN);
<>	161:2cc1468da177	2194
<>	161:2cc1468da177	2195	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	161:2cc1468da177	2196	/* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
<>	161:2cc1468da177	2197	register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	161:2cc1468da177	2198
<>	161:2cc1468da177	2199	/* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
<>	161:2cc1468da177	2200	/* to match with triggers literals definition. */
<>	161:2cc1468da177	2201	return ((TriggerSource
<>	161:2cc1468da177	2202	& (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
<>	161:2cc1468da177	2203	\| ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
<>	161:2cc1468da177	2204	);
<>	161:2cc1468da177	2205	}
<>	161:2cc1468da177	2206
<>	161:2cc1468da177	2207	/**
<>	161:2cc1468da177	2208	* @brief Get ADC group regular conversion trigger source internal (SW start)
<>	161:2cc1468da177	2209	or external.
<>	161:2cc1468da177	2210	* @note In case of group regular trigger source set to external trigger,
<>	161:2cc1468da177	2211	* to determine which peripheral is selected as external trigger,
<>	161:2cc1468da177	2212	* use function @ref LL_ADC_REG_GetTriggerSource().
<>	161:2cc1468da177	2213	* @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
<>	161:2cc1468da177	2214	* @param ADCx ADC instance
<>	161:2cc1468da177	2215	* @retval Value "0" if trigger source external trigger
<>	161:2cc1468da177	2216	* Value "1" if trigger source SW start.
<>	161:2cc1468da177	2217	*/
<>	161:2cc1468da177	2218	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2219	{
<>	161:2cc1468da177	2220	return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
<>	161:2cc1468da177	2221	}
<>	161:2cc1468da177	2222
<>	161:2cc1468da177	2223	/**
<>	161:2cc1468da177	2224	* @brief Get ADC group regular conversion trigger polarity.
<>	161:2cc1468da177	2225	* @note Applicable only for trigger source set to external trigger.
<>	161:2cc1468da177	2226	* @note On this STM32 serie, setting of external trigger edge is performed
<>	161:2cc1468da177	2227	* using function @ref LL_ADC_REG_StartConversionExtTrig().
<>	161:2cc1468da177	2228	* @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge
<>	161:2cc1468da177	2229	* @param ADCx ADC instance
<>	161:2cc1468da177	2230	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2231	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	161:2cc1468da177	2232	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	161:2cc1468da177	2233	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	161:2cc1468da177	2234	*/
<>	161:2cc1468da177	2235	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2236	{
<>	161:2cc1468da177	2237	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
<>	161:2cc1468da177	2238	}
<>	161:2cc1468da177	2239
<>	161:2cc1468da177	2240
<>	161:2cc1468da177	2241	/**
<>	161:2cc1468da177	2242	* @brief Set ADC group regular sequencer length and scan direction.
<>	161:2cc1468da177	2243	* @note Description of ADC group regular sequencer features:
<>	161:2cc1468da177	2244	* - For devices with sequencer fully configurable
<>	161:2cc1468da177	2245	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	161:2cc1468da177	2246	* sequencer length and each rank affectation to a channel
<>	161:2cc1468da177	2247	* are configurable.
<>	161:2cc1468da177	2248	* This function performs configuration of:
<>	161:2cc1468da177	2249	* - Sequence length: Number of ranks in the scan sequence.
<>	161:2cc1468da177	2250	* - Sequence direction: Unless specified in parameters, sequencer
<>	161:2cc1468da177	2251	* scan direction is forward (from rank 1 to rank n).
<>	161:2cc1468da177	2252	* Sequencer ranks are selected using
<>	161:2cc1468da177	2253	* function "LL_ADC_REG_SetSequencerRanks()".
<>	161:2cc1468da177	2254	* - For devices with sequencer not fully configurable
<>	161:2cc1468da177	2255	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	161:2cc1468da177	2256	* sequencer length and each rank affectation to a channel
<>	161:2cc1468da177	2257	* are defined by channel number.
<>	161:2cc1468da177	2258	* This function performs configuration of:
<>	161:2cc1468da177	2259	* - Sequence length: Number of ranks in the scan sequence is
<>	161:2cc1468da177	2260	* defined by number of channels set in the sequence,
<>	161:2cc1468da177	2261	* rank of each channel is fixed by channel HW number.
<>	161:2cc1468da177	2262	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	161:2cc1468da177	2263	* - Sequence direction: Unless specified in parameters, sequencer
<>	161:2cc1468da177	2264	* scan direction is forward (from lowest channel number to
<>	161:2cc1468da177	2265	* highest channel number).
<>	161:2cc1468da177	2266	* Sequencer ranks are selected using
<>	161:2cc1468da177	2267	* function "LL_ADC_REG_SetSequencerChannels()".
<>	161:2cc1468da177	2268	* @note On this STM32 serie, group regular sequencer configuration
<>	161:2cc1468da177	2269	* is conditioned to ADC instance sequencer mode.
<>	161:2cc1468da177	2270	* If ADC instance sequencer mode is disabled, sequencers of
<>	161:2cc1468da177	2271	* all groups (group regular, group injected) can be configured
<>	161:2cc1468da177	2272	* but their execution is disabled (limited to rank 1).
<>	161:2cc1468da177	2273	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	161:2cc1468da177	2274	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	161:2cc1468da177	2275	* ADC conversion on only 1 channel.
<>	161:2cc1468da177	2276	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
<>	161:2cc1468da177	2277	* @param ADCx ADC instance
<>	161:2cc1468da177	2278	* @param SequencerNbRanks This parameter can be one of the following values:
<>	161:2cc1468da177	2279	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	161:2cc1468da177	2280	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	161:2cc1468da177	2281	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	161:2cc1468da177	2282	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	161:2cc1468da177	2283	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	161:2cc1468da177	2284	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	161:2cc1468da177	2285	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	161:2cc1468da177	2286	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	161:2cc1468da177	2287	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	161:2cc1468da177	2288	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	161:2cc1468da177	2289	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	161:2cc1468da177	2290	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	161:2cc1468da177	2291	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	161:2cc1468da177	2292	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	161:2cc1468da177	2293	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	161:2cc1468da177	2294	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	161:2cc1468da177	2295	* @retval None
<>	161:2cc1468da177	2296	*/
<>	161:2cc1468da177	2297	__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	161:2cc1468da177	2298	{
<>	161:2cc1468da177	2299	MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
<>	161:2cc1468da177	2300	}
<>	161:2cc1468da177	2301
<>	161:2cc1468da177	2302	/**
<>	161:2cc1468da177	2303	* @brief Get ADC group regular sequencer length and scan direction.
<>	161:2cc1468da177	2304	* @note Description of ADC group regular sequencer features:
<>	161:2cc1468da177	2305	* - For devices with sequencer fully configurable
<>	161:2cc1468da177	2306	* (function "LL_ADC_REG_SetSequencerRanks()" available):
<>	161:2cc1468da177	2307	* sequencer length and each rank affectation to a channel
<>	161:2cc1468da177	2308	* are configurable.
<>	161:2cc1468da177	2309	* This function retrieves:
<>	161:2cc1468da177	2310	* - Sequence length: Number of ranks in the scan sequence.
<>	161:2cc1468da177	2311	* - Sequence direction: Unless specified in parameters, sequencer
<>	161:2cc1468da177	2312	* scan direction is forward (from rank 1 to rank n).
<>	161:2cc1468da177	2313	* Sequencer ranks are selected using
<>	161:2cc1468da177	2314	* function "LL_ADC_REG_SetSequencerRanks()".
<>	161:2cc1468da177	2315	* - For devices with sequencer not fully configurable
<>	161:2cc1468da177	2316	* (function "LL_ADC_REG_SetSequencerChannels()" available):
<>	161:2cc1468da177	2317	* sequencer length and each rank affectation to a channel
<>	161:2cc1468da177	2318	* are defined by channel number.
<>	161:2cc1468da177	2319	* This function retrieves:
<>	161:2cc1468da177	2320	* - Sequence length: Number of ranks in the scan sequence is
<>	161:2cc1468da177	2321	* defined by number of channels set in the sequence,
<>	161:2cc1468da177	2322	* rank of each channel is fixed by channel HW number.
<>	161:2cc1468da177	2323	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	161:2cc1468da177	2324	* - Sequence direction: Unless specified in parameters, sequencer
<>	161:2cc1468da177	2325	* scan direction is forward (from lowest channel number to
<>	161:2cc1468da177	2326	* highest channel number).
<>	161:2cc1468da177	2327	* Sequencer ranks are selected using
<>	161:2cc1468da177	2328	* function "LL_ADC_REG_SetSequencerChannels()".
<>	161:2cc1468da177	2329	* @note On this STM32 serie, group regular sequencer configuration
<>	161:2cc1468da177	2330	* is conditioned to ADC instance sequencer mode.
<>	161:2cc1468da177	2331	* If ADC instance sequencer mode is disabled, sequencers of
<>	161:2cc1468da177	2332	* all groups (group regular, group injected) can be configured
<>	161:2cc1468da177	2333	* but their execution is disabled (limited to rank 1).
<>	161:2cc1468da177	2334	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	161:2cc1468da177	2335	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	161:2cc1468da177	2336	* ADC conversion on only 1 channel.
<>	161:2cc1468da177	2337	* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
<>	161:2cc1468da177	2338	* @param ADCx ADC instance
<>	161:2cc1468da177	2339	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2340	* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
<>	161:2cc1468da177	2341	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
<>	161:2cc1468da177	2342	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
<>	161:2cc1468da177	2343	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
<>	161:2cc1468da177	2344	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
<>	161:2cc1468da177	2345	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
<>	161:2cc1468da177	2346	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
<>	161:2cc1468da177	2347	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
<>	161:2cc1468da177	2348	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
<>	161:2cc1468da177	2349	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
<>	161:2cc1468da177	2350	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
<>	161:2cc1468da177	2351	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
<>	161:2cc1468da177	2352	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
<>	161:2cc1468da177	2353	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
<>	161:2cc1468da177	2354	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
<>	161:2cc1468da177	2355	* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
<>	161:2cc1468da177	2356	*/
<>	161:2cc1468da177	2357	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2358	{
<>	161:2cc1468da177	2359	return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
<>	161:2cc1468da177	2360	}
<>	161:2cc1468da177	2361
<>	161:2cc1468da177	2362	/**
<>	161:2cc1468da177	2363	* @brief Set ADC group regular sequencer discontinuous mode:
<>	161:2cc1468da177	2364	* sequence subdivided and scan conversions interrupted every selected
<>	161:2cc1468da177	2365	* number of ranks.
<>	161:2cc1468da177	2366	* @note It is not possible to enable both ADC group regular
<>	161:2cc1468da177	2367	* continuous mode and sequencer discontinuous mode.
<>	161:2cc1468da177	2368	* @note It is not possible to enable both ADC auto-injected mode
<>	161:2cc1468da177	2369	* and ADC group regular sequencer discontinuous mode.
<>	161:2cc1468da177	2370	* @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
<>	161:2cc1468da177	2371	* CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
<>	161:2cc1468da177	2372	* @param ADCx ADC instance
<>	161:2cc1468da177	2373	* @param SeqDiscont This parameter can be one of the following values:
<>	161:2cc1468da177	2374	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	161:2cc1468da177	2375	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	161:2cc1468da177	2376	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	161:2cc1468da177	2377	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	161:2cc1468da177	2378	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	161:2cc1468da177	2379	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	161:2cc1468da177	2380	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	161:2cc1468da177	2381	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	161:2cc1468da177	2382	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	161:2cc1468da177	2383	* @retval None
<>	161:2cc1468da177	2384	*/
<>	161:2cc1468da177	2385	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	161:2cc1468da177	2386	{
<>	161:2cc1468da177	2387	MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM, SeqDiscont);
<>	161:2cc1468da177	2388	}
<>	161:2cc1468da177	2389
<>	161:2cc1468da177	2390	/**
<>	161:2cc1468da177	2391	* @brief Get ADC group regular sequencer discontinuous mode:
<>	161:2cc1468da177	2392	* sequence subdivided and scan conversions interrupted every selected
<>	161:2cc1468da177	2393	* number of ranks.
<>	161:2cc1468da177	2394	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
<>	161:2cc1468da177	2395	* CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
<>	161:2cc1468da177	2396	* @param ADCx ADC instance
<>	161:2cc1468da177	2397	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2398	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	161:2cc1468da177	2399	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	161:2cc1468da177	2400	* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
<>	161:2cc1468da177	2401	* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
<>	161:2cc1468da177	2402	* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
<>	161:2cc1468da177	2403	* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
<>	161:2cc1468da177	2404	* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
<>	161:2cc1468da177	2405	* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
<>	161:2cc1468da177	2406	* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
<>	161:2cc1468da177	2407	*/
<>	161:2cc1468da177	2408	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2409	{
<>	161:2cc1468da177	2410	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN \| ADC_CR1_DISCNUM));
<>	161:2cc1468da177	2411	}
<>	161:2cc1468da177	2412
<>	161:2cc1468da177	2413	/**
<>	161:2cc1468da177	2414	* @brief Set ADC group regular sequence: channel on the selected
<>	161:2cc1468da177	2415	* scan sequence rank.
<>	161:2cc1468da177	2416	* @note This function performs configuration of:
<>	161:2cc1468da177	2417	* - Channels ordering into each rank of scan sequence:
<>	161:2cc1468da177	2418	* whatever channel can be placed into whatever rank.
<>	161:2cc1468da177	2419	* @note On this STM32 serie, ADC group regular sequencer is
<>	161:2cc1468da177	2420	* fully configurable: sequencer length and each rank
<>	161:2cc1468da177	2421	* affectation to a channel are configurable.
<>	161:2cc1468da177	2422	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	161:2cc1468da177	2423	* @note Depending on devices and packages, some channels may not be available.
<>	161:2cc1468da177	2424	* Refer to device datasheet for channels availability.
<>	161:2cc1468da177	2425	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	161:2cc1468da177	2426	* TempSensor, ...), measurement paths to internal channels must be
<>	161:2cc1468da177	2427	* enabled separately.
<>	161:2cc1468da177	2428	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	161:2cc1468da177	2429	* @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2430	* SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2431	* SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2432	* SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2433	* SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2434	* SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2435	* SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2436	* SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2437	* SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2438	* SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2439	* SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2440	* SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2441	* SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2442	* SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2443	* SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
<>	161:2cc1468da177	2444	* SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
<>	161:2cc1468da177	2445	* @param ADCx ADC instance
<>	161:2cc1468da177	2446	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	2447	* @arg @ref LL_ADC_REG_RANK_1
<>	161:2cc1468da177	2448	* @arg @ref LL_ADC_REG_RANK_2
<>	161:2cc1468da177	2449	* @arg @ref LL_ADC_REG_RANK_3
<>	161:2cc1468da177	2450	* @arg @ref LL_ADC_REG_RANK_4
<>	161:2cc1468da177	2451	* @arg @ref LL_ADC_REG_RANK_5
<>	161:2cc1468da177	2452	* @arg @ref LL_ADC_REG_RANK_6
<>	161:2cc1468da177	2453	* @arg @ref LL_ADC_REG_RANK_7
<>	161:2cc1468da177	2454	* @arg @ref LL_ADC_REG_RANK_8
<>	161:2cc1468da177	2455	* @arg @ref LL_ADC_REG_RANK_9
<>	161:2cc1468da177	2456	* @arg @ref LL_ADC_REG_RANK_10
<>	161:2cc1468da177	2457	* @arg @ref LL_ADC_REG_RANK_11
<>	161:2cc1468da177	2458	* @arg @ref LL_ADC_REG_RANK_12
<>	161:2cc1468da177	2459	* @arg @ref LL_ADC_REG_RANK_13
<>	161:2cc1468da177	2460	* @arg @ref LL_ADC_REG_RANK_14
<>	161:2cc1468da177	2461	* @arg @ref LL_ADC_REG_RANK_15
<>	161:2cc1468da177	2462	* @arg @ref LL_ADC_REG_RANK_16
<>	161:2cc1468da177	2463	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2464	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	2465	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	2466	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	2467	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	2468	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	2469	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	2470	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	2471	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	2472	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	2473	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	2474	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	2475	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	2476	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	2477	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	2478	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	2479	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	2480	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	2481	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	2482	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	2483	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	2484	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	2485	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	2486	*
<>	161:2cc1468da177	2487	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	2488	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	2489	* @retval None
<>	161:2cc1468da177	2490	*/
<>	161:2cc1468da177	2491	__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	161:2cc1468da177	2492	{
<>	161:2cc1468da177	2493	/* Set bits with content of parameter "Channel" with bits position */
<>	161:2cc1468da177	2494	/* in register and register position depending on parameter "Rank". */
<>	161:2cc1468da177	2495	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	161:2cc1468da177	2496	/* other bits reserved for other purpose. */
<>	161:2cc1468da177	2497	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	161:2cc1468da177	2498
<>	161:2cc1468da177	2499	MODIFY_REG(*preg,
<>	161:2cc1468da177	2500	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
<>	161:2cc1468da177	2501	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
<>	161:2cc1468da177	2502	}
<>	161:2cc1468da177	2503
<>	161:2cc1468da177	2504	/**
<>	161:2cc1468da177	2505	* @brief Get ADC group regular sequence: channel on the selected
<>	161:2cc1468da177	2506	* scan sequence rank.
<>	161:2cc1468da177	2507	* @note On this STM32 serie, ADC group regular sequencer is
<>	161:2cc1468da177	2508	* fully configurable: sequencer length and each rank
<>	161:2cc1468da177	2509	* affectation to a channel are configurable.
<>	161:2cc1468da177	2510	* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
<>	161:2cc1468da177	2511	* @note Depending on devices and packages, some channels may not be available.
<>	161:2cc1468da177	2512	* Refer to device datasheet for channels availability.
<>	161:2cc1468da177	2513	* @note Usage of the returned channel number:
<>	161:2cc1468da177	2514	* - To reinject this channel into another function LL_ADC_xxx:
<>	161:2cc1468da177	2515	* the returned channel number is only partly formatted on definition
<>	161:2cc1468da177	2516	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	161:2cc1468da177	2517	* with parts of literals LL_ADC_CHANNEL_x or using
<>	161:2cc1468da177	2518	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	161:2cc1468da177	2519	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	161:2cc1468da177	2520	* as parameter for another function.
<>	161:2cc1468da177	2521	* - To get the channel number in decimal format:
<>	161:2cc1468da177	2522	* process the returned value with the helper macro
<>	161:2cc1468da177	2523	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	161:2cc1468da177	2524	* @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2525	* SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2526	* SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2527	* SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2528	* SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2529	* SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2530	* SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2531	* SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2532	* SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2533	* SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2534	* SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2535	* SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2536	* SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2537	* SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2538	* SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
<>	161:2cc1468da177	2539	* SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
<>	161:2cc1468da177	2540	* @param ADCx ADC instance
<>	161:2cc1468da177	2541	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	2542	* @arg @ref LL_ADC_REG_RANK_1
<>	161:2cc1468da177	2543	* @arg @ref LL_ADC_REG_RANK_2
<>	161:2cc1468da177	2544	* @arg @ref LL_ADC_REG_RANK_3
<>	161:2cc1468da177	2545	* @arg @ref LL_ADC_REG_RANK_4
<>	161:2cc1468da177	2546	* @arg @ref LL_ADC_REG_RANK_5
<>	161:2cc1468da177	2547	* @arg @ref LL_ADC_REG_RANK_6
<>	161:2cc1468da177	2548	* @arg @ref LL_ADC_REG_RANK_7
<>	161:2cc1468da177	2549	* @arg @ref LL_ADC_REG_RANK_8
<>	161:2cc1468da177	2550	* @arg @ref LL_ADC_REG_RANK_9
<>	161:2cc1468da177	2551	* @arg @ref LL_ADC_REG_RANK_10
<>	161:2cc1468da177	2552	* @arg @ref LL_ADC_REG_RANK_11
<>	161:2cc1468da177	2553	* @arg @ref LL_ADC_REG_RANK_12
<>	161:2cc1468da177	2554	* @arg @ref LL_ADC_REG_RANK_13
<>	161:2cc1468da177	2555	* @arg @ref LL_ADC_REG_RANK_14
<>	161:2cc1468da177	2556	* @arg @ref LL_ADC_REG_RANK_15
<>	161:2cc1468da177	2557	* @arg @ref LL_ADC_REG_RANK_16
<>	161:2cc1468da177	2558	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2559	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	2560	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	2561	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	2562	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	2563	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	2564	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	2565	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	2566	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	2567	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	2568	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	2569	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	2570	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	2571	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	2572	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	2573	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	2574	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	2575	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	2576	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	2577	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	2578	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	2579	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	2580	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	2581	*
<>	161:2cc1468da177	2582	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	2583	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	161:2cc1468da177	2584	* (1) For ADC channel read back from ADC register,
<>	161:2cc1468da177	2585	* comparison with internal channel parameter to be done
<>	161:2cc1468da177	2586	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	161:2cc1468da177	2587	*/
<>	161:2cc1468da177	2588	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	2589	{
<>	161:2cc1468da177	2590	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
<>	161:2cc1468da177	2591
<>	161:2cc1468da177	2592	return (uint32_t) (READ_BIT(*preg,
<>	161:2cc1468da177	2593	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
<>	161:2cc1468da177	2594	>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
<>	161:2cc1468da177	2595	);
<>	161:2cc1468da177	2596	}
<>	161:2cc1468da177	2597
<>	161:2cc1468da177	2598	/**
<>	161:2cc1468da177	2599	* @brief Set ADC continuous conversion mode on ADC group regular.
<>	161:2cc1468da177	2600	* @note Description of ADC continuous conversion mode:
<>	161:2cc1468da177	2601	* - single mode: one conversion per trigger
<>	161:2cc1468da177	2602	* - continuous mode: after the first trigger, following
<>	161:2cc1468da177	2603	* conversions launched successively automatically.
<>	161:2cc1468da177	2604	* @note It is not possible to enable both ADC group regular
<>	161:2cc1468da177	2605	* continuous mode and sequencer discontinuous mode.
<>	161:2cc1468da177	2606	* @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
<>	161:2cc1468da177	2607	* @param ADCx ADC instance
<>	161:2cc1468da177	2608	* @param Continuous This parameter can be one of the following values:
<>	161:2cc1468da177	2609	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	161:2cc1468da177	2610	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	161:2cc1468da177	2611	* @retval None
<>	161:2cc1468da177	2612	*/
<>	161:2cc1468da177	2613	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
<>	161:2cc1468da177	2614	{
<>	161:2cc1468da177	2615	MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
<>	161:2cc1468da177	2616	}
<>	161:2cc1468da177	2617
<>	161:2cc1468da177	2618	/**
<>	161:2cc1468da177	2619	* @brief Get ADC continuous conversion mode on ADC group regular.
<>	161:2cc1468da177	2620	* @note Description of ADC continuous conversion mode:
<>	161:2cc1468da177	2621	* - single mode: one conversion per trigger
<>	161:2cc1468da177	2622	* - continuous mode: after the first trigger, following
<>	161:2cc1468da177	2623	* conversions launched successively automatically.
<>	161:2cc1468da177	2624	* @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
<>	161:2cc1468da177	2625	* @param ADCx ADC instance
<>	161:2cc1468da177	2626	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2627	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	161:2cc1468da177	2628	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	161:2cc1468da177	2629	*/
<>	161:2cc1468da177	2630	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2631	{
<>	161:2cc1468da177	2632	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
<>	161:2cc1468da177	2633	}
<>	161:2cc1468da177	2634
<>	161:2cc1468da177	2635	/**
<>	161:2cc1468da177	2636	* @brief Set ADC group regular conversion data transfer: no transfer or
<>	161:2cc1468da177	2637	* transfer by DMA, and DMA requests mode.
<>	161:2cc1468da177	2638	* @note If transfer by DMA selected, specifies the DMA requests
<>	161:2cc1468da177	2639	* mode:
<>	161:2cc1468da177	2640	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	161:2cc1468da177	2641	* when number of DMA data transfers (number of
<>	161:2cc1468da177	2642	* ADC conversions) is reached.
<>	161:2cc1468da177	2643	* This ADC mode is intended to be used with DMA mode non-circular.
<>	161:2cc1468da177	2644	* - Unlimited mode: DMA transfer requests are unlimited,
<>	161:2cc1468da177	2645	* whatever number of DMA data transfers (number of
<>	161:2cc1468da177	2646	* ADC conversions).
<>	161:2cc1468da177	2647	* This ADC mode is intended to be used with DMA mode circular.
<>	161:2cc1468da177	2648	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	161:2cc1468da177	2649	* mode non-circular:
<>	161:2cc1468da177	2650	* when DMA transfers size will be reached, DMA will stop transfers of
<>	161:2cc1468da177	2651	* ADC conversions data ADC will raise an overrun error
<>	161:2cc1468da177	2652	* (overrun flag and interruption if enabled).
<>	161:2cc1468da177	2653	* @note For devices with several ADC instances: ADC multimode DMA
<>	161:2cc1468da177	2654	* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
<>	161:2cc1468da177	2655	* @note To configure DMA source address (peripheral address),
<>	161:2cc1468da177	2656	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	161:2cc1468da177	2657	* @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n
<>	161:2cc1468da177	2658	* CR2 DDS LL_ADC_REG_SetDMATransfer
<>	161:2cc1468da177	2659	* @param ADCx ADC instance
<>	161:2cc1468da177	2660	* @param DMATransfer This parameter can be one of the following values:
<>	161:2cc1468da177	2661	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	161:2cc1468da177	2662	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	161:2cc1468da177	2663	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	161:2cc1468da177	2664	* @retval None
<>	161:2cc1468da177	2665	*/
<>	161:2cc1468da177	2666	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
<>	161:2cc1468da177	2667	{
<>	161:2cc1468da177	2668	MODIFY_REG(ADCx->CR2, ADC_CR2_DMA \| ADC_CR2_DDS, DMATransfer);
<>	161:2cc1468da177	2669	}
<>	161:2cc1468da177	2670
<>	161:2cc1468da177	2671	/**
<>	161:2cc1468da177	2672	* @brief Get ADC group regular conversion data transfer: no transfer or
<>	161:2cc1468da177	2673	* transfer by DMA, and DMA requests mode.
<>	161:2cc1468da177	2674	* @note If transfer by DMA selected, specifies the DMA requests
<>	161:2cc1468da177	2675	* mode:
<>	161:2cc1468da177	2676	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	161:2cc1468da177	2677	* when number of DMA data transfers (number of
<>	161:2cc1468da177	2678	* ADC conversions) is reached.
<>	161:2cc1468da177	2679	* This ADC mode is intended to be used with DMA mode non-circular.
<>	161:2cc1468da177	2680	* - Unlimited mode: DMA transfer requests are unlimited,
<>	161:2cc1468da177	2681	* whatever number of DMA data transfers (number of
<>	161:2cc1468da177	2682	* ADC conversions).
<>	161:2cc1468da177	2683	* This ADC mode is intended to be used with DMA mode circular.
<>	161:2cc1468da177	2684	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	161:2cc1468da177	2685	* mode non-circular:
<>	161:2cc1468da177	2686	* when DMA transfers size will be reached, DMA will stop transfers of
<>	161:2cc1468da177	2687	* ADC conversions data ADC will raise an overrun error
<>	161:2cc1468da177	2688	* (overrun flag and interruption if enabled).
<>	161:2cc1468da177	2689	* @note For devices with several ADC instances: ADC multimode DMA
<>	161:2cc1468da177	2690	* settings are available using function @ref LL_ADC_GetMultiDMATransfer().
<>	161:2cc1468da177	2691	* @note To configure DMA source address (peripheral address),
<>	161:2cc1468da177	2692	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	161:2cc1468da177	2693	* @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n
<>	161:2cc1468da177	2694	* CR2 DDS LL_ADC_REG_GetDMATransfer
<>	161:2cc1468da177	2695	* @param ADCx ADC instance
<>	161:2cc1468da177	2696	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2697	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	161:2cc1468da177	2698	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	161:2cc1468da177	2699	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	161:2cc1468da177	2700	*/
<>	161:2cc1468da177	2701	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2702	{
<>	161:2cc1468da177	2703	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA \| ADC_CR2_DDS));
<>	161:2cc1468da177	2704	}
<>	161:2cc1468da177	2705
<>	161:2cc1468da177	2706	/**
<>	161:2cc1468da177	2707	* @brief Specify which ADC flag between EOC (end of unitary conversion)
<>	161:2cc1468da177	2708	* or EOS (end of sequence conversions) is used to indicate
<>	161:2cc1468da177	2709	* the end of conversion.
<>	161:2cc1468da177	2710	* @note This feature is aimed to be set when using ADC with
<>	161:2cc1468da177	2711	* programming model by polling or interruption
<>	161:2cc1468da177	2712	* (programming model by DMA usually uses DMA interruptions
<>	161:2cc1468da177	2713	* to indicate end of conversion and data transfer).
<>	161:2cc1468da177	2714	* @note For ADC group injected, end of conversion (flag&IT) is raised
<>	161:2cc1468da177	2715	* only at the end of the sequence.
<>	161:2cc1468da177	2716	* @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion
<>	161:2cc1468da177	2717	* @param ADCx ADC instance
<>	161:2cc1468da177	2718	* @param EocSelection This parameter can be one of the following values:
<>	161:2cc1468da177	2719	* @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
<>	161:2cc1468da177	2720	* @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
<>	161:2cc1468da177	2721	* @retval None
<>	161:2cc1468da177	2722	*/
<>	161:2cc1468da177	2723	__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
<>	161:2cc1468da177	2724	{
<>	161:2cc1468da177	2725	MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
<>	161:2cc1468da177	2726	}
<>	161:2cc1468da177	2727
<>	161:2cc1468da177	2728	/**
<>	161:2cc1468da177	2729	* @brief Get which ADC flag between EOC (end of unitary conversion)
<>	161:2cc1468da177	2730	* or EOS (end of sequence conversions) is used to indicate
<>	161:2cc1468da177	2731	* the end of conversion.
<>	161:2cc1468da177	2732	* @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion
<>	161:2cc1468da177	2733	* @param ADCx ADC instance
<>	161:2cc1468da177	2734	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2735	* @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV
<>	161:2cc1468da177	2736	* @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV
<>	161:2cc1468da177	2737	*/
<>	161:2cc1468da177	2738	__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2739	{
<>	161:2cc1468da177	2740	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
<>	161:2cc1468da177	2741	}
<>	161:2cc1468da177	2742
<>	161:2cc1468da177	2743	/**
<>	161:2cc1468da177	2744	* @}
<>	161:2cc1468da177	2745	*/
<>	161:2cc1468da177	2746
<>	161:2cc1468da177	2747	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
<>	161:2cc1468da177	2748	* @{
<>	161:2cc1468da177	2749	*/
<>	161:2cc1468da177	2750
<>	161:2cc1468da177	2751	/**
<>	161:2cc1468da177	2752	* @brief Set ADC group injected conversion trigger source:
<>	161:2cc1468da177	2753	* internal (SW start) or from external IP (timer event,
<>	161:2cc1468da177	2754	* external interrupt line).
<>	161:2cc1468da177	2755	* @note On this STM32 serie, setting of external trigger edge is performed
<>	161:2cc1468da177	2756	* using function @ref LL_ADC_INJ_StartConversionExtTrig().
<>	161:2cc1468da177	2757	* @note Availability of parameters of trigger sources from timer
<>	161:2cc1468da177	2758	* depends on timers availability on the selected device.
<>	161:2cc1468da177	2759	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n
<>	161:2cc1468da177	2760	* CR2 JEXTEN LL_ADC_INJ_SetTriggerSource
<>	161:2cc1468da177	2761	* @param ADCx ADC instance
<>	161:2cc1468da177	2762	* @param TriggerSource This parameter can be one of the following values:
<>	161:2cc1468da177	2763	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	161:2cc1468da177	2764	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
<>	161:2cc1468da177	2765	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
<>	161:2cc1468da177	2766	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	161:2cc1468da177	2767	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	161:2cc1468da177	2768	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	161:2cc1468da177	2769	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	161:2cc1468da177	2770	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
<>	161:2cc1468da177	2771	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
<>	161:2cc1468da177	2772	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
<>	161:2cc1468da177	2773	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
<>	161:2cc1468da177	2774	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
<>	161:2cc1468da177	2775	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
<>	161:2cc1468da177	2776	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
<>	161:2cc1468da177	2777	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
<>	161:2cc1468da177	2778	* @retval None
<>	161:2cc1468da177	2779	*/
<>	161:2cc1468da177	2780	__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	161:2cc1468da177	2781	{
<>	161:2cc1468da177	2782	/* Note: On this STM32 serie, ADC group injected external trigger edge */
<>	161:2cc1468da177	2783	/* is used to perform a ADC conversion start. */
<>	161:2cc1468da177	2784	/* This function does not set external trigger edge. */
<>	161:2cc1468da177	2785	/* This feature is set using function */
<>	161:2cc1468da177	2786	/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
<>	161:2cc1468da177	2787	MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
<>	161:2cc1468da177	2788	}
<>	161:2cc1468da177	2789
<>	161:2cc1468da177	2790	/**
<>	161:2cc1468da177	2791	* @brief Get ADC group injected conversion trigger source:
<>	161:2cc1468da177	2792	* internal (SW start) or from external IP (timer event,
<>	161:2cc1468da177	2793	* external interrupt line).
<>	161:2cc1468da177	2794	* @note To determine whether group injected trigger source is
<>	161:2cc1468da177	2795	* internal (SW start) or external, without detail
<>	161:2cc1468da177	2796	* of which peripheral is selected as external trigger,
<>	161:2cc1468da177	2797	* (equivalent to
<>	161:2cc1468da177	2798	* "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
<>	161:2cc1468da177	2799	* use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
<>	161:2cc1468da177	2800	* @note Availability of parameters of trigger sources from timer
<>	161:2cc1468da177	2801	* depends on timers availability on the selected device.
<>	161:2cc1468da177	2802	* @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n
<>	161:2cc1468da177	2803	* CR2 JEXTEN LL_ADC_INJ_GetTriggerSource
<>	161:2cc1468da177	2804	* @param ADCx ADC instance
<>	161:2cc1468da177	2805	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2806	* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
<>	161:2cc1468da177	2807	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
<>	161:2cc1468da177	2808	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
<>	161:2cc1468da177	2809	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
<>	161:2cc1468da177	2810	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
<>	161:2cc1468da177	2811	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4
<>	161:2cc1468da177	2812	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
<>	161:2cc1468da177	2813	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
<>	161:2cc1468da177	2814	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
<>	161:2cc1468da177	2815	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
<>	161:2cc1468da177	2816	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
<>	161:2cc1468da177	2817	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3
<>	161:2cc1468da177	2818	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO
<>	161:2cc1468da177	2819	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1
<>	161:2cc1468da177	2820	* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
<>	161:2cc1468da177	2821	*/
<>	161:2cc1468da177	2822	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2823	{
<>	161:2cc1468da177	2824	register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL \| ADC_CR2_JEXTEN);
<>	161:2cc1468da177	2825
<>	161:2cc1468da177	2826	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	161:2cc1468da177	2827	/* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
<>	161:2cc1468da177	2828	register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	161:2cc1468da177	2829
<>	161:2cc1468da177	2830	/* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
<>	161:2cc1468da177	2831	/* to match with triggers literals definition. */
<>	161:2cc1468da177	2832	return ((TriggerSource
<>	161:2cc1468da177	2833	& (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
<>	161:2cc1468da177	2834	\| ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
<>	161:2cc1468da177	2835	);
<>	161:2cc1468da177	2836	}
<>	161:2cc1468da177	2837
<>	161:2cc1468da177	2838	/**
<>	161:2cc1468da177	2839	* @brief Get ADC group injected conversion trigger source internal (SW start)
<>	161:2cc1468da177	2840	or external
<>	161:2cc1468da177	2841	* @note In case of group injected trigger source set to external trigger,
<>	161:2cc1468da177	2842	* to determine which peripheral is selected as external trigger,
<>	161:2cc1468da177	2843	* use function @ref LL_ADC_INJ_GetTriggerSource.
<>	161:2cc1468da177	2844	* @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
<>	161:2cc1468da177	2845	* @param ADCx ADC instance
<>	161:2cc1468da177	2846	* @retval Value "0" if trigger source external trigger
<>	161:2cc1468da177	2847	* Value "1" if trigger source SW start.
<>	161:2cc1468da177	2848	*/
<>	161:2cc1468da177	2849	__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2850	{
<>	161:2cc1468da177	2851	return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
<>	161:2cc1468da177	2852	}
<>	161:2cc1468da177	2853
<>	161:2cc1468da177	2854	/**
<>	161:2cc1468da177	2855	* @brief Get ADC group injected conversion trigger polarity.
<>	161:2cc1468da177	2856	* Applicable only for trigger source set to external trigger.
<>	161:2cc1468da177	2857	* @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge
<>	161:2cc1468da177	2858	* @param ADCx ADC instance
<>	161:2cc1468da177	2859	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2860	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	161:2cc1468da177	2861	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	161:2cc1468da177	2862	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	161:2cc1468da177	2863	*/
<>	161:2cc1468da177	2864	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2865	{
<>	161:2cc1468da177	2866	return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
<>	161:2cc1468da177	2867	}
<>	161:2cc1468da177	2868
<>	161:2cc1468da177	2869	/**
<>	161:2cc1468da177	2870	* @brief Set ADC group injected sequencer length and scan direction.
<>	161:2cc1468da177	2871	* @note This function performs configuration of:
<>	161:2cc1468da177	2872	* - Sequence length: Number of ranks in the scan sequence.
<>	161:2cc1468da177	2873	* - Sequence direction: Unless specified in parameters, sequencer
<>	161:2cc1468da177	2874	* scan direction is forward (from rank 1 to rank n).
<>	161:2cc1468da177	2875	* @note On this STM32 serie, group injected sequencer configuration
<>	161:2cc1468da177	2876	* is conditioned to ADC instance sequencer mode.
<>	161:2cc1468da177	2877	* If ADC instance sequencer mode is disabled, sequencers of
<>	161:2cc1468da177	2878	* all groups (group regular, group injected) can be configured
<>	161:2cc1468da177	2879	* but their execution is disabled (limited to rank 1).
<>	161:2cc1468da177	2880	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	161:2cc1468da177	2881	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	161:2cc1468da177	2882	* ADC conversion on only 1 channel.
<>	161:2cc1468da177	2883	* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
<>	161:2cc1468da177	2884	* @param ADCx ADC instance
<>	161:2cc1468da177	2885	* @param SequencerNbRanks This parameter can be one of the following values:
<>	161:2cc1468da177	2886	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	161:2cc1468da177	2887	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	161:2cc1468da177	2888	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	161:2cc1468da177	2889	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	161:2cc1468da177	2890	* @retval None
<>	161:2cc1468da177	2891	*/
<>	161:2cc1468da177	2892	__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
<>	161:2cc1468da177	2893	{
<>	161:2cc1468da177	2894	MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
<>	161:2cc1468da177	2895	}
<>	161:2cc1468da177	2896
<>	161:2cc1468da177	2897	/**
<>	161:2cc1468da177	2898	* @brief Get ADC group injected sequencer length and scan direction.
<>	161:2cc1468da177	2899	* @note This function retrieves:
<>	161:2cc1468da177	2900	* - Sequence length: Number of ranks in the scan sequence.
<>	161:2cc1468da177	2901	* - Sequence direction: Unless specified in parameters, sequencer
<>	161:2cc1468da177	2902	* scan direction is forward (from rank 1 to rank n).
<>	161:2cc1468da177	2903	* @note On this STM32 serie, group injected sequencer configuration
<>	161:2cc1468da177	2904	* is conditioned to ADC instance sequencer mode.
<>	161:2cc1468da177	2905	* If ADC instance sequencer mode is disabled, sequencers of
<>	161:2cc1468da177	2906	* all groups (group regular, group injected) can be configured
<>	161:2cc1468da177	2907	* but their execution is disabled (limited to rank 1).
<>	161:2cc1468da177	2908	* Refer to function @ref LL_ADC_SetSequencersScanMode().
<>	161:2cc1468da177	2909	* @note Sequencer disabled is equivalent to sequencer of 1 rank:
<>	161:2cc1468da177	2910	* ADC conversion on only 1 channel.
<>	161:2cc1468da177	2911	* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
<>	161:2cc1468da177	2912	* @param ADCx ADC instance
<>	161:2cc1468da177	2913	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2914	* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
<>	161:2cc1468da177	2915	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
<>	161:2cc1468da177	2916	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
<>	161:2cc1468da177	2917	* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
<>	161:2cc1468da177	2918	*/
<>	161:2cc1468da177	2919	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2920	{
<>	161:2cc1468da177	2921	return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
<>	161:2cc1468da177	2922	}
<>	161:2cc1468da177	2923
<>	161:2cc1468da177	2924	/**
<>	161:2cc1468da177	2925	* @brief Set ADC group injected sequencer discontinuous mode:
<>	161:2cc1468da177	2926	* sequence subdivided and scan conversions interrupted every selected
<>	161:2cc1468da177	2927	* number of ranks.
<>	161:2cc1468da177	2928	* @note It is not possible to enable both ADC group injected
<>	161:2cc1468da177	2929	* auto-injected mode and sequencer discontinuous mode.
<>	161:2cc1468da177	2930	* @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
<>	161:2cc1468da177	2931	* @param ADCx ADC instance
<>	161:2cc1468da177	2932	* @param SeqDiscont This parameter can be one of the following values:
<>	161:2cc1468da177	2933	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	161:2cc1468da177	2934	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	161:2cc1468da177	2935	* @retval None
<>	161:2cc1468da177	2936	*/
<>	161:2cc1468da177	2937	__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	161:2cc1468da177	2938	{
<>	161:2cc1468da177	2939	MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
<>	161:2cc1468da177	2940	}
<>	161:2cc1468da177	2941
<>	161:2cc1468da177	2942	/**
<>	161:2cc1468da177	2943	* @brief Get ADC group injected sequencer discontinuous mode:
<>	161:2cc1468da177	2944	* sequence subdivided and scan conversions interrupted every selected
<>	161:2cc1468da177	2945	* number of ranks.
<>	161:2cc1468da177	2946	* @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
<>	161:2cc1468da177	2947	* @param ADCx ADC instance
<>	161:2cc1468da177	2948	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2949	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
<>	161:2cc1468da177	2950	* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
<>	161:2cc1468da177	2951	*/
<>	161:2cc1468da177	2952	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	2953	{
<>	161:2cc1468da177	2954	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
<>	161:2cc1468da177	2955	}
<>	161:2cc1468da177	2956
<>	161:2cc1468da177	2957	/**
<>	161:2cc1468da177	2958	* @brief Set ADC group injected sequence: channel on the selected
<>	161:2cc1468da177	2959	* sequence rank.
<>	161:2cc1468da177	2960	* @note Depending on devices and packages, some channels may not be available.
<>	161:2cc1468da177	2961	* Refer to device datasheet for channels availability.
<>	161:2cc1468da177	2962	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	161:2cc1468da177	2963	* TempSensor, ...), measurement paths to internal channels must be
<>	161:2cc1468da177	2964	* enabled separately.
<>	161:2cc1468da177	2965	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	161:2cc1468da177	2966	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
<>	161:2cc1468da177	2967	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
<>	161:2cc1468da177	2968	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
<>	161:2cc1468da177	2969	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
<>	161:2cc1468da177	2970	* @param ADCx ADC instance
<>	161:2cc1468da177	2971	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	2972	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	2973	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	2974	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	2975	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	2976	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	2977	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	2978	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	2979	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	2980	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	2981	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	2982	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	2983	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	2984	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	2985	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	2986	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	2987	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	2988	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	2989	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	2990	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	2991	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	2992	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	2993	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	2994	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	2995	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	2996	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	2997	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	2998	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	2999	*
<>	161:2cc1468da177	3000	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	3001	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	3002	* @retval None
<>	161:2cc1468da177	3003	*/
<>	161:2cc1468da177	3004	__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
<>	161:2cc1468da177	3005	{
<>	161:2cc1468da177	3006	/* Set bits with content of parameter "Channel" with bits position */
<>	161:2cc1468da177	3007	/* in register depending on parameter "Rank". */
<>	161:2cc1468da177	3008	/* Parameters "Rank" and "Channel" are used with masks because containing */
<>	161:2cc1468da177	3009	/* other bits reserved for other purpose. */
<>	161:2cc1468da177	3010	MODIFY_REG(ADCx->JSQR,
<>	161:2cc1468da177	3011	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
<>	161:2cc1468da177	3012	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
<>	161:2cc1468da177	3013	}
<>	161:2cc1468da177	3014
<>	161:2cc1468da177	3015	/**
<>	161:2cc1468da177	3016	* @brief Get ADC group injected sequence: channel on the selected
<>	161:2cc1468da177	3017	* sequence rank.
<>	161:2cc1468da177	3018	* @note Depending on devices and packages, some channels may not be available.
<>	161:2cc1468da177	3019	* Refer to device datasheet for channels availability.
<>	161:2cc1468da177	3020	* @note Usage of the returned channel number:
<>	161:2cc1468da177	3021	* - To reinject this channel into another function LL_ADC_xxx:
<>	161:2cc1468da177	3022	* the returned channel number is only partly formatted on definition
<>	161:2cc1468da177	3023	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	161:2cc1468da177	3024	* with parts of literals LL_ADC_CHANNEL_x or using
<>	161:2cc1468da177	3025	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	161:2cc1468da177	3026	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	161:2cc1468da177	3027	* as parameter for another function.
<>	161:2cc1468da177	3028	* - To get the channel number in decimal format:
<>	161:2cc1468da177	3029	* process the returned value with the helper macro
<>	161:2cc1468da177	3030	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	161:2cc1468da177	3031	* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
<>	161:2cc1468da177	3032	* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
<>	161:2cc1468da177	3033	* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
<>	161:2cc1468da177	3034	* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
<>	161:2cc1468da177	3035	* @param ADCx ADC instance
<>	161:2cc1468da177	3036	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	3037	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	3038	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	3039	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	3040	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	3041	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3042	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	3043	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	3044	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	3045	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	3046	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	3047	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	3048	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	3049	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	3050	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	3051	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	3052	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	3053	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	3054	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	3055	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	3056	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	3057	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	3058	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	3059	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	3060	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	3061	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	3062	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	3063	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	3064	*
<>	161:2cc1468da177	3065	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	3066	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n
<>	161:2cc1468da177	3067	* (1) For ADC channel read back from ADC register,
<>	161:2cc1468da177	3068	* comparison with internal channel parameter to be done
<>	161:2cc1468da177	3069	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	161:2cc1468da177	3070	*/
<>	161:2cc1468da177	3071	__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	3072	{
<>	161:2cc1468da177	3073	return (uint32_t)(READ_BIT(ADCx->JSQR,
<>	161:2cc1468da177	3074	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
<>	161:2cc1468da177	3075	>> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)
<>	161:2cc1468da177	3076	);
<>	161:2cc1468da177	3077	}
<>	161:2cc1468da177	3078
<>	161:2cc1468da177	3079	/**
<>	161:2cc1468da177	3080	* @brief Set ADC group injected conversion trigger:
<>	161:2cc1468da177	3081	* independent or from ADC group regular.
<>	161:2cc1468da177	3082	* @note This mode can be used to extend number of data registers
<>	161:2cc1468da177	3083	* updated after one ADC conversion trigger and with data
<>	161:2cc1468da177	3084	* permanently kept (not erased by successive conversions of scan of
<>	161:2cc1468da177	3085	* ADC sequencer ranks), up to 5 data registers:
<>	161:2cc1468da177	3086	* 1 data register on ADC group regular, 4 data registers
<>	161:2cc1468da177	3087	* on ADC group injected.
<>	161:2cc1468da177	3088	* @note If ADC group injected injected trigger source is set to an
<>	161:2cc1468da177	3089	* external trigger, this feature must be must be set to
<>	161:2cc1468da177	3090	* independent trigger.
<>	161:2cc1468da177	3091	* ADC group injected automatic trigger is compliant only with
<>	161:2cc1468da177	3092	* group injected trigger source set to SW start, without any
<>	161:2cc1468da177	3093	* further action on ADC group injected conversion start or stop:
<>	161:2cc1468da177	3094	* in this case, ADC group injected is controlled only
<>	161:2cc1468da177	3095	* from ADC group regular.
<>	161:2cc1468da177	3096	* @note It is not possible to enable both ADC group injected
<>	161:2cc1468da177	3097	* auto-injected mode and sequencer discontinuous mode.
<>	161:2cc1468da177	3098	* @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
<>	161:2cc1468da177	3099	* @param ADCx ADC instance
<>	161:2cc1468da177	3100	* @param TrigAuto This parameter can be one of the following values:
<>	161:2cc1468da177	3101	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	161:2cc1468da177	3102	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	161:2cc1468da177	3103	* @retval None
<>	161:2cc1468da177	3104	*/
<>	161:2cc1468da177	3105	__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
<>	161:2cc1468da177	3106	{
<>	161:2cc1468da177	3107	MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
<>	161:2cc1468da177	3108	}
<>	161:2cc1468da177	3109
<>	161:2cc1468da177	3110	/**
<>	161:2cc1468da177	3111	* @brief Get ADC group injected conversion trigger:
<>	161:2cc1468da177	3112	* independent or from ADC group regular.
<>	161:2cc1468da177	3113	* @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
<>	161:2cc1468da177	3114	* @param ADCx ADC instance
<>	161:2cc1468da177	3115	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3116	* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
<>	161:2cc1468da177	3117	* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
<>	161:2cc1468da177	3118	*/
<>	161:2cc1468da177	3119	__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3120	{
<>	161:2cc1468da177	3121	return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
<>	161:2cc1468da177	3122	}
<>	161:2cc1468da177	3123
<>	161:2cc1468da177	3124	/**
<>	161:2cc1468da177	3125	* @brief Set ADC group injected offset.
<>	161:2cc1468da177	3126	* @note It sets:
<>	161:2cc1468da177	3127	* - ADC group injected rank to which the offset programmed
<>	161:2cc1468da177	3128	* will be applied
<>	161:2cc1468da177	3129	* - Offset level (offset to be subtracted from the raw
<>	161:2cc1468da177	3130	* converted data).
<>	161:2cc1468da177	3131	* Caution: Offset format is dependent to ADC resolution:
<>	161:2cc1468da177	3132	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	161:2cc1468da177	3133	* are set to 0.
<>	161:2cc1468da177	3134	* @note Offset cannot be enabled or disabled.
<>	161:2cc1468da177	3135	* To emulate offset disabled, set an offset value equal to 0.
<>	161:2cc1468da177	3136	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
<>	161:2cc1468da177	3137	* JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
<>	161:2cc1468da177	3138	* JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
<>	161:2cc1468da177	3139	* JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
<>	161:2cc1468da177	3140	* @param ADCx ADC instance
<>	161:2cc1468da177	3141	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	3142	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	3143	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	3144	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	3145	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	3146	* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	3147	* @retval None
<>	161:2cc1468da177	3148	*/
<>	161:2cc1468da177	3149	__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
<>	161:2cc1468da177	3150	{
<>	161:2cc1468da177	3151	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
<>	161:2cc1468da177	3152
<>	161:2cc1468da177	3153	MODIFY_REG(*preg,
<>	161:2cc1468da177	3154	ADC_JOFR1_JOFFSET1,
<>	161:2cc1468da177	3155	OffsetLevel);
<>	161:2cc1468da177	3156	}
<>	161:2cc1468da177	3157
<>	161:2cc1468da177	3158	/**
<>	161:2cc1468da177	3159	* @brief Get ADC group injected offset.
<>	161:2cc1468da177	3160	* @note It gives offset level (offset to be subtracted from the raw converted data).
<>	161:2cc1468da177	3161	* Caution: Offset format is dependent to ADC resolution:
<>	161:2cc1468da177	3162	* offset has to be left-aligned on bit 11, the LSB (right bits)
<>	161:2cc1468da177	3163	* are set to 0.
<>	161:2cc1468da177	3164	* @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
<>	161:2cc1468da177	3165	* JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
<>	161:2cc1468da177	3166	* JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
<>	161:2cc1468da177	3167	* JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
<>	161:2cc1468da177	3168	* @param ADCx ADC instance
<>	161:2cc1468da177	3169	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	3170	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	3171	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	3172	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	3173	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	3174	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	3175	*/
<>	161:2cc1468da177	3176	__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	3177	{
<>	161:2cc1468da177	3178	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
<>	161:2cc1468da177	3179
<>	161:2cc1468da177	3180	return (uint32_t)(READ_BIT(*preg,
<>	161:2cc1468da177	3181	ADC_JOFR1_JOFFSET1)
<>	161:2cc1468da177	3182	);
<>	161:2cc1468da177	3183	}
<>	161:2cc1468da177	3184
<>	161:2cc1468da177	3185	/**
<>	161:2cc1468da177	3186	* @}
<>	161:2cc1468da177	3187	*/
<>	161:2cc1468da177	3188
<>	161:2cc1468da177	3189	/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
<>	161:2cc1468da177	3190	* @{
<>	161:2cc1468da177	3191	*/
<>	161:2cc1468da177	3192
<>	161:2cc1468da177	3193	/**
<>	161:2cc1468da177	3194	* @brief Set sampling time of the selected ADC channel
<>	161:2cc1468da177	3195	* Unit: ADC clock cycles.
<>	161:2cc1468da177	3196	* @note On this device, sampling time is on channel scope: independently
<>	161:2cc1468da177	3197	* of channel mapped on ADC group regular or injected.
<>	161:2cc1468da177	3198	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
<>	161:2cc1468da177	3199	* converted:
<>	161:2cc1468da177	3200	* sampling time constraints must be respected (sampling time can be
<>	161:2cc1468da177	3201	* adjusted in function of ADC clock frequency and sampling time
<>	161:2cc1468da177	3202	* setting).
<>	161:2cc1468da177	3203	* Refer to device datasheet for timings values (parameters TS_vrefint,
<>	161:2cc1468da177	3204	* TS_temp, ...).
<>	161:2cc1468da177	3205	* @note Conversion time is the addition of sampling time and processing time.
<>	161:2cc1468da177	3206	* Refer to reference manual for ADC processing time of
<>	161:2cc1468da177	3207	* this STM32 serie.
<>	161:2cc1468da177	3208	* @note In case of ADC conversion of internal channel (VrefInt,
<>	161:2cc1468da177	3209	* temperature sensor, ...), a sampling time minimum value
<>	161:2cc1468da177	3210	* is required.
<>	161:2cc1468da177	3211	* Refer to device datasheet.
<>	161:2cc1468da177	3212	* @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3213	* SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3214	* SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3215	* SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3216	* SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3217	* SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3218	* SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3219	* SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3220	* SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3221	* SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3222	* SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3223	* SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3224	* SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3225	* SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3226	* SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3227	* SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3228	* SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3229	* SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
<>	161:2cc1468da177	3230	* SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
<>	161:2cc1468da177	3231	* @param ADCx ADC instance
<>	161:2cc1468da177	3232	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	3233	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	3234	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	3235	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	3236	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	3237	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	3238	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	3239	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	3240	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	3241	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	3242	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	3243	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	3244	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	3245	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	3246	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	3247	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	3248	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	3249	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	3250	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	3251	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	3252	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	3253	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	3254	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	3255	*
<>	161:2cc1468da177	3256	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	3257	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	3258	* @param SamplingTime This parameter can be one of the following values:
<>	161:2cc1468da177	3259	* @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
<>	161:2cc1468da177	3260	* @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
<>	161:2cc1468da177	3261	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
<>	161:2cc1468da177	3262	* @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
<>	161:2cc1468da177	3263	* @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
<>	161:2cc1468da177	3264	* @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
<>	161:2cc1468da177	3265	* @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
<>	161:2cc1468da177	3266	* @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
<>	161:2cc1468da177	3267	* @retval None
<>	161:2cc1468da177	3268	*/
<>	161:2cc1468da177	3269	__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
<>	161:2cc1468da177	3270	{
<>	161:2cc1468da177	3271	/* Set bits with content of parameter "SamplingTime" with bits position */
<>	161:2cc1468da177	3272	/* in register and register position depending on parameter "Channel". */
<>	161:2cc1468da177	3273	/* Parameter "Channel" is used with masks because containing */
<>	161:2cc1468da177	3274	/* other bits reserved for other purpose. */
<>	161:2cc1468da177	3275	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	161:2cc1468da177	3276
<>	161:2cc1468da177	3277	MODIFY_REG(*preg,
<>	161:2cc1468da177	3278	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
<>	161:2cc1468da177	3279	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
<>	161:2cc1468da177	3280	}
<>	161:2cc1468da177	3281
<>	161:2cc1468da177	3282	/**
<>	161:2cc1468da177	3283	* @brief Get sampling time of the selected ADC channel
<>	161:2cc1468da177	3284	* Unit: ADC clock cycles.
<>	161:2cc1468da177	3285	* @note On this device, sampling time is on channel scope: independently
<>	161:2cc1468da177	3286	* of channel mapped on ADC group regular or injected.
<>	161:2cc1468da177	3287	* @note Conversion time is the addition of sampling time and processing time.
<>	161:2cc1468da177	3288	* Refer to reference manual for ADC processing time of
<>	161:2cc1468da177	3289	* this STM32 serie.
<>	161:2cc1468da177	3290	* @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3291	* SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3292	* SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3293	* SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3294	* SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3295	* SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3296	* SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3297	* SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3298	* SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3299	* SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3300	* SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3301	* SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3302	* SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3303	* SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3304	* SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3305	* SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3306	* SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3307	* SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
<>	161:2cc1468da177	3308	* SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
<>	161:2cc1468da177	3309	* @param ADCx ADC instance
<>	161:2cc1468da177	3310	* @param Channel This parameter can be one of the following values:
<>	161:2cc1468da177	3311	* @arg @ref LL_ADC_CHANNEL_0
<>	161:2cc1468da177	3312	* @arg @ref LL_ADC_CHANNEL_1
<>	161:2cc1468da177	3313	* @arg @ref LL_ADC_CHANNEL_2
<>	161:2cc1468da177	3314	* @arg @ref LL_ADC_CHANNEL_3
<>	161:2cc1468da177	3315	* @arg @ref LL_ADC_CHANNEL_4
<>	161:2cc1468da177	3316	* @arg @ref LL_ADC_CHANNEL_5
<>	161:2cc1468da177	3317	* @arg @ref LL_ADC_CHANNEL_6
<>	161:2cc1468da177	3318	* @arg @ref LL_ADC_CHANNEL_7
<>	161:2cc1468da177	3319	* @arg @ref LL_ADC_CHANNEL_8
<>	161:2cc1468da177	3320	* @arg @ref LL_ADC_CHANNEL_9
<>	161:2cc1468da177	3321	* @arg @ref LL_ADC_CHANNEL_10
<>	161:2cc1468da177	3322	* @arg @ref LL_ADC_CHANNEL_11
<>	161:2cc1468da177	3323	* @arg @ref LL_ADC_CHANNEL_12
<>	161:2cc1468da177	3324	* @arg @ref LL_ADC_CHANNEL_13
<>	161:2cc1468da177	3325	* @arg @ref LL_ADC_CHANNEL_14
<>	161:2cc1468da177	3326	* @arg @ref LL_ADC_CHANNEL_15
<>	161:2cc1468da177	3327	* @arg @ref LL_ADC_CHANNEL_16
<>	161:2cc1468da177	3328	* @arg @ref LL_ADC_CHANNEL_17
<>	161:2cc1468da177	3329	* @arg @ref LL_ADC_CHANNEL_18
<>	161:2cc1468da177	3330	* @arg @ref LL_ADC_CHANNEL_VREFINT (1)
<>	161:2cc1468da177	3331	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2)
<>	161:2cc1468da177	3332	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	161:2cc1468da177	3333	*
<>	161:2cc1468da177	3334	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	3335	* (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	3336	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3337	* @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES
<>	161:2cc1468da177	3338	* @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES
<>	161:2cc1468da177	3339	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES
<>	161:2cc1468da177	3340	* @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES
<>	161:2cc1468da177	3341	* @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES
<>	161:2cc1468da177	3342	* @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES
<>	161:2cc1468da177	3343	* @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES
<>	161:2cc1468da177	3344	* @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES
<>	161:2cc1468da177	3345	*/
<>	161:2cc1468da177	3346	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
<>	161:2cc1468da177	3347	{
<>	161:2cc1468da177	3348	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
<>	161:2cc1468da177	3349
<>	161:2cc1468da177	3350	return (uint32_t)(READ_BIT(*preg,
<>	161:2cc1468da177	3351	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
<>	161:2cc1468da177	3352	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
<>	161:2cc1468da177	3353	);
<>	161:2cc1468da177	3354	}
<>	161:2cc1468da177	3355
<>	161:2cc1468da177	3356	/**
<>	161:2cc1468da177	3357	* @}
<>	161:2cc1468da177	3358	*/
<>	161:2cc1468da177	3359
<>	161:2cc1468da177	3360	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
<>	161:2cc1468da177	3361	* @{
<>	161:2cc1468da177	3362	*/
<>	161:2cc1468da177	3363
<>	161:2cc1468da177	3364	/**
<>	161:2cc1468da177	3365	* @brief Set ADC analog watchdog monitored channels:
<>	161:2cc1468da177	3366	* a single channel or all channels,
<>	161:2cc1468da177	3367	* on ADC groups regular and-or injected.
<>	161:2cc1468da177	3368	* @note Once monitored channels are selected, analog watchdog
<>	161:2cc1468da177	3369	* is enabled.
<>	161:2cc1468da177	3370	* @note In case of need to define a single channel to monitor
<>	161:2cc1468da177	3371	* with analog watchdog from sequencer channel definition,
<>	161:2cc1468da177	3372	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
<>	161:2cc1468da177	3373	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	161:2cc1468da177	3374	* instance:
<>	161:2cc1468da177	3375	* - AWD standard (instance AWD1):
<>	161:2cc1468da177	3376	* - channels monitored: can monitor 1 channel or all channels.
<>	161:2cc1468da177	3377	* - groups monitored: ADC groups regular and-or injected.
<>	161:2cc1468da177	3378	* - resolution: resolution is not limited (corresponds to
<>	161:2cc1468da177	3379	* ADC resolution configured).
<>	161:2cc1468da177	3380	* @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
<>	161:2cc1468da177	3381	* CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
<>	161:2cc1468da177	3382	* CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
<>	161:2cc1468da177	3383	* @param ADCx ADC instance
<>	161:2cc1468da177	3384	* @param AWDChannelGroup This parameter can be one of the following values:
<>	161:2cc1468da177	3385	* @arg @ref LL_ADC_AWD_DISABLE
<>	161:2cc1468da177	3386	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	161:2cc1468da177	3387	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	161:2cc1468da177	3388	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	161:2cc1468da177	3389	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	161:2cc1468da177	3390	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
<>	161:2cc1468da177	3391	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	161:2cc1468da177	3392	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	161:2cc1468da177	3393	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
<>	161:2cc1468da177	3394	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	161:2cc1468da177	3395	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	161:2cc1468da177	3396	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
<>	161:2cc1468da177	3397	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	161:2cc1468da177	3398	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	161:2cc1468da177	3399	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
<>	161:2cc1468da177	3400	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	161:2cc1468da177	3401	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	161:2cc1468da177	3402	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
<>	161:2cc1468da177	3403	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	161:2cc1468da177	3404	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	161:2cc1468da177	3405	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
<>	161:2cc1468da177	3406	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	161:2cc1468da177	3407	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	161:2cc1468da177	3408	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
<>	161:2cc1468da177	3409	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	161:2cc1468da177	3410	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	161:2cc1468da177	3411	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
<>	161:2cc1468da177	3412	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	161:2cc1468da177	3413	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	161:2cc1468da177	3414	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
<>	161:2cc1468da177	3415	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	161:2cc1468da177	3416	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	161:2cc1468da177	3417	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
<>	161:2cc1468da177	3418	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	161:2cc1468da177	3419	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	161:2cc1468da177	3420	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
<>	161:2cc1468da177	3421	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	161:2cc1468da177	3422	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	161:2cc1468da177	3423	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
<>	161:2cc1468da177	3424	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	161:2cc1468da177	3425	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	161:2cc1468da177	3426	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
<>	161:2cc1468da177	3427	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	161:2cc1468da177	3428	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	161:2cc1468da177	3429	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
<>	161:2cc1468da177	3430	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	161:2cc1468da177	3431	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	161:2cc1468da177	3432	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
<>	161:2cc1468da177	3433	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	161:2cc1468da177	3434	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	161:2cc1468da177	3435	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
<>	161:2cc1468da177	3436	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	161:2cc1468da177	3437	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	161:2cc1468da177	3438	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
<>	161:2cc1468da177	3439	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	161:2cc1468da177	3440	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	161:2cc1468da177	3441	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
<>	161:2cc1468da177	3442	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	161:2cc1468da177	3443	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<>	161:2cc1468da177	3444	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
<>	161:2cc1468da177	3445	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	161:2cc1468da177	3446	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
<>	161:2cc1468da177	3447	* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
<>	161:2cc1468da177	3448	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
<>	161:2cc1468da177	3449	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2)
<>	161:2cc1468da177	3450	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2)
<>	161:2cc1468da177	3451	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2)
<>	161:2cc1468da177	3452	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<>	161:2cc1468da177	3453	* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1)
<>	161:2cc1468da177	3454	* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1)
<>	161:2cc1468da177	3455	*
<>	161:2cc1468da177	3456	* (1) On STM32F7, parameter available only on ADC instance: ADC1.\n
<>	161:2cc1468da177	3457	* (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.
<>	161:2cc1468da177	3458	* @retval None
<>	161:2cc1468da177	3459	*/
<>	161:2cc1468da177	3460	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
<>	161:2cc1468da177	3461	{
<>	161:2cc1468da177	3462	MODIFY_REG(ADCx->CR1,
<>	161:2cc1468da177	3463	(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH),
<>	161:2cc1468da177	3464	AWDChannelGroup);
<>	161:2cc1468da177	3465	}
<>	161:2cc1468da177	3466
<>	161:2cc1468da177	3467	/**
<>	161:2cc1468da177	3468	* @brief Get ADC analog watchdog monitored channel.
<>	161:2cc1468da177	3469	* @note Usage of the returned channel number:
<>	161:2cc1468da177	3470	* - To reinject this channel into another function LL_ADC_xxx:
<>	161:2cc1468da177	3471	* the returned channel number is only partly formatted on definition
<>	161:2cc1468da177	3472	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	161:2cc1468da177	3473	* with parts of literals LL_ADC_CHANNEL_x or using
<>	161:2cc1468da177	3474	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	161:2cc1468da177	3475	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	161:2cc1468da177	3476	* as parameter for another function.
<>	161:2cc1468da177	3477	* - To get the channel number in decimal format:
<>	161:2cc1468da177	3478	* process the returned value with the helper macro
<>	161:2cc1468da177	3479	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	161:2cc1468da177	3480	* Applicable only when the analog watchdog is set to monitor
<>	161:2cc1468da177	3481	* one channel.
<>	161:2cc1468da177	3482	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	161:2cc1468da177	3483	* instance:
<>	161:2cc1468da177	3484	* - AWD standard (instance AWD1):
<>	161:2cc1468da177	3485	* - channels monitored: can monitor 1 channel or all channels.
<>	161:2cc1468da177	3486	* - groups monitored: ADC groups regular and-or injected.
<>	161:2cc1468da177	3487	* - resolution: resolution is not limited (corresponds to
<>	161:2cc1468da177	3488	* ADC resolution configured).
<>	161:2cc1468da177	3489	* @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
<>	161:2cc1468da177	3490	* CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
<>	161:2cc1468da177	3491	* CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
<>	161:2cc1468da177	3492	* @param ADCx ADC instance
<>	161:2cc1468da177	3493	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3494	* @arg @ref LL_ADC_AWD_DISABLE
<>	161:2cc1468da177	3495	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	161:2cc1468da177	3496	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
<>	161:2cc1468da177	3497	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
<>	161:2cc1468da177	3498	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	161:2cc1468da177	3499	* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
<>	161:2cc1468da177	3500	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
<>	161:2cc1468da177	3501	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	161:2cc1468da177	3502	* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
<>	161:2cc1468da177	3503	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
<>	161:2cc1468da177	3504	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	161:2cc1468da177	3505	* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
<>	161:2cc1468da177	3506	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
<>	161:2cc1468da177	3507	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	161:2cc1468da177	3508	* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
<>	161:2cc1468da177	3509	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
<>	161:2cc1468da177	3510	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	161:2cc1468da177	3511	* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
<>	161:2cc1468da177	3512	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
<>	161:2cc1468da177	3513	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	161:2cc1468da177	3514	* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
<>	161:2cc1468da177	3515	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
<>	161:2cc1468da177	3516	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	161:2cc1468da177	3517	* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
<>	161:2cc1468da177	3518	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
<>	161:2cc1468da177	3519	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	161:2cc1468da177	3520	* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
<>	161:2cc1468da177	3521	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
<>	161:2cc1468da177	3522	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	161:2cc1468da177	3523	* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
<>	161:2cc1468da177	3524	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
<>	161:2cc1468da177	3525	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	161:2cc1468da177	3526	* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
<>	161:2cc1468da177	3527	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
<>	161:2cc1468da177	3528	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	161:2cc1468da177	3529	* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
<>	161:2cc1468da177	3530	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
<>	161:2cc1468da177	3531	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	161:2cc1468da177	3532	* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
<>	161:2cc1468da177	3533	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
<>	161:2cc1468da177	3534	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	161:2cc1468da177	3535	* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
<>	161:2cc1468da177	3536	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
<>	161:2cc1468da177	3537	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	161:2cc1468da177	3538	* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
<>	161:2cc1468da177	3539	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
<>	161:2cc1468da177	3540	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	161:2cc1468da177	3541	* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
<>	161:2cc1468da177	3542	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
<>	161:2cc1468da177	3543	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	161:2cc1468da177	3544	* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
<>	161:2cc1468da177	3545	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
<>	161:2cc1468da177	3546	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	161:2cc1468da177	3547	* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
<>	161:2cc1468da177	3548	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
<>	161:2cc1468da177	3549	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	161:2cc1468da177	3550	* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
<>	161:2cc1468da177	3551	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
<>	161:2cc1468da177	3552	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<>	161:2cc1468da177	3553	* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ
<>	161:2cc1468da177	3554	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
<>	161:2cc1468da177	3555	*/
<>	161:2cc1468da177	3556	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3557	{
<>	161:2cc1468da177	3558	return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN \| ADC_CR1_JAWDEN \| ADC_CR1_AWDSGL \| ADC_CR1_AWDCH)));
<>	161:2cc1468da177	3559	}
<>	161:2cc1468da177	3560
<>	161:2cc1468da177	3561	/**
<>	161:2cc1468da177	3562	* @brief Set ADC analog watchdog threshold value of threshold
<>	161:2cc1468da177	3563	* high or low.
<>	161:2cc1468da177	3564	* @note In case of ADC resolution different of 12 bits,
<>	161:2cc1468da177	3565	* analog watchdog thresholds data require a specific shift.
<>	161:2cc1468da177	3566	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<>	161:2cc1468da177	3567	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	161:2cc1468da177	3568	* instance:
<>	161:2cc1468da177	3569	* - AWD standard (instance AWD1):
<>	161:2cc1468da177	3570	* - channels monitored: can monitor 1 channel or all channels.
<>	161:2cc1468da177	3571	* - groups monitored: ADC groups regular and-or injected.
<>	161:2cc1468da177	3572	* - resolution: resolution is not limited (corresponds to
<>	161:2cc1468da177	3573	* ADC resolution configured).
<>	161:2cc1468da177	3574	* @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
<>	161:2cc1468da177	3575	* LTR LT LL_ADC_SetAnalogWDThresholds
<>	161:2cc1468da177	3576	* @param ADCx ADC instance
<>	161:2cc1468da177	3577	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	161:2cc1468da177	3578	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	161:2cc1468da177	3579	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	161:2cc1468da177	3580	* @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	3581	* @retval None
<>	161:2cc1468da177	3582	*/
<>	161:2cc1468da177	3583	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
<>	161:2cc1468da177	3584	{
<>	161:2cc1468da177	3585	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
<>	161:2cc1468da177	3586
<>	161:2cc1468da177	3587	MODIFY_REG(*preg,
<>	161:2cc1468da177	3588	ADC_HTR_HT,
<>	161:2cc1468da177	3589	AWDThresholdValue);
<>	161:2cc1468da177	3590	}
<>	161:2cc1468da177	3591
<>	161:2cc1468da177	3592	/**
<>	161:2cc1468da177	3593	* @brief Get ADC analog watchdog threshold value of threshold high or
<>	161:2cc1468da177	3594	* threshold low.
<>	161:2cc1468da177	3595	* @note In case of ADC resolution different of 12 bits,
<>	161:2cc1468da177	3596	* analog watchdog thresholds data require a specific shift.
<>	161:2cc1468da177	3597	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
<>	161:2cc1468da177	3598	* @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
<>	161:2cc1468da177	3599	* LTR LT LL_ADC_GetAnalogWDThresholds
<>	161:2cc1468da177	3600	* @param ADCx ADC instance
<>	161:2cc1468da177	3601	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	161:2cc1468da177	3602	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	161:2cc1468da177	3603	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	161:2cc1468da177	3604	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	3605	*/
<>	161:2cc1468da177	3606	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
<>	161:2cc1468da177	3607	{
<>	161:2cc1468da177	3608	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
<>	161:2cc1468da177	3609
<>	161:2cc1468da177	3610	return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
<>	161:2cc1468da177	3611	}
<>	161:2cc1468da177	3612
<>	161:2cc1468da177	3613	/**
<>	161:2cc1468da177	3614	* @}
<>	161:2cc1468da177	3615	*/
<>	161:2cc1468da177	3616
<>	161:2cc1468da177	3617	/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
<>	161:2cc1468da177	3618	* @{
<>	161:2cc1468da177	3619	*/
<>	161:2cc1468da177	3620
<>	161:2cc1468da177	3621	/**
<>	161:2cc1468da177	3622	* @brief Set ADC multimode configuration to operate in independent mode
<>	161:2cc1468da177	3623	* or multimode (for devices with several ADC instances).
<>	161:2cc1468da177	3624	* @note If multimode configuration: the selected ADC instance is
<>	161:2cc1468da177	3625	* either master or slave depending on hardware.
<>	161:2cc1468da177	3626	* Refer to reference manual.
<>	161:2cc1468da177	3627	* @rmtoll CCR MULTI LL_ADC_SetMultimode
<>	161:2cc1468da177	3628	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	3629	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	3630	* @param Multimode This parameter can be one of the following values:
<>	161:2cc1468da177	3631	* @arg @ref LL_ADC_MULTI_INDEPENDENT
<>	161:2cc1468da177	3632	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
<>	161:2cc1468da177	3633	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
<>	161:2cc1468da177	3634	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
<>	161:2cc1468da177	3635	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
<>	161:2cc1468da177	3636	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
<>	161:2cc1468da177	3637	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
<>	161:2cc1468da177	3638	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
<>	161:2cc1468da177	3639	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
<>	161:2cc1468da177	3640	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
<>	161:2cc1468da177	3641	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
<>	161:2cc1468da177	3642	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
<>	161:2cc1468da177	3643	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
<>	161:2cc1468da177	3644	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
<>	161:2cc1468da177	3645	* @retval None
<>	161:2cc1468da177	3646	*/
<>	161:2cc1468da177	3647	__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
<>	161:2cc1468da177	3648	{
<>	161:2cc1468da177	3649	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
<>	161:2cc1468da177	3650	}
<>	161:2cc1468da177	3651
<>	161:2cc1468da177	3652	/**
<>	161:2cc1468da177	3653	* @brief Get ADC multimode configuration to operate in independent mode
<>	161:2cc1468da177	3654	* or multimode (for devices with several ADC instances).
<>	161:2cc1468da177	3655	* @note If multimode configuration: the selected ADC instance is
<>	161:2cc1468da177	3656	* either master or slave depending on hardware.
<>	161:2cc1468da177	3657	* Refer to reference manual.
<>	161:2cc1468da177	3658	* @rmtoll CCR MULTI LL_ADC_GetMultimode
<>	161:2cc1468da177	3659	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	3660	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	3661	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3662	* @arg @ref LL_ADC_MULTI_INDEPENDENT
<>	161:2cc1468da177	3663	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
<>	161:2cc1468da177	3664	* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
<>	161:2cc1468da177	3665	* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
<>	161:2cc1468da177	3666	* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
<>	161:2cc1468da177	3667	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
<>	161:2cc1468da177	3668	* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
<>	161:2cc1468da177	3669	* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
<>	161:2cc1468da177	3670	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM
<>	161:2cc1468da177	3671	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT
<>	161:2cc1468da177	3672	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT
<>	161:2cc1468da177	3673	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT
<>	161:2cc1468da177	3674	* @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL
<>	161:2cc1468da177	3675	* @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN
<>	161:2cc1468da177	3676	*/
<>	161:2cc1468da177	3677	__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	3678	{
<>	161:2cc1468da177	3679	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
<>	161:2cc1468da177	3680	}
<>	161:2cc1468da177	3681
<>	161:2cc1468da177	3682	/**
<>	161:2cc1468da177	3683	* @brief Set ADC multimode conversion data transfer: no transfer
<>	161:2cc1468da177	3684	* or transfer by DMA.
<>	161:2cc1468da177	3685	* @note If ADC multimode transfer by DMA is not selected:
<>	161:2cc1468da177	3686	* each ADC uses its own DMA channel, with its individual
<>	161:2cc1468da177	3687	* DMA transfer settings.
<>	161:2cc1468da177	3688	* If ADC multimode transfer by DMA is selected:
<>	161:2cc1468da177	3689	* One DMA channel is used for both ADC (DMA of ADC master)
<>	161:2cc1468da177	3690	* Specifies the DMA requests mode:
<>	161:2cc1468da177	3691	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	161:2cc1468da177	3692	* when number of DMA data transfers (number of
<>	161:2cc1468da177	3693	* ADC conversions) is reached.
<>	161:2cc1468da177	3694	* This ADC mode is intended to be used with DMA mode non-circular.
<>	161:2cc1468da177	3695	* - Unlimited mode: DMA transfer requests are unlimited,
<>	161:2cc1468da177	3696	* whatever number of DMA data transfers (number of
<>	161:2cc1468da177	3697	* ADC conversions).
<>	161:2cc1468da177	3698	* This ADC mode is intended to be used with DMA mode circular.
<>	161:2cc1468da177	3699	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	161:2cc1468da177	3700	* mode non-circular:
<>	161:2cc1468da177	3701	* when DMA transfers size will be reached, DMA will stop transfers of
<>	161:2cc1468da177	3702	* ADC conversions data ADC will raise an overrun error
<>	161:2cc1468da177	3703	* (overrun flag and interruption if enabled).
<>	161:2cc1468da177	3704	* @note How to retrieve multimode conversion data:
<>	161:2cc1468da177	3705	* Whatever multimode transfer by DMA setting: using function
<>	161:2cc1468da177	3706	* @ref LL_ADC_REG_ReadMultiConversionData32().
<>	161:2cc1468da177	3707	* If ADC multimode transfer by DMA is selected: conversion data
<>	161:2cc1468da177	3708	* is a raw data with ADC master and slave concatenated.
<>	161:2cc1468da177	3709	* A macro is available to get the conversion data of
<>	161:2cc1468da177	3710	* ADC master or ADC slave: see helper macro
<>	161:2cc1468da177	3711	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	161:2cc1468da177	3712	* @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
<>	161:2cc1468da177	3713	* CCR DDS LL_ADC_SetMultiDMATransfer
<>	161:2cc1468da177	3714	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	3715	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	3716	* @param MultiDMATransfer This parameter can be one of the following values:
<>	161:2cc1468da177	3717	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
<>	161:2cc1468da177	3718	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
<>	161:2cc1468da177	3719	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
<>	161:2cc1468da177	3720	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
<>	161:2cc1468da177	3721	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
<>	161:2cc1468da177	3722	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
<>	161:2cc1468da177	3723	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
<>	161:2cc1468da177	3724	* @retval None
<>	161:2cc1468da177	3725	*/
<>	161:2cc1468da177	3726	__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
<>	161:2cc1468da177	3727	{
<>	161:2cc1468da177	3728	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA \| ADC_CCR_DDS, MultiDMATransfer);
<>	161:2cc1468da177	3729	}
<>	161:2cc1468da177	3730
<>	161:2cc1468da177	3731	/**
<>	161:2cc1468da177	3732	* @brief Get ADC multimode conversion data transfer: no transfer
<>	161:2cc1468da177	3733	* or transfer by DMA.
<>	161:2cc1468da177	3734	* @note If ADC multimode transfer by DMA is not selected:
<>	161:2cc1468da177	3735	* each ADC uses its own DMA channel, with its individual
<>	161:2cc1468da177	3736	* DMA transfer settings.
<>	161:2cc1468da177	3737	* If ADC multimode transfer by DMA is selected:
<>	161:2cc1468da177	3738	* One DMA channel is used for both ADC (DMA of ADC master)
<>	161:2cc1468da177	3739	* Specifies the DMA requests mode:
<>	161:2cc1468da177	3740	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	161:2cc1468da177	3741	* when number of DMA data transfers (number of
<>	161:2cc1468da177	3742	* ADC conversions) is reached.
<>	161:2cc1468da177	3743	* This ADC mode is intended to be used with DMA mode non-circular.
<>	161:2cc1468da177	3744	* - Unlimited mode: DMA transfer requests are unlimited,
<>	161:2cc1468da177	3745	* whatever number of DMA data transfers (number of
<>	161:2cc1468da177	3746	* ADC conversions).
<>	161:2cc1468da177	3747	* This ADC mode is intended to be used with DMA mode circular.
<>	161:2cc1468da177	3748	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	161:2cc1468da177	3749	* mode non-circular:
<>	161:2cc1468da177	3750	* when DMA transfers size will be reached, DMA will stop transfers of
<>	161:2cc1468da177	3751	* ADC conversions data ADC will raise an overrun error
<>	161:2cc1468da177	3752	* (overrun flag and interruption if enabled).
<>	161:2cc1468da177	3753	* @note How to retrieve multimode conversion data:
<>	161:2cc1468da177	3754	* Whatever multimode transfer by DMA setting: using function
<>	161:2cc1468da177	3755	* @ref LL_ADC_REG_ReadMultiConversionData32().
<>	161:2cc1468da177	3756	* If ADC multimode transfer by DMA is selected: conversion data
<>	161:2cc1468da177	3757	* is a raw data with ADC master and slave concatenated.
<>	161:2cc1468da177	3758	* A macro is available to get the conversion data of
<>	161:2cc1468da177	3759	* ADC master or ADC slave: see helper macro
<>	161:2cc1468da177	3760	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	161:2cc1468da177	3761	* @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
<>	161:2cc1468da177	3762	* CCR DDS LL_ADC_GetMultiDMATransfer
<>	161:2cc1468da177	3763	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	3764	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	3765	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3766	* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
<>	161:2cc1468da177	3767	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1
<>	161:2cc1468da177	3768	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2
<>	161:2cc1468da177	3769	* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3
<>	161:2cc1468da177	3770	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1
<>	161:2cc1468da177	3771	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2
<>	161:2cc1468da177	3772	* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3
<>	161:2cc1468da177	3773	*/
<>	161:2cc1468da177	3774	__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	3775	{
<>	161:2cc1468da177	3776	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA \| ADC_CCR_DDS));
<>	161:2cc1468da177	3777	}
<>	161:2cc1468da177	3778
<>	161:2cc1468da177	3779	/**
<>	161:2cc1468da177	3780	* @brief Set ADC multimode delay between 2 sampling phases.
<>	161:2cc1468da177	3781	* @note The sampling delay range depends on ADC resolution:
<>	161:2cc1468da177	3782	* - ADC resolution 12 bits can have maximum delay of 12 cycles.
<>	161:2cc1468da177	3783	* - ADC resolution 10 bits can have maximum delay of 10 cycles.
<>	161:2cc1468da177	3784	* - ADC resolution 8 bits can have maximum delay of 8 cycles.
<>	161:2cc1468da177	3785	* - ADC resolution 6 bits can have maximum delay of 6 cycles.
<>	161:2cc1468da177	3786	* @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
<>	161:2cc1468da177	3787	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	3788	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	3789	* @param MultiTwoSamplingDelay This parameter can be one of the following values:
<>	161:2cc1468da177	3790	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
<>	161:2cc1468da177	3791	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
<>	161:2cc1468da177	3792	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
<>	161:2cc1468da177	3793	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
<>	161:2cc1468da177	3794	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
<>	161:2cc1468da177	3795	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
<>	161:2cc1468da177	3796	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
<>	161:2cc1468da177	3797	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
<>	161:2cc1468da177	3798	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
<>	161:2cc1468da177	3799	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
<>	161:2cc1468da177	3800	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
<>	161:2cc1468da177	3801	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
<>	161:2cc1468da177	3802	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
<>	161:2cc1468da177	3803	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
<>	161:2cc1468da177	3804	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
<>	161:2cc1468da177	3805	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
<>	161:2cc1468da177	3806	* @retval None
<>	161:2cc1468da177	3807	*/
<>	161:2cc1468da177	3808	__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
<>	161:2cc1468da177	3809	{
<>	161:2cc1468da177	3810	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
<>	161:2cc1468da177	3811	}
<>	161:2cc1468da177	3812
<>	161:2cc1468da177	3813	/**
<>	161:2cc1468da177	3814	* @brief Get ADC multimode delay between 2 sampling phases.
<>	161:2cc1468da177	3815	* @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
<>	161:2cc1468da177	3816	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	3817	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	3818	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	3819	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
<>	161:2cc1468da177	3820	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES
<>	161:2cc1468da177	3821	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES
<>	161:2cc1468da177	3822	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES
<>	161:2cc1468da177	3823	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES
<>	161:2cc1468da177	3824	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES
<>	161:2cc1468da177	3825	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES
<>	161:2cc1468da177	3826	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES
<>	161:2cc1468da177	3827	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES
<>	161:2cc1468da177	3828	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES
<>	161:2cc1468da177	3829	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES
<>	161:2cc1468da177	3830	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES
<>	161:2cc1468da177	3831	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES
<>	161:2cc1468da177	3832	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES
<>	161:2cc1468da177	3833	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES
<>	161:2cc1468da177	3834	* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES
<>	161:2cc1468da177	3835	*/
<>	161:2cc1468da177	3836	__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	3837	{
<>	161:2cc1468da177	3838	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
<>	161:2cc1468da177	3839	}
<>	161:2cc1468da177	3840
<>	161:2cc1468da177	3841	/**
<>	161:2cc1468da177	3842	* @}
<>	161:2cc1468da177	3843	*/
<>	161:2cc1468da177	3844	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
<>	161:2cc1468da177	3845	* @{
<>	161:2cc1468da177	3846	*/
<>	161:2cc1468da177	3847
<>	161:2cc1468da177	3848	/**
<>	161:2cc1468da177	3849	* @brief Enable the selected ADC instance.
<>	161:2cc1468da177	3850	* @note On this STM32 serie, after ADC enable, a delay for
<>	161:2cc1468da177	3851	* ADC internal analog stabilization is required before performing a
<>	161:2cc1468da177	3852	* ADC conversion start.
<>	161:2cc1468da177	3853	* Refer to device datasheet, parameter tSTAB.
<>	161:2cc1468da177	3854	* @rmtoll CR2 ADON LL_ADC_Enable
<>	161:2cc1468da177	3855	* @param ADCx ADC instance
<>	161:2cc1468da177	3856	* @retval None
<>	161:2cc1468da177	3857	*/
<>	161:2cc1468da177	3858	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3859	{
<>	161:2cc1468da177	3860	SET_BIT(ADCx->CR2, ADC_CR2_ADON);
<>	161:2cc1468da177	3861	}
<>	161:2cc1468da177	3862
<>	161:2cc1468da177	3863	/**
<>	161:2cc1468da177	3864	* @brief Disable the selected ADC instance.
<>	161:2cc1468da177	3865	* @rmtoll CR2 ADON LL_ADC_Disable
<>	161:2cc1468da177	3866	* @param ADCx ADC instance
<>	161:2cc1468da177	3867	* @retval None
<>	161:2cc1468da177	3868	*/
<>	161:2cc1468da177	3869	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3870	{
<>	161:2cc1468da177	3871	CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
<>	161:2cc1468da177	3872	}
<>	161:2cc1468da177	3873
<>	161:2cc1468da177	3874	/**
<>	161:2cc1468da177	3875	* @brief Get the selected ADC instance enable state.
<>	161:2cc1468da177	3876	* @rmtoll CR2 ADON LL_ADC_IsEnabled
<>	161:2cc1468da177	3877	* @param ADCx ADC instance
<>	161:2cc1468da177	3878	* @retval 0: ADC is disabled, 1: ADC is enabled.
<>	161:2cc1468da177	3879	*/
<>	161:2cc1468da177	3880	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3881	{
<>	161:2cc1468da177	3882	return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
<>	161:2cc1468da177	3883	}
<>	161:2cc1468da177	3884
<>	161:2cc1468da177	3885	/**
<>	161:2cc1468da177	3886	* @}
<>	161:2cc1468da177	3887	*/
<>	161:2cc1468da177	3888
<>	161:2cc1468da177	3889	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
<>	161:2cc1468da177	3890	* @{
<>	161:2cc1468da177	3891	*/
<>	161:2cc1468da177	3892
<>	161:2cc1468da177	3893	/**
<>	161:2cc1468da177	3894	* @brief Start ADC group regular conversion.
<>	161:2cc1468da177	3895	* @note On this STM32 serie, this function is relevant only for
<>	161:2cc1468da177	3896	* internal trigger (SW start), not for external trigger:
<>	161:2cc1468da177	3897	* - If ADC trigger has been set to software start, ADC conversion
<>	161:2cc1468da177	3898	* starts immediately.
<>	161:2cc1468da177	3899	* - If ADC trigger has been set to external trigger, ADC conversion
<>	161:2cc1468da177	3900	* start must be performed using function
<>	161:2cc1468da177	3901	* @ref LL_ADC_REG_StartConversionExtTrig().
<>	161:2cc1468da177	3902	* (if external trigger edge would have been set during ADC other
<>	161:2cc1468da177	3903	* settings, ADC conversion would start at trigger event
<>	161:2cc1468da177	3904	* as soon as ADC is enabled).
<>	161:2cc1468da177	3905	* @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
<>	161:2cc1468da177	3906	* @param ADCx ADC instance
<>	161:2cc1468da177	3907	* @retval None
<>	161:2cc1468da177	3908	*/
<>	161:2cc1468da177	3909	__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3910	{
<>	161:2cc1468da177	3911	SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
<>	161:2cc1468da177	3912	}
<>	161:2cc1468da177	3913
<>	161:2cc1468da177	3914	/**
<>	161:2cc1468da177	3915	* @brief Start ADC group regular conversion from external trigger.
<>	161:2cc1468da177	3916	* @note ADC conversion will start at next trigger event (on the selected
<>	161:2cc1468da177	3917	* trigger edge) following the ADC start conversion command.
<>	161:2cc1468da177	3918	* @note On this STM32 serie, this function is relevant for
<>	161:2cc1468da177	3919	* ADC conversion start from external trigger.
<>	161:2cc1468da177	3920	* If internal trigger (SW start) is needed, perform ADC conversion
<>	161:2cc1468da177	3921	* start using function @ref LL_ADC_REG_StartConversionSWStart().
<>	161:2cc1468da177	3922	* @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
<>	161:2cc1468da177	3923	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	161:2cc1468da177	3924	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	161:2cc1468da177	3925	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	161:2cc1468da177	3926	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	161:2cc1468da177	3927	* @param ADCx ADC instance
<>	161:2cc1468da177	3928	* @retval None
<>	161:2cc1468da177	3929	*/
<>	161:2cc1468da177	3930	__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	161:2cc1468da177	3931	{
<>	161:2cc1468da177	3932	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
<>	161:2cc1468da177	3933	}
<>	161:2cc1468da177	3934
<>	161:2cc1468da177	3935	/**
<>	161:2cc1468da177	3936	* @brief Stop ADC group regular conversion from external trigger.
<>	161:2cc1468da177	3937	* @note No more ADC conversion will start at next trigger event
<>	161:2cc1468da177	3938	* following the ADC stop conversion command.
<>	161:2cc1468da177	3939	* If a conversion is on-going, it will be completed.
<>	161:2cc1468da177	3940	* @note On this STM32 serie, there is no specific command
<>	161:2cc1468da177	3941	* to stop a conversion on-going or to stop ADC converting
<>	161:2cc1468da177	3942	* in continuous mode. These actions can be performed
<>	161:2cc1468da177	3943	* using function @ref LL_ADC_Disable().
<>	161:2cc1468da177	3944	* @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig
<>	161:2cc1468da177	3945	* @param ADCx ADC instance
<>	161:2cc1468da177	3946	* @retval None
<>	161:2cc1468da177	3947	*/
<>	161:2cc1468da177	3948	__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3949	{
<>	161:2cc1468da177	3950	CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
<>	161:2cc1468da177	3951	}
<>	161:2cc1468da177	3952
<>	161:2cc1468da177	3953	/**
<>	161:2cc1468da177	3954	* @brief Get ADC group regular conversion data, range fit for
<>	161:2cc1468da177	3955	* all ADC configurations: all ADC resolutions and
<>	161:2cc1468da177	3956	* all oversampling increased data width (for devices
<>	161:2cc1468da177	3957	* with feature oversampling).
<>	161:2cc1468da177	3958	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
<>	161:2cc1468da177	3959	* @param ADCx ADC instance
<>	161:2cc1468da177	3960	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	3961	*/
<>	161:2cc1468da177	3962	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3963	{
<>	161:2cc1468da177	3964	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	161:2cc1468da177	3965	}
<>	161:2cc1468da177	3966
<>	161:2cc1468da177	3967	/**
<>	161:2cc1468da177	3968	* @brief Get ADC group regular conversion data, range fit for
<>	161:2cc1468da177	3969	* ADC resolution 12 bits.
<>	161:2cc1468da177	3970	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	3971	* can increase data width, function for extended range
<>	161:2cc1468da177	3972	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	161:2cc1468da177	3973	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
<>	161:2cc1468da177	3974	* @param ADCx ADC instance
<>	161:2cc1468da177	3975	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	3976	*/
<>	161:2cc1468da177	3977	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3978	{
<>	161:2cc1468da177	3979	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	161:2cc1468da177	3980	}
<>	161:2cc1468da177	3981
<>	161:2cc1468da177	3982	/**
<>	161:2cc1468da177	3983	* @brief Get ADC group regular conversion data, range fit for
<>	161:2cc1468da177	3984	* ADC resolution 10 bits.
<>	161:2cc1468da177	3985	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	3986	* can increase data width, function for extended range
<>	161:2cc1468da177	3987	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	161:2cc1468da177	3988	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
<>	161:2cc1468da177	3989	* @param ADCx ADC instance
<>	161:2cc1468da177	3990	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	161:2cc1468da177	3991	*/
<>	161:2cc1468da177	3992	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	3993	{
<>	161:2cc1468da177	3994	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	161:2cc1468da177	3995	}
<>	161:2cc1468da177	3996
<>	161:2cc1468da177	3997	/**
<>	161:2cc1468da177	3998	* @brief Get ADC group regular conversion data, range fit for
<>	161:2cc1468da177	3999	* ADC resolution 8 bits.
<>	161:2cc1468da177	4000	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	4001	* can increase data width, function for extended range
<>	161:2cc1468da177	4002	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	161:2cc1468da177	4003	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
<>	161:2cc1468da177	4004	* @param ADCx ADC instance
<>	161:2cc1468da177	4005	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	4006	*/
<>	161:2cc1468da177	4007	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4008	{
<>	161:2cc1468da177	4009	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	161:2cc1468da177	4010	}
<>	161:2cc1468da177	4011
<>	161:2cc1468da177	4012	/**
<>	161:2cc1468da177	4013	* @brief Get ADC group regular conversion data, range fit for
<>	161:2cc1468da177	4014	* ADC resolution 6 bits.
<>	161:2cc1468da177	4015	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	4016	* can increase data width, function for extended range
<>	161:2cc1468da177	4017	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	161:2cc1468da177	4018	* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
<>	161:2cc1468da177	4019	* @param ADCx ADC instance
<>	161:2cc1468da177	4020	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	161:2cc1468da177	4021	*/
<>	161:2cc1468da177	4022	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4023	{
<>	161:2cc1468da177	4024	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	161:2cc1468da177	4025	}
<>	161:2cc1468da177	4026
<>	161:2cc1468da177	4027	/**
<>	161:2cc1468da177	4028	* @brief Get ADC multimode conversion data of ADC master, ADC slave
<>	161:2cc1468da177	4029	* or raw data with ADC master and slave concatenated.
<>	161:2cc1468da177	4030	* @note If raw data with ADC master and slave concatenated is retrieved,
<>	161:2cc1468da177	4031	* a macro is available to get the conversion data of
<>	161:2cc1468da177	4032	* ADC master or ADC slave: see helper macro
<>	161:2cc1468da177	4033	* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
<>	161:2cc1468da177	4034	* (however this macro is mainly intended for multimode
<>	161:2cc1468da177	4035	* transfer by DMA, because this function can do the same
<>	161:2cc1468da177	4036	* by getting multimode conversion data of ADC master or ADC slave
<>	161:2cc1468da177	4037	* separately).
<>	161:2cc1468da177	4038	* @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n
<>	161:2cc1468da177	4039	* CDR DATA2 LL_ADC_REG_ReadMultiConversionData32
<>	161:2cc1468da177	4040	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4041	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4042	* @param ConversionData This parameter can be one of the following values:
<>	161:2cc1468da177	4043	* @arg @ref LL_ADC_MULTI_MASTER
<>	161:2cc1468da177	4044	* @arg @ref LL_ADC_MULTI_SLAVE
<>	161:2cc1468da177	4045	* @arg @ref LL_ADC_MULTI_MASTER_SLAVE
<>	161:2cc1468da177	4046	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	4047	*/
<>	161:2cc1468da177	4048	__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
<>	161:2cc1468da177	4049	{
<>	161:2cc1468da177	4050	return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
<>	161:2cc1468da177	4051	ADC_DR_ADC2DATA)
<>	161:2cc1468da177	4052	>> POSITION_VAL(ConversionData)
<>	161:2cc1468da177	4053	);
<>	161:2cc1468da177	4054	}
<>	161:2cc1468da177	4055
<>	161:2cc1468da177	4056	/**
<>	161:2cc1468da177	4057	* @}
<>	161:2cc1468da177	4058	*/
<>	161:2cc1468da177	4059
<>	161:2cc1468da177	4060	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
<>	161:2cc1468da177	4061	* @{
<>	161:2cc1468da177	4062	*/
<>	161:2cc1468da177	4063
<>	161:2cc1468da177	4064	/**
<>	161:2cc1468da177	4065	* @brief Start ADC group injected conversion.
<>	161:2cc1468da177	4066	* @note On this STM32 serie, this function is relevant only for
<>	161:2cc1468da177	4067	* internal trigger (SW start), not for external trigger:
<>	161:2cc1468da177	4068	* - If ADC trigger has been set to software start, ADC conversion
<>	161:2cc1468da177	4069	* starts immediately.
<>	161:2cc1468da177	4070	* - If ADC trigger has been set to external trigger, ADC conversion
<>	161:2cc1468da177	4071	* start must be performed using function
<>	161:2cc1468da177	4072	* @ref LL_ADC_INJ_StartConversionExtTrig().
<>	161:2cc1468da177	4073	* (if external trigger edge would have been set during ADC other
<>	161:2cc1468da177	4074	* settings, ADC conversion would start at trigger event
<>	161:2cc1468da177	4075	* as soon as ADC is enabled).
<>	161:2cc1468da177	4076	* @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
<>	161:2cc1468da177	4077	* @param ADCx ADC instance
<>	161:2cc1468da177	4078	* @retval None
<>	161:2cc1468da177	4079	*/
<>	161:2cc1468da177	4080	__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4081	{
<>	161:2cc1468da177	4082	SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
<>	161:2cc1468da177	4083	}
<>	161:2cc1468da177	4084
<>	161:2cc1468da177	4085	/**
<>	161:2cc1468da177	4086	* @brief Start ADC group injected conversion from external trigger.
<>	161:2cc1468da177	4087	* @note ADC conversion will start at next trigger event (on the selected
<>	161:2cc1468da177	4088	* trigger edge) following the ADC start conversion command.
<>	161:2cc1468da177	4089	* @note On this STM32 serie, this function is relevant for
<>	161:2cc1468da177	4090	* ADC conversion start from external trigger.
<>	161:2cc1468da177	4091	* If internal trigger (SW start) is needed, perform ADC conversion
<>	161:2cc1468da177	4092	* start using function @ref LL_ADC_INJ_StartConversionSWStart().
<>	161:2cc1468da177	4093	* @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
<>	161:2cc1468da177	4094	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	161:2cc1468da177	4095	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
<>	161:2cc1468da177	4096	* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
<>	161:2cc1468da177	4097	* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
<>	161:2cc1468da177	4098	* @param ADCx ADC instance
<>	161:2cc1468da177	4099	* @retval None
<>	161:2cc1468da177	4100	*/
<>	161:2cc1468da177	4101	__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	161:2cc1468da177	4102	{
<>	161:2cc1468da177	4103	SET_BIT(ADCx->CR2, ExternalTriggerEdge);
<>	161:2cc1468da177	4104	}
<>	161:2cc1468da177	4105
<>	161:2cc1468da177	4106	/**
<>	161:2cc1468da177	4107	* @brief Stop ADC group injected conversion from external trigger.
<>	161:2cc1468da177	4108	* @note No more ADC conversion will start at next trigger event
<>	161:2cc1468da177	4109	* following the ADC stop conversion command.
<>	161:2cc1468da177	4110	* If a conversion is on-going, it will be completed.
<>	161:2cc1468da177	4111	* @note On this STM32 serie, there is no specific command
<>	161:2cc1468da177	4112	* to stop a conversion on-going or to stop ADC converting
<>	161:2cc1468da177	4113	* in continuous mode. These actions can be performed
<>	161:2cc1468da177	4114	* using function @ref LL_ADC_Disable().
<>	161:2cc1468da177	4115	* @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig
<>	161:2cc1468da177	4116	* @param ADCx ADC instance
<>	161:2cc1468da177	4117	* @retval None
<>	161:2cc1468da177	4118	*/
<>	161:2cc1468da177	4119	__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4120	{
<>	161:2cc1468da177	4121	CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
<>	161:2cc1468da177	4122	}
<>	161:2cc1468da177	4123
<>	161:2cc1468da177	4124	/**
<>	161:2cc1468da177	4125	* @brief Get ADC group regular conversion data, range fit for
<>	161:2cc1468da177	4126	* all ADC configurations: all ADC resolutions and
<>	161:2cc1468da177	4127	* all oversampling increased data width (for devices
<>	161:2cc1468da177	4128	* with feature oversampling).
<>	161:2cc1468da177	4129	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	161:2cc1468da177	4130	* JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	161:2cc1468da177	4131	* JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
<>	161:2cc1468da177	4132	* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
<>	161:2cc1468da177	4133	* @param ADCx ADC instance
<>	161:2cc1468da177	4134	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	4135	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	4136	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	4137	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	4138	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	4139	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	4140	*/
<>	161:2cc1468da177	4141	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	4142	{
<>	161:2cc1468da177	4143	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	161:2cc1468da177	4144
<>	161:2cc1468da177	4145	return (uint32_t)(READ_BIT(*preg,
<>	161:2cc1468da177	4146	ADC_JDR1_JDATA)
<>	161:2cc1468da177	4147	);
<>	161:2cc1468da177	4148	}
<>	161:2cc1468da177	4149
<>	161:2cc1468da177	4150	/**
<>	161:2cc1468da177	4151	* @brief Get ADC group injected conversion data, range fit for
<>	161:2cc1468da177	4152	* ADC resolution 12 bits.
<>	161:2cc1468da177	4153	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	4154	* can increase data width, function for extended range
<>	161:2cc1468da177	4155	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	161:2cc1468da177	4156	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	161:2cc1468da177	4157	* JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	161:2cc1468da177	4158	* JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
<>	161:2cc1468da177	4159	* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
<>	161:2cc1468da177	4160	* @param ADCx ADC instance
<>	161:2cc1468da177	4161	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	4162	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	4163	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	4164	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	4165	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	4166	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	161:2cc1468da177	4167	*/
<>	161:2cc1468da177	4168	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	4169	{
<>	161:2cc1468da177	4170	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	161:2cc1468da177	4171
<>	161:2cc1468da177	4172	return (uint16_t)(READ_BIT(*preg,
<>	161:2cc1468da177	4173	ADC_JDR1_JDATA)
<>	161:2cc1468da177	4174	);
<>	161:2cc1468da177	4175	}
<>	161:2cc1468da177	4176
<>	161:2cc1468da177	4177	/**
<>	161:2cc1468da177	4178	* @brief Get ADC group injected conversion data, range fit for
<>	161:2cc1468da177	4179	* ADC resolution 10 bits.
<>	161:2cc1468da177	4180	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	4181	* can increase data width, function for extended range
<>	161:2cc1468da177	4182	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	161:2cc1468da177	4183	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	161:2cc1468da177	4184	* JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	161:2cc1468da177	4185	* JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
<>	161:2cc1468da177	4186	* JDR4 JDATA LL_ADC_INJ_ReadConversionData10
<>	161:2cc1468da177	4187	* @param ADCx ADC instance
<>	161:2cc1468da177	4188	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	4189	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	4190	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	4191	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	4192	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	4193	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	161:2cc1468da177	4194	*/
<>	161:2cc1468da177	4195	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	4196	{
<>	161:2cc1468da177	4197	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	161:2cc1468da177	4198
<>	161:2cc1468da177	4199	return (uint16_t)(READ_BIT(*preg,
<>	161:2cc1468da177	4200	ADC_JDR1_JDATA)
<>	161:2cc1468da177	4201	);
<>	161:2cc1468da177	4202	}
<>	161:2cc1468da177	4203
<>	161:2cc1468da177	4204	/**
<>	161:2cc1468da177	4205	* @brief Get ADC group injected conversion data, range fit for
<>	161:2cc1468da177	4206	* ADC resolution 8 bits.
<>	161:2cc1468da177	4207	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	4208	* can increase data width, function for extended range
<>	161:2cc1468da177	4209	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	161:2cc1468da177	4210	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	161:2cc1468da177	4211	* JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	161:2cc1468da177	4212	* JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
<>	161:2cc1468da177	4213	* JDR4 JDATA LL_ADC_INJ_ReadConversionData8
<>	161:2cc1468da177	4214	* @param ADCx ADC instance
<>	161:2cc1468da177	4215	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	4216	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	4217	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	4218	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	4219	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	4220	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	4221	*/
<>	161:2cc1468da177	4222	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	4223	{
<>	161:2cc1468da177	4224	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	161:2cc1468da177	4225
<>	161:2cc1468da177	4226	return (uint8_t)(READ_BIT(*preg,
<>	161:2cc1468da177	4227	ADC_JDR1_JDATA)
<>	161:2cc1468da177	4228	);
<>	161:2cc1468da177	4229	}
<>	161:2cc1468da177	4230
<>	161:2cc1468da177	4231	/**
<>	161:2cc1468da177	4232	* @brief Get ADC group injected conversion data, range fit for
<>	161:2cc1468da177	4233	* ADC resolution 6 bits.
<>	161:2cc1468da177	4234	* @note For devices with feature oversampling: Oversampling
<>	161:2cc1468da177	4235	* can increase data width, function for extended range
<>	161:2cc1468da177	4236	* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
<>	161:2cc1468da177	4237	* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	161:2cc1468da177	4238	* JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	161:2cc1468da177	4239	* JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
<>	161:2cc1468da177	4240	* JDR4 JDATA LL_ADC_INJ_ReadConversionData6
<>	161:2cc1468da177	4241	* @param ADCx ADC instance
<>	161:2cc1468da177	4242	* @param Rank This parameter can be one of the following values:
<>	161:2cc1468da177	4243	* @arg @ref LL_ADC_INJ_RANK_1
<>	161:2cc1468da177	4244	* @arg @ref LL_ADC_INJ_RANK_2
<>	161:2cc1468da177	4245	* @arg @ref LL_ADC_INJ_RANK_3
<>	161:2cc1468da177	4246	* @arg @ref LL_ADC_INJ_RANK_4
<>	161:2cc1468da177	4247	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	161:2cc1468da177	4248	*/
<>	161:2cc1468da177	4249	__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
<>	161:2cc1468da177	4250	{
<>	161:2cc1468da177	4251	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
<>	161:2cc1468da177	4252
<>	161:2cc1468da177	4253	return (uint8_t)(READ_BIT(*preg,
<>	161:2cc1468da177	4254	ADC_JDR1_JDATA)
<>	161:2cc1468da177	4255	);
<>	161:2cc1468da177	4256	}
<>	161:2cc1468da177	4257
<>	161:2cc1468da177	4258	/**
<>	161:2cc1468da177	4259	* @}
<>	161:2cc1468da177	4260	*/
<>	161:2cc1468da177	4261
<>	161:2cc1468da177	4262	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
<>	161:2cc1468da177	4263	* @{
<>	161:2cc1468da177	4264	*/
<>	161:2cc1468da177	4265
<>	161:2cc1468da177	4266	/**
<>	161:2cc1468da177	4267	* @brief Get flag ADC group regular end of unitary conversion
<>	161:2cc1468da177	4268	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4269	* ADC configuration.
<>	161:2cc1468da177	4270	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4271	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4272	* @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS
<>	161:2cc1468da177	4273	* @param ADCx ADC instance
<>	161:2cc1468da177	4274	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4275	*/
<>	161:2cc1468da177	4276	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4277	{
<>	161:2cc1468da177	4278	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
<>	161:2cc1468da177	4279	}
<>	161:2cc1468da177	4280
<>	161:2cc1468da177	4281	/**
<>	161:2cc1468da177	4282	* @brief Get flag ADC group regular overrun.
<>	161:2cc1468da177	4283	* @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR
<>	161:2cc1468da177	4284	* @param ADCx ADC instance
<>	161:2cc1468da177	4285	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4286	*/
<>	161:2cc1468da177	4287	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4288	{
<>	161:2cc1468da177	4289	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
<>	161:2cc1468da177	4290	}
<>	161:2cc1468da177	4291
<>	161:2cc1468da177	4292
<>	161:2cc1468da177	4293	/**
<>	161:2cc1468da177	4294	* @brief Get flag ADC group injected end of sequence conversions.
<>	161:2cc1468da177	4295	* @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
<>	161:2cc1468da177	4296	* @param ADCx ADC instance
<>	161:2cc1468da177	4297	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4298	*/
<>	161:2cc1468da177	4299	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4300	{
<>	161:2cc1468da177	4301	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4302	/* end of unitary conversion. */
<>	161:2cc1468da177	4303	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4304	/* in other STM32 families). */
<>	161:2cc1468da177	4305	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
<>	161:2cc1468da177	4306	}
<>	161:2cc1468da177	4307
<>	161:2cc1468da177	4308	/**
<>	161:2cc1468da177	4309	* @brief Get flag ADC analog watchdog 1 flag
<>	161:2cc1468da177	4310	* @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
<>	161:2cc1468da177	4311	* @param ADCx ADC instance
<>	161:2cc1468da177	4312	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4313	*/
<>	161:2cc1468da177	4314	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4315	{
<>	161:2cc1468da177	4316	return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
<>	161:2cc1468da177	4317	}
<>	161:2cc1468da177	4318
<>	161:2cc1468da177	4319	/**
<>	161:2cc1468da177	4320	* @brief Clear flag ADC group regular end of unitary conversion
<>	161:2cc1468da177	4321	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4322	* ADC configuration.
<>	161:2cc1468da177	4323	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4324	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4325	* @rmtoll SR EOC LL_ADC_ClearFlag_EOCS
<>	161:2cc1468da177	4326	* @param ADCx ADC instance
<>	161:2cc1468da177	4327	* @retval None
<>	161:2cc1468da177	4328	*/
<>	161:2cc1468da177	4329	__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4330	{
<>	161:2cc1468da177	4331	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
<>	161:2cc1468da177	4332	}
<>	161:2cc1468da177	4333
<>	161:2cc1468da177	4334	/**
<>	161:2cc1468da177	4335	* @brief Clear flag ADC group regular overrun.
<>	161:2cc1468da177	4336	* @rmtoll SR OVR LL_ADC_ClearFlag_OVR
<>	161:2cc1468da177	4337	* @param ADCx ADC instance
<>	161:2cc1468da177	4338	* @retval None
<>	161:2cc1468da177	4339	*/
<>	161:2cc1468da177	4340	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4341	{
<>	161:2cc1468da177	4342	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
<>	161:2cc1468da177	4343	}
<>	161:2cc1468da177	4344
<>	161:2cc1468da177	4345
<>	161:2cc1468da177	4346	/**
<>	161:2cc1468da177	4347	* @brief Clear flag ADC group injected end of sequence conversions.
<>	161:2cc1468da177	4348	* @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
<>	161:2cc1468da177	4349	* @param ADCx ADC instance
<>	161:2cc1468da177	4350	* @retval None
<>	161:2cc1468da177	4351	*/
<>	161:2cc1468da177	4352	__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4353	{
<>	161:2cc1468da177	4354	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4355	/* end of unitary conversion. */
<>	161:2cc1468da177	4356	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4357	/* in other STM32 families). */
<>	161:2cc1468da177	4358	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
<>	161:2cc1468da177	4359	}
<>	161:2cc1468da177	4360
<>	161:2cc1468da177	4361	/**
<>	161:2cc1468da177	4362	* @brief Clear flag ADC analog watchdog 1.
<>	161:2cc1468da177	4363	* @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
<>	161:2cc1468da177	4364	* @param ADCx ADC instance
<>	161:2cc1468da177	4365	* @retval None
<>	161:2cc1468da177	4366	*/
<>	161:2cc1468da177	4367	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4368	{
<>	161:2cc1468da177	4369	WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
<>	161:2cc1468da177	4370	}
<>	161:2cc1468da177	4371
<>	161:2cc1468da177	4372	/**
<>	161:2cc1468da177	4373	* @brief Get flag multimode ADC group regular end of unitary conversion
<>	161:2cc1468da177	4374	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4375	* ADC configuration, of the ADC master.
<>	161:2cc1468da177	4376	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4377	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4378	* @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS
<>	161:2cc1468da177	4379	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4380	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4381	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4382	*/
<>	161:2cc1468da177	4383	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4384	{
<>	161:2cc1468da177	4385	return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
<>	161:2cc1468da177	4386	}
<>	161:2cc1468da177	4387
<>	161:2cc1468da177	4388	/**
<>	161:2cc1468da177	4389	* @brief Get flag multimode ADC group regular end of unitary conversion
<>	161:2cc1468da177	4390	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4391	* ADC configuration, of the ADC slave 1.
<>	161:2cc1468da177	4392	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4393	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4394	* @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS
<>	161:2cc1468da177	4395	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4396	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4397	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4398	*/
<>	161:2cc1468da177	4399	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4400	{
<>	161:2cc1468da177	4401	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
<>	161:2cc1468da177	4402	}
<>	161:2cc1468da177	4403
<>	161:2cc1468da177	4404	/**
<>	161:2cc1468da177	4405	* @brief Get flag multimode ADC group regular end of unitary conversion
<>	161:2cc1468da177	4406	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4407	* ADC configuration, of the ADC slave 2.
<>	161:2cc1468da177	4408	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4409	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4410	* @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS
<>	161:2cc1468da177	4411	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4412	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4413	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4414	*/
<>	161:2cc1468da177	4415	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4416	{
<>	161:2cc1468da177	4417	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
<>	161:2cc1468da177	4418	}
<>	161:2cc1468da177	4419	/**
<>	161:2cc1468da177	4420	* @brief Get flag multimode ADC group regular overrun of the ADC master.
<>	161:2cc1468da177	4421	* @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR
<>	161:2cc1468da177	4422	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4423	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4424	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4425	*/
<>	161:2cc1468da177	4426	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4427	{
<>	161:2cc1468da177	4428	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
<>	161:2cc1468da177	4429	}
<>	161:2cc1468da177	4430
<>	161:2cc1468da177	4431	/**
<>	161:2cc1468da177	4432	* @brief Get flag multimode ADC group regular overrun of the ADC slave 1.
<>	161:2cc1468da177	4433	* @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR
<>	161:2cc1468da177	4434	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4435	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4436	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4437	*/
<>	161:2cc1468da177	4438	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4439	{
<>	161:2cc1468da177	4440	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
<>	161:2cc1468da177	4441	}
<>	161:2cc1468da177	4442
<>	161:2cc1468da177	4443	/**
<>	161:2cc1468da177	4444	* @brief Get flag multimode ADC group regular overrun of the ADC slave 2.
<>	161:2cc1468da177	4445	* @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR
<>	161:2cc1468da177	4446	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4447	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4448	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4449	*/
<>	161:2cc1468da177	4450	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4451	{
<>	161:2cc1468da177	4452	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
<>	161:2cc1468da177	4453	}
<>	161:2cc1468da177	4454
<>	161:2cc1468da177	4455
<>	161:2cc1468da177	4456	/**
<>	161:2cc1468da177	4457	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
<>	161:2cc1468da177	4458	* @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS
<>	161:2cc1468da177	4459	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4460	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4461	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4462	*/
<>	161:2cc1468da177	4463	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4464	{
<>	161:2cc1468da177	4465	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4466	/* end of unitary conversion. */
<>	161:2cc1468da177	4467	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4468	/* in other STM32 families). */
<>	161:2cc1468da177	4469	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
<>	161:2cc1468da177	4470	}
<>	161:2cc1468da177	4471
<>	161:2cc1468da177	4472	/**
<>	161:2cc1468da177	4473	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.
<>	161:2cc1468da177	4474	* @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS
<>	161:2cc1468da177	4475	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4476	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4477	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4478	*/
<>	161:2cc1468da177	4479	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4480	{
<>	161:2cc1468da177	4481	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4482	/* end of unitary conversion. */
<>	161:2cc1468da177	4483	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4484	/* in other STM32 families). */
<>	161:2cc1468da177	4485	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
<>	161:2cc1468da177	4486	}
<>	161:2cc1468da177	4487
<>	161:2cc1468da177	4488	/**
<>	161:2cc1468da177	4489	* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.
<>	161:2cc1468da177	4490	* @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS
<>	161:2cc1468da177	4491	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4492	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4493	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4494	*/
<>	161:2cc1468da177	4495	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4496	{
<>	161:2cc1468da177	4497	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4498	/* end of unitary conversion. */
<>	161:2cc1468da177	4499	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4500	/* in other STM32 families). */
<>	161:2cc1468da177	4501	return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
<>	161:2cc1468da177	4502	}
<>	161:2cc1468da177	4503
<>	161:2cc1468da177	4504	/**
<>	161:2cc1468da177	4505	* @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
<>	161:2cc1468da177	4506	* @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1
<>	161:2cc1468da177	4507	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4508	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4509	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4510	*/
<>	161:2cc1468da177	4511	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4512	{
<>	161:2cc1468da177	4513	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
<>	161:2cc1468da177	4514	}
<>	161:2cc1468da177	4515
<>	161:2cc1468da177	4516	/**
<>	161:2cc1468da177	4517	* @brief Get flag multimode analog watchdog 1 of the ADC slave 1.
<>	161:2cc1468da177	4518	* @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1
<>	161:2cc1468da177	4519	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4520	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4521	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4522	*/
<>	161:2cc1468da177	4523	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4524	{
<>	161:2cc1468da177	4525	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
<>	161:2cc1468da177	4526	}
<>	161:2cc1468da177	4527
<>	161:2cc1468da177	4528	/**
<>	161:2cc1468da177	4529	* @brief Get flag multimode analog watchdog 1 of the ADC slave 2.
<>	161:2cc1468da177	4530	* @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1
<>	161:2cc1468da177	4531	* @param ADCxy_COMMON ADC common instance
<>	161:2cc1468da177	4532	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	161:2cc1468da177	4533	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4534	*/
<>	161:2cc1468da177	4535	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
<>	161:2cc1468da177	4536	{
<>	161:2cc1468da177	4537	return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
<>	161:2cc1468da177	4538	}
<>	161:2cc1468da177	4539
<>	161:2cc1468da177	4540
<>	161:2cc1468da177	4541	/**
<>	161:2cc1468da177	4542	* @}
<>	161:2cc1468da177	4543	*/
<>	161:2cc1468da177	4544
<>	161:2cc1468da177	4545	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
<>	161:2cc1468da177	4546	* @{
<>	161:2cc1468da177	4547	*/
<>	161:2cc1468da177	4548
<>	161:2cc1468da177	4549	/**
<>	161:2cc1468da177	4550	* @brief Enable interruption ADC group regular end of unitary conversion
<>	161:2cc1468da177	4551	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4552	* ADC configuration.
<>	161:2cc1468da177	4553	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4554	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4555	* @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS
<>	161:2cc1468da177	4556	* @param ADCx ADC instance
<>	161:2cc1468da177	4557	* @retval None
<>	161:2cc1468da177	4558	*/
<>	161:2cc1468da177	4559	__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4560	{
<>	161:2cc1468da177	4561	SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
<>	161:2cc1468da177	4562	}
<>	161:2cc1468da177	4563
<>	161:2cc1468da177	4564	/**
<>	161:2cc1468da177	4565	* @brief Enable ADC group regular interruption overrun.
<>	161:2cc1468da177	4566	* @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR
<>	161:2cc1468da177	4567	* @param ADCx ADC instance
<>	161:2cc1468da177	4568	* @retval None
<>	161:2cc1468da177	4569	*/
<>	161:2cc1468da177	4570	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4571	{
<>	161:2cc1468da177	4572	SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
<>	161:2cc1468da177	4573	}
<>	161:2cc1468da177	4574
<>	161:2cc1468da177	4575
<>	161:2cc1468da177	4576	/**
<>	161:2cc1468da177	4577	* @brief Enable interruption ADC group injected end of sequence conversions.
<>	161:2cc1468da177	4578	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	161:2cc1468da177	4579	* @param ADCx ADC instance
<>	161:2cc1468da177	4580	* @retval None
<>	161:2cc1468da177	4581	*/
<>	161:2cc1468da177	4582	__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4583	{
<>	161:2cc1468da177	4584	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4585	/* end of unitary conversion. */
<>	161:2cc1468da177	4586	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4587	/* in other STM32 families). */
<>	161:2cc1468da177	4588	SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
<>	161:2cc1468da177	4589	}
<>	161:2cc1468da177	4590
<>	161:2cc1468da177	4591	/**
<>	161:2cc1468da177	4592	* @brief Enable interruption ADC analog watchdog 1.
<>	161:2cc1468da177	4593	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	161:2cc1468da177	4594	* @param ADCx ADC instance
<>	161:2cc1468da177	4595	* @retval None
<>	161:2cc1468da177	4596	*/
<>	161:2cc1468da177	4597	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4598	{
<>	161:2cc1468da177	4599	SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
<>	161:2cc1468da177	4600	}
<>	161:2cc1468da177	4601
<>	161:2cc1468da177	4602	/**
<>	161:2cc1468da177	4603	* @brief Disable interruption ADC group regular end of unitary conversion
<>	161:2cc1468da177	4604	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4605	* ADC configuration.
<>	161:2cc1468da177	4606	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4607	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4608	* @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS
<>	161:2cc1468da177	4609	* @param ADCx ADC instance
<>	161:2cc1468da177	4610	* @retval None
<>	161:2cc1468da177	4611	*/
<>	161:2cc1468da177	4612	__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4613	{
<>	161:2cc1468da177	4614	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
<>	161:2cc1468da177	4615	}
<>	161:2cc1468da177	4616
<>	161:2cc1468da177	4617	/**
<>	161:2cc1468da177	4618	* @brief Disable interruption ADC group regular overrun.
<>	161:2cc1468da177	4619	* @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR
<>	161:2cc1468da177	4620	* @param ADCx ADC instance
<>	161:2cc1468da177	4621	* @retval None
<>	161:2cc1468da177	4622	*/
<>	161:2cc1468da177	4623	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4624	{
<>	161:2cc1468da177	4625	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
<>	161:2cc1468da177	4626	}
<>	161:2cc1468da177	4627
<>	161:2cc1468da177	4628
<>	161:2cc1468da177	4629	/**
<>	161:2cc1468da177	4630	* @brief Disable interruption ADC group injected end of sequence conversions.
<>	161:2cc1468da177	4631	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	161:2cc1468da177	4632	* @param ADCx ADC instance
<>	161:2cc1468da177	4633	* @retval None
<>	161:2cc1468da177	4634	*/
<>	161:2cc1468da177	4635	__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4636	{
<>	161:2cc1468da177	4637	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4638	/* end of unitary conversion. */
<>	161:2cc1468da177	4639	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4640	/* in other STM32 families). */
<>	161:2cc1468da177	4641	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
<>	161:2cc1468da177	4642	}
<>	161:2cc1468da177	4643
<>	161:2cc1468da177	4644	/**
<>	161:2cc1468da177	4645	* @brief Disable interruption ADC analog watchdog 1.
<>	161:2cc1468da177	4646	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	161:2cc1468da177	4647	* @param ADCx ADC instance
<>	161:2cc1468da177	4648	* @retval None
<>	161:2cc1468da177	4649	*/
<>	161:2cc1468da177	4650	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4651	{
<>	161:2cc1468da177	4652	CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
<>	161:2cc1468da177	4653	}
<>	161:2cc1468da177	4654
<>	161:2cc1468da177	4655	/**
<>	161:2cc1468da177	4656	* @brief Get state of interruption ADC group regular end of unitary conversion
<>	161:2cc1468da177	4657	* or end of sequence conversions, depending on
<>	161:2cc1468da177	4658	* ADC configuration.
<>	161:2cc1468da177	4659	* @note To configure flag of end of conversion,
<>	161:2cc1468da177	4660	* use function @ref LL_ADC_REG_SetFlagEndOfConversion().
<>	161:2cc1468da177	4661	* (0: interrupt disabled, 1: interrupt enabled)
<>	161:2cc1468da177	4662	* @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS
<>	161:2cc1468da177	4663	* @param ADCx ADC instance
<>	161:2cc1468da177	4664	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4665	*/
<>	161:2cc1468da177	4666	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4667	{
<>	161:2cc1468da177	4668	return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
<>	161:2cc1468da177	4669	}
<>	161:2cc1468da177	4670
<>	161:2cc1468da177	4671	/**
<>	161:2cc1468da177	4672	* @brief Get state of interruption ADC group regular overrun
<>	161:2cc1468da177	4673	* (0: interrupt disabled, 1: interrupt enabled).
<>	161:2cc1468da177	4674	* @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR
<>	161:2cc1468da177	4675	* @param ADCx ADC instance
<>	161:2cc1468da177	4676	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4677	*/
<>	161:2cc1468da177	4678	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4679	{
<>	161:2cc1468da177	4680	return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
<>	161:2cc1468da177	4681	}
<>	161:2cc1468da177	4682
<>	161:2cc1468da177	4683
<>	161:2cc1468da177	4684	/**
<>	161:2cc1468da177	4685	* @brief Get state of interruption ADC group injected end of sequence conversions
<>	161:2cc1468da177	4686	* (0: interrupt disabled, 1: interrupt enabled).
<>	161:2cc1468da177	4687	* @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
<>	161:2cc1468da177	4688	* @param ADCx ADC instance
<>	161:2cc1468da177	4689	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4690	*/
<>	161:2cc1468da177	4691	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4692	{
<>	161:2cc1468da177	4693	/* Note: on this STM32 serie, there is no flag ADC group injected */
<>	161:2cc1468da177	4694	/* end of unitary conversion. */
<>	161:2cc1468da177	4695	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
<>	161:2cc1468da177	4696	/* in other STM32 families). */
<>	161:2cc1468da177	4697	return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
<>	161:2cc1468da177	4698	}
<>	161:2cc1468da177	4699
<>	161:2cc1468da177	4700	/**
<>	161:2cc1468da177	4701	* @brief Get state of interruption ADC analog watchdog 1
<>	161:2cc1468da177	4702	* (0: interrupt disabled, 1: interrupt enabled).
<>	161:2cc1468da177	4703	* @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
<>	161:2cc1468da177	4704	* @param ADCx ADC instance
<>	161:2cc1468da177	4705	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	4706	*/
<>	161:2cc1468da177	4707	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
<>	161:2cc1468da177	4708	{
<>	161:2cc1468da177	4709	return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
<>	161:2cc1468da177	4710	}
<>	161:2cc1468da177	4711
<>	161:2cc1468da177	4712	/**
<>	161:2cc1468da177	4713	* @}
<>	161:2cc1468da177	4714	*/
<>	161:2cc1468da177	4715
<>	161:2cc1468da177	4716	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	4717	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
<>	161:2cc1468da177	4718	* @{
<>	161:2cc1468da177	4719	*/
<>	161:2cc1468da177	4720
<>	161:2cc1468da177	4721	/* Initialization of some features of ADC common parameters and multimode */
<>	161:2cc1468da177	4722	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
<>	161:2cc1468da177	4723	ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef ADCxy_COMMON, LL_ADC_CommonInitTypeDef ADC_CommonInitStruct);
<>	161:2cc1468da177	4724	void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
<>	161:2cc1468da177	4725
<>	161:2cc1468da177	4726	/* De-initialization of ADC instance, ADC group regular and ADC group injected */
<>	161:2cc1468da177	4727	/* (availability of ADC group injected depends on STM32 families) */
<>	161:2cc1468da177	4728	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
<>	161:2cc1468da177	4729
<>	161:2cc1468da177	4730	/* Initialization of some features of ADC instance */
<>	161:2cc1468da177	4731	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
<>	161:2cc1468da177	4732	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
<>	161:2cc1468da177	4733
<>	161:2cc1468da177	4734	/* Initialization of some features of ADC instance and ADC group regular */
<>	161:2cc1468da177	4735	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
<>	161:2cc1468da177	4736	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
<>	161:2cc1468da177	4737
<>	161:2cc1468da177	4738	/* Initialization of some features of ADC instance and ADC group injected */
<>	161:2cc1468da177	4739	ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef ADCx, LL_ADC_INJ_InitTypeDef ADC_INJ_InitStruct);
<>	161:2cc1468da177	4740	void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
<>	161:2cc1468da177	4741
<>	161:2cc1468da177	4742	/**
<>	161:2cc1468da177	4743	* @}
<>	161:2cc1468da177	4744	*/
<>	161:2cc1468da177	4745	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	4746
<>	161:2cc1468da177	4747	/**
<>	161:2cc1468da177	4748	* @}
<>	161:2cc1468da177	4749	*/
<>	161:2cc1468da177	4750
<>	161:2cc1468da177	4751	/**
<>	161:2cc1468da177	4752	* @}
<>	161:2cc1468da177	4753	*/
<>	161:2cc1468da177	4754
<>	161:2cc1468da177	4755	#endif /* ADC1 \|\| ADC2 \|\| ADC3 */
<>	161:2cc1468da177	4756
<>	161:2cc1468da177	4757	/**
<>	161:2cc1468da177	4758	* @}
<>	161:2cc1468da177	4759	*/
<>	161:2cc1468da177	4760
<>	161:2cc1468da177	4761	#ifdef __cplusplus
<>	161:2cc1468da177	4762	}
<>	161:2cc1468da177	4763	#endif
<>	161:2cc1468da177	4764
<>	161:2cc1468da177	4765	#endif /* __STM32F7xx_LL_ADC_H */
<>	161:2cc1468da177	4766
<>	161:2cc1468da177	4767	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/