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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
161:2cc1468da177
Child:
168:9672193075cf
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_tim_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of TIM HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_TIM_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_TIM_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup TIMEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup TIMEx_Exported_Types TIM Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief TIM Hall sensor Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t IC1Filter; /*!< Specifies the input capture filter.
<> 144:ef7eb2e8f9f7 76 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 77 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 144:ef7eb2e8f9f7 78 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 79 } TIM_HallSensor_InitTypeDef;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /**
<> 144:ef7eb2e8f9f7 82 * @brief TIM Master configuration Structure definition
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 typedef struct {
<> 144:ef7eb2e8f9f7 85 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref TIM_Master_Mode_Selection */
<> 144:ef7eb2e8f9f7 87 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
<> 144:ef7eb2e8f9f7 89 uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
<> 144:ef7eb2e8f9f7 90 This parameter can be a value of @ref TIM_Master_Slave_Mode */
<> 144:ef7eb2e8f9f7 91 }TIM_MasterConfigTypeDef;
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @brief TIM Break input(s) and Dead time configuration Structure definition
<> 144:ef7eb2e8f9f7 95 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
<> 144:ef7eb2e8f9f7 96 * filter and polarity.
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98 typedef struct
<> 144:ef7eb2e8f9f7 99 {
<> 144:ef7eb2e8f9f7 100 uint32_t OffStateRunMode; /*!< TIM off state in run mode.
<> 144:ef7eb2e8f9f7 101 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
<> 144:ef7eb2e8f9f7 102 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
<> 144:ef7eb2e8f9f7 103 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
<> 144:ef7eb2e8f9f7 104 uint32_t LockLevel; /*!< TIM Lock level.
<> 144:ef7eb2e8f9f7 105 This parameter can be a value of @ref TIM_Lock_level */
<> 144:ef7eb2e8f9f7 106 uint32_t DeadTime; /*!< TIM dead Time.
<> 144:ef7eb2e8f9f7 107 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<> 144:ef7eb2e8f9f7 108 uint32_t BreakState; /*!< TIM Break State.
<> 144:ef7eb2e8f9f7 109 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
<> 144:ef7eb2e8f9f7 110 uint32_t BreakPolarity; /*!< TIM Break input polarity.
<> 144:ef7eb2e8f9f7 111 This parameter can be a value of @ref TIM_Break_Polarity */
<> 144:ef7eb2e8f9f7 112 uint32_t BreakFilter; /*!< Specifies the break input filter.
<> 144:ef7eb2e8f9f7 113 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 114 uint32_t Break2State; /*!< TIM Break2 State
<> 144:ef7eb2e8f9f7 115 This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
<> 144:ef7eb2e8f9f7 116 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
<> 144:ef7eb2e8f9f7 117 This parameter can be a value of @ref TIMEx_Break2_Polarity */
<> 144:ef7eb2e8f9f7 118 uint32_t Break2Filter; /*!< TIM break2 input filter.
<> 144:ef7eb2e8f9f7 119 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 144:ef7eb2e8f9f7 120 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
<> 144:ef7eb2e8f9f7 121 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
<> 144:ef7eb2e8f9f7 122 } TIM_BreakDeadTimeConfigTypeDef;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @brief TIM Break/Break2 input configuration
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 typedef struct {
<> 144:ef7eb2e8f9f7 129 uint32_t Source; /*!< Specifies the source of the timer break input.
<> 144:ef7eb2e8f9f7 130 This parameter can be a value of @ref TIMEx_Break_Input_Source */
<> 144:ef7eb2e8f9f7 131 uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
<> 144:ef7eb2e8f9f7 132 This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
<> 144:ef7eb2e8f9f7 133 } TIMEx_BreakInputConfigTypeDef;
<> 144:ef7eb2e8f9f7 134 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @}
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /** @defgroup TIMEx_Channel TIMEx Channel
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 #define TIM_CHANNEL_1 ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 148 #define TIM_CHANNEL_2 ((uint32_t)0x0004U)
<> 144:ef7eb2e8f9f7 149 #define TIM_CHANNEL_3 ((uint32_t)0x0008U)
<> 144:ef7eb2e8f9f7 150 #define TIM_CHANNEL_4 ((uint32_t)0x000CU)
<> 144:ef7eb2e8f9f7 151 #define TIM_CHANNEL_5 ((uint32_t)0x0010U)
<> 144:ef7eb2e8f9f7 152 #define TIM_CHANNEL_6 ((uint32_t)0x0014U)
<> 144:ef7eb2e8f9f7 153 #define TIM_CHANNEL_ALL ((uint32_t)0x003CU)
<> 161:2cc1468da177 154
<> 144:ef7eb2e8f9f7 155 /**
<> 144:ef7eb2e8f9f7 156 * @}
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes
<> 144:ef7eb2e8f9f7 160 * @{
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162 #define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 163 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 164 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 165 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 166 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
<> 144:ef7eb2e8f9f7 167 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 168 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 169 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
<> 144:ef7eb2e8f9f7 172 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
<> 144:ef7eb2e8f9f7 173 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 174 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 175 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
<> 144:ef7eb2e8f9f7 176 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /** @defgroup TIMEx_Remap TIMEx Remap
<> 144:ef7eb2e8f9f7 182 * @{
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184 #define TIM_TIM2_TIM8_TRGO (0x00000000U)
<> 144:ef7eb2e8f9f7 185 #define TIM_TIM2_ETH_PTP (0x00000400U)
<> 144:ef7eb2e8f9f7 186 #define TIM_TIM2_USBFS_SOF (0x00000800U)
<> 144:ef7eb2e8f9f7 187 #define TIM_TIM2_USBHS_SOF (0x00000C00U)
<> 144:ef7eb2e8f9f7 188 #define TIM_TIM5_GPIO (0x00000000U)
<> 144:ef7eb2e8f9f7 189 #define TIM_TIM5_LSI (0x00000040U)
<> 144:ef7eb2e8f9f7 190 #define TIM_TIM5_LSE (0x00000080U)
<> 144:ef7eb2e8f9f7 191 #define TIM_TIM5_RTC (0x000000C0U)
<> 144:ef7eb2e8f9f7 192 #define TIM_TIM11_GPIO (0x00000000U)
<> 144:ef7eb2e8f9f7 193 #define TIM_TIM11_SPDIFRX (0x00000001U)
<> 144:ef7eb2e8f9f7 194 #define TIM_TIM11_HSE (0x00000002U)
<> 144:ef7eb2e8f9f7 195 #define TIM_TIM11_MCO1 (0x00000003U)
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @}
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source
<> 144:ef7eb2e8f9f7 201 * @{
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
<> 144:ef7eb2e8f9f7 204 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 205 /**
<> 144:ef7eb2e8f9f7 206 * @}
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable
<> 144:ef7eb2e8f9f7 210 * @{
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 213 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @}
<> 144:ef7eb2e8f9f7 216 */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity
<> 144:ef7eb2e8f9f7 219 * @{
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 222 #define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #define TIM_GROUPCH5_NONE ((uint32_t)0x00000000U) /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
<> 144:ef7eb2e8f9f7 231 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
<> 144:ef7eb2e8f9f7 232 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
<> 144:ef7eb2e8f9f7 233 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2)
<> 144:ef7eb2e8f9f7 239 * @{
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 #define TIM_TRGO2_RESET ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 242 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 243 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 244 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 245 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
<> 144:ef7eb2e8f9f7 246 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 247 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 248 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 249 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
<> 144:ef7eb2e8f9f7 250 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 251 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 252 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 253 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
<> 144:ef7eb2e8f9f7 254 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 255 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
<> 144:ef7eb2e8f9f7 256 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @}
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode
<> 144:ef7eb2e8f9f7 262 * @{
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
<> 144:ef7eb2e8f9f7 265 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
<> 144:ef7eb2e8f9f7 266 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 267 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
<> 144:ef7eb2e8f9f7 268 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
<> 144:ef7eb2e8f9f7 269 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @}
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 #if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 274 /** @defgroup TIMEx_Break_Input TIM Extended Break input
<> 144:ef7eb2e8f9f7 275 * @{
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 #define TIM_BREAKINPUT_BRK ((uint32_t)0x00000001U) /* !< Timer break input */
<> 144:ef7eb2e8f9f7 278 #define TIM_BREAKINPUT_BRK2 ((uint32_t)0x00000002U) /* !< Timer break2 input */
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
<> 144:ef7eb2e8f9f7 287 #define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @}
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
<> 144:ef7eb2e8f9f7 293 * @{
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 #define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) /* !< Break input source is disabled */
<> 144:ef7eb2e8f9f7 296 #define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)0x00000001U) /* !< Break input source is enabled */
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @}
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 310 /** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros
<> 144:ef7eb2e8f9f7 311 * @{
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Sets the TIM Capture Compare Register value on runtime without
<> 144:ef7eb2e8f9f7 316 * calling another time ConfigChannel function.
<> 144:ef7eb2e8f9f7 317 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 318 * @param __CHANNEL__ : TIM Channels to be configured.
<> 144:ef7eb2e8f9f7 319 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 320 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 321 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 322 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 323 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 324 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 144:ef7eb2e8f9f7 325 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 144:ef7eb2e8f9f7 326 * @param __COMPARE__: specifies the Capture Compare register new value.
<> 144:ef7eb2e8f9f7 327 * @retval None
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<> 144:ef7eb2e8f9f7 330 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 331 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 332 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 333 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 334 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
<> 144:ef7eb2e8f9f7 335 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Gets the TIM Capture Compare Register value on runtime
<> 144:ef7eb2e8f9f7 339 * @param __HANDLE__: TIM handle.
<> 144:ef7eb2e8f9f7 340 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
<> 144:ef7eb2e8f9f7 341 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 342 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
<> 144:ef7eb2e8f9f7 343 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
<> 144:ef7eb2e8f9f7 344 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
<> 144:ef7eb2e8f9f7 345 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
<> 144:ef7eb2e8f9f7 346 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
<> 144:ef7eb2e8f9f7 347 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
<> 144:ef7eb2e8f9f7 348 * @retval None
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 351 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
<> 144:ef7eb2e8f9f7 352 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
<> 144:ef7eb2e8f9f7 353 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
<> 144:ef7eb2e8f9f7 354 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
<> 144:ef7eb2e8f9f7 355 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
<> 144:ef7eb2e8f9f7 356 ((__HANDLE__)->Instance->CCR6))
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /**
<> 161:2cc1468da177 359 * @brief Sets the TIM Output compare preload.
<> 161:2cc1468da177 360 * @param __HANDLE__: TIM handle.
<> 161:2cc1468da177 361 * @param __CHANNEL__: TIM Channels to be configured.
<> 161:2cc1468da177 362 * This parameter can be one of the following values:
<> 161:2cc1468da177 363 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 161:2cc1468da177 364 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 161:2cc1468da177 365 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 161:2cc1468da177 366 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 161:2cc1468da177 367 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 161:2cc1468da177 368 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 161:2cc1468da177 369 * @retval None
<> 161:2cc1468da177 370 */
<> 161:2cc1468da177 371 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<> 161:2cc1468da177 372 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
<> 161:2cc1468da177 373 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
<> 161:2cc1468da177 374 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
<> 161:2cc1468da177 375 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
<> 161:2cc1468da177 376 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
<> 161:2cc1468da177 377 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
<> 161:2cc1468da177 378
<> 161:2cc1468da177 379 /**
<> 161:2cc1468da177 380 * @brief Resets the TIM Output compare preload.
<> 161:2cc1468da177 381 * @param __HANDLE__: TIM handle.
<> 161:2cc1468da177 382 * @param __CHANNEL__: TIM Channels to be configured.
<> 161:2cc1468da177 383 * This parameter can be one of the following values:
<> 161:2cc1468da177 384 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 161:2cc1468da177 385 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 161:2cc1468da177 386 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 161:2cc1468da177 387 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 161:2cc1468da177 388 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 161:2cc1468da177 389 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 161:2cc1468da177 390 * @retval None
<> 161:2cc1468da177 391 */
<> 161:2cc1468da177 392 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
<> 161:2cc1468da177 393 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
<> 161:2cc1468da177 394 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
<> 161:2cc1468da177 395 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
<> 161:2cc1468da177 396 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
<> 161:2cc1468da177 397 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
<> 161:2cc1468da177 398 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
<> 161:2cc1468da177 399
<> 161:2cc1468da177 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 405 /** @addtogroup TIMEx_Exported_Functions
<> 144:ef7eb2e8f9f7 406 * @{
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /** @addtogroup TIMEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 410 * @{
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412 /* Timer Hall Sensor functions **********************************************/
<> 144:ef7eb2e8f9f7 413 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
<> 144:ef7eb2e8f9f7 414 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 417 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 420 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 421 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 422 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 423 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 424 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 425 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 426 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 427 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @}
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /** @addtogroup TIMEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 433 * @{
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 /* Timer Complementary Output Compare functions *****************************/
<> 144:ef7eb2e8f9f7 436 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 437 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 438 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 441 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 442 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 445 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 446 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /** @addtogroup TIMEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 452 * @{
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454 /* Timer Complementary PWM functions ****************************************/
<> 144:ef7eb2e8f9f7 455 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 456 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 457 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 460 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 461 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 462 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 463 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 144:ef7eb2e8f9f7 464 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @addtogroup TIMEx_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 470 * @{
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 /* Timer Complementary One Pulse functions **********************************/
<> 144:ef7eb2e8f9f7 473 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 474 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 475 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 478 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 479 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /** @addtogroup TIMEx_Exported_Functions_Group5
<> 144:ef7eb2e8f9f7 485 * @{
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487 /* Extension Control functions ************************************************/
<> 144:ef7eb2e8f9f7 488 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
<> 144:ef7eb2e8f9f7 489 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
<> 144:ef7eb2e8f9f7 491 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
<> 144:ef7eb2e8f9f7 492 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
<> 144:ef7eb2e8f9f7 493 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 494 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
<> 144:ef7eb2e8f9f7 495 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
<> 144:ef7eb2e8f9f7 497 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef);
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @}
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /** @addtogroup TIMEx_Exported_Functions_Group6
<> 144:ef7eb2e8f9f7 503 * @{
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 /* Extension Callback *********************************************************/
<> 144:ef7eb2e8f9f7 506 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 507 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 508 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @}
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /** @addtogroup TIMEx_Exported_Functions_Group7
<> 144:ef7eb2e8f9f7 514 * @{
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516 /* Extension Peripheral State functions **************************************/
<> 144:ef7eb2e8f9f7 517 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @}
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /**
<> 144:ef7eb2e8f9f7 523 * @}
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 527 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 528 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 529 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 530 /** @defgroup TIMEx_Private_Macros TIMEx Private Macros
<> 144:ef7eb2e8f9f7 531 * @{
<> 144:ef7eb2e8f9f7 532 */
<> 144:ef7eb2e8f9f7 533 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 534 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 535 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 536 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 537 ((CHANNEL) == TIM_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 538 ((CHANNEL) == TIM_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 539 ((CHANNEL) == TIM_CHANNEL_ALL))
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 542 ((CHANNEL) == TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 545 ((CHANNEL) == TIM_CHANNEL_2))
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 548 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 549 ((CHANNEL) == TIM_CHANNEL_3))
<> 144:ef7eb2e8f9f7 550 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
<> 144:ef7eb2e8f9f7 551 ((MODE) == TIM_OCMODE_PWM2) || \
<> 144:ef7eb2e8f9f7 552 ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
<> 144:ef7eb2e8f9f7 553 ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
<> 144:ef7eb2e8f9f7 554 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
<> 144:ef7eb2e8f9f7 555 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
<> 144:ef7eb2e8f9f7 558 ((MODE) == TIM_OCMODE_ACTIVE) || \
<> 144:ef7eb2e8f9f7 559 ((MODE) == TIM_OCMODE_INACTIVE) || \
<> 144:ef7eb2e8f9f7 560 ((MODE) == TIM_OCMODE_TOGGLE) || \
<> 144:ef7eb2e8f9f7 561 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
<> 144:ef7eb2e8f9f7 562 ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
<> 144:ef7eb2e8f9f7 563 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
<> 144:ef7eb2e8f9f7 564 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
<> 144:ef7eb2e8f9f7 565 #define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
<> 144:ef7eb2e8f9f7 566 ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\
<> 144:ef7eb2e8f9f7 567 ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
<> 144:ef7eb2e8f9f7 568 ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
<> 144:ef7eb2e8f9f7 569 ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\
<> 144:ef7eb2e8f9f7 570 ((__TIM_REMAP__) == TIM_TIM5_LSI)||\
<> 144:ef7eb2e8f9f7 571 ((__TIM_REMAP__) == TIM_TIM5_LSE)||\
<> 144:ef7eb2e8f9f7 572 ((__TIM_REMAP__) == TIM_TIM5_RTC)||\
<> 144:ef7eb2e8f9f7 573 ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\
<> 144:ef7eb2e8f9f7 574 ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\
<> 144:ef7eb2e8f9f7 575 ((__TIM_REMAP__) == TIM_TIM11_HSE)||\
<> 144:ef7eb2e8f9f7 576 ((__TIM_REMAP__) == TIM_TIM11_MCO1))
<> 144:ef7eb2e8f9f7 577 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF)
<> 144:ef7eb2e8f9f7 578 #define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF)
<> 144:ef7eb2e8f9f7 579 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
<> 144:ef7eb2e8f9f7 580 ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
<> 144:ef7eb2e8f9f7 581 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
<> 144:ef7eb2e8f9f7 582 ((STATE) == TIM_BREAK2_DISABLE))
<> 144:ef7eb2e8f9f7 583 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 584 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 585 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
<> 144:ef7eb2e8f9f7 586 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
<> 144:ef7eb2e8f9f7 587 ((SOURCE) == TIM_TRGO2_ENABLE) || \
<> 144:ef7eb2e8f9f7 588 ((SOURCE) == TIM_TRGO2_UPDATE) || \
<> 144:ef7eb2e8f9f7 589 ((SOURCE) == TIM_TRGO2_OC1) || \
<> 144:ef7eb2e8f9f7 590 ((SOURCE) == TIM_TRGO2_OC1REF) || \
<> 144:ef7eb2e8f9f7 591 ((SOURCE) == TIM_TRGO2_OC2REF) || \
<> 144:ef7eb2e8f9f7 592 ((SOURCE) == TIM_TRGO2_OC3REF) || \
<> 144:ef7eb2e8f9f7 593 ((SOURCE) == TIM_TRGO2_OC3REF) || \
<> 144:ef7eb2e8f9f7 594 ((SOURCE) == TIM_TRGO2_OC4REF) || \
<> 144:ef7eb2e8f9f7 595 ((SOURCE) == TIM_TRGO2_OC5REF) || \
<> 144:ef7eb2e8f9f7 596 ((SOURCE) == TIM_TRGO2_OC6REF) || \
<> 144:ef7eb2e8f9f7 597 ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
<> 144:ef7eb2e8f9f7 598 ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
<> 144:ef7eb2e8f9f7 599 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
<> 144:ef7eb2e8f9f7 600 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
<> 144:ef7eb2e8f9f7 601 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
<> 144:ef7eb2e8f9f7 602 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
<> 144:ef7eb2e8f9f7 603 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 604 ((MODE) == TIM_SLAVEMODE_RESET) || \
<> 144:ef7eb2e8f9f7 605 ((MODE) == TIM_SLAVEMODE_GATED) || \
<> 144:ef7eb2e8f9f7 606 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
<> 144:ef7eb2e8f9f7 607 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
<> 144:ef7eb2e8f9f7 608 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 611 #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
<> 144:ef7eb2e8f9f7 612 ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
<> 144:ef7eb2e8f9f7 615 ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
<> 144:ef7eb2e8f9f7 618 ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @}
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 626 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<> 144:ef7eb2e8f9f7 627 * @{
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /**
<> 144:ef7eb2e8f9f7 631 * @}
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /**
<> 144:ef7eb2e8f9f7 635 * @}
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /**
<> 144:ef7eb2e8f9f7 639 * @}
<> 144:ef7eb2e8f9f7 640 */
<> 144:ef7eb2e8f9f7 641
<> 144:ef7eb2e8f9f7 642 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644 #endif
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 #endif /* __STM32F7xx_HAL_TIM_EX_H */
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/