mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
161:2cc1468da177
Child:
168:9672193075cf
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
<> 144:ef7eb2e8f9f7 15 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 16 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 17 @verbatim
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 20 ==============================================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 The Timer Extension features include:
<> 144:ef7eb2e8f9f7 23 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 24 (++) Input Capture
<> 144:ef7eb2e8f9f7 25 (++) Output Compare
<> 144:ef7eb2e8f9f7 26 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 27 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 28 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 29 interconnect several timers together.
<> 144:ef7eb2e8f9f7 30 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 31 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 32 positioning purposes
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 [..]
<> 144:ef7eb2e8f9f7 37 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 38 depending from feature used :
<> 144:ef7eb2e8f9f7 39 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 40 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 41 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 42 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 (#) Initialize the TIM low level resources :
<> 157:ff67d9f36b67 45 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 46 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 47 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 157:ff67d9f36b67 48 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 49 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 52 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 53 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 54 any start function.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 57 initialization function of this driver:
<> 144:ef7eb2e8f9f7 58 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 59 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 60 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 61 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 62 the commutation event).
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 65 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
<> 144:ef7eb2e8f9f7 66 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 67 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 68 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 @endverbatim
<> 144:ef7eb2e8f9f7 72 ******************************************************************************
<> 144:ef7eb2e8f9f7 73 * @attention
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 78 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 79 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 80 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 81 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 82 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 83 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 85 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 86 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 87 *
<> 144:ef7eb2e8f9f7 88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 98 *
<> 144:ef7eb2e8f9f7 99 ******************************************************************************
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 110 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 #define BDTR_BKF_SHIFT (16)
<> 144:ef7eb2e8f9f7 119 #define BDTR_BK2F_SHIFT (20)
<> 144:ef7eb2e8f9f7 120 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 127 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 128 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @}
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 139 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 @verbatim
<> 144:ef7eb2e8f9f7 142 ==============================================================================
<> 144:ef7eb2e8f9f7 143 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 144 ==============================================================================
<> 144:ef7eb2e8f9f7 145 [..]
<> 144:ef7eb2e8f9f7 146 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 147 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 148 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 149 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 150 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 151 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 152 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 153 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 154 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 @endverbatim
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 161 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 162 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 163 * @param sConfig: TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 164 * @retval HAL status
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 171 if(htim == NULL)
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 177 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 178 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 161:2cc1468da177 179 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 180 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 181 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 182 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 185 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 188 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 191 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 194 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 197 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 198 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 199 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 202 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 205 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 206 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 209 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 210 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 213 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 214 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 215 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 216 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 217 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 218 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 219 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 224 register to 101 */
<> 144:ef7eb2e8f9f7 225 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 226 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 229 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 return HAL_OK;
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 236 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 237 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 238 * @retval HAL status
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 /* Check the parameters */
<> 144:ef7eb2e8f9f7 243 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 248 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 251 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Change TIM state */
<> 144:ef7eb2e8f9f7 254 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Release Lock */
<> 144:ef7eb2e8f9f7 257 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 return HAL_OK;
<> 144:ef7eb2e8f9f7 260 }
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 264 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 265 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 266 * @retval None
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 271 UNUSED(htim);
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 274 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 280 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 281 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 282 * @retval None
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 287 UNUSED(htim);
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 290 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 296 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 297 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 298 * @retval HAL status
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 /* Check the parameters */
<> 144:ef7eb2e8f9f7 303 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 306 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 307 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 310 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Return function status */
<> 144:ef7eb2e8f9f7 313 return HAL_OK;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 318 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 319 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 320 * @retval HAL status
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Check the parameters */
<> 144:ef7eb2e8f9f7 325 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 328 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 329 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 332 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Return function status */
<> 144:ef7eb2e8f9f7 335 return HAL_OK;
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 340 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 341 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 342 * @retval HAL status
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 345 {
<> 144:ef7eb2e8f9f7 346 /* Check the parameters */
<> 144:ef7eb2e8f9f7 347 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 350 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 353 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 354 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 357 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Return function status */
<> 144:ef7eb2e8f9f7 360 return HAL_OK;
<> 144:ef7eb2e8f9f7 361 }
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 366 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 367 * @retval HAL status
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 /* Check the parameters */
<> 144:ef7eb2e8f9f7 372 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 375 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 376 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 379 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 382 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /* Return function status */
<> 144:ef7eb2e8f9f7 385 return HAL_OK;
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 390 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 391 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 392 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 393 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 394 * @retval HAL status
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 /* Check the parameters */
<> 144:ef7eb2e8f9f7 399 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411 else
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 417 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 418 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 421 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 422 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 423 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Enable the DMA Stream for Capture 1*/
<> 144:ef7eb2e8f9f7 426 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 429 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 432 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 /* Return function status */
<> 144:ef7eb2e8f9f7 435 return HAL_OK;
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 440 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 441 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 442 * @retval HAL status
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 /* Check the parameters */
<> 144:ef7eb2e8f9f7 447 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 450 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 451 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 455 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 458 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /* Return function status */
<> 144:ef7eb2e8f9f7 461 return HAL_OK;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @}
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 469 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 470 *
<> 144:ef7eb2e8f9f7 471 @verbatim
<> 144:ef7eb2e8f9f7 472 ==============================================================================
<> 144:ef7eb2e8f9f7 473 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 474 ==============================================================================
<> 144:ef7eb2e8f9f7 475 [..]
<> 144:ef7eb2e8f9f7 476 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 477 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 478 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 479 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 480 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 481 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 482 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 @endverbatim
<> 144:ef7eb2e8f9f7 485 * @{
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /**
<> 144:ef7eb2e8f9f7 489 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 490 * output.
<> 144:ef7eb2e8f9f7 491 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 492 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 493 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 494 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 495 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 496 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 497 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 498 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 499 * @retval HAL status
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 /* Check the parameters */
<> 144:ef7eb2e8f9f7 504 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 507 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 510 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 513 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Return function status */
<> 144:ef7eb2e8f9f7 516 return HAL_OK;
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /**
<> 144:ef7eb2e8f9f7 520 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 521 * output.
<> 144:ef7eb2e8f9f7 522 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 523 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 524 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 525 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 526 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 527 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 528 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 529 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 530 * @retval HAL status
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 /* Check the parameters */
<> 144:ef7eb2e8f9f7 535 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 538 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 541 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 544 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Return function status */
<> 144:ef7eb2e8f9f7 547 return HAL_OK;
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 552 * on the complementary output.
<> 144:ef7eb2e8f9f7 553 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 554 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 555 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 556 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 557 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 558 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 559 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 560 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 561 * @retval HAL status
<> 144:ef7eb2e8f9f7 562 */
<> 144:ef7eb2e8f9f7 563 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 /* Check the parameters */
<> 144:ef7eb2e8f9f7 566 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 switch (Channel)
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 573 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 break;
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 580 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582 break;
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 587 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 break;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 594 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 break;
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 default:
<> 144:ef7eb2e8f9f7 599 break;
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 603 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 606 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 609 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 612 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 /* Return function status */
<> 144:ef7eb2e8f9f7 615 return HAL_OK;
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /**
<> 144:ef7eb2e8f9f7 619 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 620 * on the complementary output.
<> 144:ef7eb2e8f9f7 621 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 622 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 623 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 624 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 625 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 626 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 627 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 628 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 629 * @retval HAL status
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Check the parameters */
<> 144:ef7eb2e8f9f7 636 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 switch (Channel)
<> 144:ef7eb2e8f9f7 639 {
<> 144:ef7eb2e8f9f7 640 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 643 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 644 }
<> 144:ef7eb2e8f9f7 645 break;
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 650 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652 break;
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 657 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659 break;
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 664 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 665 }
<> 144:ef7eb2e8f9f7 666 break;
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 default:
<> 144:ef7eb2e8f9f7 669 break;
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 673 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 676 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 677 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 683 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 686 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /* Return function status */
<> 144:ef7eb2e8f9f7 689 return HAL_OK;
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 /**
<> 144:ef7eb2e8f9f7 693 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 694 * on the complementary output.
<> 144:ef7eb2e8f9f7 695 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 696 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 697 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 698 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 699 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 700 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 701 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 702 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 703 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 704 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 705 * @retval HAL status
<> 144:ef7eb2e8f9f7 706 */
<> 144:ef7eb2e8f9f7 707 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 708 {
<> 144:ef7eb2e8f9f7 709 /* Check the parameters */
<> 144:ef7eb2e8f9f7 710 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722 else
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727 switch (Channel)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 732 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 735 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 738 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 741 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743 break;
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 748 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 751 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 754 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 757 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 758 }
<> 144:ef7eb2e8f9f7 759 break;
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 762 {
<> 144:ef7eb2e8f9f7 763 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 764 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 767 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 770 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 773 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775 break;
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 778 {
<> 144:ef7eb2e8f9f7 779 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 780 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 783 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 786 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 789 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 break;
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 default:
<> 144:ef7eb2e8f9f7 794 break;
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 798 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 801 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 804 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Return function status */
<> 144:ef7eb2e8f9f7 807 return HAL_OK;
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 /**
<> 144:ef7eb2e8f9f7 811 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 812 * on the complementary output.
<> 144:ef7eb2e8f9f7 813 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 814 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 815 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 816 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 817 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 818 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 819 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 820 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 821 * @retval HAL status
<> 144:ef7eb2e8f9f7 822 */
<> 144:ef7eb2e8f9f7 823 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 /* Check the parameters */
<> 144:ef7eb2e8f9f7 826 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 switch (Channel)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 831 {
<> 144:ef7eb2e8f9f7 832 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 833 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 break;
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 840 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 break;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 847 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 break;
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 854 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856 break;
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 default:
<> 144:ef7eb2e8f9f7 859 break;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 863 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 866 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 869 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* Change the htim state */
<> 144:ef7eb2e8f9f7 872 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 /* Return function status */
<> 144:ef7eb2e8f9f7 875 return HAL_OK;
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @}
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 883 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 884 *
<> 144:ef7eb2e8f9f7 885 @verbatim
<> 144:ef7eb2e8f9f7 886 ==============================================================================
<> 144:ef7eb2e8f9f7 887 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 888 ==============================================================================
<> 144:ef7eb2e8f9f7 889 [..]
<> 144:ef7eb2e8f9f7 890 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 891 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 892 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 893 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 894 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 895 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 896 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 897 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 898 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 899 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 900 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 901 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 902 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 903 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 904 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 905 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 906 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 @endverbatim
<> 144:ef7eb2e8f9f7 909 * @{
<> 144:ef7eb2e8f9f7 910 */
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /**
<> 144:ef7eb2e8f9f7 913 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 914 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 915 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 916 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 917 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 918 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 919 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 920 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 921 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 922 * @retval HAL status
<> 144:ef7eb2e8f9f7 923 */
<> 144:ef7eb2e8f9f7 924 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 /* Check the parameters */
<> 144:ef7eb2e8f9f7 927 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 930 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 933 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 936 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Return function status */
<> 144:ef7eb2e8f9f7 939 return HAL_OK;
<> 144:ef7eb2e8f9f7 940 }
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /**
<> 144:ef7eb2e8f9f7 943 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 944 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 945 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 946 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 947 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 948 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 949 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 950 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 951 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 952 * @retval HAL status
<> 144:ef7eb2e8f9f7 953 */
<> 144:ef7eb2e8f9f7 954 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 955 {
<> 144:ef7eb2e8f9f7 956 /* Check the parameters */
<> 144:ef7eb2e8f9f7 957 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 960 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 961
<> 144:ef7eb2e8f9f7 962 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 963 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 966 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /* Return function status */
<> 144:ef7eb2e8f9f7 969 return HAL_OK;
<> 144:ef7eb2e8f9f7 970 }
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /**
<> 144:ef7eb2e8f9f7 973 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 974 * complementary output.
<> 144:ef7eb2e8f9f7 975 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 976 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 977 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 978 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 979 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 980 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 981 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 982 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 983 * @retval HAL status
<> 144:ef7eb2e8f9f7 984 */
<> 144:ef7eb2e8f9f7 985 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Check the parameters */
<> 144:ef7eb2e8f9f7 988 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 switch (Channel)
<> 144:ef7eb2e8f9f7 991 {
<> 144:ef7eb2e8f9f7 992 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 995 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 996 }
<> 144:ef7eb2e8f9f7 997 break;
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1002 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004 break;
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1007 {
<> 144:ef7eb2e8f9f7 1008 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1009 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1010 }
<> 144:ef7eb2e8f9f7 1011 break;
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1014 {
<> 144:ef7eb2e8f9f7 1015 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1016 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 break;
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 default:
<> 144:ef7eb2e8f9f7 1021 break;
<> 144:ef7eb2e8f9f7 1022 }
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1025 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1028 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1031 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1034 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /* Return function status */
<> 144:ef7eb2e8f9f7 1037 return HAL_OK;
<> 144:ef7eb2e8f9f7 1038 }
<> 144:ef7eb2e8f9f7 1039
<> 144:ef7eb2e8f9f7 1040 /**
<> 144:ef7eb2e8f9f7 1041 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1042 * complementary output.
<> 144:ef7eb2e8f9f7 1043 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1044 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1045 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1046 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1047 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1048 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1049 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1050 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1051 * @retval HAL status
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1058 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 switch (Channel)
<> 144:ef7eb2e8f9f7 1061 {
<> 144:ef7eb2e8f9f7 1062 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1063 {
<> 144:ef7eb2e8f9f7 1064 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1065 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1066 }
<> 144:ef7eb2e8f9f7 1067 break;
<> 144:ef7eb2e8f9f7 1068
<> 144:ef7eb2e8f9f7 1069 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1070 {
<> 144:ef7eb2e8f9f7 1071 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1072 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074 break;
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1077 {
<> 144:ef7eb2e8f9f7 1078 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1079 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081 break;
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1086 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1087 }
<> 144:ef7eb2e8f9f7 1088 break;
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 default:
<> 144:ef7eb2e8f9f7 1091 break;
<> 144:ef7eb2e8f9f7 1092 }
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1095 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1098 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1099 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1100 {
<> 144:ef7eb2e8f9f7 1101 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1102 }
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1105 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1108 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 /* Return function status */
<> 144:ef7eb2e8f9f7 1111 return HAL_OK;
<> 144:ef7eb2e8f9f7 1112 }
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 /**
<> 144:ef7eb2e8f9f7 1115 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1116 * complementary output
<> 144:ef7eb2e8f9f7 1117 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1118 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1119 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1120 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1121 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1122 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1123 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1124 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1125 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1126 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1127 * @retval HAL status
<> 144:ef7eb2e8f9f7 1128 */
<> 144:ef7eb2e8f9f7 1129 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1130 {
<> 144:ef7eb2e8f9f7 1131 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1132 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1135 {
<> 144:ef7eb2e8f9f7 1136 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1137 }
<> 144:ef7eb2e8f9f7 1138 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1139 {
<> 144:ef7eb2e8f9f7 1140 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1141 {
<> 144:ef7eb2e8f9f7 1142 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144 else
<> 144:ef7eb2e8f9f7 1145 {
<> 144:ef7eb2e8f9f7 1146 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149 switch (Channel)
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1152 {
<> 144:ef7eb2e8f9f7 1153 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1154 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1157 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1160 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1163 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1164 }
<> 144:ef7eb2e8f9f7 1165 break;
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1168 {
<> 144:ef7eb2e8f9f7 1169 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1170 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1173 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1174
<> 144:ef7eb2e8f9f7 1175 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1176 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1179 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1180 }
<> 144:ef7eb2e8f9f7 1181 break;
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1184 {
<> 144:ef7eb2e8f9f7 1185 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1186 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1189 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1192 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1195 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1196 }
<> 144:ef7eb2e8f9f7 1197 break;
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1200 {
<> 144:ef7eb2e8f9f7 1201 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1202 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1205 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1208 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1211 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1212 }
<> 144:ef7eb2e8f9f7 1213 break;
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 default:
<> 144:ef7eb2e8f9f7 1216 break;
<> 144:ef7eb2e8f9f7 1217 }
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1220 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1223 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1226 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /* Return function status */
<> 144:ef7eb2e8f9f7 1229 return HAL_OK;
<> 144:ef7eb2e8f9f7 1230 }
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /**
<> 144:ef7eb2e8f9f7 1233 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1234 * output
<> 144:ef7eb2e8f9f7 1235 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1236 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1237 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1238 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1239 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1240 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1241 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1242 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1243 * @retval HAL status
<> 144:ef7eb2e8f9f7 1244 */
<> 144:ef7eb2e8f9f7 1245 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1246 {
<> 144:ef7eb2e8f9f7 1247 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1248 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1249
<> 144:ef7eb2e8f9f7 1250 switch (Channel)
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1253 {
<> 144:ef7eb2e8f9f7 1254 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1255 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1256 }
<> 144:ef7eb2e8f9f7 1257 break;
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1260 {
<> 144:ef7eb2e8f9f7 1261 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1262 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264 break;
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1267 {
<> 144:ef7eb2e8f9f7 1268 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1269 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1270 }
<> 144:ef7eb2e8f9f7 1271 break;
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1274 {
<> 144:ef7eb2e8f9f7 1275 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1276 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278 break;
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 default:
<> 144:ef7eb2e8f9f7 1281 break;
<> 144:ef7eb2e8f9f7 1282 }
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1285 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1288 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1289
<> 144:ef7eb2e8f9f7 1290 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1291 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1294 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /* Return function status */
<> 144:ef7eb2e8f9f7 1297 return HAL_OK;
<> 144:ef7eb2e8f9f7 1298 }
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 /**
<> 144:ef7eb2e8f9f7 1301 * @}
<> 144:ef7eb2e8f9f7 1302 */
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1305 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1306 *
<> 144:ef7eb2e8f9f7 1307 @verbatim
<> 144:ef7eb2e8f9f7 1308 ==============================================================================
<> 144:ef7eb2e8f9f7 1309 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1310 ==============================================================================
<> 144:ef7eb2e8f9f7 1311 [..]
<> 144:ef7eb2e8f9f7 1312 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1313 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1314 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1315 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1316 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 @endverbatim
<> 144:ef7eb2e8f9f7 1319 * @{
<> 144:ef7eb2e8f9f7 1320 */
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /**
<> 144:ef7eb2e8f9f7 1323 * @brief Starts the TIM One Pulse signal generation on the complemetary
<> 144:ef7eb2e8f9f7 1324 * output.
<> 144:ef7eb2e8f9f7 1325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1326 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1327 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1328 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1329 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1330 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1331 * @retval HAL status
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1334 {
<> 144:ef7eb2e8f9f7 1335 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1336 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1337
<> 144:ef7eb2e8f9f7 1338 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1339 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1340
<> 144:ef7eb2e8f9f7 1341 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1342 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /* Return function status */
<> 144:ef7eb2e8f9f7 1345 return HAL_OK;
<> 144:ef7eb2e8f9f7 1346 }
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 /**
<> 144:ef7eb2e8f9f7 1349 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1350 * output.
<> 144:ef7eb2e8f9f7 1351 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1352 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1353 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1354 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1355 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1356 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1357 * @retval HAL status
<> 144:ef7eb2e8f9f7 1358 */
<> 144:ef7eb2e8f9f7 1359 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1363 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1364
<> 144:ef7eb2e8f9f7 1365 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1366 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1369 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1372 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1373
<> 144:ef7eb2e8f9f7 1374 /* Return function status */
<> 144:ef7eb2e8f9f7 1375 return HAL_OK;
<> 144:ef7eb2e8f9f7 1376 }
<> 144:ef7eb2e8f9f7 1377
<> 144:ef7eb2e8f9f7 1378 /**
<> 144:ef7eb2e8f9f7 1379 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1380 * complementary channel.
<> 144:ef7eb2e8f9f7 1381 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1382 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1383 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1384 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1385 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1386 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1387 * @retval HAL status
<> 144:ef7eb2e8f9f7 1388 */
<> 144:ef7eb2e8f9f7 1389 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1390 {
<> 144:ef7eb2e8f9f7 1391 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1392 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1393
<> 144:ef7eb2e8f9f7 1394 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1395 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1396
<> 144:ef7eb2e8f9f7 1397 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1398 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1401 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1404 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /* Return function status */
<> 144:ef7eb2e8f9f7 1407 return HAL_OK;
<> 144:ef7eb2e8f9f7 1408 }
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /**
<> 144:ef7eb2e8f9f7 1411 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1412 * complementary channel.
<> 144:ef7eb2e8f9f7 1413 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1414 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1415 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1416 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1417 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1418 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1419 * @retval HAL status
<> 144:ef7eb2e8f9f7 1420 */
<> 144:ef7eb2e8f9f7 1421 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1422 {
<> 144:ef7eb2e8f9f7 1423 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1424 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1425
<> 144:ef7eb2e8f9f7 1426 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1427 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1428
<> 144:ef7eb2e8f9f7 1429 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1430 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1433 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1436 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1439 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 /* Return function status */
<> 144:ef7eb2e8f9f7 1442 return HAL_OK;
<> 144:ef7eb2e8f9f7 1443 }
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /**
<> 144:ef7eb2e8f9f7 1446 * @}
<> 144:ef7eb2e8f9f7 1447 */
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 1450 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1451 *
<> 144:ef7eb2e8f9f7 1452 @verbatim
<> 144:ef7eb2e8f9f7 1453 ==============================================================================
<> 144:ef7eb2e8f9f7 1454 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1455 ==============================================================================
<> 144:ef7eb2e8f9f7 1456 [..]
<> 144:ef7eb2e8f9f7 1457 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1458 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 1459 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 1460 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1461 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 1462 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1463 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 @endverbatim
<> 144:ef7eb2e8f9f7 1466 * @{
<> 144:ef7eb2e8f9f7 1467 */
<> 144:ef7eb2e8f9f7 1468 /**
<> 144:ef7eb2e8f9f7 1469 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1470 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1471 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1472 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1473 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1474 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1475 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1476 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1477 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1478 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1479 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1480 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1481 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1482 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1483 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1484 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1485 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1486 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1487 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1488 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1489 * @retval HAL status
<> 144:ef7eb2e8f9f7 1490 */
<> 144:ef7eb2e8f9f7 1491 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1492 {
<> 144:ef7eb2e8f9f7 1493 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1494 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1495 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1496
<> 144:ef7eb2e8f9f7 1497 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1498
<> 144:ef7eb2e8f9f7 1499 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1500 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1501 {
<> 144:ef7eb2e8f9f7 1502 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1503 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1504 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1505 }
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1508 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1509 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1510 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1511 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 return HAL_OK;
<> 144:ef7eb2e8f9f7 1516 }
<> 144:ef7eb2e8f9f7 1517
<> 144:ef7eb2e8f9f7 1518 /**
<> 144:ef7eb2e8f9f7 1519 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1520 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1521 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1522 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1523 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1524 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1525 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1526 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1527 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1528 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1529 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1530 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1531 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1532 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1533 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1534 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1535 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1536 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1537 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1538 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1539 * @retval HAL status
<> 144:ef7eb2e8f9f7 1540 */
<> 144:ef7eb2e8f9f7 1541 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1542 {
<> 144:ef7eb2e8f9f7 1543 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1544 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1545 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1550 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1551 {
<> 144:ef7eb2e8f9f7 1552 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1553 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1554 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1555 }
<> 144:ef7eb2e8f9f7 1556
<> 144:ef7eb2e8f9f7 1557 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1558 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1559 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1560 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1561 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1564 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1567
<> 144:ef7eb2e8f9f7 1568 return HAL_OK;
<> 144:ef7eb2e8f9f7 1569 }
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 /**
<> 144:ef7eb2e8f9f7 1572 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1573 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1574 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1575 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1576 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1577 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1578 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1579 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1580 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1581 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1582 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1583 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1584 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1585 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1586 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1587 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1588 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1589 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1590 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1591 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1592 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1593 * @retval HAL status
<> 144:ef7eb2e8f9f7 1594 */
<> 144:ef7eb2e8f9f7 1595 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1596 {
<> 144:ef7eb2e8f9f7 1597 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1598 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1599 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1600
<> 144:ef7eb2e8f9f7 1601 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1602
<> 144:ef7eb2e8f9f7 1603 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1604 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1605 {
<> 144:ef7eb2e8f9f7 1606 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1607 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1608 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1609 }
<> 144:ef7eb2e8f9f7 1610
<> 144:ef7eb2e8f9f7 1611 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1612 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1613 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1614 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1615 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1618 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1619 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1620 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1621 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError;
<> 144:ef7eb2e8f9f7 1622
<> 144:ef7eb2e8f9f7 1623 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1624 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 return HAL_OK;
<> 161:2cc1468da177 1629 }
<> 161:2cc1468da177 1630
<> 161:2cc1468da177 1631 /**
<> 161:2cc1468da177 1632 * @brief Configures the TIM in master mode.
<> 161:2cc1468da177 1633 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 161:2cc1468da177 1634 * the configuration information for TIM module.
<> 161:2cc1468da177 1635 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<> 161:2cc1468da177 1636 * contains the selected trigger output (TRGO) and the Master/Slave
<> 161:2cc1468da177 1637 * mode.
<> 161:2cc1468da177 1638 * @retval HAL status
<> 161:2cc1468da177 1639 */
<> 161:2cc1468da177 1640 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 161:2cc1468da177 1641 {
<> 161:2cc1468da177 1642 uint32_t tmpcr2;
<> 161:2cc1468da177 1643 uint32_t tmpsmcr;
<> 161:2cc1468da177 1644
<> 161:2cc1468da177 1645 /* Check the parameters */
<> 161:2cc1468da177 1646 assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
<> 161:2cc1468da177 1647 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 161:2cc1468da177 1648 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 161:2cc1468da177 1649
<> 161:2cc1468da177 1650 /* Check input state */
<> 161:2cc1468da177 1651 __HAL_LOCK(htim);
<> 161:2cc1468da177 1652
<> 161:2cc1468da177 1653 /* Get the TIMx CR2 register value */
<> 161:2cc1468da177 1654 tmpcr2 = htim->Instance->CR2;
<> 161:2cc1468da177 1655
<> 161:2cc1468da177 1656 /* Get the TIMx SMCR register value */
<> 161:2cc1468da177 1657 tmpsmcr = htim->Instance->SMCR;
<> 161:2cc1468da177 1658
<> 161:2cc1468da177 1659 /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
<> 161:2cc1468da177 1660 if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
<> 161:2cc1468da177 1661 {
<> 161:2cc1468da177 1662 /* Check the parameters */
<> 161:2cc1468da177 1663 assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
<> 161:2cc1468da177 1664
<> 161:2cc1468da177 1665 /* Clear the MMS2 bits */
<> 161:2cc1468da177 1666 tmpcr2 &= ~TIM_CR2_MMS2;
<> 161:2cc1468da177 1667 /* Select the TRGO2 source*/
<> 161:2cc1468da177 1668 tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
<> 161:2cc1468da177 1669 }
<> 161:2cc1468da177 1670
<> 161:2cc1468da177 1671 /* Reset the MMS Bits */
<> 161:2cc1468da177 1672 tmpcr2 &= ~TIM_CR2_MMS;
<> 161:2cc1468da177 1673 /* Select the TRGO source */
<> 161:2cc1468da177 1674 tmpcr2 |= sMasterConfig->MasterOutputTrigger;
<> 161:2cc1468da177 1675
<> 161:2cc1468da177 1676 /* Reset the MSM Bit */
<> 161:2cc1468da177 1677 tmpsmcr &= ~TIM_SMCR_MSM;
<> 161:2cc1468da177 1678 /* Set master mode */
<> 161:2cc1468da177 1679 tmpsmcr |= sMasterConfig->MasterSlaveMode;
<> 161:2cc1468da177 1680
<> 161:2cc1468da177 1681 /* Update TIMx CR2 */
<> 161:2cc1468da177 1682 htim->Instance->CR2 = tmpcr2;
<> 161:2cc1468da177 1683
<> 161:2cc1468da177 1684 /* Update TIMx SMCR */
<> 161:2cc1468da177 1685 htim->Instance->SMCR = tmpsmcr;
<> 161:2cc1468da177 1686
<> 161:2cc1468da177 1687 __HAL_UNLOCK(htim);
<> 161:2cc1468da177 1688
<> 161:2cc1468da177 1689 return HAL_OK;
<> 161:2cc1468da177 1690 }
<> 161:2cc1468da177 1691
<> 161:2cc1468da177 1692 /**
<> 161:2cc1468da177 1693 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 161:2cc1468da177 1694 * and the AOE(automatic output enable).
<> 161:2cc1468da177 1695 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 161:2cc1468da177 1696 * the configuration information for TIM module.
<> 161:2cc1468da177 1697 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
<> 161:2cc1468da177 1698 * contains the BDTR Register configuration information for the TIM peripheral.
<> 161:2cc1468da177 1699 * @retval HAL status
<> 161:2cc1468da177 1700 */
<> 161:2cc1468da177 1701 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 161:2cc1468da177 1702 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
<> 161:2cc1468da177 1703 {
<> 161:2cc1468da177 1704 uint32_t tmpbdtr = 0;
<> 161:2cc1468da177 1705
<> 161:2cc1468da177 1706 /* Check the parameters */
<> 161:2cc1468da177 1707 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 161:2cc1468da177 1708 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 161:2cc1468da177 1709 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 161:2cc1468da177 1710 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 161:2cc1468da177 1711 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 161:2cc1468da177 1712 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 161:2cc1468da177 1713 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 161:2cc1468da177 1714 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
<> 161:2cc1468da177 1715 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 161:2cc1468da177 1716 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
<> 161:2cc1468da177 1717 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
<> 161:2cc1468da177 1718 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
<> 161:2cc1468da177 1719
<> 161:2cc1468da177 1720 /* Check input state */
<> 161:2cc1468da177 1721 __HAL_LOCK(htim);
<> 161:2cc1468da177 1722
<> 161:2cc1468da177 1723 htim->State = HAL_TIM_STATE_BUSY;
<> 161:2cc1468da177 1724
<> 161:2cc1468da177 1725 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 161:2cc1468da177 1726 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 161:2cc1468da177 1727 /* Set the BDTR bits */
<> 161:2cc1468da177 1728 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
<> 161:2cc1468da177 1729 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
<> 161:2cc1468da177 1730 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
<> 161:2cc1468da177 1731 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
<> 161:2cc1468da177 1732 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
<> 161:2cc1468da177 1733 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
<> 161:2cc1468da177 1734 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
<> 161:2cc1468da177 1735 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
<> 161:2cc1468da177 1736 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT));
<> 161:2cc1468da177 1737
<> 161:2cc1468da177 1738 if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
<> 161:2cc1468da177 1739 {
<> 161:2cc1468da177 1740 assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
<> 161:2cc1468da177 1741 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
<> 161:2cc1468da177 1742 assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
<> 161:2cc1468da177 1743
<> 161:2cc1468da177 1744 /* Set the BREAK2 input related BDTR bits */
<> 161:2cc1468da177 1745 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT));
<> 161:2cc1468da177 1746 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
<> 161:2cc1468da177 1747 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
<> 161:2cc1468da177 1748 }
<> 161:2cc1468da177 1749
<> 161:2cc1468da177 1750
<> 161:2cc1468da177 1751
<> 161:2cc1468da177 1752 /* Set TIMx_BDTR */
<> 161:2cc1468da177 1753 htim->Instance->BDTR = tmpbdtr;
<> 161:2cc1468da177 1754
<> 161:2cc1468da177 1755 __HAL_UNLOCK(htim);
<> 161:2cc1468da177 1756
<> 161:2cc1468da177 1757 return HAL_OK;
<> 161:2cc1468da177 1758 }
<> 161:2cc1468da177 1759 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 161:2cc1468da177 1760 /**
<> 161:2cc1468da177 1761 * @brief Configures the break input source.
<> 161:2cc1468da177 1762 * @param htim: TIM handle.
<> 161:2cc1468da177 1763 * @param BreakInput: Break input to configure
<> 161:2cc1468da177 1764 * This parameter can be one of the following values:
<> 161:2cc1468da177 1765 * @arg TIM_BREAKINPUT_BRK: Timer break input
<> 161:2cc1468da177 1766 * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
<> 161:2cc1468da177 1767 * @param sBreakInputConfig: Break input source configuration
<> 161:2cc1468da177 1768 * @retval HAL status
<> 161:2cc1468da177 1769 */
<> 161:2cc1468da177 1770 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
<> 161:2cc1468da177 1771 uint32_t BreakInput,
<> 161:2cc1468da177 1772 TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
<> 161:2cc1468da177 1773
<> 161:2cc1468da177 1774 {
<> 161:2cc1468da177 1775 uint32_t tmporx = 0;
<> 161:2cc1468da177 1776 uint32_t bkin_enable_mask = 0;
<> 161:2cc1468da177 1777 uint32_t bkin_enable_bitpos = 0;
<> 161:2cc1468da177 1778
<> 161:2cc1468da177 1779 /* Check the parameters */
<> 161:2cc1468da177 1780 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 161:2cc1468da177 1781 assert_param(IS_TIM_BREAKINPUT(BreakInput));
<> 161:2cc1468da177 1782 assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
<> 161:2cc1468da177 1783 assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
<> 161:2cc1468da177 1784
<> 161:2cc1468da177 1785 /* Check input state */
<> 161:2cc1468da177 1786 __HAL_LOCK(htim);
<> 161:2cc1468da177 1787
<> 161:2cc1468da177 1788 switch(sBreakInputConfig->Source)
<> 161:2cc1468da177 1789 {
<> 161:2cc1468da177 1790 case TIM_BREAKINPUTSOURCE_BKIN:
<> 161:2cc1468da177 1791 {
<> 161:2cc1468da177 1792 bkin_enable_mask = TIM1_AF1_BKINE;
<> 161:2cc1468da177 1793 bkin_enable_bitpos = 0;
<> 161:2cc1468da177 1794 }
<> 161:2cc1468da177 1795 break;
<> 161:2cc1468da177 1796
<> 161:2cc1468da177 1797 case TIM_BREAKINPUTSOURCE_DFSDM1:
<> 161:2cc1468da177 1798 {
<> 161:2cc1468da177 1799 bkin_enable_mask = TIM1_AF1_BKDF1BKE;
<> 161:2cc1468da177 1800 bkin_enable_bitpos = 8;
<> 161:2cc1468da177 1801 }
<> 161:2cc1468da177 1802 break;
<> 161:2cc1468da177 1803
<> 161:2cc1468da177 1804 default:
<> 161:2cc1468da177 1805 break;
<> 161:2cc1468da177 1806 }
<> 161:2cc1468da177 1807
<> 161:2cc1468da177 1808 switch(BreakInput)
<> 161:2cc1468da177 1809 {
<> 161:2cc1468da177 1810 case TIM_BREAKINPUT_BRK:
<> 161:2cc1468da177 1811 {
<> 161:2cc1468da177 1812 /* Get the TIMx_AF1 register value */
<> 161:2cc1468da177 1813 tmporx = htim->Instance->AF1;
<> 161:2cc1468da177 1814
<> 161:2cc1468da177 1815 /* Enable the break input */
<> 161:2cc1468da177 1816 tmporx &= ~bkin_enable_mask;
<> 161:2cc1468da177 1817 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
<> 161:2cc1468da177 1818
<> 161:2cc1468da177 1819 /* Set TIMx_AF1 */
<> 161:2cc1468da177 1820 htim->Instance->AF1 = tmporx;
<> 161:2cc1468da177 1821 }
<> 161:2cc1468da177 1822 break;
<> 161:2cc1468da177 1823 case TIM_BREAKINPUT_BRK2:
<> 161:2cc1468da177 1824 {
<> 161:2cc1468da177 1825 /* Get the TIMx_AF2 register value */
<> 161:2cc1468da177 1826 tmporx = htim->Instance->AF2;
<> 161:2cc1468da177 1827
<> 161:2cc1468da177 1828 /* Enable the break input */
<> 161:2cc1468da177 1829 tmporx &= ~bkin_enable_mask;
<> 161:2cc1468da177 1830 tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
<> 161:2cc1468da177 1831
<> 161:2cc1468da177 1832 /* Set TIMx_AF2 */
<> 161:2cc1468da177 1833 htim->Instance->AF2 = tmporx;
<> 161:2cc1468da177 1834 }
<> 161:2cc1468da177 1835 break;
<> 161:2cc1468da177 1836 default:
<> 161:2cc1468da177 1837 break;
<> 161:2cc1468da177 1838 }
<> 161:2cc1468da177 1839
<> 161:2cc1468da177 1840 __HAL_UNLOCK(htim);
<> 161:2cc1468da177 1841
<> 161:2cc1468da177 1842 return HAL_OK;
<> 161:2cc1468da177 1843 }
<> 161:2cc1468da177 1844 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 161:2cc1468da177 1845
<> 161:2cc1468da177 1846 /**
<> 161:2cc1468da177 1847 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
<> 161:2cc1468da177 1848 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 161:2cc1468da177 1849 * the configuration information for TIM module.
<> 161:2cc1468da177 1850 * @param Remap: specifies the TIM input remapping source.
<> 161:2cc1468da177 1851 * This parameter can be one of the following values:
<> 161:2cc1468da177 1852 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
<> 161:2cc1468da177 1853 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
<> 161:2cc1468da177 1854 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
<> 161:2cc1468da177 1855 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
<> 161:2cc1468da177 1856 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
<> 161:2cc1468da177 1857 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
<> 161:2cc1468da177 1858 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
<> 161:2cc1468da177 1859 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
<> 161:2cc1468da177 1860 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
<> 161:2cc1468da177 1861 * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous
<> 161:2cc1468da177 1862 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
<> 161:2cc1468da177 1863 * (HSE divided by a programmable prescaler)
<> 161:2cc1468da177 1864 * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1
<> 161:2cc1468da177 1865 * @retval HAL status
<> 161:2cc1468da177 1866 */
<> 161:2cc1468da177 1867 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 161:2cc1468da177 1868 {
<> 161:2cc1468da177 1869 __HAL_LOCK(htim);
<> 161:2cc1468da177 1870
<> 161:2cc1468da177 1871 /* Check parameters */
<> 161:2cc1468da177 1872 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 161:2cc1468da177 1873 assert_param(IS_TIM_REMAP(Remap));
<> 161:2cc1468da177 1874
<> 161:2cc1468da177 1875 /* Set the Timer remapping configuration */
<> 161:2cc1468da177 1876 htim->Instance->OR = Remap;
<> 161:2cc1468da177 1877
<> 161:2cc1468da177 1878 htim->State = HAL_TIM_STATE_READY;
<> 161:2cc1468da177 1879
<> 161:2cc1468da177 1880 __HAL_UNLOCK(htim);
<> 161:2cc1468da177 1881
<> 161:2cc1468da177 1882 return HAL_OK;
<> 161:2cc1468da177 1883 }
<> 161:2cc1468da177 1884
<> 161:2cc1468da177 1885 /**
<> 161:2cc1468da177 1886 * @brief Group channel 5 and channel 1, 2 or 3
<> 161:2cc1468da177 1887 * @param htim: TIM handle.
<> 161:2cc1468da177 1888 * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
<> 161:2cc1468da177 1889 * This parameter can be any combination of the following values:
<> 161:2cc1468da177 1890 * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
<> 161:2cc1468da177 1891 * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
<> 161:2cc1468da177 1892 * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
<> 161:2cc1468da177 1893 * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
<> 161:2cc1468da177 1894 * @retval HAL status
<> 161:2cc1468da177 1895 */
<> 161:2cc1468da177 1896 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef)
<> 161:2cc1468da177 1897 {
<> 161:2cc1468da177 1898 /* Check parameters */
<> 161:2cc1468da177 1899 assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
<> 161:2cc1468da177 1900 assert_param(IS_TIM_GROUPCH5(OCRef));
<> 161:2cc1468da177 1901
<> 161:2cc1468da177 1902 /* Process Locked */
<> 161:2cc1468da177 1903 __HAL_LOCK(htim);
<> 161:2cc1468da177 1904
<> 161:2cc1468da177 1905 htim->State = HAL_TIM_STATE_BUSY;
<> 161:2cc1468da177 1906
<> 161:2cc1468da177 1907 /* Clear GC5Cx bit fields */
<> 161:2cc1468da177 1908 htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
<> 161:2cc1468da177 1909
<> 161:2cc1468da177 1910 /* Set GC5Cx bit fields */
<> 161:2cc1468da177 1911 htim->Instance->CCR5 |= OCRef;
<> 161:2cc1468da177 1912
<> 161:2cc1468da177 1913 htim->State = HAL_TIM_STATE_READY;
<> 161:2cc1468da177 1914
<> 161:2cc1468da177 1915 __HAL_UNLOCK(htim);
<> 161:2cc1468da177 1916
<> 161:2cc1468da177 1917 return HAL_OK;
<> 161:2cc1468da177 1918 }
<> 161:2cc1468da177 1919 /**
<> 161:2cc1468da177 1920 * @}
<> 161:2cc1468da177 1921 */
<> 161:2cc1468da177 1922
<> 161:2cc1468da177 1923 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
<> 161:2cc1468da177 1924 * @brief Extended Callbacks functions
<> 161:2cc1468da177 1925 *
<> 161:2cc1468da177 1926 @verbatim
<> 161:2cc1468da177 1927 ==============================================================================
<> 161:2cc1468da177 1928 ##### Extension Callbacks functions #####
<> 161:2cc1468da177 1929 ==============================================================================
<> 161:2cc1468da177 1930 [..]
<> 161:2cc1468da177 1931 This section provides Extension TIM callback functions:
<> 161:2cc1468da177 1932 (+) Timer Commutation callback
<> 161:2cc1468da177 1933 (+) Timer Break callback
<> 161:2cc1468da177 1934
<> 161:2cc1468da177 1935 @endverbatim
<> 161:2cc1468da177 1936 * @{
<> 161:2cc1468da177 1937 */
<> 161:2cc1468da177 1938
<> 161:2cc1468da177 1939 /**
<> 161:2cc1468da177 1940 * @brief Hall commutation changed callback in non blocking mode
<> 161:2cc1468da177 1941 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 161:2cc1468da177 1942 * the configuration information for TIM module.
<> 161:2cc1468da177 1943 * @retval None
<> 161:2cc1468da177 1944 */
<> 161:2cc1468da177 1945 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 161:2cc1468da177 1946 {
<> 161:2cc1468da177 1947 /* Prevent unused argument(s) compilation warning */
<> 161:2cc1468da177 1948 UNUSED(htim);
<> 161:2cc1468da177 1949
<> 161:2cc1468da177 1950 /* NOTE : This function Should not be modified, when the callback is needed,
<> 161:2cc1468da177 1951 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 161:2cc1468da177 1952 */
<> 161:2cc1468da177 1953 }
<> 161:2cc1468da177 1954
<> 161:2cc1468da177 1955 /**
<> 161:2cc1468da177 1956 * @brief Hall Break detection callback in non blocking mode
<> 161:2cc1468da177 1957 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 161:2cc1468da177 1958 * the configuration information for TIM module.
<> 161:2cc1468da177 1959 * @retval None
<> 161:2cc1468da177 1960 */
<> 161:2cc1468da177 1961 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 161:2cc1468da177 1962 {
<> 161:2cc1468da177 1963 /* Prevent unused argument(s) compilation warning */
<> 161:2cc1468da177 1964 UNUSED(htim);
<> 161:2cc1468da177 1965
<> 161:2cc1468da177 1966 /* NOTE : This function Should not be modified, when the callback is needed,
<> 161:2cc1468da177 1967 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 161:2cc1468da177 1968 */
<> 161:2cc1468da177 1969 }
<> 161:2cc1468da177 1970
<> 161:2cc1468da177 1971 /**
<> 161:2cc1468da177 1972 * @}
<> 161:2cc1468da177 1973 */
<> 161:2cc1468da177 1974
<> 161:2cc1468da177 1975 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
<> 161:2cc1468da177 1976 * @brief Extended Peripheral State functions
<> 161:2cc1468da177 1977 *
<> 161:2cc1468da177 1978 @verbatim
<> 161:2cc1468da177 1979 ==============================================================================
<> 161:2cc1468da177 1980 ##### Extension Peripheral State functions #####
<> 161:2cc1468da177 1981 ==============================================================================
<> 161:2cc1468da177 1982 [..]
<> 161:2cc1468da177 1983 This subsection permits to get in run-time the status of the peripheral
<> 161:2cc1468da177 1984 and the data flow.
<> 161:2cc1468da177 1985
<> 161:2cc1468da177 1986 @endverbatim
<> 161:2cc1468da177 1987 * @{
<> 161:2cc1468da177 1988 */
<> 161:2cc1468da177 1989
<> 161:2cc1468da177 1990 /**
<> 161:2cc1468da177 1991 * @brief Return the TIM Hall Sensor interface state
<> 161:2cc1468da177 1992 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 161:2cc1468da177 1993 * the configuration information for TIM module.
<> 161:2cc1468da177 1994 * @retval HAL state
<> 161:2cc1468da177 1995 */
<> 161:2cc1468da177 1996 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 161:2cc1468da177 1997 {
<> 161:2cc1468da177 1998 return htim->State;
<> 161:2cc1468da177 1999 }
<> 161:2cc1468da177 2000
<> 161:2cc1468da177 2001 /**
<> 161:2cc1468da177 2002 * @}
<> 161:2cc1468da177 2003 */
<> 161:2cc1468da177 2004
<> 161:2cc1468da177 2005 /**
<> 161:2cc1468da177 2006 * @brief TIM DMA Commutation callback.
<> 161:2cc1468da177 2007 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 161:2cc1468da177 2008 * the configuration information for the specified DMA module.
<> 161:2cc1468da177 2009 * @retval None
<> 161:2cc1468da177 2010 */
<> 161:2cc1468da177 2011 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 161:2cc1468da177 2012 {
<> 161:2cc1468da177 2013 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 161:2cc1468da177 2014
<> 161:2cc1468da177 2015 htim->State= HAL_TIM_STATE_READY;
<> 161:2cc1468da177 2016
<> 161:2cc1468da177 2017 HAL_TIMEx_CommutationCallback(htim);
<> 161:2cc1468da177 2018 }
<> 161:2cc1468da177 2019 /**
<> 161:2cc1468da177 2020 * @}
<> 161:2cc1468da177 2021 */
<> 161:2cc1468da177 2022
<> 161:2cc1468da177 2023 /**
<> 161:2cc1468da177 2024 * @brief Configures the OCRef clear feature
<> 161:2cc1468da177 2025 * @param htim: TIM handle
<> 161:2cc1468da177 2026 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 161:2cc1468da177 2027 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 161:2cc1468da177 2028 * @param Channel: specifies the TIM Channel
<> 161:2cc1468da177 2029 * This parameter can be one of the following values:
<> 161:2cc1468da177 2030 * @arg TIM_Channel_1: TIM Channel 1
<> 161:2cc1468da177 2031 * @arg TIM_Channel_2: TIM Channel 2
<> 161:2cc1468da177 2032 * @arg TIM_Channel_3: TIM Channel 3
<> 161:2cc1468da177 2033 * @arg TIM_Channel_4: TIM Channel 4
<> 161:2cc1468da177 2034 * @arg TIM_Channel_5: TIM Channel 5
<> 161:2cc1468da177 2035 * @arg TIM_Channel_6: TIM Channel 6
<> 161:2cc1468da177 2036 * @retval None
<> 161:2cc1468da177 2037 */
<> 161:2cc1468da177 2038 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
<> 161:2cc1468da177 2039 TIM_ClearInputConfigTypeDef *sClearInputConfig,
<> 161:2cc1468da177 2040 uint32_t Channel)
<> 161:2cc1468da177 2041 {
<> 161:2cc1468da177 2042 uint32_t tmpsmcr = 0;
<> 161:2cc1468da177 2043
<> 161:2cc1468da177 2044 /* Check the parameters */
<> 161:2cc1468da177 2045 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<> 161:2cc1468da177 2046 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 161:2cc1468da177 2047
<> 161:2cc1468da177 2048 /* Check input state */
<> 161:2cc1468da177 2049 __HAL_LOCK(htim);
<> 161:2cc1468da177 2050
<> 161:2cc1468da177 2051 switch (sClearInputConfig->ClearInputSource)
<> 161:2cc1468da177 2052 {
<> 161:2cc1468da177 2053 case TIM_CLEARINPUTSOURCE_NONE:
<> 161:2cc1468da177 2054 {
<> 161:2cc1468da177 2055 /* Get the TIMx SMCR register value */
<> 161:2cc1468da177 2056 tmpsmcr = htim->Instance->SMCR;
<> 161:2cc1468da177 2057
<> 161:2cc1468da177 2058 /* Clear the ETR Bits */
<> 161:2cc1468da177 2059 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 161:2cc1468da177 2060
<> 161:2cc1468da177 2061 /* Set TIMx_SMCR */
<> 161:2cc1468da177 2062 htim->Instance->SMCR = tmpsmcr;
<> 161:2cc1468da177 2063 }
<> 161:2cc1468da177 2064 break;
<> 161:2cc1468da177 2065
<> 161:2cc1468da177 2066 case TIM_CLEARINPUTSOURCE_ETR:
<> 161:2cc1468da177 2067 {
<> 161:2cc1468da177 2068 /* Check the parameters */
<> 161:2cc1468da177 2069 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 161:2cc1468da177 2070 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 161:2cc1468da177 2071 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 161:2cc1468da177 2072
<> 161:2cc1468da177 2073 TIM_ETR_SetConfig(htim->Instance,
<> 161:2cc1468da177 2074 sClearInputConfig->ClearInputPrescaler,
<> 161:2cc1468da177 2075 sClearInputConfig->ClearInputPolarity,
<> 161:2cc1468da177 2076 sClearInputConfig->ClearInputFilter);
<> 161:2cc1468da177 2077 }
<> 161:2cc1468da177 2078 break;
<> 161:2cc1468da177 2079 default:
<> 161:2cc1468da177 2080 break;
<> 161:2cc1468da177 2081 }
<> 161:2cc1468da177 2082
<> 161:2cc1468da177 2083 switch (Channel)
<> 161:2cc1468da177 2084 {
<> 161:2cc1468da177 2085 case TIM_CHANNEL_1:
<> 161:2cc1468da177 2086 {
<> 161:2cc1468da177 2087 if(sClearInputConfig->ClearInputState != RESET)
<> 161:2cc1468da177 2088 {
<> 161:2cc1468da177 2089 /* Enable the Ocref clear feature for Channel 1 */
<> 161:2cc1468da177 2090 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 161:2cc1468da177 2091 }
<> 161:2cc1468da177 2092 else
<> 161:2cc1468da177 2093 {
<> 161:2cc1468da177 2094 /* Disable the Ocref clear feature for Channel 1 */
<> 161:2cc1468da177 2095 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 161:2cc1468da177 2096 }
<> 161:2cc1468da177 2097 }
<> 161:2cc1468da177 2098 break;
<> 161:2cc1468da177 2099 case TIM_CHANNEL_2:
<> 161:2cc1468da177 2100 {
<> 161:2cc1468da177 2101 if(sClearInputConfig->ClearInputState != RESET)
<> 161:2cc1468da177 2102 {
<> 161:2cc1468da177 2103 /* Enable the Ocref clear feature for Channel 2 */
<> 161:2cc1468da177 2104 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 161:2cc1468da177 2105 }
<> 161:2cc1468da177 2106 else
<> 161:2cc1468da177 2107 {
<> 161:2cc1468da177 2108 /* Disable the Ocref clear feature for Channel 2 */
<> 161:2cc1468da177 2109 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 161:2cc1468da177 2110 }
<> 161:2cc1468da177 2111 }
<> 161:2cc1468da177 2112 break;
<> 161:2cc1468da177 2113 case TIM_CHANNEL_3:
<> 161:2cc1468da177 2114 {
<> 161:2cc1468da177 2115 if(sClearInputConfig->ClearInputState != RESET)
<> 161:2cc1468da177 2116 {
<> 161:2cc1468da177 2117 /* Enable the Ocref clear feature for Channel 3 */
<> 161:2cc1468da177 2118 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 161:2cc1468da177 2119 }
<> 161:2cc1468da177 2120 else
<> 161:2cc1468da177 2121 {
<> 161:2cc1468da177 2122 /* Disable the Ocref clear feature for Channel 3 */
<> 161:2cc1468da177 2123 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 161:2cc1468da177 2124 }
<> 161:2cc1468da177 2125 }
<> 161:2cc1468da177 2126 break;
<> 161:2cc1468da177 2127 case TIM_CHANNEL_4:
<> 161:2cc1468da177 2128 {
<> 161:2cc1468da177 2129 if(sClearInputConfig->ClearInputState != RESET)
<> 161:2cc1468da177 2130 {
<> 161:2cc1468da177 2131 /* Enable the Ocref clear feature for Channel 4 */
<> 161:2cc1468da177 2132 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 161:2cc1468da177 2133 }
<> 161:2cc1468da177 2134 else
<> 161:2cc1468da177 2135 {
<> 161:2cc1468da177 2136 /* Disable the Ocref clear feature for Channel 4 */
<> 161:2cc1468da177 2137 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 161:2cc1468da177 2138 }
<> 161:2cc1468da177 2139 }
<> 161:2cc1468da177 2140 break;
<> 161:2cc1468da177 2141 case TIM_CHANNEL_5:
<> 161:2cc1468da177 2142 {
<> 161:2cc1468da177 2143 if(sClearInputConfig->ClearInputState != RESET)
<> 161:2cc1468da177 2144 {
<> 161:2cc1468da177 2145 /* Enable the Ocref clear feature for Channel 1 */
<> 161:2cc1468da177 2146 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE;
<> 161:2cc1468da177 2147 }
<> 161:2cc1468da177 2148 else
<> 161:2cc1468da177 2149 {
<> 161:2cc1468da177 2150 /* Disable the Ocref clear feature for Channel 1 */
<> 161:2cc1468da177 2151 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
<> 161:2cc1468da177 2152 }
<> 161:2cc1468da177 2153 }
<> 161:2cc1468da177 2154 break;
<> 161:2cc1468da177 2155 case TIM_CHANNEL_6:
<> 161:2cc1468da177 2156 {
<> 161:2cc1468da177 2157 if(sClearInputConfig->ClearInputState != RESET)
<> 161:2cc1468da177 2158 {
<> 161:2cc1468da177 2159 /* Enable the Ocref clear feature for Channel 1 */
<> 161:2cc1468da177 2160 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE;
<> 161:2cc1468da177 2161 }
<> 161:2cc1468da177 2162 else
<> 161:2cc1468da177 2163 {
<> 161:2cc1468da177 2164 /* Disable the Ocref clear feature for Channel 1 */
<> 161:2cc1468da177 2165 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
<> 161:2cc1468da177 2166 }
<> 161:2cc1468da177 2167 }
<> 161:2cc1468da177 2168 break;
<> 161:2cc1468da177 2169 default:
<> 161:2cc1468da177 2170 break;
<> 161:2cc1468da177 2171 }
<> 161:2cc1468da177 2172
<> 161:2cc1468da177 2173 __HAL_UNLOCK(htim);
<> 161:2cc1468da177 2174
<> 161:2cc1468da177 2175 return HAL_OK;
<> 144:ef7eb2e8f9f7 2176 }
<> 144:ef7eb2e8f9f7 2177
<> 144:ef7eb2e8f9f7 2178 /**
<> 144:ef7eb2e8f9f7 2179 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 2180 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2181 * @param htim: TIM Output Compare handle
<> 144:ef7eb2e8f9f7 2182 * @param sConfig: TIM Output Compare configuration structure
<> 144:ef7eb2e8f9f7 2183 * @param Channel : TIM Channels to configure
<> 144:ef7eb2e8f9f7 2184 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2185 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2186 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2187 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2188 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2189 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 144:ef7eb2e8f9f7 2190 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 144:ef7eb2e8f9f7 2191 * @retval HAL status
<> 144:ef7eb2e8f9f7 2192 */
<> 144:ef7eb2e8f9f7 2193 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2194 {
<> 144:ef7eb2e8f9f7 2195 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2196 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2197 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2198 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2199
<> 144:ef7eb2e8f9f7 2200 /* Check input state */
<> 144:ef7eb2e8f9f7 2201 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2202
<> 144:ef7eb2e8f9f7 2203 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2204
<> 144:ef7eb2e8f9f7 2205 switch (Channel)
<> 144:ef7eb2e8f9f7 2206 {
<> 144:ef7eb2e8f9f7 2207 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2208 {
<> 144:ef7eb2e8f9f7 2209 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2210 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2211
<> 144:ef7eb2e8f9f7 2212 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 2213 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2214 }
<> 144:ef7eb2e8f9f7 2215 break;
<> 144:ef7eb2e8f9f7 2216
<> 144:ef7eb2e8f9f7 2217 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2218 {
<> 144:ef7eb2e8f9f7 2219 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2220 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 2223 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2224 }
<> 144:ef7eb2e8f9f7 2225 break;
<> 144:ef7eb2e8f9f7 2226
<> 144:ef7eb2e8f9f7 2227 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 2228 {
<> 144:ef7eb2e8f9f7 2229 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2230 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2231
<> 144:ef7eb2e8f9f7 2232 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 2233 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2234 }
<> 144:ef7eb2e8f9f7 2235 break;
<> 144:ef7eb2e8f9f7 2236
<> 144:ef7eb2e8f9f7 2237 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 2238 {
<> 144:ef7eb2e8f9f7 2239 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2240 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2241
<> 144:ef7eb2e8f9f7 2242 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 2243 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2244 }
<> 144:ef7eb2e8f9f7 2245 break;
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 case TIM_CHANNEL_5:
<> 144:ef7eb2e8f9f7 2248 {
<> 144:ef7eb2e8f9f7 2249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2250 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2251
<> 144:ef7eb2e8f9f7 2252 /* Configure the TIM Channel 5 in Output Compare */
<> 144:ef7eb2e8f9f7 2253 TIM_OC5_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2254 }
<> 144:ef7eb2e8f9f7 2255 break;
<> 144:ef7eb2e8f9f7 2256
<> 144:ef7eb2e8f9f7 2257 case TIM_CHANNEL_6:
<> 144:ef7eb2e8f9f7 2258 {
<> 144:ef7eb2e8f9f7 2259 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2260 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2261
<> 144:ef7eb2e8f9f7 2262 /* Configure the TIM Channel 6 in Output Compare */
<> 144:ef7eb2e8f9f7 2263 TIM_OC6_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2264 }
<> 144:ef7eb2e8f9f7 2265 break;
<> 144:ef7eb2e8f9f7 2266
<> 144:ef7eb2e8f9f7 2267 default:
<> 144:ef7eb2e8f9f7 2268 break;
<> 144:ef7eb2e8f9f7 2269 }
<> 144:ef7eb2e8f9f7 2270
<> 144:ef7eb2e8f9f7 2271 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2272
<> 144:ef7eb2e8f9f7 2273 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2274
<> 144:ef7eb2e8f9f7 2275 return HAL_OK;
<> 144:ef7eb2e8f9f7 2276 }
<> 144:ef7eb2e8f9f7 2277
<> 144:ef7eb2e8f9f7 2278 /**
<> 144:ef7eb2e8f9f7 2279 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 2280 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2281 * @param htim: TIM PWM handle
<> 144:ef7eb2e8f9f7 2282 * @param sConfig: TIM PWM configuration structure
<> 144:ef7eb2e8f9f7 2283 * @param Channel : TIM Channels to be configured
<> 144:ef7eb2e8f9f7 2284 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2285 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2286 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2287 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2288 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2289 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
<> 144:ef7eb2e8f9f7 2290 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
<> 144:ef7eb2e8f9f7 2291 * @retval HAL status
<> 144:ef7eb2e8f9f7 2292 */
<> 144:ef7eb2e8f9f7 2293 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 2294 TIM_OC_InitTypeDef* sConfig,
<> 144:ef7eb2e8f9f7 2295 uint32_t Channel)
<> 144:ef7eb2e8f9f7 2296 {
<> 144:ef7eb2e8f9f7 2297 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2298 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2299 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2300 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2301 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 2302
<> 144:ef7eb2e8f9f7 2303 /* Check input state */
<> 144:ef7eb2e8f9f7 2304 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2305
<> 144:ef7eb2e8f9f7 2306 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2307
<> 144:ef7eb2e8f9f7 2308 switch (Channel)
<> 144:ef7eb2e8f9f7 2309 {
<> 144:ef7eb2e8f9f7 2310 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2311 {
<> 144:ef7eb2e8f9f7 2312 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2313 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2314
<> 144:ef7eb2e8f9f7 2315 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 2316 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2317
<> 144:ef7eb2e8f9f7 2318 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 2319 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 2320
<> 144:ef7eb2e8f9f7 2321 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 2322 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 2323 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 2324 }
<> 144:ef7eb2e8f9f7 2325 break;
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2328 {
<> 144:ef7eb2e8f9f7 2329 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2330 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2331
<> 144:ef7eb2e8f9f7 2332 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 2333 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2334
<> 144:ef7eb2e8f9f7 2335 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 2336 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 2339 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 144:ef7eb2e8f9f7 2340 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 2341 }
<> 144:ef7eb2e8f9f7 2342 break;
<> 144:ef7eb2e8f9f7 2343
<> 144:ef7eb2e8f9f7 2344 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 2345 {
<> 144:ef7eb2e8f9f7 2346 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2347 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2348
<> 144:ef7eb2e8f9f7 2349 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 2350 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2351
<> 144:ef7eb2e8f9f7 2352 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 2353 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 2354
<> 144:ef7eb2e8f9f7 2355 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 2356 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 2357 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 2358 }
<> 144:ef7eb2e8f9f7 2359 break;
<> 144:ef7eb2e8f9f7 2360
<> 144:ef7eb2e8f9f7 2361 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 2362 {
<> 144:ef7eb2e8f9f7 2363 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2364 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2365
<> 144:ef7eb2e8f9f7 2366 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 2367 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2368
<> 144:ef7eb2e8f9f7 2369 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 2370 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 2371
<> 144:ef7eb2e8f9f7 2372 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 2373 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 144:ef7eb2e8f9f7 2374 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 2375 }
<> 144:ef7eb2e8f9f7 2376 break;
<> 144:ef7eb2e8f9f7 2377
<> 144:ef7eb2e8f9f7 2378 case TIM_CHANNEL_5:
<> 144:ef7eb2e8f9f7 2379 {
<> 144:ef7eb2e8f9f7 2380 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2381 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 /* Configure the Channel 5 in PWM mode */
<> 144:ef7eb2e8f9f7 2384 TIM_OC5_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2385
<> 144:ef7eb2e8f9f7 2386 /* Set the Preload enable bit for channel5*/
<> 144:ef7eb2e8f9f7 2387 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
<> 144:ef7eb2e8f9f7 2388
<> 144:ef7eb2e8f9f7 2389 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 2390 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
<> 144:ef7eb2e8f9f7 2391 htim->Instance->CCMR3 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 2392 }
<> 144:ef7eb2e8f9f7 2393 break;
<> 144:ef7eb2e8f9f7 2394
<> 144:ef7eb2e8f9f7 2395 case TIM_CHANNEL_6:
<> 144:ef7eb2e8f9f7 2396 {
<> 144:ef7eb2e8f9f7 2397 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2398 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2399
<> 144:ef7eb2e8f9f7 2400 /* Configure the Channel 5 in PWM mode */
<> 144:ef7eb2e8f9f7 2401 TIM_OC6_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 2402
<> 144:ef7eb2e8f9f7 2403 /* Set the Preload enable bit for channel6 */
<> 144:ef7eb2e8f9f7 2404 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
<> 144:ef7eb2e8f9f7 2405
<> 144:ef7eb2e8f9f7 2406 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 2407 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
<> 144:ef7eb2e8f9f7 2408 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 2409 }
<> 144:ef7eb2e8f9f7 2410 break;
<> 144:ef7eb2e8f9f7 2411
<> 144:ef7eb2e8f9f7 2412 default:
<> 144:ef7eb2e8f9f7 2413 break;
<> 144:ef7eb2e8f9f7 2414 }
<> 144:ef7eb2e8f9f7 2415
<> 144:ef7eb2e8f9f7 2416 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2417
<> 144:ef7eb2e8f9f7 2418 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2419
<> 144:ef7eb2e8f9f7 2420 return HAL_OK;
<> 144:ef7eb2e8f9f7 2421 }
<> 144:ef7eb2e8f9f7 2422
<> 144:ef7eb2e8f9f7 2423 /**
<> 144:ef7eb2e8f9f7 2424 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 2425 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 2426 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 2427 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2428 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 2429 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 2430 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 2431 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 2432 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 2433 * @retval None
<> 144:ef7eb2e8f9f7 2434 */
<> 144:ef7eb2e8f9f7 2435 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 2436 {
<> 144:ef7eb2e8f9f7 2437 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 2438
<> 144:ef7eb2e8f9f7 2439 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2440 assert_param(IS_TIM_ADVANCED_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 2441 assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2442
<> 144:ef7eb2e8f9f7 2443 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 2444
<> 144:ef7eb2e8f9f7 2445 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 2446 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 2447
<> 144:ef7eb2e8f9f7 2448 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 2449 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 2450 }
<> 144:ef7eb2e8f9f7 2451
<> 144:ef7eb2e8f9f7 2452 /**
<> 144:ef7eb2e8f9f7 2453 * @brief Timer Output Compare 5 configuration
<> 144:ef7eb2e8f9f7 2454 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 2455 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 2456 * @retval None
<> 144:ef7eb2e8f9f7 2457 */
<> 144:ef7eb2e8f9f7 2458 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 2459 {
<> 144:ef7eb2e8f9f7 2460 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 2461 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 2462 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 2463
<> 144:ef7eb2e8f9f7 2464 /* Disable the output: Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 2465 TIMx->CCER &= ~TIM_CCER_CC5E;
<> 144:ef7eb2e8f9f7 2466
<> 144:ef7eb2e8f9f7 2467 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2468 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 2469 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 2470 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 2471 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2472 tmpccmrx = TIMx->CCMR3;
<> 144:ef7eb2e8f9f7 2473
<> 144:ef7eb2e8f9f7 2474 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 2475 tmpccmrx &= ~(TIM_CCMR3_OC5M);
<> 144:ef7eb2e8f9f7 2476 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 2477 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 2478
<> 144:ef7eb2e8f9f7 2479 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 2480 tmpccer &= ~TIM_CCER_CC5P;
<> 144:ef7eb2e8f9f7 2481 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 2482 tmpccer |= (OC_Config->OCPolarity << 16);
<> 144:ef7eb2e8f9f7 2483
<> 144:ef7eb2e8f9f7 2484 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 2485 {
<> 144:ef7eb2e8f9f7 2486 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 2487 tmpcr2 &= ~TIM_CR2_OIS5;
<> 144:ef7eb2e8f9f7 2488 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 2489 tmpcr2 |= (OC_Config->OCIdleState << 8);
<> 144:ef7eb2e8f9f7 2490 }
<> 144:ef7eb2e8f9f7 2491 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 2492 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 2493
<> 144:ef7eb2e8f9f7 2494 /* Write to TIMx CCMR3 */
<> 144:ef7eb2e8f9f7 2495 TIMx->CCMR3 = tmpccmrx;
<> 144:ef7eb2e8f9f7 2496
<> 144:ef7eb2e8f9f7 2497 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 2498 TIMx->CCR5 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 2499
<> 144:ef7eb2e8f9f7 2500 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2501 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2502 }
<> 144:ef7eb2e8f9f7 2503
<> 144:ef7eb2e8f9f7 2504 /**
<> 144:ef7eb2e8f9f7 2505 * @brief Timer Output Compare 6 configuration
<> 144:ef7eb2e8f9f7 2506 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 2507 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 2508 * @retval None
<> 144:ef7eb2e8f9f7 2509 */
<> 144:ef7eb2e8f9f7 2510 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 2511 {
<> 144:ef7eb2e8f9f7 2512 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 2513 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 2514 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 2515
<> 144:ef7eb2e8f9f7 2516 /* Disable the output: Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 2517 TIMx->CCER &= ~TIM_CCER_CC6E;
<> 144:ef7eb2e8f9f7 2518
<> 144:ef7eb2e8f9f7 2519 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2520 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 2521 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 2522 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 2523 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2524 tmpccmrx = TIMx->CCMR3;
<> 144:ef7eb2e8f9f7 2525
<> 144:ef7eb2e8f9f7 2526 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 2527 tmpccmrx &= ~(TIM_CCMR3_OC6M);
<> 144:ef7eb2e8f9f7 2528 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 2529 tmpccmrx |= (OC_Config->OCMode << 8);
<> 144:ef7eb2e8f9f7 2530
<> 144:ef7eb2e8f9f7 2531 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 2532 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
<> 144:ef7eb2e8f9f7 2533 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 2534 tmpccer |= (OC_Config->OCPolarity << 20);
<> 144:ef7eb2e8f9f7 2535
<> 144:ef7eb2e8f9f7 2536 if(IS_TIM_BREAK_INSTANCE(TIMx))
<> 144:ef7eb2e8f9f7 2537 {
<> 144:ef7eb2e8f9f7 2538 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 2539 tmpcr2 &= ~TIM_CR2_OIS6;
<> 144:ef7eb2e8f9f7 2540 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 2541 tmpcr2 |= (OC_Config->OCIdleState << 10);
<> 144:ef7eb2e8f9f7 2542 }
<> 144:ef7eb2e8f9f7 2543
<> 144:ef7eb2e8f9f7 2544 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 2545 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 2546
<> 144:ef7eb2e8f9f7 2547 /* Write to TIMx CCMR3 */
<> 144:ef7eb2e8f9f7 2548 TIMx->CCMR3 = tmpccmrx;
<> 144:ef7eb2e8f9f7 2549
<> 144:ef7eb2e8f9f7 2550 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 2551 TIMx->CCR6 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 2552
<> 144:ef7eb2e8f9f7 2553 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2554 TIMx->CCER = tmpccer;
<> 161:2cc1468da177 2555 }
<> 144:ef7eb2e8f9f7 2556
<> 144:ef7eb2e8f9f7 2557 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2558 /**
<> 144:ef7eb2e8f9f7 2559 * @}
<> 144:ef7eb2e8f9f7 2560 */
<> 144:ef7eb2e8f9f7 2561
<> 144:ef7eb2e8f9f7 2562 /**
<> 144:ef7eb2e8f9f7 2563 * @}
<> 144:ef7eb2e8f9f7 2564 */
<> 144:ef7eb2e8f9f7 2565 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/