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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 161:2cc1468da177
Child:: 168:9672193075cf

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_nand.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief NAND HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides a generic firmware to drive NAND memories mounted
<>	144:ef7eb2e8f9f7	9	* as external device.
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	@verbatim
<>	144:ef7eb2e8f9f7	12	==============================================================================
<>	144:ef7eb2e8f9f7	13	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	14	==============================================================================
<>	144:ef7eb2e8f9f7	15	[..]
<>	144:ef7eb2e8f9f7	16	This driver is a generic layered driver which contains a set of APIs used to
<>	144:ef7eb2e8f9f7	17	control NAND flash memories. It uses the FMC/FSMC layer functions to interface
<>	144:ef7eb2e8f9f7	18	with NAND devices. This driver is used as follows:
<>	144:ef7eb2e8f9f7	19
<>	144:ef7eb2e8f9f7	20	(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
<>	144:ef7eb2e8f9f7	21	with control and timing parameters for both common and attribute spaces.
<>	144:ef7eb2e8f9f7	22
<>	144:ef7eb2e8f9f7	23	(+) Read NAND flash memory maker and device IDs using the function
<>	144:ef7eb2e8f9f7	24	HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
<>	144:ef7eb2e8f9f7	25	structure declared by the function caller.
<>	144:ef7eb2e8f9f7	26
<>	144:ef7eb2e8f9f7	27	(+) Access NAND flash memory by read/write operations using the functions
<>	161:2cc1468da177	28	HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
<>	161:2cc1468da177	29	HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
<>	161:2cc1468da177	30	HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
<>	161:2cc1468da177	31	HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
<>	144:ef7eb2e8f9f7	32	to read/write page(s)/spare area(s). These functions use specific device
<>	161:2cc1468da177	33	information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
<>	144:ef7eb2e8f9f7	34	structure. The read/write address information is contained by the Nand_Address_Typedef
<>	144:ef7eb2e8f9f7	35	structure passed as parameter.
<>	144:ef7eb2e8f9f7	36
<>	144:ef7eb2e8f9f7	37	(+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	(+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
<>	144:ef7eb2e8f9f7	40	The erase block address information is contained in the Nand_Address_Typedef
<>	144:ef7eb2e8f9f7	41	structure passed as parameter.
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43	(+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
<>	144:ef7eb2e8f9f7	44
<>	144:ef7eb2e8f9f7	45	(+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
<>	144:ef7eb2e8f9f7	46	HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
<>	144:ef7eb2e8f9f7	47	feature or the function HAL_NAND_GetECC() to get the ECC correction code.
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(+) You can monitor the NAND device HAL state by calling the function
<>	144:ef7eb2e8f9f7	50	HAL_NAND_GetState()
<>	144:ef7eb2e8f9f7	51
<>	144:ef7eb2e8f9f7	52	[..]
<>	144:ef7eb2e8f9f7	53	(@) This driver is a set of generic APIs which handle standard NAND flash operations.
<>	144:ef7eb2e8f9f7	54	If a NAND flash device contains different operations and/or implementations,
<>	144:ef7eb2e8f9f7	55	it should be implemented separately.
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	@endverbatim
<>	144:ef7eb2e8f9f7	58	******************************************************************************
<>	144:ef7eb2e8f9f7	59	* @attention
<>	144:ef7eb2e8f9f7	60	*
<>	144:ef7eb2e8f9f7	61	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	62	*
<>	144:ef7eb2e8f9f7	63	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	64	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	65	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	66	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	67	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	68	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	69	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	70	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	71	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	72	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	73	*
<>	144:ef7eb2e8f9f7	74	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	75	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	76	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	77	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	78	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	79	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	80	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	81	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	82	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	83	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	84	*
<>	144:ef7eb2e8f9f7	85	******************************************************************************
<>	144:ef7eb2e8f9f7	86	*/
<>	144:ef7eb2e8f9f7	87
<>	144:ef7eb2e8f9f7	88	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	89	#include "stm32f7xx_hal.h"
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	92	* @{
<>	144:ef7eb2e8f9f7	93	*/
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95
<>	144:ef7eb2e8f9f7	96	#ifdef HAL_NAND_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	/** @defgroup NAND NAND
<>	144:ef7eb2e8f9f7	99	* @brief NAND HAL module driver
<>	144:ef7eb2e8f9f7	100	* @{
<>	144:ef7eb2e8f9f7	101	*/
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	104	/* Private Constants ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	105	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	106	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	107	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	108	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	/** @defgroup NAND_Exported_Functions NAND Exported Functions
<>	144:ef7eb2e8f9f7	111	* @{
<>	144:ef7eb2e8f9f7	112	*/
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	115	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	116	*
<>	144:ef7eb2e8f9f7	117	@verbatim
<>	144:ef7eb2e8f9f7	118	==============================================================================
<>	144:ef7eb2e8f9f7	119	##### NAND Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	120	==============================================================================
<>	144:ef7eb2e8f9f7	121	[..]
<>	144:ef7eb2e8f9f7	122	This section provides functions allowing to initialize/de-initialize
<>	144:ef7eb2e8f9f7	123	the NAND memory
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	@endverbatim
<>	144:ef7eb2e8f9f7	126	* @{
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/**
<>	144:ef7eb2e8f9f7	130	* @brief Perform NAND memory Initialization sequence
<>	144:ef7eb2e8f9f7	131	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	132	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	133	* @param ComSpace_Timing: pointer to Common space timing structure
<>	144:ef7eb2e8f9f7	134	* @param AttSpace_Timing: pointer to Attribute space timing structure
<>	144:ef7eb2e8f9f7	135	* @retval HAL status
<>	144:ef7eb2e8f9f7	136	*/
<>	144:ef7eb2e8f9f7	137	HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef hnand, FMC_NAND_PCC_TimingTypeDef ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
<>	144:ef7eb2e8f9f7	138	{
<>	144:ef7eb2e8f9f7	139	/* Check the NAND handle state */
<>	144:ef7eb2e8f9f7	140	if(hnand == NULL)
<>	144:ef7eb2e8f9f7	141	{
<>	144:ef7eb2e8f9f7	142	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	143	}
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	if(hnand->State == HAL_NAND_STATE_RESET)
<>	144:ef7eb2e8f9f7	146	{
<>	144:ef7eb2e8f9f7	147	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	148	hnand->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	149	/* Initialize the low level hardware (MSP) */
<>	144:ef7eb2e8f9f7	150	HAL_NAND_MspInit(hnand);
<>	144:ef7eb2e8f9f7	151	}
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	/* Initialize NAND control Interface */
<>	144:ef7eb2e8f9f7	154	FMC_NAND_Init(hnand->Instance, &(hnand->Init));
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/* Initialize NAND common space timing Interface */
<>	144:ef7eb2e8f9f7	157	FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	/* Initialize NAND attribute space timing Interface */
<>	144:ef7eb2e8f9f7	160	FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	/* Enable the NAND device */
<>	144:ef7eb2e8f9f7	163	__FMC_NAND_ENABLE(hnand->Instance);
<>	144:ef7eb2e8f9f7	164
<>	144:ef7eb2e8f9f7	165	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	166	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	return HAL_OK;
<>	144:ef7eb2e8f9f7	169	}
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	/**
<>	144:ef7eb2e8f9f7	172	* @brief Perform NAND memory De-Initialization sequence
<>	144:ef7eb2e8f9f7	173	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	174	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	175	* @retval HAL status
<>	144:ef7eb2e8f9f7	176	*/
<>	144:ef7eb2e8f9f7	177	HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	178	{
<>	144:ef7eb2e8f9f7	179	/* Initialize the low level hardware (MSP) */
<>	144:ef7eb2e8f9f7	180	HAL_NAND_MspDeInit(hnand);
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	/* Configure the NAND registers with their reset values */
<>	144:ef7eb2e8f9f7	183	FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	/* Reset the NAND controller state */
<>	144:ef7eb2e8f9f7	186	hnand->State = HAL_NAND_STATE_RESET;
<>	144:ef7eb2e8f9f7	187
<>	144:ef7eb2e8f9f7	188	/* Release Lock */
<>	144:ef7eb2e8f9f7	189	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	return HAL_OK;
<>	144:ef7eb2e8f9f7	192	}
<>	144:ef7eb2e8f9f7	193
<>	144:ef7eb2e8f9f7	194	/**
<>	144:ef7eb2e8f9f7	195	* @brief NAND MSP Init
<>	144:ef7eb2e8f9f7	196	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	197	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	198	* @retval None
<>	144:ef7eb2e8f9f7	199	*/
<>	144:ef7eb2e8f9f7	200	__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	201	{
<>	144:ef7eb2e8f9f7	202	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	203	UNUSED(hnand);
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	206	the HAL_NAND_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	}
<>	144:ef7eb2e8f9f7	209
<>	144:ef7eb2e8f9f7	210	/**
<>	144:ef7eb2e8f9f7	211	* @brief NAND MSP DeInit
<>	144:ef7eb2e8f9f7	212	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	213	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	214	* @retval None
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216	__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	217	{
<>	144:ef7eb2e8f9f7	218	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	219	UNUSED(hnand);
<>	144:ef7eb2e8f9f7	220
<>	144:ef7eb2e8f9f7	221	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	222	the HAL_NAND_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	223	*/
<>	144:ef7eb2e8f9f7	224	}
<>	144:ef7eb2e8f9f7	225
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	/**
<>	144:ef7eb2e8f9f7	228	* @brief This function handles NAND device interrupt request.
<>	144:ef7eb2e8f9f7	229	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	230	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	231	* @retval HAL status
<>	144:ef7eb2e8f9f7	232	*/
<>	144:ef7eb2e8f9f7	233	void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	234	{
<>	144:ef7eb2e8f9f7	235	/* Check NAND interrupt Rising edge flag */
<>	144:ef7eb2e8f9f7	236	if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
<>	144:ef7eb2e8f9f7	237	{
<>	144:ef7eb2e8f9f7	238	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	239	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	/* Clear NAND interrupt Rising edge pending bit */
<>	144:ef7eb2e8f9f7	242	__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
<>	144:ef7eb2e8f9f7	243	}
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	/* Check NAND interrupt Level flag */
<>	144:ef7eb2e8f9f7	246	if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
<>	144:ef7eb2e8f9f7	247	{
<>	144:ef7eb2e8f9f7	248	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	249	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/* Clear NAND interrupt Level pending bit */
<>	144:ef7eb2e8f9f7	252	__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
<>	144:ef7eb2e8f9f7	253	}
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	/* Check NAND interrupt Falling edge flag */
<>	144:ef7eb2e8f9f7	256	if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
<>	144:ef7eb2e8f9f7	257	{
<>	144:ef7eb2e8f9f7	258	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	259	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	/* Clear NAND interrupt Falling edge pending bit */
<>	144:ef7eb2e8f9f7	262	__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
<>	144:ef7eb2e8f9f7	263	}
<>	144:ef7eb2e8f9f7	264
<>	144:ef7eb2e8f9f7	265	/* Check NAND interrupt FIFO empty flag */
<>	144:ef7eb2e8f9f7	266	if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
<>	144:ef7eb2e8f9f7	267	{
<>	144:ef7eb2e8f9f7	268	/* NAND interrupt callback*/
<>	144:ef7eb2e8f9f7	269	HAL_NAND_ITCallback(hnand);
<>	144:ef7eb2e8f9f7	270
<>	144:ef7eb2e8f9f7	271	/* Clear NAND interrupt FIFO empty pending bit */
<>	144:ef7eb2e8f9f7	272	__FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
<>	144:ef7eb2e8f9f7	273	}
<>	144:ef7eb2e8f9f7	274
<>	144:ef7eb2e8f9f7	275	}
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/**
<>	144:ef7eb2e8f9f7	278	* @brief NAND interrupt feature callback
<>	144:ef7eb2e8f9f7	279	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	280	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	281	* @retval None
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283	__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	284	{
<>	144:ef7eb2e8f9f7	285	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	286	UNUSED(hnand);
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	289	the HAL_NAND_ITCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	290	*/
<>	144:ef7eb2e8f9f7	291	}
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/**
<>	144:ef7eb2e8f9f7	294	* @}
<>	144:ef7eb2e8f9f7	295	*/
<>	144:ef7eb2e8f9f7	296
<>	144:ef7eb2e8f9f7	297	/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
<>	144:ef7eb2e8f9f7	298	* @brief Input Output and memory control functions
<>	144:ef7eb2e8f9f7	299	*
<>	144:ef7eb2e8f9f7	300	@verbatim
<>	144:ef7eb2e8f9f7	301	==============================================================================
<>	144:ef7eb2e8f9f7	302	##### NAND Input and Output functions #####
<>	144:ef7eb2e8f9f7	303	==============================================================================
<>	144:ef7eb2e8f9f7	304	[..]
<>	144:ef7eb2e8f9f7	305	This section provides functions allowing to use and control the NAND
<>	144:ef7eb2e8f9f7	306	memory
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	@endverbatim
<>	144:ef7eb2e8f9f7	309	* @{
<>	144:ef7eb2e8f9f7	310	*/
<>	144:ef7eb2e8f9f7	311
<>	144:ef7eb2e8f9f7	312	/**
<>	144:ef7eb2e8f9f7	313	* @brief Read the NAND memory electronic signature
<>	144:ef7eb2e8f9f7	314	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	315	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	316	* @param pNAND_ID: NAND ID structure
<>	144:ef7eb2e8f9f7	317	* @retval HAL status
<>	144:ef7eb2e8f9f7	318	*/
<>	144:ef7eb2e8f9f7	319	HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef hnand, NAND_IDTypeDef pNAND_ID)
<>	144:ef7eb2e8f9f7	320	{
<>	144:ef7eb2e8f9f7	321	__IO uint32_t data = 0;
<>	144:ef7eb2e8f9f7	322	__IO uint32_t data1 = 0;
<>	144:ef7eb2e8f9f7	323	uint32_t deviceAddress = 0;
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/* Process Locked */
<>	144:ef7eb2e8f9f7	326	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	329	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	330	{
<>	144:ef7eb2e8f9f7	331	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	332	}
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	/* Identify the device address */
<>	144:ef7eb2e8f9f7	335	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	336
<>	144:ef7eb2e8f9f7	337	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	338	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	/* Send Read ID command sequence */
<>	144:ef7eb2e8f9f7	341	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_READID;
<>	144:ef7eb2e8f9f7	342	__DSB();
<>	144:ef7eb2e8f9f7	343	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	144:ef7eb2e8f9f7	344	__DSB();
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/* Read the electronic signature from NAND flash */
<>	144:ef7eb2e8f9f7	347	if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
<>	144:ef7eb2e8f9f7	348	{
<>	144:ef7eb2e8f9f7	349	data = (__IO uint32_t )deviceAddress;
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/* Return the data read */
<>	144:ef7eb2e8f9f7	352	pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
<>	144:ef7eb2e8f9f7	353	pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
<>	144:ef7eb2e8f9f7	354	pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
<>	144:ef7eb2e8f9f7	355	pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
<>	144:ef7eb2e8f9f7	356	}
<>	144:ef7eb2e8f9f7	357	else
<>	144:ef7eb2e8f9f7	358	{
<>	144:ef7eb2e8f9f7	359	data = (__IO uint32_t )deviceAddress;
<>	144:ef7eb2e8f9f7	360	data1 = ((__IO uint32_t )deviceAddress + 4);
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	/* Return the data read */
<>	144:ef7eb2e8f9f7	363	pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
<>	144:ef7eb2e8f9f7	364	pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
<>	144:ef7eb2e8f9f7	365	pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
<>	144:ef7eb2e8f9f7	366	pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
<>	144:ef7eb2e8f9f7	367	}
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	370	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	371
<>	144:ef7eb2e8f9f7	372	/* Process unlocked */
<>	144:ef7eb2e8f9f7	373	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375	return HAL_OK;
<>	144:ef7eb2e8f9f7	376	}
<>	144:ef7eb2e8f9f7	377
<>	144:ef7eb2e8f9f7	378	/**
<>	144:ef7eb2e8f9f7	379	* @brief NAND memory reset
<>	144:ef7eb2e8f9f7	380	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	381	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	382	* @retval HAL status
<>	144:ef7eb2e8f9f7	383	*/
<>	144:ef7eb2e8f9f7	384	HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	385	{
<>	144:ef7eb2e8f9f7	386	uint32_t deviceAddress = 0;
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	/* Process Locked */
<>	144:ef7eb2e8f9f7	389	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	390
<>	144:ef7eb2e8f9f7	391	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	392	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	393	{
<>	144:ef7eb2e8f9f7	394	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	395	}
<>	144:ef7eb2e8f9f7	396
<>	144:ef7eb2e8f9f7	397	/* Identify the device address */
<>	144:ef7eb2e8f9f7	398	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	399
<>	144:ef7eb2e8f9f7	400	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	401	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	/* Send NAND reset command */
<>	144:ef7eb2e8f9f7	404	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = 0xFF;
<>	161:2cc1468da177	405
<>	144:ef7eb2e8f9f7	406	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	407	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/* Process unlocked */
<>	144:ef7eb2e8f9f7	410	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	return HAL_OK;
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	}
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/**
<>	161:2cc1468da177	417	* @brief Configure the device: Enter the physical parameters of the device
<>	161:2cc1468da177	418	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	161:2cc1468da177	419	* the configuration information for NAND module.
<>	161:2cc1468da177	420	* @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
<>	161:2cc1468da177	421	* @retval HAL status
<>	161:2cc1468da177	422	*/
<>	161:2cc1468da177	423	HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef hnand, NAND_DeviceConfigTypeDef pDeviceConfig)
<>	161:2cc1468da177	424	{
<>	161:2cc1468da177	425	hnand->Config.PageSize = pDeviceConfig->PageSize;
<>	161:2cc1468da177	426	hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
<>	161:2cc1468da177	427	hnand->Config.BlockSize = pDeviceConfig->BlockSize;
<>	161:2cc1468da177	428	hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
<>	161:2cc1468da177	429	hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
<>	161:2cc1468da177	430	hnand->Config.PlaneNbr = pDeviceConfig->BlockNbr;
<>	161:2cc1468da177	431	hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
<>	161:2cc1468da177	432
<>	161:2cc1468da177	433	return HAL_OK;
<>	161:2cc1468da177	434	}
<>	161:2cc1468da177	435
<>	161:2cc1468da177	436
<>	161:2cc1468da177	437	/**
<>	144:ef7eb2e8f9f7	438	* @brief Read Page(s) from NAND memory block (8-bits addressing)
<>	144:ef7eb2e8f9f7	439	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	440	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	441	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	442	* @param pBuffer : pointer to destination read buffer
<>	144:ef7eb2e8f9f7	443	* @param NumPageToRead : number of pages to read from block
<>	144:ef7eb2e8f9f7	444	* @retval HAL status
<>	144:ef7eb2e8f9f7	445	*/
<>	144:ef7eb2e8f9f7	446	HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
<>	144:ef7eb2e8f9f7	447	{
<>	144:ef7eb2e8f9f7	448	__IO uint32_t index = 0;
<>	161:2cc1468da177	449	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	450	uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
<>	144:ef7eb2e8f9f7	451
<>	144:ef7eb2e8f9f7	452	/* Process Locked */
<>	144:ef7eb2e8f9f7	453	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	456	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	457	{
<>	144:ef7eb2e8f9f7	458	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	459	}
<>	144:ef7eb2e8f9f7	460
<>	144:ef7eb2e8f9f7	461	/* Identify the device address */
<>	144:ef7eb2e8f9f7	462	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	465	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	466
<>	144:ef7eb2e8f9f7	467	/* NAND raw address calculation */
<>	144:ef7eb2e8f9f7	468	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	/* Page(s) read loop */
<>	161:2cc1468da177	471	while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	161:2cc1468da177	472	{
<>	144:ef7eb2e8f9f7	473	/* update the buffer size */
<>	161:2cc1468da177	474	size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/* Send read page command sequence */
<>	161:2cc1468da177	477	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	144:ef7eb2e8f9f7	478	__DSB();
<>	161:2cc1468da177	479
<>	161:2cc1468da177	480	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	481	if((hnand->Config.PageSize) <= 512)
<>	161:2cc1468da177	482	{
<>	161:2cc1468da177	483	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	484	{
<>	161:2cc1468da177	485	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	486	__DSB();
<>	161:2cc1468da177	487	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	488	__DSB();
<>	161:2cc1468da177	489	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	490	__DSB();
<>	161:2cc1468da177	491	}
<>	161:2cc1468da177	492	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	493	{
<>	161:2cc1468da177	494	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	495	__DSB();
<>	161:2cc1468da177	496	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	497	__DSB();
<>	161:2cc1468da177	498	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	499	__DSB();
<>	161:2cc1468da177	500	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	501	__DSB();
<>	161:2cc1468da177	502	}
<>	161:2cc1468da177	503	}
<>	161:2cc1468da177	504	else /* (hnand->Config.PageSize) > 512 */
<>	144:ef7eb2e8f9f7	505	{
<>	161:2cc1468da177	506	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	507	{
<>	161:2cc1468da177	508	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	509	__DSB();
<>	161:2cc1468da177	510	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	511	__DSB();
<>	161:2cc1468da177	512	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	513	__DSB();
<>	161:2cc1468da177	514	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	515	__DSB();
<>	161:2cc1468da177	516	}
<>	161:2cc1468da177	517	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	518	{
<>	161:2cc1468da177	519	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	520	__DSB();
<>	161:2cc1468da177	521	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	522	__DSB();
<>	161:2cc1468da177	523	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	524	__DSB();
<>	161:2cc1468da177	525	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	526	__DSB();
<>	161:2cc1468da177	527	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	528	__DSB();
<>	161:2cc1468da177	529	}
<>	144:ef7eb2e8f9f7	530	}
<>	161:2cc1468da177	531
<>	144:ef7eb2e8f9f7	532	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<>	144:ef7eb2e8f9f7	533	__DSB();
<>	144:ef7eb2e8f9f7	534
<>	161:2cc1468da177	535
<>	161:2cc1468da177	536	if(hnand->Config.ExtraCommandEnable == ENABLE)
<>	144:ef7eb2e8f9f7	537	{
<>	161:2cc1468da177	538	/* Get tick */
<>	161:2cc1468da177	539	tickstart = HAL_GetTick();
<>	161:2cc1468da177	540
<>	161:2cc1468da177	541	/* Read status until NAND is ready */
<>	161:2cc1468da177	542	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	543	{
<>	161:2cc1468da177	544	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	161:2cc1468da177	545	{
<>	161:2cc1468da177	546	return HAL_TIMEOUT;
<>	161:2cc1468da177	547	}
<>	144:ef7eb2e8f9f7	548	}
<>	161:2cc1468da177	549
<>	161:2cc1468da177	550	/* Go back to read mode */
<>	161:2cc1468da177	551	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
<>	161:2cc1468da177	552	__DSB();
<>	144:ef7eb2e8f9f7	553	}
<>	161:2cc1468da177	554
<>	161:2cc1468da177	555	/* Get Data into Buffer */
<>	161:2cc1468da177	556	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	557	{
<>	161:2cc1468da177	558	(uint8_t )pBuffer++ = (uint8_t )deviceAddress;
<>	144:ef7eb2e8f9f7	559	}
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561	/* Increment read pages number */
<>	144:ef7eb2e8f9f7	562	numPagesRead++;
<>	144:ef7eb2e8f9f7	563
<>	144:ef7eb2e8f9f7	564	/* Decrement pages to read */
<>	144:ef7eb2e8f9f7	565	NumPageToRead--;
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/* Increment the NAND address */
<>	161:2cc1468da177	568	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	569	}
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	572	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/* Process unlocked */
<>	144:ef7eb2e8f9f7	575	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	return HAL_OK;
<>	144:ef7eb2e8f9f7	578
<>	144:ef7eb2e8f9f7	579	}
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/**
<>	144:ef7eb2e8f9f7	582	* @brief Read Page(s) from NAND memory block (16-bits addressing)
<>	144:ef7eb2e8f9f7	583	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	584	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	585	* @param pAddress : pointer to NAND address structure
<>	161:2cc1468da177	586	* @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
<>	144:ef7eb2e8f9f7	587	* @param NumPageToRead : number of pages to read from block
<>	144:ef7eb2e8f9f7	588	* @retval HAL status
<>	144:ef7eb2e8f9f7	589	*/
<>	144:ef7eb2e8f9f7	590	HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
<>	144:ef7eb2e8f9f7	591	{
<>	144:ef7eb2e8f9f7	592	__IO uint32_t index = 0;
<>	161:2cc1468da177	593	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	594	uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
<>	144:ef7eb2e8f9f7	595
<>	144:ef7eb2e8f9f7	596	/* Process Locked */
<>	144:ef7eb2e8f9f7	597	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	600	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	601	{
<>	144:ef7eb2e8f9f7	602	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	603	}
<>	144:ef7eb2e8f9f7	604
<>	144:ef7eb2e8f9f7	605	/* Identify the device address */
<>	144:ef7eb2e8f9f7	606	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	607
<>	144:ef7eb2e8f9f7	608	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	609	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	610
<>	144:ef7eb2e8f9f7	611	/* NAND raw address calculation */
<>	144:ef7eb2e8f9f7	612	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	/* Page(s) read loop */
<>	161:2cc1468da177	615	while((NumPageToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	616	{
<>	144:ef7eb2e8f9f7	617	/* update the buffer size */
<>	161:2cc1468da177	618	size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/* Send read page command sequence */
<>	144:ef7eb2e8f9f7	621	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	144:ef7eb2e8f9f7	622	__DSB();
<>	161:2cc1468da177	623
<>	161:2cc1468da177	624	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	625	if((hnand->Config.PageSize) <= 512)
<>	144:ef7eb2e8f9f7	626	{
<>	161:2cc1468da177	627	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	628	{
<>	161:2cc1468da177	629	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	630	__DSB();
<>	161:2cc1468da177	631	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	632	__DSB();
<>	161:2cc1468da177	633	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	634	__DSB();
<>	161:2cc1468da177	635	}
<>	161:2cc1468da177	636	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	637	{
<>	161:2cc1468da177	638	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	639	__DSB();
<>	161:2cc1468da177	640	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	641	__DSB();
<>	161:2cc1468da177	642	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	643	__DSB();
<>	161:2cc1468da177	644	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	645	__DSB();
<>	161:2cc1468da177	646	}
<>	161:2cc1468da177	647	}
<>	161:2cc1468da177	648	else /* (hnand->Config.PageSize) > 512 */
<>	161:2cc1468da177	649	{
<>	161:2cc1468da177	650	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	651	{
<>	161:2cc1468da177	652	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	653	__DSB();
<>	161:2cc1468da177	654	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	655	__DSB();
<>	161:2cc1468da177	656	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	657	__DSB();
<>	161:2cc1468da177	658	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	659	__DSB();
<>	161:2cc1468da177	660	}
<>	161:2cc1468da177	661	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	662	{
<>	161:2cc1468da177	663	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	664	__DSB();
<>	161:2cc1468da177	665	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	666	__DSB();
<>	161:2cc1468da177	667	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	668	__DSB();
<>	161:2cc1468da177	669	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	670	__DSB();
<>	161:2cc1468da177	671	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	672	__DSB();
<>	161:2cc1468da177	673	}
<>	144:ef7eb2e8f9f7	674	}
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<>	144:ef7eb2e8f9f7	677	__DSB();
<>	161:2cc1468da177	678
<>	161:2cc1468da177	679	if(hnand->Config.ExtraCommandEnable == ENABLE)
<>	161:2cc1468da177	680	{
<>	161:2cc1468da177	681	/* Get tick */
<>	161:2cc1468da177	682	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	683
<>	161:2cc1468da177	684	/* Read status until NAND is ready */
<>	161:2cc1468da177	685	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	161:2cc1468da177	686	{
<>	161:2cc1468da177	687	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	161:2cc1468da177	688	{
<>	161:2cc1468da177	689	return HAL_TIMEOUT;
<>	161:2cc1468da177	690	}
<>	161:2cc1468da177	691	}
<>	161:2cc1468da177	692
<>	161:2cc1468da177	693	/* Go back to read mode */
<>	161:2cc1468da177	694	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
<>	161:2cc1468da177	695	__DSB();
<>	161:2cc1468da177	696	}
<>	161:2cc1468da177	697
<>	144:ef7eb2e8f9f7	698	/* Get Data into Buffer */
<>	144:ef7eb2e8f9f7	699	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	700	{
<>	144:ef7eb2e8f9f7	701	(uint16_t )pBuffer++ = (uint16_t )deviceAddress;
<>	144:ef7eb2e8f9f7	702	}
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	/* Increment read pages number */
<>	144:ef7eb2e8f9f7	705	numPagesRead++;
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/* Decrement pages to read */
<>	144:ef7eb2e8f9f7	708	NumPageToRead--;
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	/* Increment the NAND address */
<>	161:2cc1468da177	711	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	712	}
<>	144:ef7eb2e8f9f7	713
<>	144:ef7eb2e8f9f7	714	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	715	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/* Process unlocked */
<>	144:ef7eb2e8f9f7	718	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	719
<>	144:ef7eb2e8f9f7	720	return HAL_OK;
<>	144:ef7eb2e8f9f7	721	}
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/**
<>	144:ef7eb2e8f9f7	724	* @brief Write Page(s) to NAND memory block (8-bits addressing)
<>	144:ef7eb2e8f9f7	725	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	726	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	727	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	728	* @param pBuffer : pointer to source buffer to write
<>	144:ef7eb2e8f9f7	729	* @param NumPageToWrite : number of pages to write to block
<>	144:ef7eb2e8f9f7	730	* @retval HAL status
<>	144:ef7eb2e8f9f7	731	*/
<>	144:ef7eb2e8f9f7	732	HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
<>	144:ef7eb2e8f9f7	733	{
<>	144:ef7eb2e8f9f7	734	__IO uint32_t index = 0;
<>	144:ef7eb2e8f9f7	735	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	736	uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738	/* Process Locked */
<>	144:ef7eb2e8f9f7	739	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	742	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	745	}
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	/* Identify the device address */
<>	144:ef7eb2e8f9f7	748	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	751	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	/* NAND raw address calculation */
<>	144:ef7eb2e8f9f7	754	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	144:ef7eb2e8f9f7	755
<>	144:ef7eb2e8f9f7	756	/* Page(s) write loop */
<>	161:2cc1468da177	757	while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	758	{
<>	144:ef7eb2e8f9f7	759	/* update the buffer size */
<>	161:2cc1468da177	760	size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/* Send write page command sequence */
<>	144:ef7eb2e8f9f7	763	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	144:ef7eb2e8f9f7	764	__DSB();
<>	144:ef7eb2e8f9f7	765	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
<>	144:ef7eb2e8f9f7	766	__DSB();
<>	144:ef7eb2e8f9f7	767
<>	161:2cc1468da177	768	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	769	if((hnand->Config.PageSize) <= 512)
<>	144:ef7eb2e8f9f7	770	{
<>	161:2cc1468da177	771	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	144:ef7eb2e8f9f7	772	{
<>	161:2cc1468da177	773	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	774	__DSB();
<>	161:2cc1468da177	775	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	776	__DSB();
<>	161:2cc1468da177	777	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	778	__DSB();
<>	161:2cc1468da177	779	}
<>	161:2cc1468da177	780	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	781	{
<>	161:2cc1468da177	782	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	783	__DSB();
<>	161:2cc1468da177	784	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	785	__DSB();
<>	161:2cc1468da177	786	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	787	__DSB();
<>	161:2cc1468da177	788	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	144:ef7eb2e8f9f7	789	__DSB();
<>	144:ef7eb2e8f9f7	790	}
<>	144:ef7eb2e8f9f7	791	}
<>	161:2cc1468da177	792	else /* (hnand->Config.PageSize) > 512 */
<>	144:ef7eb2e8f9f7	793	{
<>	161:2cc1468da177	794	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	144:ef7eb2e8f9f7	795	{
<>	161:2cc1468da177	796	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	797	__DSB();
<>	161:2cc1468da177	798	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	799	__DSB();
<>	161:2cc1468da177	800	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	801	__DSB();
<>	161:2cc1468da177	802	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	144:ef7eb2e8f9f7	803	__DSB();
<>	144:ef7eb2e8f9f7	804	}
<>	161:2cc1468da177	805	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	806	{
<>	161:2cc1468da177	807	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	808	__DSB();
<>	161:2cc1468da177	809	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	810	__DSB();
<>	161:2cc1468da177	811	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	812	__DSB();
<>	161:2cc1468da177	813	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	814	__DSB();
<>	161:2cc1468da177	815	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	816	__DSB();
<>	161:2cc1468da177	817	}
<>	161:2cc1468da177	818	}
<>	161:2cc1468da177	819
<>	161:2cc1468da177	820	/* Write data to memory */
<>	161:2cc1468da177	821	for(; index < size; index++)
<>	161:2cc1468da177	822	{
<>	161:2cc1468da177	823	(__IO uint8_t )deviceAddress = (uint8_t )pBuffer++;
<>	161:2cc1468da177	824	__DSB();
<>	144:ef7eb2e8f9f7	825	}
<>	144:ef7eb2e8f9f7	826
<>	144:ef7eb2e8f9f7	827	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<>	144:ef7eb2e8f9f7	828	__DSB();
<>	144:ef7eb2e8f9f7	829
<>	144:ef7eb2e8f9f7	830	/* Read status until NAND is ready */
<>	144:ef7eb2e8f9f7	831	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	832	{
<>	144:ef7eb2e8f9f7	833	/* Get tick */
<>	144:ef7eb2e8f9f7	834	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	835
<>	144:ef7eb2e8f9f7	836	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	144:ef7eb2e8f9f7	837	{
<>	144:ef7eb2e8f9f7	838	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	839	}
<>	144:ef7eb2e8f9f7	840	}
<>	144:ef7eb2e8f9f7	841
<>	144:ef7eb2e8f9f7	842	/* Increment written pages number */
<>	144:ef7eb2e8f9f7	843	numPagesWritten++;
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/* Decrement pages to write */
<>	144:ef7eb2e8f9f7	846	NumPageToWrite--;
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	/* Increment the NAND address */
<>	161:2cc1468da177	849	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	850	}
<>	144:ef7eb2e8f9f7	851
<>	144:ef7eb2e8f9f7	852	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	853	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	/* Process unlocked */
<>	144:ef7eb2e8f9f7	856	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	return HAL_OK;
<>	144:ef7eb2e8f9f7	859	}
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/**
<>	144:ef7eb2e8f9f7	862	* @brief Write Page(s) to NAND memory block (16-bits addressing)
<>	144:ef7eb2e8f9f7	863	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	864	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	865	* @param pAddress : pointer to NAND address structure
<>	161:2cc1468da177	866	* @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
<>	144:ef7eb2e8f9f7	867	* @param NumPageToWrite : number of pages to write to block
<>	144:ef7eb2e8f9f7	868	* @retval HAL status
<>	144:ef7eb2e8f9f7	869	*/
<>	144:ef7eb2e8f9f7	870	HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
<>	144:ef7eb2e8f9f7	871	{
<>	144:ef7eb2e8f9f7	872	__IO uint32_t index = 0;
<>	144:ef7eb2e8f9f7	873	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	874	uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/* Process Locked */
<>	144:ef7eb2e8f9f7	877	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	878
<>	144:ef7eb2e8f9f7	879	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	880	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	881	{
<>	144:ef7eb2e8f9f7	882	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	883	}
<>	144:ef7eb2e8f9f7	884
<>	144:ef7eb2e8f9f7	885	/* Identify the device address */
<>	144:ef7eb2e8f9f7	886	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	887
<>	144:ef7eb2e8f9f7	888	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	889	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	890
<>	144:ef7eb2e8f9f7	891	/* NAND raw address calculation */
<>	144:ef7eb2e8f9f7	892	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	144:ef7eb2e8f9f7	893
<>	144:ef7eb2e8f9f7	894	/* Page(s) write loop */
<>	161:2cc1468da177	895	while((NumPageToWrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	896	{
<>	144:ef7eb2e8f9f7	897	/* update the buffer size */
<>	161:2cc1468da177	898	size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
<>	144:ef7eb2e8f9f7	899
<>	144:ef7eb2e8f9f7	900	/* Send write page command sequence */
<>	144:ef7eb2e8f9f7	901	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	144:ef7eb2e8f9f7	902	__DSB();
<>	144:ef7eb2e8f9f7	903	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
<>	144:ef7eb2e8f9f7	904	__DSB();
<>	144:ef7eb2e8f9f7	905
<>	161:2cc1468da177	906	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	907	if((hnand->Config.PageSize) <= 512)
<>	144:ef7eb2e8f9f7	908	{
<>	161:2cc1468da177	909	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	910	{
<>	161:2cc1468da177	911	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	912	__DSB();
<>	161:2cc1468da177	913	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	914	__DSB();
<>	161:2cc1468da177	915	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	916	__DSB();
<>	161:2cc1468da177	917	}
<>	161:2cc1468da177	918	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	919	{
<>	161:2cc1468da177	920	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	921	__DSB();
<>	161:2cc1468da177	922	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	923	__DSB();
<>	161:2cc1468da177	924	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	925	__DSB();
<>	161:2cc1468da177	926	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	927	__DSB();
<>	161:2cc1468da177	928	}
<>	161:2cc1468da177	929	}
<>	161:2cc1468da177	930	else /* (hnand->Config.PageSize) > 512 */
<>	161:2cc1468da177	931	{
<>	161:2cc1468da177	932	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	933	{
<>	161:2cc1468da177	934	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	935	__DSB();
<>	161:2cc1468da177	936	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	937	__DSB();
<>	161:2cc1468da177	938	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	939	__DSB();
<>	161:2cc1468da177	940	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	941	__DSB();
<>	161:2cc1468da177	942	}
<>	161:2cc1468da177	943	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	944	{
<>	161:2cc1468da177	945	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	946	__DSB();
<>	161:2cc1468da177	947	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	948	__DSB();
<>	161:2cc1468da177	949	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	950	__DSB();
<>	161:2cc1468da177	951	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	952	__DSB();
<>	161:2cc1468da177	953	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	954	__DSB();
<>	161:2cc1468da177	955	}
<>	144:ef7eb2e8f9f7	956	}
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	/* Write data to memory */
<>	144:ef7eb2e8f9f7	959	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	960	{
<>	144:ef7eb2e8f9f7	961	(__IO uint16_t )deviceAddress = (uint16_t )pBuffer++;
<>	144:ef7eb2e8f9f7	962	__DSB();
<>	144:ef7eb2e8f9f7	963	}
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<>	144:ef7eb2e8f9f7	966	__DSB();
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	/* Read status until NAND is ready */
<>	144:ef7eb2e8f9f7	969	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	970	{
<>	144:ef7eb2e8f9f7	971	/* Get tick */
<>	144:ef7eb2e8f9f7	972	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	144:ef7eb2e8f9f7	975	{
<>	144:ef7eb2e8f9f7	976	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	977	}
<>	144:ef7eb2e8f9f7	978	}
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	/* Increment written pages number */
<>	144:ef7eb2e8f9f7	981	numPagesWritten++;
<>	144:ef7eb2e8f9f7	982
<>	144:ef7eb2e8f9f7	983	/* Decrement pages to write */
<>	144:ef7eb2e8f9f7	984	NumPageToWrite--;
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/* Increment the NAND address */
<>	161:2cc1468da177	987	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	988	}
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	991	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	992
<>	144:ef7eb2e8f9f7	993	/* Process unlocked */
<>	144:ef7eb2e8f9f7	994	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	995
<>	144:ef7eb2e8f9f7	996	return HAL_OK;
<>	144:ef7eb2e8f9f7	997	}
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/**
<>	144:ef7eb2e8f9f7	1000	* @brief Read Spare area(s) from NAND memory (8-bits addressing)
<>	144:ef7eb2e8f9f7	1001	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1002	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1003	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	1004	* @param pBuffer: pointer to source buffer to write
<>	144:ef7eb2e8f9f7	1005	* @param NumSpareAreaToRead: Number of spare area to read
<>	144:ef7eb2e8f9f7	1006	* @retval HAL status
<>	144:ef7eb2e8f9f7	1007	*/
<>	144:ef7eb2e8f9f7	1008	HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
<>	144:ef7eb2e8f9f7	1009	{
<>	161:2cc1468da177	1010	__IO uint32_t index = 0;
<>	161:2cc1468da177	1011	uint32_t tickstart = 0U;
<>	161:2cc1468da177	1012	uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	/* Process Locked */
<>	144:ef7eb2e8f9f7	1015	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	1016
<>	144:ef7eb2e8f9f7	1017	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1018	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1019	{
<>	144:ef7eb2e8f9f7	1020	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1021	}
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1024	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1027	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/* NAND raw address calculation */
<>	161:2cc1468da177	1030	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	161:2cc1468da177	1031
<>	161:2cc1468da177	1032	/* Column in page address */
<>	161:2cc1468da177	1033	columnAddress = COLUMN_ADDRESS(hnand);
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/* Spare area(s) read loop */
<>	161:2cc1468da177	1036	while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	1037	{
<>	144:ef7eb2e8f9f7	1038	/* update the buffer size */
<>	161:2cc1468da177	1039	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
<>	161:2cc1468da177	1040
<>	161:2cc1468da177	1041	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	1042	if((hnand->Config.PageSize) <= 512)
<>	144:ef7eb2e8f9f7	1043	{
<>	161:2cc1468da177	1044	/* Send read spare area command sequence */
<>	161:2cc1468da177	1045	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
<>	144:ef7eb2e8f9f7	1046	__DSB();
<>	161:2cc1468da177	1047
<>	161:2cc1468da177	1048	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1049	{
<>	161:2cc1468da177	1050	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1051	__DSB();
<>	161:2cc1468da177	1052	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1053	__DSB();
<>	161:2cc1468da177	1054	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1055	__DSB();
<>	161:2cc1468da177	1056	}
<>	161:2cc1468da177	1057	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1058	{
<>	161:2cc1468da177	1059	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1060	__DSB();
<>	161:2cc1468da177	1061	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1062	__DSB();
<>	161:2cc1468da177	1063	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1064	__DSB();
<>	161:2cc1468da177	1065	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1066	__DSB();
<>	161:2cc1468da177	1067	}
<>	161:2cc1468da177	1068	}
<>	161:2cc1468da177	1069	else /* (hnand->Config.PageSize) > 512 */
<>	161:2cc1468da177	1070	{
<>	161:2cc1468da177	1071	/* Send read spare area command sequence */
<>	161:2cc1468da177	1072	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	161:2cc1468da177	1073	__DSB();
<>	161:2cc1468da177	1074
<>	161:2cc1468da177	1075	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1076	{
<>	161:2cc1468da177	1077	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1078	__DSB();
<>	161:2cc1468da177	1079	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1080	__DSB();
<>	161:2cc1468da177	1081	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1082	__DSB();
<>	161:2cc1468da177	1083	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1084	__DSB();
<>	161:2cc1468da177	1085	}
<>	161:2cc1468da177	1086	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1087	{
<>	161:2cc1468da177	1088	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1089	__DSB();
<>	161:2cc1468da177	1090	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1091	__DSB();
<>	161:2cc1468da177	1092	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1093	__DSB();
<>	161:2cc1468da177	1094	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1095	__DSB();
<>	161:2cc1468da177	1096	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1097	__DSB();
<>	161:2cc1468da177	1098	}
<>	161:2cc1468da177	1099	}
<>	144:ef7eb2e8f9f7	1100
<>	144:ef7eb2e8f9f7	1101	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<>	144:ef7eb2e8f9f7	1102	__DSB();
<>	144:ef7eb2e8f9f7	1103
<>	161:2cc1468da177	1104	if(hnand->Config.ExtraCommandEnable == ENABLE)
<>	161:2cc1468da177	1105	{
<>	161:2cc1468da177	1106	/* Get tick */
<>	161:2cc1468da177	1107	tickstart = HAL_GetTick();
<>	161:2cc1468da177	1108
<>	161:2cc1468da177	1109	/* Read status until NAND is ready */
<>	161:2cc1468da177	1110	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	161:2cc1468da177	1111	{
<>	161:2cc1468da177	1112	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	161:2cc1468da177	1113	{
<>	161:2cc1468da177	1114	return HAL_TIMEOUT;
<>	161:2cc1468da177	1115	}
<>	161:2cc1468da177	1116	}
<>	161:2cc1468da177	1117
<>	161:2cc1468da177	1118	/* Go back to read mode */
<>	161:2cc1468da177	1119	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
<>	161:2cc1468da177	1120	__DSB();
<>	161:2cc1468da177	1121	}
<>	161:2cc1468da177	1122
<>	144:ef7eb2e8f9f7	1123	/* Get Data into Buffer */
<>	144:ef7eb2e8f9f7	1124	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	1125	{
<>	144:ef7eb2e8f9f7	1126	(uint8_t )pBuffer++ = (uint8_t )deviceAddress;
<>	144:ef7eb2e8f9f7	1127	}
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	/* Increment read spare areas number */
<>	144:ef7eb2e8f9f7	1130	numSpareAreaRead++;
<>	144:ef7eb2e8f9f7	1131
<>	144:ef7eb2e8f9f7	1132	/* Decrement spare areas to read */
<>	144:ef7eb2e8f9f7	1133	NumSpareAreaToRead--;
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135	/* Increment the NAND address */
<>	161:2cc1468da177	1136	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	1137	}
<>	144:ef7eb2e8f9f7	1138
<>	144:ef7eb2e8f9f7	1139	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1140	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1143	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	return HAL_OK;
<>	144:ef7eb2e8f9f7	1146	}
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/**
<>	144:ef7eb2e8f9f7	1149	* @brief Read Spare area(s) from NAND memory (16-bits addressing)
<>	144:ef7eb2e8f9f7	1150	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1151	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1152	* @param pAddress : pointer to NAND address structure
<>	161:2cc1468da177	1153	* @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
<>	144:ef7eb2e8f9f7	1154	* @param NumSpareAreaToRead: Number of spare area to read
<>	144:ef7eb2e8f9f7	1155	* @retval HAL status
<>	144:ef7eb2e8f9f7	1156	*/
<>	144:ef7eb2e8f9f7	1157	HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
<>	144:ef7eb2e8f9f7	1158	{
<>	144:ef7eb2e8f9f7	1159	__IO uint32_t index = 0;
<>	161:2cc1468da177	1160	uint32_t tickstart = 0U;
<>	161:2cc1468da177	1161	uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0, columnAddress = 0;
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	/* Process Locked */
<>	144:ef7eb2e8f9f7	1164	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1167	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1168	{
<>	144:ef7eb2e8f9f7	1169	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1170	}
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1173	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1176	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	/* NAND raw address calculation */
<>	161:2cc1468da177	1179	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	161:2cc1468da177	1180
<>	161:2cc1468da177	1181	/* Column in page address */
<>	161:2cc1468da177	1182	columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184	/* Spare area(s) read loop */
<>	161:2cc1468da177	1185	while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	1186	{
<>	144:ef7eb2e8f9f7	1187	/* update the buffer size */
<>	161:2cc1468da177	1188	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
<>	144:ef7eb2e8f9f7	1189
<>	161:2cc1468da177	1190	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	1191	if((hnand->Config.PageSize) <= 512)
<>	161:2cc1468da177	1192	{
<>	161:2cc1468da177	1193	/* Send read spare area command sequence */
<>	161:2cc1468da177	1194	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
<>	161:2cc1468da177	1195	__DSB();
<>	161:2cc1468da177	1196
<>	161:2cc1468da177	1197	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1198	{
<>	161:2cc1468da177	1199	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1200	__DSB();
<>	161:2cc1468da177	1201	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1202	__DSB();
<>	161:2cc1468da177	1203	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1204	__DSB();
<>	161:2cc1468da177	1205	}
<>	161:2cc1468da177	1206	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1207	{
<>	161:2cc1468da177	1208	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1209	__DSB();
<>	161:2cc1468da177	1210	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1211	__DSB();
<>	161:2cc1468da177	1212	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1213	__DSB();
<>	161:2cc1468da177	1214	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1215	__DSB();
<>	161:2cc1468da177	1216	}
<>	161:2cc1468da177	1217	}
<>	161:2cc1468da177	1218	else /* (hnand->Config.PageSize) > 512 */
<>	144:ef7eb2e8f9f7	1219	{
<>	161:2cc1468da177	1220	/* Send read spare area command sequence */
<>	161:2cc1468da177	1221	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	144:ef7eb2e8f9f7	1222	__DSB();
<>	161:2cc1468da177	1223
<>	161:2cc1468da177	1224	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1225	{
<>	161:2cc1468da177	1226	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1227	__DSB();
<>	161:2cc1468da177	1228	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1229	__DSB();
<>	161:2cc1468da177	1230	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1231	__DSB();
<>	161:2cc1468da177	1232	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1233	__DSB();
<>	161:2cc1468da177	1234	}
<>	161:2cc1468da177	1235	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1236	{
<>	161:2cc1468da177	1237	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1238	__DSB();
<>	161:2cc1468da177	1239	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1240	__DSB();
<>	161:2cc1468da177	1241	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1242	__DSB();
<>	161:2cc1468da177	1243	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1244	__DSB();
<>	161:2cc1468da177	1245	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1246	__DSB();
<>	161:2cc1468da177	1247	}
<>	161:2cc1468da177	1248	}
<>	144:ef7eb2e8f9f7	1249
<>	144:ef7eb2e8f9f7	1250	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_TRUE1;
<>	144:ef7eb2e8f9f7	1251	__DSB();
<>	161:2cc1468da177	1252
<>	161:2cc1468da177	1253	if(hnand->Config.ExtraCommandEnable == ENABLE)
<>	161:2cc1468da177	1254	{
<>	161:2cc1468da177	1255	/* Get tick */
<>	161:2cc1468da177	1256	tickstart = HAL_GetTick();
<>	161:2cc1468da177	1257
<>	161:2cc1468da177	1258	/* Read status until NAND is ready */
<>	161:2cc1468da177	1259	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	161:2cc1468da177	1260	{
<>	161:2cc1468da177	1261	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	161:2cc1468da177	1262	{
<>	161:2cc1468da177	1263	return HAL_TIMEOUT;
<>	161:2cc1468da177	1264	}
<>	161:2cc1468da177	1265	}
<>	161:2cc1468da177	1266
<>	161:2cc1468da177	1267	/* Go back to read mode */
<>	161:2cc1468da177	1268	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = ((uint8_t)0x00U);
<>	161:2cc1468da177	1269	__DSB();
<>	161:2cc1468da177	1270	}
<>	144:ef7eb2e8f9f7	1271
<>	144:ef7eb2e8f9f7	1272	/* Get Data into Buffer */
<>	144:ef7eb2e8f9f7	1273	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	1274	{
<>	144:ef7eb2e8f9f7	1275	(uint16_t )pBuffer++ = (uint16_t )deviceAddress;
<>	144:ef7eb2e8f9f7	1276	}
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	/* Increment read spare areas number */
<>	144:ef7eb2e8f9f7	1279	numSpareAreaRead++;
<>	144:ef7eb2e8f9f7	1280
<>	144:ef7eb2e8f9f7	1281	/* Decrement spare areas to read */
<>	144:ef7eb2e8f9f7	1282	NumSpareAreaToRead--;
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/* Increment the NAND address */
<>	161:2cc1468da177	1285	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	1286	}
<>	144:ef7eb2e8f9f7	1287
<>	144:ef7eb2e8f9f7	1288	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1289	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1292	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1293
<>	144:ef7eb2e8f9f7	1294	return HAL_OK;
<>	144:ef7eb2e8f9f7	1295	}
<>	144:ef7eb2e8f9f7	1296
<>	144:ef7eb2e8f9f7	1297	/**
<>	144:ef7eb2e8f9f7	1298	* @brief Write Spare area(s) to NAND memory (8-bits addressing)
<>	144:ef7eb2e8f9f7	1299	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1300	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1301	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	1302	* @param pBuffer : pointer to source buffer to write
<>	144:ef7eb2e8f9f7	1303	* @param NumSpareAreaTowrite : number of spare areas to write to block
<>	144:ef7eb2e8f9f7	1304	* @retval HAL status
<>	144:ef7eb2e8f9f7	1305	*/
<>	144:ef7eb2e8f9f7	1306	HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
<>	144:ef7eb2e8f9f7	1307	{
<>	144:ef7eb2e8f9f7	1308	__IO uint32_t index = 0;
<>	144:ef7eb2e8f9f7	1309	uint32_t tickstart = 0;
<>	161:2cc1468da177	1310	uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress =0;
<>	144:ef7eb2e8f9f7	1311
<>	144:ef7eb2e8f9f7	1312	/* Process Locked */
<>	144:ef7eb2e8f9f7	1313	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	1314
<>	144:ef7eb2e8f9f7	1315	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1316	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1317	{
<>	144:ef7eb2e8f9f7	1318	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1319	}
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1322	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/* Update the FMC_NAND controller state */
<>	144:ef7eb2e8f9f7	1325	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1326
<>	161:2cc1468da177	1327	/* Page address calculation */
<>	161:2cc1468da177	1328	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	161:2cc1468da177	1329
<>	161:2cc1468da177	1330	/* Column in page address */
<>	161:2cc1468da177	1331	columnAddress = COLUMN_ADDRESS(hnand);
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	/* Spare area(s) write loop */
<>	161:2cc1468da177	1334	while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	1335	{
<>	144:ef7eb2e8f9f7	1336	/* update the buffer size */
<>	161:2cc1468da177	1337	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
<>	144:ef7eb2e8f9f7	1338
<>	161:2cc1468da177	1339	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	1340	if((hnand->Config.PageSize) <= 512)
<>	144:ef7eb2e8f9f7	1341	{
<>	161:2cc1468da177	1342	/* Send write Spare area command sequence */
<>	161:2cc1468da177	1343	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
<>	161:2cc1468da177	1344	__DSB();
<>	161:2cc1468da177	1345	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
<>	144:ef7eb2e8f9f7	1346	__DSB();
<>	161:2cc1468da177	1347
<>	161:2cc1468da177	1348	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1349	{
<>	161:2cc1468da177	1350	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1351	__DSB();
<>	161:2cc1468da177	1352	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1353	__DSB();
<>	161:2cc1468da177	1354	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1355	__DSB();
<>	161:2cc1468da177	1356	}
<>	161:2cc1468da177	1357	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1358	{
<>	161:2cc1468da177	1359	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1360	__DSB();
<>	161:2cc1468da177	1361	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1362	__DSB();
<>	161:2cc1468da177	1363	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1364	__DSB();
<>	161:2cc1468da177	1365	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1366	__DSB();
<>	161:2cc1468da177	1367	}
<>	161:2cc1468da177	1368	}
<>	161:2cc1468da177	1369	else /* (hnand->Config.PageSize) > 512 */
<>	161:2cc1468da177	1370	{
<>	161:2cc1468da177	1371	/* Send write Spare area command sequence */
<>	161:2cc1468da177	1372	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	161:2cc1468da177	1373	__DSB();
<>	161:2cc1468da177	1374	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
<>	161:2cc1468da177	1375	__DSB();
<>	161:2cc1468da177	1376
<>	161:2cc1468da177	1377	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1378	{
<>	161:2cc1468da177	1379	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1380	__DSB();
<>	161:2cc1468da177	1381	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1382	__DSB();
<>	161:2cc1468da177	1383	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1384	__DSB();
<>	161:2cc1468da177	1385	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1386	__DSB();
<>	161:2cc1468da177	1387	}
<>	161:2cc1468da177	1388	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1389	{
<>	161:2cc1468da177	1390	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1391	__DSB();
<>	161:2cc1468da177	1392	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1393	__DSB();
<>	161:2cc1468da177	1394	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1395	__DSB();
<>	161:2cc1468da177	1396	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1397	__DSB();
<>	161:2cc1468da177	1398	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1399	__DSB();
<>	161:2cc1468da177	1400	}
<>	144:ef7eb2e8f9f7	1401	}
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403	/* Write data to memory */
<>	144:ef7eb2e8f9f7	1404	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	1405	{
<>	144:ef7eb2e8f9f7	1406	(__IO uint8_t )deviceAddress = (uint8_t )pBuffer++;
<>	144:ef7eb2e8f9f7	1407	__DSB();
<>	144:ef7eb2e8f9f7	1408	}
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<>	144:ef7eb2e8f9f7	1411	__DSB();
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	/* Read status until NAND is ready */
<>	144:ef7eb2e8f9f7	1414	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	1415	{
<>	144:ef7eb2e8f9f7	1416	/* Get tick */
<>	144:ef7eb2e8f9f7	1417	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1418
<>	144:ef7eb2e8f9f7	1419	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	144:ef7eb2e8f9f7	1420	{
<>	144:ef7eb2e8f9f7	1421	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1422	}
<>	144:ef7eb2e8f9f7	1423	}
<>	144:ef7eb2e8f9f7	1424
<>	144:ef7eb2e8f9f7	1425	/* Increment written spare areas number */
<>	144:ef7eb2e8f9f7	1426	numSpareAreaWritten++;
<>	144:ef7eb2e8f9f7	1427
<>	144:ef7eb2e8f9f7	1428	/* Decrement spare areas to write */
<>	144:ef7eb2e8f9f7	1429	NumSpareAreaTowrite--;
<>	144:ef7eb2e8f9f7	1430
<>	144:ef7eb2e8f9f7	1431	/* Increment the NAND address */
<>	161:2cc1468da177	1432	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	1433	}
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1436	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1437
<>	144:ef7eb2e8f9f7	1438	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1439	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	return HAL_OK;
<>	144:ef7eb2e8f9f7	1442	}
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	/**
<>	144:ef7eb2e8f9f7	1445	* @brief Write Spare area(s) to NAND memory (16-bits addressing)
<>	144:ef7eb2e8f9f7	1446	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1447	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1448	* @param pAddress : pointer to NAND address structure
<>	161:2cc1468da177	1449	* @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
<>	144:ef7eb2e8f9f7	1450	* @param NumSpareAreaTowrite : number of spare areas to write to block
<>	144:ef7eb2e8f9f7	1451	* @retval HAL status
<>	144:ef7eb2e8f9f7	1452	*/
<>	144:ef7eb2e8f9f7	1453	HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
<>	144:ef7eb2e8f9f7	1454	{
<>	144:ef7eb2e8f9f7	1455	__IO uint32_t index = 0;
<>	144:ef7eb2e8f9f7	1456	uint32_t tickstart = 0;
<>	161:2cc1468da177	1457	uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0, columnAddress = 0;
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	/* Process Locked */
<>	144:ef7eb2e8f9f7	1460	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1463	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1464	{
<>	144:ef7eb2e8f9f7	1465	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1466	}
<>	144:ef7eb2e8f9f7	1467
<>	144:ef7eb2e8f9f7	1468	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1469	deviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	1470
<>	144:ef7eb2e8f9f7	1471	/* Update the FMC_NAND controller state */
<>	144:ef7eb2e8f9f7	1472	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1473
<>	144:ef7eb2e8f9f7	1474	/* NAND raw address calculation */
<>	161:2cc1468da177	1475	nandAddress = ARRAY_ADDRESS(pAddress, hnand);
<>	161:2cc1468da177	1476
<>	161:2cc1468da177	1477	/* Column in page address */
<>	161:2cc1468da177	1478	columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2);
<>	144:ef7eb2e8f9f7	1479
<>	144:ef7eb2e8f9f7	1480	/* Spare area(s) write loop */
<>	161:2cc1468da177	1481	while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
<>	144:ef7eb2e8f9f7	1482	{
<>	144:ef7eb2e8f9f7	1483	/* update the buffer size */
<>	161:2cc1468da177	1484	size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
<>	144:ef7eb2e8f9f7	1485
<>	161:2cc1468da177	1486	/* Cards with page size <= 512 bytes */
<>	161:2cc1468da177	1487	if((hnand->Config.PageSize) <= 512)
<>	144:ef7eb2e8f9f7	1488	{
<>	161:2cc1468da177	1489	/* Send write Spare area command sequence */
<>	161:2cc1468da177	1490	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_C;
<>	161:2cc1468da177	1491	__DSB();
<>	161:2cc1468da177	1492	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
<>	144:ef7eb2e8f9f7	1493	__DSB();
<>	161:2cc1468da177	1494
<>	161:2cc1468da177	1495	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1496	{
<>	161:2cc1468da177	1497	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1498	__DSB();
<>	161:2cc1468da177	1499	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1500	__DSB();
<>	161:2cc1468da177	1501	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1502	__DSB();
<>	161:2cc1468da177	1503	}
<>	161:2cc1468da177	1504	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1505	{
<>	161:2cc1468da177	1506	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = 0x00;
<>	161:2cc1468da177	1507	__DSB();
<>	161:2cc1468da177	1508	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1509	__DSB();
<>	161:2cc1468da177	1510	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1511	__DSB();
<>	161:2cc1468da177	1512	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1513	__DSB();
<>	161:2cc1468da177	1514	}
<>	161:2cc1468da177	1515	}
<>	161:2cc1468da177	1516	else /* (hnand->Config.PageSize) > 512 */
<>	161:2cc1468da177	1517	{
<>	161:2cc1468da177	1518	/* Send write Spare area command sequence */
<>	161:2cc1468da177	1519	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_AREA_A;
<>	161:2cc1468da177	1520	__DSB();
<>	161:2cc1468da177	1521	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE0;
<>	161:2cc1468da177	1522	__DSB();
<>	161:2cc1468da177	1523
<>	161:2cc1468da177	1524	if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535)
<>	161:2cc1468da177	1525	{
<>	161:2cc1468da177	1526	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1527	__DSB();
<>	161:2cc1468da177	1528	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1529	__DSB();
<>	161:2cc1468da177	1530	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1531	__DSB();
<>	161:2cc1468da177	1532	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1533	__DSB();
<>	161:2cc1468da177	1534	}
<>	161:2cc1468da177	1535	else /* ((hnand->Config.BlockSize)(hnand->Config.BlockNbr)) > 65535 /
<>	161:2cc1468da177	1536	{
<>	161:2cc1468da177	1537	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
<>	161:2cc1468da177	1538	__DSB();
<>	161:2cc1468da177	1539	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
<>	161:2cc1468da177	1540	__DSB();
<>	161:2cc1468da177	1541	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
<>	161:2cc1468da177	1542	__DSB();
<>	161:2cc1468da177	1543	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
<>	161:2cc1468da177	1544	__DSB();
<>	161:2cc1468da177	1545	(__IO uint8_t )((uint32_t)(deviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
<>	161:2cc1468da177	1546	__DSB();
<>	161:2cc1468da177	1547	}
<>	144:ef7eb2e8f9f7	1548	}
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Write data to memory */
<>	144:ef7eb2e8f9f7	1551	for(; index < size; index++)
<>	144:ef7eb2e8f9f7	1552	{
<>	144:ef7eb2e8f9f7	1553	(__IO uint16_t )deviceAddress = (uint16_t )pBuffer++;
<>	144:ef7eb2e8f9f7	1554	__DSB();
<>	144:ef7eb2e8f9f7	1555	}
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	(__IO uint8_t )((uint32_t)(deviceAddress \| CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
<>	144:ef7eb2e8f9f7	1558	__DSB();
<>	144:ef7eb2e8f9f7	1559
<>	144:ef7eb2e8f9f7	1560	/* Read status until NAND is ready */
<>	144:ef7eb2e8f9f7	1561	while(HAL_NAND_Read_Status(hnand) != NAND_READY)
<>	144:ef7eb2e8f9f7	1562	{
<>	144:ef7eb2e8f9f7	1563	/* Get tick */
<>	144:ef7eb2e8f9f7	1564	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1565
<>	144:ef7eb2e8f9f7	1566	if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
<>	144:ef7eb2e8f9f7	1567	{
<>	144:ef7eb2e8f9f7	1568	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1569	}
<>	144:ef7eb2e8f9f7	1570	}
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/* Increment written spare areas number */
<>	144:ef7eb2e8f9f7	1573	numSpareAreaWritten++;
<>	144:ef7eb2e8f9f7	1574
<>	144:ef7eb2e8f9f7	1575	/* Decrement spare areas to write */
<>	144:ef7eb2e8f9f7	1576	NumSpareAreaTowrite--;
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	/* Increment the NAND address */
<>	161:2cc1468da177	1579	nandAddress = (uint32_t)(nandAddress + 1);
<>	144:ef7eb2e8f9f7	1580	}
<>	144:ef7eb2e8f9f7	1581
<>	144:ef7eb2e8f9f7	1582	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1583	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1586	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1587
<>	144:ef7eb2e8f9f7	1588	return HAL_OK;
<>	144:ef7eb2e8f9f7	1589	}
<>	144:ef7eb2e8f9f7	1590
<>	144:ef7eb2e8f9f7	1591	/**
<>	144:ef7eb2e8f9f7	1592	* @brief NAND memory Block erase
<>	144:ef7eb2e8f9f7	1593	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1594	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1595	* @param pAddress : pointer to NAND address structure
<>	144:ef7eb2e8f9f7	1596	* @retval HAL status
<>	144:ef7eb2e8f9f7	1597	*/
<>	144:ef7eb2e8f9f7	1598	HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress)
<>	144:ef7eb2e8f9f7	1599	{
<>	144:ef7eb2e8f9f7	1600	uint32_t DeviceAddress = 0;
<>	144:ef7eb2e8f9f7	1601
<>	144:ef7eb2e8f9f7	1602	/* Process Locked */
<>	144:ef7eb2e8f9f7	1603	__HAL_LOCK(hnand);
<>	144:ef7eb2e8f9f7	1604
<>	144:ef7eb2e8f9f7	1605	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1606	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1607	{
<>	144:ef7eb2e8f9f7	1608	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1609	}
<>	144:ef7eb2e8f9f7	1610
<>	144:ef7eb2e8f9f7	1611	/* Identify the device address */
<>	144:ef7eb2e8f9f7	1612	DeviceAddress = NAND_DEVICE;
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1615	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1616
<>	144:ef7eb2e8f9f7	1617	/* Send Erase block command sequence */
<>	144:ef7eb2e8f9f7	1618	(__IO uint8_t )((uint32_t)(DeviceAddress \| CMD_AREA)) = NAND_CMD_ERASE0;
<>	144:ef7eb2e8f9f7	1619	__DSB();
<>	144:ef7eb2e8f9f7	1620	(__IO uint8_t )((uint32_t)(DeviceAddress \| ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<>	144:ef7eb2e8f9f7	1621	__DSB();
<>	144:ef7eb2e8f9f7	1622	(__IO uint8_t )((uint32_t)(DeviceAddress \| ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<>	144:ef7eb2e8f9f7	1623	__DSB();
<>	144:ef7eb2e8f9f7	1624	(__IO uint8_t )((uint32_t)(DeviceAddress \| ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
<>	144:ef7eb2e8f9f7	1625	__DSB();
<>	144:ef7eb2e8f9f7	1626
<>	144:ef7eb2e8f9f7	1627	(__IO uint8_t )((uint32_t)(DeviceAddress \| CMD_AREA)) = NAND_CMD_ERASE1;
<>	144:ef7eb2e8f9f7	1628	__DSB();
<>	144:ef7eb2e8f9f7	1629
<>	144:ef7eb2e8f9f7	1630	/* Update the NAND controller state */
<>	144:ef7eb2e8f9f7	1631	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1632
<>	144:ef7eb2e8f9f7	1633	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1634	__HAL_UNLOCK(hnand);
<>	144:ef7eb2e8f9f7	1635
<>	144:ef7eb2e8f9f7	1636	return HAL_OK;
<>	144:ef7eb2e8f9f7	1637	}
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	/**
<>	144:ef7eb2e8f9f7	1640	* @brief Increment the NAND memory address
<>	144:ef7eb2e8f9f7	1641	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1642	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1643	* @param pAddress: pointer to NAND address structure
<>	144:ef7eb2e8f9f7	1644	* @retval The new status of the increment address operation. It can be:
<>	144:ef7eb2e8f9f7	1645	* - NAND_VALID_ADDRESS: When the new address is valid address
<>	144:ef7eb2e8f9f7	1646	* - NAND_INVALID_ADDRESS: When the new address is invalid address
<>	144:ef7eb2e8f9f7	1647	*/
<>	144:ef7eb2e8f9f7	1648	uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef hnand, NAND_AddressTypeDef pAddress)
<>	144:ef7eb2e8f9f7	1649	{
<>	144:ef7eb2e8f9f7	1650	uint32_t status = NAND_VALID_ADDRESS;
<>	144:ef7eb2e8f9f7	1651
<>	144:ef7eb2e8f9f7	1652	/* Increment page address */
<>	144:ef7eb2e8f9f7	1653	pAddress->Page++;
<>	144:ef7eb2e8f9f7	1654
<>	144:ef7eb2e8f9f7	1655	/* Check NAND address is valid */
<>	161:2cc1468da177	1656	if(pAddress->Page == hnand->Config.BlockSize)
<>	144:ef7eb2e8f9f7	1657	{
<>	144:ef7eb2e8f9f7	1658	pAddress->Page = 0;
<>	144:ef7eb2e8f9f7	1659	pAddress->Block++;
<>	144:ef7eb2e8f9f7	1660
<>	161:2cc1468da177	1661	if(pAddress->Block == hnand->Config.PlaneSize)
<>	144:ef7eb2e8f9f7	1662	{
<>	144:ef7eb2e8f9f7	1663	pAddress->Block = 0;
<>	161:2cc1468da177	1664	pAddress->Plane++;
<>	144:ef7eb2e8f9f7	1665
<>	161:2cc1468da177	1666	if(pAddress->Plane == (hnand->Config.PlaneSize/ hnand->Config.BlockNbr))
<>	144:ef7eb2e8f9f7	1667	{
<>	144:ef7eb2e8f9f7	1668	status = NAND_INVALID_ADDRESS;
<>	144:ef7eb2e8f9f7	1669	}
<>	144:ef7eb2e8f9f7	1670	}
<>	144:ef7eb2e8f9f7	1671	}
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673	return (status);
<>	144:ef7eb2e8f9f7	1674	}
<>	144:ef7eb2e8f9f7	1675	/**
<>	144:ef7eb2e8f9f7	1676	* @}
<>	144:ef7eb2e8f9f7	1677	*/
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1680	* @brief management functions
<>	144:ef7eb2e8f9f7	1681	*
<>	144:ef7eb2e8f9f7	1682	@verbatim
<>	144:ef7eb2e8f9f7	1683	==============================================================================
<>	144:ef7eb2e8f9f7	1684	##### NAND Control functions #####
<>	144:ef7eb2e8f9f7	1685	==============================================================================
<>	144:ef7eb2e8f9f7	1686	[..]
<>	144:ef7eb2e8f9f7	1687	This subsection provides a set of functions allowing to control dynamically
<>	144:ef7eb2e8f9f7	1688	the NAND interface.
<>	144:ef7eb2e8f9f7	1689
<>	144:ef7eb2e8f9f7	1690	@endverbatim
<>	144:ef7eb2e8f9f7	1691	* @{
<>	144:ef7eb2e8f9f7	1692	*/
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/**
<>	144:ef7eb2e8f9f7	1696	* @brief Enables dynamically NAND ECC feature.
<>	144:ef7eb2e8f9f7	1697	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1698	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1699	* @retval HAL status
<>	144:ef7eb2e8f9f7	1700	*/
<>	144:ef7eb2e8f9f7	1701	HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	1702	{
<>	144:ef7eb2e8f9f7	1703	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1704	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1705	{
<>	144:ef7eb2e8f9f7	1706	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1707	}
<>	144:ef7eb2e8f9f7	1708
<>	144:ef7eb2e8f9f7	1709	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1710	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1711
<>	144:ef7eb2e8f9f7	1712	/* Enable ECC feature */
<>	144:ef7eb2e8f9f7	1713	FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	1714
<>	144:ef7eb2e8f9f7	1715	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1716	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1717
<>	144:ef7eb2e8f9f7	1718	return HAL_OK;
<>	144:ef7eb2e8f9f7	1719	}
<>	144:ef7eb2e8f9f7	1720
<>	144:ef7eb2e8f9f7	1721	/**
<>	144:ef7eb2e8f9f7	1722	* @brief Disables dynamically FMC_NAND ECC feature.
<>	144:ef7eb2e8f9f7	1723	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1724	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1725	* @retval HAL status
<>	144:ef7eb2e8f9f7	1726	*/
<>	144:ef7eb2e8f9f7	1727	HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	1728	{
<>	144:ef7eb2e8f9f7	1729	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1730	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1731	{
<>	144:ef7eb2e8f9f7	1732	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1733	}
<>	144:ef7eb2e8f9f7	1734
<>	144:ef7eb2e8f9f7	1735	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1736	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1737
<>	144:ef7eb2e8f9f7	1738	/* Disable ECC feature */
<>	144:ef7eb2e8f9f7	1739	FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
<>	144:ef7eb2e8f9f7	1740
<>	144:ef7eb2e8f9f7	1741	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1742	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1743
<>	144:ef7eb2e8f9f7	1744	return HAL_OK;
<>	144:ef7eb2e8f9f7	1745	}
<>	144:ef7eb2e8f9f7	1746
<>	144:ef7eb2e8f9f7	1747	/**
<>	144:ef7eb2e8f9f7	1748	* @brief Disables dynamically NAND ECC feature.
<>	144:ef7eb2e8f9f7	1749	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1750	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1751	* @param ECCval: pointer to ECC value
<>	144:ef7eb2e8f9f7	1752	* @param Timeout: maximum timeout to wait
<>	144:ef7eb2e8f9f7	1753	* @retval HAL status
<>	144:ef7eb2e8f9f7	1754	*/
<>	144:ef7eb2e8f9f7	1755	HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef hnand, uint32_t ECCval, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1756	{
<>	144:ef7eb2e8f9f7	1757	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	/* Check the NAND controller state */
<>	144:ef7eb2e8f9f7	1760	if(hnand->State == HAL_NAND_STATE_BUSY)
<>	144:ef7eb2e8f9f7	1761	{
<>	144:ef7eb2e8f9f7	1762	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1763	}
<>	144:ef7eb2e8f9f7	1764
<>	144:ef7eb2e8f9f7	1765	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1766	hnand->State = HAL_NAND_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1767
<>	144:ef7eb2e8f9f7	1768	/* Get NAND ECC value */
<>	144:ef7eb2e8f9f7	1769	status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/* Update the NAND state */
<>	144:ef7eb2e8f9f7	1772	hnand->State = HAL_NAND_STATE_READY;
<>	144:ef7eb2e8f9f7	1773
<>	144:ef7eb2e8f9f7	1774	return status;
<>	144:ef7eb2e8f9f7	1775	}
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/**
<>	144:ef7eb2e8f9f7	1778	* @}
<>	144:ef7eb2e8f9f7	1779	*/
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781
<>	144:ef7eb2e8f9f7	1782	/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
<>	144:ef7eb2e8f9f7	1783	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	1784	*
<>	144:ef7eb2e8f9f7	1785	@verbatim
<>	144:ef7eb2e8f9f7	1786	==============================================================================
<>	144:ef7eb2e8f9f7	1787	##### NAND State functions #####
<>	144:ef7eb2e8f9f7	1788	==============================================================================
<>	144:ef7eb2e8f9f7	1789	[..]
<>	144:ef7eb2e8f9f7	1790	This subsection permits to get in run-time the status of the NAND controller
<>	144:ef7eb2e8f9f7	1791	and the data flow.
<>	144:ef7eb2e8f9f7	1792
<>	144:ef7eb2e8f9f7	1793	@endverbatim
<>	144:ef7eb2e8f9f7	1794	* @{
<>	144:ef7eb2e8f9f7	1795	*/
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797	/**
<>	144:ef7eb2e8f9f7	1798	* @brief return the NAND state
<>	144:ef7eb2e8f9f7	1799	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1800	* the configuration information for NAND module.
<>	144:ef7eb2e8f9f7	1801	* @retval HAL state
<>	144:ef7eb2e8f9f7	1802	*/
<>	144:ef7eb2e8f9f7	1803	HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
<>	144:ef7eb2e8f9f7	1804	{
<>	144:ef7eb2e8f9f7	1805	return hnand->State;
<>	144:ef7eb2e8f9f7	1806	}
<>	144:ef7eb2e8f9f7	1807
<>	144:ef7eb2e8f9f7	1808	/**
<>	161:2cc1468da177	1809	* @brief NAND memory read status
<>	161:2cc1468da177	1810	* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
<>	161:2cc1468da177	1811	* the configuration information for NAND module.
<>	161:2cc1468da177	1812	* @retval NAND status
<>	161:2cc1468da177	1813	*/
<>	161:2cc1468da177	1814	uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
<>	161:2cc1468da177	1815	{
<>	161:2cc1468da177	1816	uint32_t data = 0;
<>	161:2cc1468da177	1817	uint32_t DeviceAddress = 0;
<>	161:2cc1468da177	1818
<>	161:2cc1468da177	1819	/* Identify the device address */
<>	161:2cc1468da177	1820	DeviceAddress = NAND_DEVICE;
<>	161:2cc1468da177	1821
<>	161:2cc1468da177	1822	/* Send Read status operation command */
<>	161:2cc1468da177	1823	(__IO uint8_t )((uint32_t)(DeviceAddress \| CMD_AREA)) = NAND_CMD_STATUS;
<>	161:2cc1468da177	1824
<>	161:2cc1468da177	1825	/* Read status register data */
<>	161:2cc1468da177	1826	data = (__IO uint8_t )DeviceAddress;
<>	161:2cc1468da177	1827
<>	161:2cc1468da177	1828	/* Return the status */
<>	161:2cc1468da177	1829	if((data & NAND_ERROR) == NAND_ERROR)
<>	161:2cc1468da177	1830	{
<>	161:2cc1468da177	1831	return NAND_ERROR;
<>	161:2cc1468da177	1832	}
<>	161:2cc1468da177	1833	else if((data & NAND_READY) == NAND_READY)
<>	161:2cc1468da177	1834	{
<>	161:2cc1468da177	1835	return NAND_READY;
<>	161:2cc1468da177	1836	}
<>	161:2cc1468da177	1837
<>	161:2cc1468da177	1838	return NAND_BUSY;
<>	161:2cc1468da177	1839	}
<>	161:2cc1468da177	1840
<>	161:2cc1468da177	1841	/**
<>	144:ef7eb2e8f9f7	1842	* @}
<>	144:ef7eb2e8f9f7	1843	*/
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845	/**
<>	144:ef7eb2e8f9f7	1846	* @}
<>	144:ef7eb2e8f9f7	1847	*/
<>	144:ef7eb2e8f9f7	1848
<>	144:ef7eb2e8f9f7	1849	#endif /* HAL_NAND_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	1850
<>	144:ef7eb2e8f9f7	1851	/**
<>	144:ef7eb2e8f9f7	1852	* @}
<>	144:ef7eb2e8f9f7	1853	*/
<>	144:ef7eb2e8f9f7	1854
<>	144:ef7eb2e8f9f7	1855	/**
<>	144:ef7eb2e8f9f7	1856	* @}
<>	144:ef7eb2e8f9f7	1857	*/
<>	144:ef7eb2e8f9f7	1858
<>	144:ef7eb2e8f9f7	1859	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/