mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
161:2cc1468da177
Child:
168:9672193075cf
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_i2s.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief I2S HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Integrated Interchip Sound (I2S) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ===============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ===============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 The I2S HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (#) Declare a I2S_HandleTypeDef handle structure.
<> 144:ef7eb2e8f9f7 21 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
<> 144:ef7eb2e8f9f7 22 (##) Enable the SPIx interface clock.
<> 144:ef7eb2e8f9f7 23 (##) I2S pins configuration:
<> 144:ef7eb2e8f9f7 24 (+++) Enable the clock for the I2S GPIOs.
<> 144:ef7eb2e8f9f7 25 (+++) Configure these I2S pins as alternate function pull-up.
<> 144:ef7eb2e8f9f7 26 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 27 and HAL_I2S_Receive_IT() APIs).
<> 144:ef7eb2e8f9f7 28 (+++) Configure the I2Sx interrupt priority.
<> 144:ef7eb2e8f9f7 29 (+++) Enable the NVIC I2S IRQ handle.
<> 144:ef7eb2e8f9f7 30 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 31 and HAL_I2S_Receive_DMA() APIs:
<> 144:ef7eb2e8f9f7 32 (+++) Declare a DMA handle structure for the Tx/Rx channel.
<> 144:ef7eb2e8f9f7 33 (+++) Enable the DMAx interface clock.
<> 144:ef7eb2e8f9f7 34 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
<> 144:ef7eb2e8f9f7 35 (+++) Configure the DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 36 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
<> 144:ef7eb2e8f9f7 37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
<> 144:ef7eb2e8f9f7 38 DMA Tx/Rx Channel.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
<> 144:ef7eb2e8f9f7 41 using HAL_I2S_Init() function.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 -@- The specific I2S interrupts (Transmission complete interrupt,
<> 144:ef7eb2e8f9f7 44 RXNE interrupt and Error Interrupts) will be managed using the macros
<> 144:ef7eb2e8f9f7 45 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
<> 144:ef7eb2e8f9f7 46 -@- Make sure that either:
<> 144:ef7eb2e8f9f7 47 (+@) I2S clock is configured based on SYSCLK or
<> 144:ef7eb2e8f9f7 48 (+@) External clock source is configured after setting correctly
<> 144:ef7eb2e8f9f7 49 the define constant EXTERNAL_CLOCK_VALUE in the stm32f3xx_hal_conf.h file.
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 (#) Three mode of operations are available within this driver :
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 54 =================================
<> 144:ef7eb2e8f9f7 55 [..]
<> 144:ef7eb2e8f9f7 56 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 57 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 60 ===================================
<> 144:ef7eb2e8f9f7 61 [..]
<> 144:ef7eb2e8f9f7 62 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 63 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 64 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 65 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 66 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 67 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 68 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 69 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 70 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 71 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 72 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 73 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 *** DMA mode IO operation ***
<> 144:ef7eb2e8f9f7 76 ==============================
<> 144:ef7eb2e8f9f7 77 [..]
<> 144:ef7eb2e8f9f7 78 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 79 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 80 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
<> 144:ef7eb2e8f9f7 81 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 82 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
<> 144:ef7eb2e8f9f7 83 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 84 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 85 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
<> 144:ef7eb2e8f9f7 86 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
<> 144:ef7eb2e8f9f7 87 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
<> 144:ef7eb2e8f9f7 88 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
<> 144:ef7eb2e8f9f7 89 add his own code by customization of function pointer HAL_I2S_ErrorCallback
<> 144:ef7eb2e8f9f7 90 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
<> 144:ef7eb2e8f9f7 91 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
<> 144:ef7eb2e8f9f7 92 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 *** I2S HAL driver macros list ***
<> 144:ef7eb2e8f9f7 95 =============================================
<> 144:ef7eb2e8f9f7 96 [..]
<> 144:ef7eb2e8f9f7 97 Below the list of most used macros in I2S HAL driver.
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 100 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
<> 144:ef7eb2e8f9f7 101 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 102 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
<> 144:ef7eb2e8f9f7 103 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 [..]
<> 144:ef7eb2e8f9f7 106 (@) You can refer to the I2S HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 @endverbatim
<> 144:ef7eb2e8f9f7 109 ******************************************************************************
<> 144:ef7eb2e8f9f7 110 * @attention
<> 144:ef7eb2e8f9f7 111 *
<> 144:ef7eb2e8f9f7 112 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 115 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 116 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 117 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 118 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 119 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 120 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 121 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 122 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 123 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 126 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 127 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 128 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 129 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 130 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 131 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 132 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 133 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 134 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 ******************************************************************************
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 143 * @{
<> 144:ef7eb2e8f9f7 144 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** @defgroup I2S I2S
<> 144:ef7eb2e8f9f7 147 * @brief I2S HAL module driver
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 #ifdef HAL_I2S_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 154 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 155 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 156 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 157 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 158 /** @defgroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 163 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 164 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 165 static void I2S_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 166 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 167 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 168 static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 169 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @defgroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 181 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 182 *
<> 144:ef7eb2e8f9f7 183 @verbatim
<> 144:ef7eb2e8f9f7 184 ===============================================================================
<> 144:ef7eb2e8f9f7 185 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 186 ===============================================================================
<> 144:ef7eb2e8f9f7 187 [..] This subsection provides a set of functions allowing to initialize and
<> 144:ef7eb2e8f9f7 188 de-initialize the I2Sx peripheral in simplex mode:
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 (+) User must Implement HAL_I2S_MspInit() function in which he configures
<> 144:ef7eb2e8f9f7 191 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 (+) Call the function HAL_I2S_Init() to configure the selected device with
<> 144:ef7eb2e8f9f7 194 the selected configuration:
<> 144:ef7eb2e8f9f7 195 (++) Mode
<> 144:ef7eb2e8f9f7 196 (++) Standard
<> 144:ef7eb2e8f9f7 197 (++) Data Format
<> 144:ef7eb2e8f9f7 198 (++) MCLK Output
<> 144:ef7eb2e8f9f7 199 (++) Audio frequency
<> 144:ef7eb2e8f9f7 200 (++) Polarity
<> 144:ef7eb2e8f9f7 201 (++) Full duplex mode
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 (+) Call the function HAL_I2S_DeInit() to restore the default configuration
<> 144:ef7eb2e8f9f7 204 of the selected I2Sx peripheral.
<> 144:ef7eb2e8f9f7 205 @endverbatim
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @brief Initializes the I2S according to the specified parameters
<> 144:ef7eb2e8f9f7 211 * in the I2S_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 212 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 213 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 214 * @retval HAL status
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
<> 144:ef7eb2e8f9f7 219 uint32_t tmp = 0, i2sclk = 0;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 222 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /* Check the parameters */
<> 144:ef7eb2e8f9f7 228 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 229 assert_param(IS_I2S_MODE(hi2s->Init.Mode));
<> 144:ef7eb2e8f9f7 230 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
<> 144:ef7eb2e8f9f7 231 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
<> 144:ef7eb2e8f9f7 232 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 233 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
<> 144:ef7eb2e8f9f7 234 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
<> 144:ef7eb2e8f9f7 235 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 if(hi2s->State == HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 240 hi2s->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 241 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
<> 144:ef7eb2e8f9f7 242 HAL_I2S_MspInit(hi2s);
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
<> 144:ef7eb2e8f9f7 248 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
<> 144:ef7eb2e8f9f7 249 hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
<> 144:ef7eb2e8f9f7 250 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
<> 144:ef7eb2e8f9f7 251 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
<> 144:ef7eb2e8f9f7 252 hi2s->Instance->I2SPR = 0x0002;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Get the I2SCFGR register value */
<> 144:ef7eb2e8f9f7 255 tmpreg = hi2s->Instance->I2SCFGR;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
<> 144:ef7eb2e8f9f7 258 if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 i2sodd = (uint16_t)0;
<> 144:ef7eb2e8f9f7 261 i2sdiv = (uint16_t)2;
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263 /* If the requested audio frequency is not the default, compute the prescaler */
<> 144:ef7eb2e8f9f7 264 else
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 /* Check the frame length (For the Prescaler computing) *******************/
<> 144:ef7eb2e8f9f7 267 if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 /* Packet length is 16 bits */
<> 144:ef7eb2e8f9f7 270 packetlength = 1;
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 else
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 /* Packet length is 32 bits */
<> 144:ef7eb2e8f9f7 275 packetlength = 2;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /* Get I2S source Clock frequency ****************************************/
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* If an external I2S clock has to be used, the specific define should be set
<> 144:ef7eb2e8f9f7 281 in the project configuration or in the stm32f3xx_conf.h file */
<> 144:ef7eb2e8f9f7 282 if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 /* Set the I2S clock to the external clock value */
<> 144:ef7eb2e8f9f7 285 i2sclk = EXTERNAL_CLOCK_VALUE;
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287 else
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Get the I2S source clock value */
<> 144:ef7eb2e8f9f7 290 i2sclk = I2S_GetClockFreq(hi2s);
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /* Compute the Real divider depending on the MCLK output state, with a floating point */
<> 144:ef7eb2e8f9f7 294 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 /* MCLK output is enabled */
<> 144:ef7eb2e8f9f7 297 tmp = (uint16_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299 else
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 /* MCLK output is disabled */
<> 144:ef7eb2e8f9f7 302 tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Remove the flatting point */
<> 144:ef7eb2e8f9f7 306 tmp = tmp / 10;
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Check the parity of the divider */
<> 144:ef7eb2e8f9f7 309 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Compute the i2sdiv prescaler */
<> 144:ef7eb2e8f9f7 312 i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
<> 144:ef7eb2e8f9f7 315 i2sodd = (uint16_t) (i2sodd << 8);
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* Test if the divider is 1 or 0 or greater than 0xFF */
<> 144:ef7eb2e8f9f7 319 if((i2sdiv < 2) || (i2sdiv > 0xFF))
<> 144:ef7eb2e8f9f7 320 {
<> 144:ef7eb2e8f9f7 321 /* Set the default values */
<> 144:ef7eb2e8f9f7 322 i2sdiv = 2;
<> 144:ef7eb2e8f9f7 323 i2sodd = 0;
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Write to SPIx I2SPR register the computed value */
<> 144:ef7eb2e8f9f7 327 hi2s->Instance->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)hi2s->Init.MCLKOutput));
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Configure the I2S with the I2S_InitStruct values */
<> 144:ef7eb2e8f9f7 330 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
<> 144:ef7eb2e8f9f7 331 (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
<> 144:ef7eb2e8f9f7 332 (uint16_t)hi2s->Init.CPOL))));
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Write to SPIx I2SCFGR */
<> 144:ef7eb2e8f9f7 335 hi2s->Instance->I2SCFGR = tmpreg;
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 338 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 return HAL_OK;
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @brief DeInitializes the I2S peripheral
<> 144:ef7eb2e8f9f7 345 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 346 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 347 * @retval HAL status
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 /* Check the I2S handle allocation */
<> 144:ef7eb2e8f9f7 352 if(hi2s == NULL)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Check the parameters */
<> 144:ef7eb2e8f9f7 358 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 hi2s->State = HAL_I2S_STATE_BUSY;
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<> 144:ef7eb2e8f9f7 363 HAL_I2S_MspDeInit(hi2s);
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 366 hi2s->State = HAL_I2S_STATE_RESET;
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Release Lock */
<> 144:ef7eb2e8f9f7 369 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 return HAL_OK;
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @brief I2S MSP Init
<> 144:ef7eb2e8f9f7 376 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 377 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 378 * @retval None
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 383 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 386 the HAL_I2S_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /**
<> 144:ef7eb2e8f9f7 391 * @brief I2S MSP DeInit
<> 144:ef7eb2e8f9f7 392 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 393 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 394 * @retval None
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 397 {
<> 144:ef7eb2e8f9f7 398 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 399 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 402 the HAL_I2S_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 403 */
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /** @defgroup I2S_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 411 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 412 *
<> 144:ef7eb2e8f9f7 413 @verbatim
<> 144:ef7eb2e8f9f7 414 ===============================================================================
<> 144:ef7eb2e8f9f7 415 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 416 ===============================================================================
<> 144:ef7eb2e8f9f7 417 [..]
<> 144:ef7eb2e8f9f7 418 This subsection provides a set of functions allowing to manage the I2S data
<> 144:ef7eb2e8f9f7 419 transfers.
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 (#) There are two modes of transfer:
<> 144:ef7eb2e8f9f7 422 (++) Blocking mode : The communication is performed in the polling mode.
<> 144:ef7eb2e8f9f7 423 The status of all data processing is returned by the same function
<> 144:ef7eb2e8f9f7 424 after finishing transfer.
<> 144:ef7eb2e8f9f7 425 (++) No-Blocking mode : The communication is performed using Interrupts
<> 144:ef7eb2e8f9f7 426 or DMA. These functions return the status of the transfer startup.
<> 144:ef7eb2e8f9f7 427 The end of the data processing will be indicated through the
<> 144:ef7eb2e8f9f7 428 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
<> 144:ef7eb2e8f9f7 429 using DMA mode.
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 (#) Blocking mode functions are :
<> 144:ef7eb2e8f9f7 432 (++) HAL_I2S_Transmit()
<> 144:ef7eb2e8f9f7 433 (++) HAL_I2S_Receive()
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 (#) No-Blocking mode functions with Interrupt are :
<> 144:ef7eb2e8f9f7 436 (++) HAL_I2S_Transmit_IT()
<> 144:ef7eb2e8f9f7 437 (++) HAL_I2S_Receive_IT()
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 (#) No-Blocking mode functions with DMA are :
<> 144:ef7eb2e8f9f7 440 (++) HAL_I2S_Transmit_DMA()
<> 144:ef7eb2e8f9f7 441 (++) HAL_I2S_Receive_DMA()
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<> 144:ef7eb2e8f9f7 444 (++) HAL_I2S_TxCpltCallback()
<> 144:ef7eb2e8f9f7 445 (++) HAL_I2S_RxCpltCallback()
<> 144:ef7eb2e8f9f7 446 (++) HAL_I2S_ErrorCallback()
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 @endverbatim
<> 144:ef7eb2e8f9f7 449 * @{
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @brief Transmit an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 454 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 455 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 456 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 457 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 458 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 459 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 460 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 461 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 462 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 463 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 464 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 465 * @retval HAL status
<> 144:ef7eb2e8f9f7 466 */
<> 144:ef7eb2e8f9f7 467 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 468 {
<> 144:ef7eb2e8f9f7 469 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 477 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 480 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 481 }
<> 144:ef7eb2e8f9f7 482 else
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 485 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Process Locked */
<> 144:ef7eb2e8f9f7 489 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 492 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 495 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 498 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 while(hi2s->TxXferCount > 0)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 hi2s->Instance->DR = (*pData++);
<> 144:ef7eb2e8f9f7 504 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 505 /* Wait until TXE flag is set */
<> 144:ef7eb2e8f9f7 506 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 509 hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 510 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 511 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Check if an underrun occurs */
<> 144:ef7eb2e8f9f7 515 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 518 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 521 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 524 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
<> 144:ef7eb2e8f9f7 525 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Check if Slave mode is selected */
<> 144:ef7eb2e8f9f7 532 if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 /* Wait until Busy flag is reset */
<> 144:ef7eb2e8f9f7 535 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 538 hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 539 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 540 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542 }
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 547 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 return HAL_OK;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 else
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /**
<> 144:ef7eb2e8f9f7 558 * @brief Receive an amount of data in blocking mode
<> 144:ef7eb2e8f9f7 559 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 560 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 561 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 562 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 563 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 564 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 565 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 566 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 567 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 568 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 569 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 570 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
<> 144:ef7eb2e8f9f7 571 * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
<> 144:ef7eb2e8f9f7 572 * @retval HAL status
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 if((pData == NULL ) || (Size == 0))
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 584 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 587 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589 else
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 592 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594 /* Process Locked */
<> 144:ef7eb2e8f9f7 595 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 598 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 601 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 604 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 608 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 611 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 612 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Receive data */
<> 144:ef7eb2e8f9f7 616 while(hi2s->RxXferCount > 0)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 /* Wait until RXNE flag is set */
<> 144:ef7eb2e8f9f7 619 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 622 hi2s->ErrorCode |= HAL_I2S_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 623 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 624 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Check if an overrun occurs */
<> 144:ef7eb2e8f9f7 628 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 631 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 634 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 637 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
<> 144:ef7eb2e8f9f7 638 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 (*pData++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 644 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 650 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 return HAL_OK;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 else
<> 144:ef7eb2e8f9f7 655 {
<> 144:ef7eb2e8f9f7 656 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658 }
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /**
<> 144:ef7eb2e8f9f7 661 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 662 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 663 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 664 * @param pData: a 16-bit pointer to data buffer.
<> 144:ef7eb2e8f9f7 665 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 666 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 667 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 668 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 669 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 670 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 671 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 672 * @retval HAL status
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 675 {
<> 144:ef7eb2e8f9f7 676 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 684 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 685 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 688 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 else
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 693 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Process Locked */
<> 144:ef7eb2e8f9f7 697 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 700 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 703 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 706 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 709 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 713 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 return HAL_OK;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717 else
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /**
<> 144:ef7eb2e8f9f7 724 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 725 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 726 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 727 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 728 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 729 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 730 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 731 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 732 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 733 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 734 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 735 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
<> 144:ef7eb2e8f9f7 736 * between Master and Slave otherwise the I2S interrupt should be optimized.
<> 144:ef7eb2e8f9f7 737 * @retval HAL status
<> 144:ef7eb2e8f9f7 738 */
<> 144:ef7eb2e8f9f7 739 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 749 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 750 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 753 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755 else
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 758 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760 /* Process Locked */
<> 144:ef7eb2e8f9f7 761 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 764 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Enable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 767 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 770 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 773 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 777 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 return HAL_OK;
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781 else
<> 144:ef7eb2e8f9f7 782 {
<> 144:ef7eb2e8f9f7 783 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 784 }
<> 144:ef7eb2e8f9f7 785 }
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @brief Transmit an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 789 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 790 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 791 * @param pData: a 16-bit pointer to the Transmit data buffer.
<> 144:ef7eb2e8f9f7 792 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 793 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 794 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 795 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 796 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 797 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 798 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 799 * @retval HAL status
<> 144:ef7eb2e8f9f7 800 */
<> 144:ef7eb2e8f9f7 801 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 hi2s->pTxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 813 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 814 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 hi2s->TxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 817 hi2s->TxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 else
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 hi2s->TxXferSize = Size;
<> 144:ef7eb2e8f9f7 822 hi2s->TxXferCount = Size;
<> 144:ef7eb2e8f9f7 823 }
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Process Locked */
<> 144:ef7eb2e8f9f7 826 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 829 hi2s->State = HAL_I2S_STATE_BUSY_TX;
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Set the I2S Tx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 832 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /* Set the I2S TxDMA transfer complete callback */
<> 144:ef7eb2e8f9f7 835 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 838 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Enable the Tx DMA Channel */
<> 144:ef7eb2e8f9f7 841 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 842 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 845 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 848 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Enable Tx DMA Request */
<> 144:ef7eb2e8f9f7 852 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 855 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 return HAL_OK;
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859 else
<> 144:ef7eb2e8f9f7 860 {
<> 144:ef7eb2e8f9f7 861 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /**
<> 144:ef7eb2e8f9f7 866 * @brief Receive an amount of data in non-blocking mode with DMA
<> 144:ef7eb2e8f9f7 867 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 868 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 869 * @param pData: a 16-bit pointer to the Receive data buffer.
<> 144:ef7eb2e8f9f7 870 * @param Size: number of data sample to be sent:
<> 144:ef7eb2e8f9f7 871 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
<> 144:ef7eb2e8f9f7 872 * configuration phase, the Size parameter means the number of 16-bit data length
<> 144:ef7eb2e8f9f7 873 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
<> 144:ef7eb2e8f9f7 874 * the Size parameter means the number of 16-bit data length.
<> 144:ef7eb2e8f9f7 875 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
<> 144:ef7eb2e8f9f7 876 * between Master and Slave(example: audio streaming).
<> 144:ef7eb2e8f9f7 877 * @retval HAL status
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
<> 144:ef7eb2e8f9f7 880 {
<> 144:ef7eb2e8f9f7 881 uint32_t *tmp;
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 if((pData == NULL) || (Size == 0))
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 886 }
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 if(hi2s->State == HAL_I2S_STATE_READY)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 hi2s->pRxBuffPtr = pData;
<> 144:ef7eb2e8f9f7 891 if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
<> 144:ef7eb2e8f9f7 892 ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 hi2s->RxXferSize = (Size << 1);
<> 144:ef7eb2e8f9f7 895 hi2s->RxXferCount = (Size << 1);
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 else
<> 144:ef7eb2e8f9f7 898 {
<> 144:ef7eb2e8f9f7 899 hi2s->RxXferSize = Size;
<> 144:ef7eb2e8f9f7 900 hi2s->RxXferCount = Size;
<> 144:ef7eb2e8f9f7 901 }
<> 144:ef7eb2e8f9f7 902 /* Process Locked */
<> 144:ef7eb2e8f9f7 903 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
<> 144:ef7eb2e8f9f7 906 hi2s->State = HAL_I2S_STATE_BUSY_RX;
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /* Set the I2S Rx DMA Half transfer complete callback */
<> 144:ef7eb2e8f9f7 909 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /* Set the I2S Rx DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 912 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 915 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* Check if Master Receiver mode is selected */
<> 144:ef7eb2e8f9f7 918 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
<> 144:ef7eb2e8f9f7 921 access to the SPI_SR register. */
<> 144:ef7eb2e8f9f7 922 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
<> 144:ef7eb2e8f9f7 923 }
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 /* Enable the Rx DMA Channel */
<> 144:ef7eb2e8f9f7 926 tmp = (uint32_t*)&pData;
<> 144:ef7eb2e8f9f7 927 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* Check if the I2S is already enabled */
<> 144:ef7eb2e8f9f7 930 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 933 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935
<> 144:ef7eb2e8f9f7 936 /* Enable Rx DMA Request */
<> 144:ef7eb2e8f9f7 937 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 940 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 return HAL_OK;
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944 else
<> 144:ef7eb2e8f9f7 945 {
<> 144:ef7eb2e8f9f7 946 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /**
<> 144:ef7eb2e8f9f7 951 * @brief Pauses the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 952 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 953 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 954 * @retval HAL status
<> 144:ef7eb2e8f9f7 955 */
<> 144:ef7eb2e8f9f7 956 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 /* Process Locked */
<> 144:ef7eb2e8f9f7 959 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 962 {
<> 144:ef7eb2e8f9f7 963 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 964 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 965 }
<> 144:ef7eb2e8f9f7 966 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 967 {
<> 144:ef7eb2e8f9f7 968 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 969 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 970 }
<> 144:ef7eb2e8f9f7 971 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 972 {
<> 144:ef7eb2e8f9f7 973 if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
<> 144:ef7eb2e8f9f7 974 {
<> 144:ef7eb2e8f9f7 975 /* Disable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 976 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 977 }
<> 144:ef7eb2e8f9f7 978 else
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 /* Disable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 981 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 982 }
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 986 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 return HAL_OK;
<> 144:ef7eb2e8f9f7 989 }
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /**
<> 144:ef7eb2e8f9f7 992 * @brief Resumes the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 993 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 994 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 995 * @retval HAL status
<> 144:ef7eb2e8f9f7 996 */
<> 144:ef7eb2e8f9f7 997 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 998 {
<> 144:ef7eb2e8f9f7 999 /* Process Locked */
<> 144:ef7eb2e8f9f7 1000 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 /* Enable the I2S DMA Tx request */
<> 144:ef7eb2e8f9f7 1005 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1006 }
<> 144:ef7eb2e8f9f7 1007 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1008 {
<> 144:ef7eb2e8f9f7 1009 /* Enable the I2S DMA Rx request */
<> 144:ef7eb2e8f9f7 1010 SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1011 }
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* If the I2S peripheral is still not enabled, enable it */
<> 144:ef7eb2e8f9f7 1014 if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 /* Enable I2S peripheral */
<> 144:ef7eb2e8f9f7 1017 __HAL_I2S_ENABLE(hi2s);
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1021 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 return HAL_OK;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
<> 144:ef7eb2e8f9f7 1027 * @brief Stops the audio stream playing from the Media.
<> 144:ef7eb2e8f9f7 1028 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1029 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1030 * @retval HAL status
<> 144:ef7eb2e8f9f7 1031 */
<> 144:ef7eb2e8f9f7 1032 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 /* Process Locked */
<> 144:ef7eb2e8f9f7 1035 __HAL_LOCK(hi2s);
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Disable the I2S Tx/Rx DMA requests */
<> 144:ef7eb2e8f9f7 1038 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1039 CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /* Abort the I2S DMA Channel tx */
<> 144:ef7eb2e8f9f7 1042 if(hi2s->hdmatx != NULL)
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 1045 __HAL_DMA_DISABLE(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1046 HAL_DMA_Abort(hi2s->hdmatx);
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048 /* Abort the I2S DMA Channel rx */
<> 144:ef7eb2e8f9f7 1049 if(hi2s->hdmarx != NULL)
<> 144:ef7eb2e8f9f7 1050 {
<> 144:ef7eb2e8f9f7 1051 /* Disable the I2S DMA channel */
<> 144:ef7eb2e8f9f7 1052 __HAL_DMA_DISABLE(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1053 HAL_DMA_Abort(hi2s->hdmarx);
<> 144:ef7eb2e8f9f7 1054 }
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /* Disable I2S peripheral */
<> 144:ef7eb2e8f9f7 1057 __HAL_I2S_DISABLE(hi2s);
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1062 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 return HAL_OK;
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /**
<> 144:ef7eb2e8f9f7 1068 * @brief This function handles I2S interrupt request.
<> 144:ef7eb2e8f9f7 1069 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1070 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1071 * @retval HAL status
<> 144:ef7eb2e8f9f7 1072 */
<> 144:ef7eb2e8f9f7 1073 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1074 {
<> 144:ef7eb2e8f9f7 1075 __IO uint32_t i2ssr = hi2s->Instance->SR;
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
<> 144:ef7eb2e8f9f7 1078 {
<> 144:ef7eb2e8f9f7 1079 /* I2S in mode Receiver ----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1080 if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
<> 144:ef7eb2e8f9f7 1081 {
<> 144:ef7eb2e8f9f7 1082 I2S_Receive_IT(hi2s);
<> 144:ef7eb2e8f9f7 1083 }
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 /* I2S Overrun error interrupt occurred -------------------------------------*/
<> 144:ef7eb2e8f9f7 1086 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1089 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1092 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1095 hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
<> 144:ef7eb2e8f9f7 1096 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1097 }
<> 144:ef7eb2e8f9f7 1098 }
<> 144:ef7eb2e8f9f7 1099 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
<> 144:ef7eb2e8f9f7 1100 {
<> 144:ef7eb2e8f9f7 1101 /* I2S in mode Transmitter ---------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1102 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 I2S_Transmit_IT(hi2s);
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* I2S Underrun error interrupt occurred ------------------------------------*/
<> 144:ef7eb2e8f9f7 1108 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
<> 144:ef7eb2e8f9f7 1109 {
<> 144:ef7eb2e8f9f7 1110 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1111 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1114 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1117 hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
<> 144:ef7eb2e8f9f7 1118 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1119 }
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 }
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /**
<> 144:ef7eb2e8f9f7 1124 * @}
<> 144:ef7eb2e8f9f7 1125 */
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /**
<> 144:ef7eb2e8f9f7 1128 * @}
<> 144:ef7eb2e8f9f7 1129 */
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 1132 * @{
<> 144:ef7eb2e8f9f7 1133 */
<> 144:ef7eb2e8f9f7 1134 /**
<> 144:ef7eb2e8f9f7 1135 * @brief This function handles I2S Communication Timeout.
<> 144:ef7eb2e8f9f7 1136 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1137 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1138 * @param Flag: Flag checked
<> 144:ef7eb2e8f9f7 1139 * @param State: Value of the flag expected
<> 144:ef7eb2e8f9f7 1140 * @param Timeout: Duration of the timeout
<> 144:ef7eb2e8f9f7 1141 * @retval HAL status
<> 144:ef7eb2e8f9f7 1142 */
<> 144:ef7eb2e8f9f7 1143 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
<> 144:ef7eb2e8f9f7 1144 uint32_t State, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1145 {
<> 144:ef7eb2e8f9f7 1146 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /* Get tick */
<> 144:ef7eb2e8f9f7 1149 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /* Wait until flag is set */
<> 144:ef7eb2e8f9f7 1152 if(State == RESET)
<> 144:ef7eb2e8f9f7 1153 {
<> 144:ef7eb2e8f9f7 1154 while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
<> 144:ef7eb2e8f9f7 1155 {
<> 144:ef7eb2e8f9f7 1156 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1157 {
<> 144:ef7eb2e8f9f7 1158 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1161 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1164 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1167 }
<> 144:ef7eb2e8f9f7 1168 }
<> 144:ef7eb2e8f9f7 1169 }
<> 144:ef7eb2e8f9f7 1170 }
<> 144:ef7eb2e8f9f7 1171 else
<> 144:ef7eb2e8f9f7 1172 {
<> 144:ef7eb2e8f9f7 1173 while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1176 {
<> 144:ef7eb2e8f9f7 1177 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1178 {
<> 144:ef7eb2e8f9f7 1179 /* Set the I2S State ready */
<> 144:ef7eb2e8f9f7 1180 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1183 __HAL_UNLOCK(hi2s);
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187 }
<> 144:ef7eb2e8f9f7 1188 }
<> 144:ef7eb2e8f9f7 1189 }
<> 144:ef7eb2e8f9f7 1190 return HAL_OK;
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 /**
<> 144:ef7eb2e8f9f7 1193 * @}
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 /** @addtogroup I2S_Exported_Functions I2S Exported Functions
<> 144:ef7eb2e8f9f7 1197 * @{
<> 144:ef7eb2e8f9f7 1198 */
<> 144:ef7eb2e8f9f7 1199
<> 144:ef7eb2e8f9f7 1200 /** @addtogroup I2S_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 1201 * @{
<> 144:ef7eb2e8f9f7 1202 */
<> 144:ef7eb2e8f9f7 1203 /**
<> 144:ef7eb2e8f9f7 1204 * @brief Tx Transfer Half completed callbacks
<> 144:ef7eb2e8f9f7 1205 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1206 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1207 * @retval None
<> 144:ef7eb2e8f9f7 1208 */
<> 144:ef7eb2e8f9f7 1209 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1210 {
<> 144:ef7eb2e8f9f7 1211 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1212 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1215 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1216 */
<> 144:ef7eb2e8f9f7 1217 }
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /**
<> 144:ef7eb2e8f9f7 1220 * @brief Tx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1221 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1222 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1223 * @retval None
<> 144:ef7eb2e8f9f7 1224 */
<> 144:ef7eb2e8f9f7 1225 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1226 {
<> 144:ef7eb2e8f9f7 1227 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1228 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1231 the HAL_I2S_TxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1232 */
<> 144:ef7eb2e8f9f7 1233 }
<> 144:ef7eb2e8f9f7 1234
<> 144:ef7eb2e8f9f7 1235 /**
<> 144:ef7eb2e8f9f7 1236 * @brief Rx Transfer half completed callbacks
<> 144:ef7eb2e8f9f7 1237 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1238 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1239 * @retval None
<> 144:ef7eb2e8f9f7 1240 */
<> 144:ef7eb2e8f9f7 1241 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1244 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1245
<> 144:ef7eb2e8f9f7 1246 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1247 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1248 */
<> 144:ef7eb2e8f9f7 1249 }
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 /**
<> 144:ef7eb2e8f9f7 1252 * @brief Rx Transfer completed callbacks
<> 144:ef7eb2e8f9f7 1253 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1254 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1255 * @retval None
<> 144:ef7eb2e8f9f7 1256 */
<> 144:ef7eb2e8f9f7 1257 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1258 {
<> 144:ef7eb2e8f9f7 1259 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1260 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1263 the HAL_I2S_RxCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1264 */
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 /**
<> 144:ef7eb2e8f9f7 1268 * @brief I2S error callbacks
<> 144:ef7eb2e8f9f7 1269 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1270 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1271 * @retval None
<> 144:ef7eb2e8f9f7 1272 */
<> 144:ef7eb2e8f9f7 1273 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1274 {
<> 144:ef7eb2e8f9f7 1275 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1276 UNUSED(hi2s);
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1279 the HAL_I2S_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1280 */
<> 144:ef7eb2e8f9f7 1281 }
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /**
<> 144:ef7eb2e8f9f7 1284 * @}
<> 144:ef7eb2e8f9f7 1285 */
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 1288 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1289 *
<> 144:ef7eb2e8f9f7 1290 @verbatim
<> 144:ef7eb2e8f9f7 1291 ===============================================================================
<> 144:ef7eb2e8f9f7 1292 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1293 ===============================================================================
<> 144:ef7eb2e8f9f7 1294 [..]
<> 144:ef7eb2e8f9f7 1295 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1296 and the data flow.
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 @endverbatim
<> 144:ef7eb2e8f9f7 1299 * @{
<> 144:ef7eb2e8f9f7 1300 */
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /**
<> 144:ef7eb2e8f9f7 1303 * @brief Return the I2S state
<> 144:ef7eb2e8f9f7 1304 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1305 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1306 * @retval HAL state
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1309 {
<> 144:ef7eb2e8f9f7 1310 return hi2s->State;
<> 144:ef7eb2e8f9f7 1311 }
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /**
<> 144:ef7eb2e8f9f7 1314 * @brief Return the I2S error code
<> 144:ef7eb2e8f9f7 1315 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1316 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1317 * @retval I2S Error Code
<> 144:ef7eb2e8f9f7 1318 */
<> 144:ef7eb2e8f9f7 1319 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 return hi2s->ErrorCode;
<> 144:ef7eb2e8f9f7 1322 }
<> 144:ef7eb2e8f9f7 1323 /**
<> 144:ef7eb2e8f9f7 1324 * @}
<> 144:ef7eb2e8f9f7 1325 */
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /**
<> 144:ef7eb2e8f9f7 1328 * @}
<> 144:ef7eb2e8f9f7 1329 */
<> 144:ef7eb2e8f9f7 1330
<> 144:ef7eb2e8f9f7 1331 /**
<> 144:ef7eb2e8f9f7 1332 * @brief Get I2S Input Clock based on I2S source clock selection
<> 144:ef7eb2e8f9f7 1333 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1334 * the configuration information for I2S module.
<> 144:ef7eb2e8f9f7 1335 * @retval I2S Clock Input
<> 144:ef7eb2e8f9f7 1336 */
<> 144:ef7eb2e8f9f7 1337 static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1338 {
<> 144:ef7eb2e8f9f7 1339 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 1340 /* This variable used to store the VCO Input (value in Hz) */
<> 144:ef7eb2e8f9f7 1341 uint32_t vcoinput = 0;
<> 144:ef7eb2e8f9f7 1342 /* This variable used to store the I2S_CK_x (value in Hz) */
<> 144:ef7eb2e8f9f7 1343 uint32_t i2sclocksource = 0;
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* Configure I2S Clock based on I2S source clock selection */
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
<> 144:ef7eb2e8f9f7 1348 switch(hi2s->Init.ClockSource)
<> 144:ef7eb2e8f9f7 1349 {
<> 144:ef7eb2e8f9f7 1350 case I2S_CLOCK_PLL :
<> 144:ef7eb2e8f9f7 1351 {
<> 144:ef7eb2e8f9f7 1352 /* Configure the PLLI2S division factor */
<> 144:ef7eb2e8f9f7 1353 /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
<> 144:ef7eb2e8f9f7 1354 if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
<> 144:ef7eb2e8f9f7 1355 {
<> 144:ef7eb2e8f9f7 1356 /* In Case the PLL Source is HSI (Internal Clock) */
<> 144:ef7eb2e8f9f7 1357 vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
<> 144:ef7eb2e8f9f7 1358 }
<> 144:ef7eb2e8f9f7 1359 else
<> 144:ef7eb2e8f9f7 1360 {
<> 144:ef7eb2e8f9f7 1361 /* In Case the PLL Source is HSE (External Clock) */
<> 144:ef7eb2e8f9f7 1362 vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
<> 144:ef7eb2e8f9f7 1363 }
<> 144:ef7eb2e8f9f7 1364
<> 144:ef7eb2e8f9f7 1365 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
<> 144:ef7eb2e8f9f7 1366 /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */
<> 144:ef7eb2e8f9f7 1367 tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28;
<> 144:ef7eb2e8f9f7 1368 i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg);
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 break;
<> 144:ef7eb2e8f9f7 1371 }
<> 144:ef7eb2e8f9f7 1372 case I2S_CLOCK_EXTERNAL :
<> 144:ef7eb2e8f9f7 1373 {
<> 144:ef7eb2e8f9f7 1374 i2sclocksource = EXTERNAL_CLOCK_VALUE;
<> 144:ef7eb2e8f9f7 1375 break;
<> 144:ef7eb2e8f9f7 1376 }
<> 144:ef7eb2e8f9f7 1377 default :
<> 144:ef7eb2e8f9f7 1378 {
<> 144:ef7eb2e8f9f7 1379 break;
<> 144:ef7eb2e8f9f7 1380 }
<> 144:ef7eb2e8f9f7 1381 }
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 /* the return result is the value of I2S clock */
<> 144:ef7eb2e8f9f7 1384 return i2sclocksource;
<> 144:ef7eb2e8f9f7 1385 }
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /** @addtogroup I2S_Private_Functions I2S Private Functions
<> 144:ef7eb2e8f9f7 1388 * @{
<> 144:ef7eb2e8f9f7 1389 */
<> 144:ef7eb2e8f9f7 1390 /**
<> 144:ef7eb2e8f9f7 1391 * @brief DMA I2S transmit process complete callback
<> 144:ef7eb2e8f9f7 1392 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1393 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1394 * @retval None
<> 144:ef7eb2e8f9f7 1395 */
<> 144:ef7eb2e8f9f7 1396 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1397 {
<> 144:ef7eb2e8f9f7 1398 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 1401 {
<> 144:ef7eb2e8f9f7 1402 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1403
<> 144:ef7eb2e8f9f7 1404 /* Disable Tx DMA Request */
<> 144:ef7eb2e8f9f7 1405 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1408 {
<> 144:ef7eb2e8f9f7 1409 if(hi2s->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1412 }
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414 else
<> 144:ef7eb2e8f9f7 1415 {
<> 144:ef7eb2e8f9f7 1416 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418 }
<> 144:ef7eb2e8f9f7 1419 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1420 }
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /**
<> 144:ef7eb2e8f9f7 1423 * @brief DMA I2S transmit process half complete callback
<> 144:ef7eb2e8f9f7 1424 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1425 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1426 * @retval None
<> 144:ef7eb2e8f9f7 1427 */
<> 144:ef7eb2e8f9f7 1428 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1429 {
<> 144:ef7eb2e8f9f7 1430 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 HAL_I2S_TxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1433 }
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 /**
<> 144:ef7eb2e8f9f7 1436 * @brief DMA I2S receive process complete callback
<> 144:ef7eb2e8f9f7 1437 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1438 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1439 * @retval None
<> 144:ef7eb2e8f9f7 1440 */
<> 144:ef7eb2e8f9f7 1441 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1442 {
<> 144:ef7eb2e8f9f7 1443 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
<> 144:ef7eb2e8f9f7 1446 {
<> 144:ef7eb2e8f9f7 1447 /* Disable Rx DMA Request */
<> 144:ef7eb2e8f9f7 1448 hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1451 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
<> 144:ef7eb2e8f9f7 1452 {
<> 144:ef7eb2e8f9f7 1453 if(hi2s->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1454 {
<> 144:ef7eb2e8f9f7 1455 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1456 }
<> 144:ef7eb2e8f9f7 1457 }
<> 144:ef7eb2e8f9f7 1458 else
<> 144:ef7eb2e8f9f7 1459 {
<> 144:ef7eb2e8f9f7 1460 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1461 }
<> 144:ef7eb2e8f9f7 1462 }
<> 144:ef7eb2e8f9f7 1463 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1464 }
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 /**
<> 144:ef7eb2e8f9f7 1467 * @brief DMA I2S receive process half complete callback
<> 144:ef7eb2e8f9f7 1468 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1469 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1470 * @retval None
<> 144:ef7eb2e8f9f7 1471 */
<> 144:ef7eb2e8f9f7 1472 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1473 {
<> 144:ef7eb2e8f9f7 1474 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 HAL_I2S_RxHalfCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1477 }
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /**
<> 144:ef7eb2e8f9f7 1480 * @brief DMA I2S communication error callback
<> 144:ef7eb2e8f9f7 1481 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1482 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1483 * @retval None
<> 144:ef7eb2e8f9f7 1484 */
<> 144:ef7eb2e8f9f7 1485 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1486 {
<> 144:ef7eb2e8f9f7 1487 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /* Disable Rx and Tx DMA Request */
<> 144:ef7eb2e8f9f7 1490 hi2s->Instance->CR2 &= (uint32_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
<> 144:ef7eb2e8f9f7 1491 hi2s->TxXferCount = 0;
<> 144:ef7eb2e8f9f7 1492 hi2s->RxXferCount = 0;
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 hi2s->State= HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 /* Set the error code and execute error callback*/
<> 144:ef7eb2e8f9f7 1497 hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
<> 144:ef7eb2e8f9f7 1498 HAL_I2S_ErrorCallback(hi2s);
<> 144:ef7eb2e8f9f7 1499 }
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /**
<> 144:ef7eb2e8f9f7 1502 * @brief Transmit an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1503 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1504 * the configuration information for I2S module
<> 144:ef7eb2e8f9f7 1505 * @retval None
<> 144:ef7eb2e8f9f7 1506 */
<> 144:ef7eb2e8f9f7 1507 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1508 {
<> 144:ef7eb2e8f9f7 1509 /* Transmit data */
<> 144:ef7eb2e8f9f7 1510 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
<> 144:ef7eb2e8f9f7 1511 hi2s->TxXferCount--;
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 if(hi2s->TxXferCount == 0)
<> 144:ef7eb2e8f9f7 1514 {
<> 144:ef7eb2e8f9f7 1515 /* Disable TXE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1516 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1517
<> 144:ef7eb2e8f9f7 1518 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1519 HAL_I2S_TxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1520 }
<> 144:ef7eb2e8f9f7 1521 }
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /**
<> 144:ef7eb2e8f9f7 1524 * @brief Receive an amount of data in non-blocking mode with Interrupt
<> 144:ef7eb2e8f9f7 1525 * @param hi2s: I2S handle
<> 144:ef7eb2e8f9f7 1526 * @retval None
<> 144:ef7eb2e8f9f7 1527 */
<> 144:ef7eb2e8f9f7 1528 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
<> 144:ef7eb2e8f9f7 1529 {
<> 144:ef7eb2e8f9f7 1530 /* Receive data */
<> 144:ef7eb2e8f9f7 1531 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
<> 144:ef7eb2e8f9f7 1532 hi2s->RxXferCount--;
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 if(hi2s->RxXferCount == 0)
<> 144:ef7eb2e8f9f7 1535 {
<> 144:ef7eb2e8f9f7 1536 /* Disable RXNE and ERR interrupt */
<> 144:ef7eb2e8f9f7 1537 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 hi2s->State = HAL_I2S_STATE_READY;
<> 144:ef7eb2e8f9f7 1540 HAL_I2S_RxCpltCallback(hi2s);
<> 144:ef7eb2e8f9f7 1541 }
<> 144:ef7eb2e8f9f7 1542 }
<> 144:ef7eb2e8f9f7 1543 /**
<> 144:ef7eb2e8f9f7 1544 * @}
<> 144:ef7eb2e8f9f7 1545 */
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 #endif /* HAL_I2S_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1548 /**
<> 144:ef7eb2e8f9f7 1549 * @}
<> 144:ef7eb2e8f9f7 1550 */
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 /**
<> 144:ef7eb2e8f9f7 1553 * @}
<> 144:ef7eb2e8f9f7 1554 */
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/