mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
161:2cc1468da177
Child:
168:9672193075cf
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_dma2d.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief DMA2D HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the DMA2D peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 (#) Program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 21 the transfer mode, the output color mode and the output offset using
<> 144:ef7eb2e8f9f7 22 HAL_DMA2D_Init() function.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 (#) Program the required configuration through the following parameters:
<> 144:ef7eb2e8f9f7 25 the input color mode, the input color, the input alpha value, the alpha mode,
<> 144:ef7eb2e8f9f7 26 the red/blue swap mode, the inverted alpha mode and the input offset using
<> 144:ef7eb2e8f9f7 27 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 *** Polling mode IO operation ***
<> 144:ef7eb2e8f9f7 30 =================================
<> 144:ef7eb2e8f9f7 31 [..]
<> 144:ef7eb2e8f9f7 32 (#) Configure pdata parameter (explained hereafter), destination and data length
<> 144:ef7eb2e8f9f7 33 and enable the transfer using HAL_DMA2D_Start().
<> 144:ef7eb2e8f9f7 34 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
<> 144:ef7eb2e8f9f7 35 user can specify the value of timeout according to his end application.
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 *** Interrupt mode IO operation ***
<> 144:ef7eb2e8f9f7 38 ===================================
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 (#) Configure pdata parameter, destination and data length and enable
<> 144:ef7eb2e8f9f7 41 the transfer using HAL_DMA2D_Start_IT().
<> 144:ef7eb2e8f9f7 42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
<> 144:ef7eb2e8f9f7 43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
<> 144:ef7eb2e8f9f7 44 add his own function by customization of function pointer XferCpltCallback (member
<> 144:ef7eb2e8f9f7 45 of DMA2D handle structure).
<> 144:ef7eb2e8f9f7 46 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
<> 144:ef7eb2e8f9f7 47 XferErrorCallback.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 -@- In Register-to-Memory transfer mode, pdata parameter is the register
<> 144:ef7eb2e8f9f7 50 color, in Memory-to-memory or Memory-to-Memory with pixel format
<> 144:ef7eb2e8f9f7 51 conversion pdata is the source address.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 -@- Configure the foreground source address, the background source address,
<> 144:ef7eb2e8f9f7 54 the destination and data length then Enable the transfer using
<> 144:ef7eb2e8f9f7 55 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
<> 144:ef7eb2e8f9f7 56 in interrupt mode.
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
<> 144:ef7eb2e8f9f7 59 are used if the memory to memory with blending transfer mode is selected.
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
<> 144:ef7eb2e8f9f7 62 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
<> 144:ef7eb2e8f9f7 67 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
<> 144:ef7eb2e8f9f7 68 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
<> 144:ef7eb2e8f9f7 69 HAL_DMA2D_DisableDeadTime().
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 (#) The transfer can be suspended, resumed and aborted using the following
<> 144:ef7eb2e8f9f7 72 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 (#) The CLUT loading can be suspended, resumed and aborted using the following
<> 144:ef7eb2e8f9f7 75 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
<> 144:ef7eb2e8f9f7 76 HAL_DMA2D_CLUTLoading_Abort().
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 *** DMA2D HAL driver macros list ***
<> 144:ef7eb2e8f9f7 83 =============================================
<> 144:ef7eb2e8f9f7 84 [..]
<> 144:ef7eb2e8f9f7 85 Below the list of most used macros in DMA2D HAL driver :
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
<> 144:ef7eb2e8f9f7 88 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
<> 144:ef7eb2e8f9f7 89 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
<> 144:ef7eb2e8f9f7 90 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
<> 144:ef7eb2e8f9f7 91 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
<> 144:ef7eb2e8f9f7 92 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 [..]
<> 144:ef7eb2e8f9f7 95 (@) You can refer to the DMA2D HAL driver header file for more useful macros
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup DMA2D DMA2D
<> 144:ef7eb2e8f9f7 136 * @brief DMA2D HAL module driver
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #ifdef HAL_DMA2D_MODULE_ENABLED
<> 157:ff67d9f36b67 141 #if defined (DMA2D)
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @defgroup DMA2D_TimeOut DMA2D Time Out
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 #define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */
<> 144:ef7eb2e8f9f7 153 #define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @}
<> 144:ef7eb2e8f9f7 156 */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /** @defgroup DMA2D_Shifts DMA2D Shifts
<> 144:ef7eb2e8f9f7 159 * @{
<> 144:ef7eb2e8f9f7 160 */
<> 144:ef7eb2e8f9f7 161 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
<> 144:ef7eb2e8f9f7 162 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
<> 144:ef7eb2e8f9f7 165 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */
<> 144:ef7eb2e8f9f7 168 #define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */
<> 144:ef7eb2e8f9f7 169 #define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */
<> 144:ef7eb2e8f9f7 172 #define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */
<> 144:ef7eb2e8f9f7 173 #define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
<> 144:ef7eb2e8f9f7 178 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
<> 144:ef7eb2e8f9f7 181 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @}
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @}
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 193 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 194 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 195 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 196 /** @addtogroup DMA2D_Private_Functions_Prototypes
<> 144:ef7eb2e8f9f7 197 * @{
<> 144:ef7eb2e8f9f7 198 */
<> 144:ef7eb2e8f9f7 199 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @}
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 205 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 206 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
<> 144:ef7eb2e8f9f7 207 * @{
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 211 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 212 *
<> 144:ef7eb2e8f9f7 213 @verbatim
<> 144:ef7eb2e8f9f7 214 ===============================================================================
<> 144:ef7eb2e8f9f7 215 ##### Initialization and Configuration functions #####
<> 144:ef7eb2e8f9f7 216 ===============================================================================
<> 144:ef7eb2e8f9f7 217 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 218 (+) Initialize and configure the DMA2D
<> 144:ef7eb2e8f9f7 219 (+) De-initialize the DMA2D
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 @endverbatim
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @brief Initialize the DMA2D according to the specified
<> 144:ef7eb2e8f9f7 227 * parameters in the DMA2D_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 228 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 229 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 230 * @retval HAL status
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 /* Check the DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 235 if(hdma2d == NULL)
<> 144:ef7eb2e8f9f7 236 {
<> 144:ef7eb2e8f9f7 237 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Check the parameters */
<> 144:ef7eb2e8f9f7 241 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
<> 144:ef7eb2e8f9f7 242 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
<> 144:ef7eb2e8f9f7 243 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
<> 144:ef7eb2e8f9f7 244 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 249 hdma2d->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 250 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 251 HAL_DMA2D_MspInit(hdma2d);
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 255 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* DMA2D CR register configuration -------------------------------------------*/
<> 144:ef7eb2e8f9f7 258 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* DMA2D OPFCCR register configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 261 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /* DMA2D OOR register configuration ------------------------------------------*/
<> 144:ef7eb2e8f9f7 264 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 #if defined (DMA2D_OPFCCR_AI)
<> 144:ef7eb2e8f9f7 267 /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
<> 144:ef7eb2e8f9f7 268 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));
<> 144:ef7eb2e8f9f7 269 #endif /* DMA2D_OPFCCR_AI */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 #if defined (DMA2D_OPFCCR_RBS)
<> 144:ef7eb2e8f9f7 272 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));
<> 144:ef7eb2e8f9f7 273 #endif /* DMA2D_OPFCCR_RBS */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Update error code */
<> 144:ef7eb2e8f9f7 277 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 280 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 return HAL_OK;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @brief Deinitializes the DMA2D peripheral registers to their default reset
<> 144:ef7eb2e8f9f7 287 * values.
<> 144:ef7eb2e8f9f7 288 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 289 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 290 * @retval None
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Check the DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 297 if(hdma2d == NULL)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Before aborting any DMA2D transfer or CLUT loading, check
<> 144:ef7eb2e8f9f7 303 first whether or not DMA2D clock is enabled */
<> 144:ef7eb2e8f9f7 304 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 /* Abort DMA2D transfer if any */
<> 144:ef7eb2e8f9f7 307 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 /* Issue when aborting DMA2D transfer */
<> 144:ef7eb2e8f9f7 312 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 else
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 /* Abort background CLUT loading if any */
<> 144:ef7eb2e8f9f7 318 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 /* Issue when aborting background CLUT loading */
<> 144:ef7eb2e8f9f7 323 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326 else
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Abort foreground CLUT loading if any */
<> 144:ef7eb2e8f9f7 329 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 /* Issue when aborting foreground CLUT loading */
<> 144:ef7eb2e8f9f7 334 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Carry on with de-initialization of low level hardware */
<> 144:ef7eb2e8f9f7 343 HAL_DMA2D_MspDeInit(hdma2d);
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Reset DMA2D control registers*/
<> 144:ef7eb2e8f9f7 346 hdma2d->Instance->CR = 0;
<> 144:ef7eb2e8f9f7 347 hdma2d->Instance->FGOR = 0;
<> 144:ef7eb2e8f9f7 348 hdma2d->Instance->BGOR = 0;
<> 144:ef7eb2e8f9f7 349 hdma2d->Instance->FGPFCCR = 0;
<> 144:ef7eb2e8f9f7 350 hdma2d->Instance->BGPFCCR = 0;
<> 144:ef7eb2e8f9f7 351 hdma2d->Instance->OPFCCR = 0;
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Update error code */
<> 144:ef7eb2e8f9f7 354 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 357 hdma2d->State = HAL_DMA2D_STATE_RESET;
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Release Lock */
<> 144:ef7eb2e8f9f7 360 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 return HAL_OK;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @brief Initializes the DMA2D MSP.
<> 144:ef7eb2e8f9f7 367 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 368 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 369 * @retval None
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
<> 144:ef7eb2e8f9f7 372 {
<> 144:ef7eb2e8f9f7 373 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 374 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 377 the HAL_DMA2D_MspInit can be implemented in the user file.
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @brief DeInitializes the DMA2D MSP.
<> 144:ef7eb2e8f9f7 383 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 384 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 385 * @retval None
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 390 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 393 the HAL_DMA2D_MspDeInit can be implemented in the user file.
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /**
<> 144:ef7eb2e8f9f7 398 * @}
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 403 * @brief IO operation functions
<> 144:ef7eb2e8f9f7 404 *
<> 144:ef7eb2e8f9f7 405 @verbatim
<> 144:ef7eb2e8f9f7 406 ===============================================================================
<> 144:ef7eb2e8f9f7 407 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 408 ===============================================================================
<> 144:ef7eb2e8f9f7 409 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 410 (+) Configure the pdata, destination address and data size then
<> 144:ef7eb2e8f9f7 411 start the DMA2D transfer.
<> 144:ef7eb2e8f9f7 412 (+) Configure the source for foreground and background, destination address
<> 144:ef7eb2e8f9f7 413 and data size then start a MultiBuffer DMA2D transfer.
<> 144:ef7eb2e8f9f7 414 (+) Configure the pdata, destination address and data size then
<> 144:ef7eb2e8f9f7 415 start the DMA2D transfer with interrupt.
<> 144:ef7eb2e8f9f7 416 (+) Configure the source for foreground and background, destination address
<> 144:ef7eb2e8f9f7 417 and data size then start a MultiBuffer DMA2D transfer with interrupt.
<> 144:ef7eb2e8f9f7 418 (+) Abort DMA2D transfer.
<> 144:ef7eb2e8f9f7 419 (+) Suspend DMA2D transfer.
<> 144:ef7eb2e8f9f7 420 (+) Resume DMA2D transfer.
<> 144:ef7eb2e8f9f7 421 (+) Enable CLUT transfer.
<> 144:ef7eb2e8f9f7 422 (+) Configure CLUT loading then start transfer in polling mode.
<> 144:ef7eb2e8f9f7 423 (+) Configure CLUT loading then start transfer in interrupt mode.
<> 144:ef7eb2e8f9f7 424 (+) Abort DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 425 (+) Suspend DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 426 (+) Resume DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 427 (+) Poll for transfer complete.
<> 144:ef7eb2e8f9f7 428 (+) handle DMA2D interrupt request.
<> 144:ef7eb2e8f9f7 429 (+) Transfer watermark callback.
<> 144:ef7eb2e8f9f7 430 (+) CLUT Transfer Complete callback.
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 @endverbatim
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @brief Start the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 439 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 440 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 441 * @param pdata: Configure the source memory Buffer address if
<> 144:ef7eb2e8f9f7 442 * Memory-to-Memory or Memory-to-Memory with pixel format
<> 144:ef7eb2e8f9f7 443 * conversion mode is selected, or configure
<> 144:ef7eb2e8f9f7 444 * the color value if Register-to-Memory mode is selected.
<> 144:ef7eb2e8f9f7 445 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 446 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 447 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 448 * @retval HAL status
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 /* Check the parameters */
<> 144:ef7eb2e8f9f7 453 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 454 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Process locked */
<> 144:ef7eb2e8f9f7 457 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 460 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 463 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 466 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 return HAL_OK;
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /**
<> 144:ef7eb2e8f9f7 472 * @brief Start the DMA2D Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 473 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 474 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 475 * @param pdata: Configure the source memory Buffer address if
<> 144:ef7eb2e8f9f7 476 * the Memory-to-Memory or Memory-to-Memory with pixel format
<> 144:ef7eb2e8f9f7 477 * conversion mode is selected, or configure
<> 144:ef7eb2e8f9f7 478 * the color value if Register-to-Memory mode is selected.
<> 144:ef7eb2e8f9f7 479 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 480 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 481 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 482 * @retval HAL status
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 /* Check the parameters */
<> 144:ef7eb2e8f9f7 487 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 488 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /* Process locked */
<> 144:ef7eb2e8f9f7 491 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 494 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 497 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /* Enable the transfer complete, transfer error and configuration error interrupts */
<> 144:ef7eb2e8f9f7 500 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 503 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 return HAL_OK;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief Start the multi-source DMA2D Transfer.
<> 144:ef7eb2e8f9f7 510 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 511 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 512 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
<> 144:ef7eb2e8f9f7 513 * @param SrcAddress2: The source memory Buffer address for the background layer.
<> 144:ef7eb2e8f9f7 514 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 515 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 516 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 517 * @retval HAL status
<> 144:ef7eb2e8f9f7 518 */
<> 144:ef7eb2e8f9f7 519 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 /* Check the parameters */
<> 144:ef7eb2e8f9f7 522 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 523 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Process locked */
<> 144:ef7eb2e8f9f7 526 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 529 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Configure DMA2D Stream source2 address */
<> 144:ef7eb2e8f9f7 532 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 535 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 538 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 return HAL_OK;
<> 144:ef7eb2e8f9f7 541 }
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /**
<> 144:ef7eb2e8f9f7 544 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
<> 144:ef7eb2e8f9f7 545 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 546 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 547 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
<> 144:ef7eb2e8f9f7 548 * @param SrcAddress2: The source memory Buffer address for the background layer.
<> 144:ef7eb2e8f9f7 549 * @param DstAddress: The destination memory Buffer address.
<> 144:ef7eb2e8f9f7 550 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
<> 144:ef7eb2e8f9f7 551 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
<> 144:ef7eb2e8f9f7 552 * @retval HAL status
<> 144:ef7eb2e8f9f7 553 */
<> 144:ef7eb2e8f9f7 554 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Check the parameters */
<> 144:ef7eb2e8f9f7 557 assert_param(IS_DMA2D_LINE(Height));
<> 144:ef7eb2e8f9f7 558 assert_param(IS_DMA2D_PIXEL(Width));
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Process locked */
<> 144:ef7eb2e8f9f7 561 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 564 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Configure DMA2D Stream source2 address */
<> 144:ef7eb2e8f9f7 567 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Configure the source, destination address and the data size */
<> 144:ef7eb2e8f9f7 570 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Enable the transfer complete, transfer error and configuration error interrupts */
<> 144:ef7eb2e8f9f7 573 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 576 __HAL_DMA2D_ENABLE(hdma2d);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 return HAL_OK;
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /**
<> 144:ef7eb2e8f9f7 582 * @brief Abort the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 583 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 584 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 585 * @retval HAL status
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Abort the DMA2D transfer */
<> 144:ef7eb2e8f9f7 592 /* START bit is reset to make sure not to set it again, in the event the HW clears it
<> 157:ff67d9f36b67 593 between the register read and the register write by the CPU (writing 0 has no
<> 157:ff67d9f36b67 594 effect on START bitvalue) */
<> 144:ef7eb2e8f9f7 595 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Get tick */
<> 144:ef7eb2e8f9f7 598 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Check if the DMA2D is effectively disabled */
<> 144:ef7eb2e8f9f7 601 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
<> 144:ef7eb2e8f9f7 604 {
<> 144:ef7eb2e8f9f7 605 /* Update error code */
<> 144:ef7eb2e8f9f7 606 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 609 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 612 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
<> 144:ef7eb2e8f9f7 619 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Change the DMA2D state*/
<> 144:ef7eb2e8f9f7 622 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 625 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 return HAL_OK;
<> 144:ef7eb2e8f9f7 628 }
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /**
<> 144:ef7eb2e8f9f7 631 * @brief Suspend the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 632 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 633 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 634 * @retval HAL status
<> 144:ef7eb2e8f9f7 635 */
<> 144:ef7eb2e8f9f7 636 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Suspend the DMA2D transfer */
<> 144:ef7eb2e8f9f7 641 /* START bit is reset to make sure not to set it again, in the event the HW clears it
<> 157:ff67d9f36b67 642 between the register read and the register write by the CPU (writing 0 has no
<> 144:ef7eb2e8f9f7 643 effect on START bitvalue). */
<> 144:ef7eb2e8f9f7 644 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Get tick */
<> 144:ef7eb2e8f9f7 647 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Check if the DMA2D is effectively suspended */
<> 144:ef7eb2e8f9f7 650 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
<> 144:ef7eb2e8f9f7 651 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 /* Update error code */
<> 144:ef7eb2e8f9f7 656 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 659 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
<> 144:ef7eb2e8f9f7 666 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670 else
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 /* Make sure SUSP bit is cleared since it is meaningless
<> 144:ef7eb2e8f9f7 673 when no tranfer is on-going */
<> 144:ef7eb2e8f9f7 674 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 return HAL_OK;
<> 144:ef7eb2e8f9f7 678 }
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /**
<> 144:ef7eb2e8f9f7 681 * @brief Resume the DMA2D Transfer.
<> 144:ef7eb2e8f9f7 682 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 683 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 684 * @retval HAL status
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 /* Check the SUSP and START bits */
<> 144:ef7eb2e8f9f7 689 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
<> 144:ef7eb2e8f9f7 690 {
<> 144:ef7eb2e8f9f7 691 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
<> 144:ef7eb2e8f9f7 692 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Resume the DMA2D transfer */
<> 144:ef7eb2e8f9f7 696 /* START bit is reset to make sure not to set it again, in the event the HW clears it
<> 157:ff67d9f36b67 697 between the register read and the register write by the CPU (writing 0 has no
<> 144:ef7eb2e8f9f7 698 effect on START bitvalue). */
<> 144:ef7eb2e8f9f7 699 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 return HAL_OK;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @brief Enable the DMA2D CLUT Transfer.
<> 144:ef7eb2e8f9f7 707 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 708 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 709 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 710 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 711 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 712 * @retval HAL status
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 /* Check the parameters */
<> 144:ef7eb2e8f9f7 717 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Process locked */
<> 144:ef7eb2e8f9f7 720 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 723 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 /* Enable the background CLUT loading */
<> 144:ef7eb2e8f9f7 728 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 else
<> 144:ef7eb2e8f9f7 731 {
<> 144:ef7eb2e8f9f7 732 /* Enable the foreground CLUT loading */
<> 144:ef7eb2e8f9f7 733 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 return HAL_OK;
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /**
<> 144:ef7eb2e8f9f7 741 * @brief Start DMA2D CLUT Loading.
<> 144:ef7eb2e8f9f7 742 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 743 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 744 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
<> 144:ef7eb2e8f9f7 745 * the configuration information for the color look up table.
<> 144:ef7eb2e8f9f7 746 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 747 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 748 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 749 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
<> 144:ef7eb2e8f9f7 750 * @retval HAL status
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 /* Check the parameters */
<> 144:ef7eb2e8f9f7 755 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 756 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
<> 144:ef7eb2e8f9f7 757 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /* Process locked */
<> 144:ef7eb2e8f9f7 760 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 763 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /* Configure the CLUT of the background DMA2D layer */
<> 144:ef7eb2e8f9f7 766 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 767 {
<> 144:ef7eb2e8f9f7 768 /* Write background CLUT memory address */
<> 144:ef7eb2e8f9f7 769 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Write background CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 772 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 773 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Enable the CLUT loading for the background */
<> 144:ef7eb2e8f9f7 776 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 /* Configure the CLUT of the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 779 else
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 /* Write foreground CLUT memory address */
<> 144:ef7eb2e8f9f7 782 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Write foreground CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 785 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 786 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 /* Enable the CLUT loading for the foreground */
<> 144:ef7eb2e8f9f7 789 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 return HAL_OK;
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @brief Start DMA2D CLUT Loading with interrupt enabled.
<> 144:ef7eb2e8f9f7 797 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 798 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 799 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
<> 144:ef7eb2e8f9f7 800 * the configuration information for the color look up table.
<> 144:ef7eb2e8f9f7 801 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 802 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 803 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 804 * @retval HAL status
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 /* Check the parameters */
<> 144:ef7eb2e8f9f7 809 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 810 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
<> 144:ef7eb2e8f9f7 811 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /* Process locked */
<> 144:ef7eb2e8f9f7 814 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 817 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /* Configure the CLUT of the background DMA2D layer */
<> 144:ef7eb2e8f9f7 820 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 821 {
<> 144:ef7eb2e8f9f7 822 /* Write background CLUT memory address */
<> 144:ef7eb2e8f9f7 823 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /* Write background CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 826 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 827 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
<> 144:ef7eb2e8f9f7 830 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Enable the CLUT loading for the background */
<> 144:ef7eb2e8f9f7 833 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 /* Configure the CLUT of the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 836 else
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 /* Write foreground CLUT memory address */
<> 144:ef7eb2e8f9f7 839 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Write foreground CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 842 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 843 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
<> 144:ef7eb2e8f9f7 846 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Enable the CLUT loading for the foreground */
<> 144:ef7eb2e8f9f7 849 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 return HAL_OK;
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 /**
<> 144:ef7eb2e8f9f7 856 * @brief Abort the DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 857 * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 858 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 859 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 860 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 861 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 862 * @retval HAL status
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 867 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /* Abort the CLUT loading */
<> 144:ef7eb2e8f9f7 870 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* If foreground CLUT loading is considered, update local variables */
<> 144:ef7eb2e8f9f7 873 if(LayerIdx == 1)
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 reg = &(hdma2d->Instance->FGPFCCR);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Get tick */
<> 144:ef7eb2e8f9f7 880 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Check if the CLUT loading is aborted */
<> 144:ef7eb2e8f9f7 883 while((*reg & DMA2D_BGPFCCR_START) != RESET)
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
<> 144:ef7eb2e8f9f7 886 {
<> 144:ef7eb2e8f9f7 887 /* Update error code */
<> 144:ef7eb2e8f9f7 888 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 891 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 894 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 897 }
<> 144:ef7eb2e8f9f7 898 }
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
<> 144:ef7eb2e8f9f7 901 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 /* Change the DMA2D state*/
<> 144:ef7eb2e8f9f7 904 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 907 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 return HAL_OK;
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 /**
<> 144:ef7eb2e8f9f7 913 * @brief Suspend the DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 914 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 915 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 916 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 917 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 918 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 919 * @retval HAL status
<> 144:ef7eb2e8f9f7 920 */
<> 144:ef7eb2e8f9f7 921 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 922 {
<> 144:ef7eb2e8f9f7 923 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 924 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /* Suspend the CLUT loading */
<> 144:ef7eb2e8f9f7 927 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /* If foreground CLUT loading is considered, update local variables */
<> 144:ef7eb2e8f9f7 930 if(LayerIdx == 1)
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 reg = &(hdma2d->Instance->FGPFCCR);
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Get tick */
<> 144:ef7eb2e8f9f7 936 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Check if the CLUT loading is suspended */
<> 144:ef7eb2e8f9f7 939 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
<> 144:ef7eb2e8f9f7 940 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
<> 144:ef7eb2e8f9f7 941 {
<> 144:ef7eb2e8f9f7 942 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
<> 144:ef7eb2e8f9f7 943 {
<> 144:ef7eb2e8f9f7 944 /* Update error code */
<> 144:ef7eb2e8f9f7 945 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 948 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952 }
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
<> 144:ef7eb2e8f9f7 955 if ((*reg & DMA2D_BGPFCCR_START) != RESET)
<> 144:ef7eb2e8f9f7 956 {
<> 144:ef7eb2e8f9f7 957 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
<> 144:ef7eb2e8f9f7 958 }
<> 144:ef7eb2e8f9f7 959 else
<> 144:ef7eb2e8f9f7 960 {
<> 144:ef7eb2e8f9f7 961 /* Make sure SUSP bit is cleared since it is meaningless
<> 144:ef7eb2e8f9f7 962 when no tranfer is on-going */
<> 144:ef7eb2e8f9f7 963 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 964 }
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 return HAL_OK;
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /**
<> 144:ef7eb2e8f9f7 970 * @brief Resume the DMA2D CLUT loading.
<> 144:ef7eb2e8f9f7 971 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 972 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 973 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 974 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 975 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 976 * @retval HAL status
<> 144:ef7eb2e8f9f7 977 */
<> 144:ef7eb2e8f9f7 978 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 /* Check the SUSP and START bits for background or foreground CLUT loading */
<> 144:ef7eb2e8f9f7 981 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 982 {
<> 144:ef7eb2e8f9f7 983 /* Background CLUT loading suspension check */
<> 144:ef7eb2e8f9f7 984 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
<> 144:ef7eb2e8f9f7 985 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
<> 144:ef7eb2e8f9f7 986 {
<> 144:ef7eb2e8f9f7 987 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
<> 144:ef7eb2e8f9f7 988 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 989 }
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 else
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* Foreground CLUT loading suspension check */
<> 144:ef7eb2e8f9f7 994 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
<> 144:ef7eb2e8f9f7 995 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
<> 144:ef7eb2e8f9f7 996 {
<> 144:ef7eb2e8f9f7 997 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
<> 144:ef7eb2e8f9f7 998 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Resume the CLUT loading */
<> 144:ef7eb2e8f9f7 1003 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 return HAL_OK;
<> 144:ef7eb2e8f9f7 1006 }
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /**
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 * @brief Polling for transfer complete or CLUT loading.
<> 144:ef7eb2e8f9f7 1012 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1013 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1014 * @param Timeout: Timeout duration
<> 144:ef7eb2e8f9f7 1015 * @retval HAL status
<> 144:ef7eb2e8f9f7 1016 */
<> 144:ef7eb2e8f9f7 1017 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1018 {
<> 144:ef7eb2e8f9f7 1019 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 1020 __IO uint32_t isrflags = 0x0;
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /* Polling for DMA2D transfer */
<> 144:ef7eb2e8f9f7 1023 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
<> 144:ef7eb2e8f9f7 1024 {
<> 144:ef7eb2e8f9f7 1025 /* Get tick */
<> 144:ef7eb2e8f9f7 1026 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 isrflags = READ_REG(hdma2d->Instance->ISR);
<> 144:ef7eb2e8f9f7 1031 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
<> 144:ef7eb2e8f9f7 1032 {
<> 144:ef7eb2e8f9f7 1033 if ((isrflags & DMA2D_FLAG_CE) != RESET)
<> 144:ef7eb2e8f9f7 1034 {
<> 144:ef7eb2e8f9f7 1035 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 if ((isrflags & DMA2D_FLAG_TE) != RESET)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041 /* Clear the transfer and configuration error flags */
<> 144:ef7eb2e8f9f7 1042 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1045 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1048 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1051 }
<> 144:ef7eb2e8f9f7 1052 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1053 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1056 {
<> 144:ef7eb2e8f9f7 1057 /* Update error code */
<> 144:ef7eb2e8f9f7 1058 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 1061 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1064 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1067 }
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 }
<> 144:ef7eb2e8f9f7 1071 /* Polling for CLUT loading (foreground or background) */
<> 144:ef7eb2e8f9f7 1072 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
<> 144:ef7eb2e8f9f7 1073 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
<> 144:ef7eb2e8f9f7 1074 {
<> 144:ef7eb2e8f9f7 1075 /* Get tick */
<> 144:ef7eb2e8f9f7 1076 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
<> 144:ef7eb2e8f9f7 1079 {
<> 144:ef7eb2e8f9f7 1080 isrflags = READ_REG(hdma2d->Instance->ISR);
<> 144:ef7eb2e8f9f7 1081 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
<> 144:ef7eb2e8f9f7 1082 {
<> 144:ef7eb2e8f9f7 1083 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087 if ((isrflags & DMA2D_FLAG_CE) != RESET)
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091 if ((isrflags & DMA2D_FLAG_TE) != RESET)
<> 144:ef7eb2e8f9f7 1092 {
<> 144:ef7eb2e8f9f7 1093 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
<> 144:ef7eb2e8f9f7 1094 }
<> 144:ef7eb2e8f9f7 1095 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
<> 144:ef7eb2e8f9f7 1096 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1099 hdma2d->State= HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1102 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1105 }
<> 144:ef7eb2e8f9f7 1106 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1107 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1108 {
<> 144:ef7eb2e8f9f7 1109 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1110 {
<> 144:ef7eb2e8f9f7 1111 /* Update error code */
<> 144:ef7eb2e8f9f7 1112 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 /* Change the DMA2D state */
<> 144:ef7eb2e8f9f7 1115 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1118 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1121 }
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123 }
<> 144:ef7eb2e8f9f7 1124 }
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /* Clear the transfer complete and CLUT loading flags */
<> 144:ef7eb2e8f9f7 1127 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1130 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1131
<> 144:ef7eb2e8f9f7 1132 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1133 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 return HAL_OK;
<> 144:ef7eb2e8f9f7 1136 }
<> 144:ef7eb2e8f9f7 1137 /**
<> 144:ef7eb2e8f9f7 1138 * @brief Handle DMA2D interrupt request.
<> 144:ef7eb2e8f9f7 1139 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1140 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1141 * @retval HAL status
<> 144:ef7eb2e8f9f7 1142 */
<> 144:ef7eb2e8f9f7 1143 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1144 {
<> 144:ef7eb2e8f9f7 1145 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
<> 144:ef7eb2e8f9f7 1146 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /* Transfer Error Interrupt management ***************************************/
<> 144:ef7eb2e8f9f7 1149 if ((isrflags & DMA2D_FLAG_TE) != RESET)
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 if ((crflags & DMA2D_IT_TE) != RESET)
<> 144:ef7eb2e8f9f7 1152 {
<> 144:ef7eb2e8f9f7 1153 /* Disable the transfer Error interrupt */
<> 144:ef7eb2e8f9f7 1154 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /* Update error code */
<> 144:ef7eb2e8f9f7 1157 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /* Clear the transfer error flag */
<> 144:ef7eb2e8f9f7 1160 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1163 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1166 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 if(hdma2d->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 1169 {
<> 144:ef7eb2e8f9f7 1170 /* Transfer error Callback */
<> 144:ef7eb2e8f9f7 1171 hdma2d->XferErrorCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1172 }
<> 144:ef7eb2e8f9f7 1173 }
<> 144:ef7eb2e8f9f7 1174 }
<> 144:ef7eb2e8f9f7 1175 /* Configuration Error Interrupt management **********************************/
<> 144:ef7eb2e8f9f7 1176 if ((isrflags & DMA2D_FLAG_CE) != RESET)
<> 144:ef7eb2e8f9f7 1177 {
<> 144:ef7eb2e8f9f7 1178 if ((crflags & DMA2D_IT_CE) != RESET)
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 /* Disable the Configuration Error interrupt */
<> 144:ef7eb2e8f9f7 1181 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /* Clear the Configuration error flag */
<> 144:ef7eb2e8f9f7 1184 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 /* Update error code */
<> 144:ef7eb2e8f9f7 1187 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1190 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1193 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 if(hdma2d->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 1196 {
<> 144:ef7eb2e8f9f7 1197 /* Transfer error Callback */
<> 144:ef7eb2e8f9f7 1198 hdma2d->XferErrorCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200 }
<> 144:ef7eb2e8f9f7 1201 }
<> 144:ef7eb2e8f9f7 1202 /* CLUT access Error Interrupt management ***********************************/
<> 144:ef7eb2e8f9f7 1203 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
<> 144:ef7eb2e8f9f7 1204 {
<> 144:ef7eb2e8f9f7 1205 if ((crflags & DMA2D_IT_CAE) != RESET)
<> 144:ef7eb2e8f9f7 1206 {
<> 144:ef7eb2e8f9f7 1207 /* Disable the CLUT access error interrupt */
<> 144:ef7eb2e8f9f7 1208 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /* Clear the CLUT access error flag */
<> 144:ef7eb2e8f9f7 1211 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /* Update error code */
<> 144:ef7eb2e8f9f7 1214 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1217 hdma2d->State = HAL_DMA2D_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1220 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 if(hdma2d->XferErrorCallback != NULL)
<> 144:ef7eb2e8f9f7 1223 {
<> 144:ef7eb2e8f9f7 1224 /* Transfer error Callback */
<> 144:ef7eb2e8f9f7 1225 hdma2d->XferErrorCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1226 }
<> 144:ef7eb2e8f9f7 1227 }
<> 144:ef7eb2e8f9f7 1228 }
<> 144:ef7eb2e8f9f7 1229 /* Transfer watermark Interrupt management **********************************/
<> 144:ef7eb2e8f9f7 1230 if ((isrflags & DMA2D_FLAG_TW) != RESET)
<> 144:ef7eb2e8f9f7 1231 {
<> 144:ef7eb2e8f9f7 1232 if ((crflags & DMA2D_IT_TW) != RESET)
<> 144:ef7eb2e8f9f7 1233 {
<> 144:ef7eb2e8f9f7 1234 /* Disable the transfer watermark interrupt */
<> 144:ef7eb2e8f9f7 1235 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /* Clear the transfer watermark flag */
<> 144:ef7eb2e8f9f7 1238 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 /* Transfer watermark Callback */
<> 144:ef7eb2e8f9f7 1241 HAL_DMA2D_LineEventCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243 }
<> 144:ef7eb2e8f9f7 1244 /* Transfer Complete Interrupt management ************************************/
<> 144:ef7eb2e8f9f7 1245 if ((isrflags & DMA2D_FLAG_TC) != RESET)
<> 144:ef7eb2e8f9f7 1246 {
<> 144:ef7eb2e8f9f7 1247 if ((crflags & DMA2D_IT_TC) != RESET)
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Disable the transfer complete interrupt */
<> 144:ef7eb2e8f9f7 1250 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /* Clear the transfer complete flag */
<> 144:ef7eb2e8f9f7 1253 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 /* Update error code */
<> 144:ef7eb2e8f9f7 1256 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1257
<> 144:ef7eb2e8f9f7 1258 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1259 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1262 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 if(hdma2d->XferCpltCallback != NULL)
<> 144:ef7eb2e8f9f7 1265 {
<> 144:ef7eb2e8f9f7 1266 /* Transfer complete Callback */
<> 144:ef7eb2e8f9f7 1267 hdma2d->XferCpltCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1268 }
<> 144:ef7eb2e8f9f7 1269 }
<> 144:ef7eb2e8f9f7 1270 }
<> 144:ef7eb2e8f9f7 1271 /* CLUT Transfer Complete Interrupt management ******************************/
<> 144:ef7eb2e8f9f7 1272 if ((isrflags & DMA2D_FLAG_CTC) != RESET)
<> 144:ef7eb2e8f9f7 1273 {
<> 144:ef7eb2e8f9f7 1274 if ((crflags & DMA2D_IT_CTC) != RESET)
<> 144:ef7eb2e8f9f7 1275 {
<> 144:ef7eb2e8f9f7 1276 /* Disable the CLUT transfer complete interrupt */
<> 144:ef7eb2e8f9f7 1277 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Clear the CLUT transfer complete flag */
<> 144:ef7eb2e8f9f7 1280 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /* Update error code */
<> 144:ef7eb2e8f9f7 1283 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /* Change DMA2D state */
<> 144:ef7eb2e8f9f7 1286 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1289 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* CLUT Transfer complete Callback */
<> 144:ef7eb2e8f9f7 1292 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /**
<> 144:ef7eb2e8f9f7 1299 * @brief Transfer watermark callback.
<> 144:ef7eb2e8f9f7 1300 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1301 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1302 * @retval None
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1307 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1310 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1311 */
<> 144:ef7eb2e8f9f7 1312 }
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @brief CLUT Transfer Complete callback.
<> 144:ef7eb2e8f9f7 1316 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1317 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1318 * @retval None
<> 144:ef7eb2e8f9f7 1319 */
<> 144:ef7eb2e8f9f7 1320 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1321 {
<> 144:ef7eb2e8f9f7 1322 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1323 UNUSED(hdma2d);
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1326 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
<> 144:ef7eb2e8f9f7 1327 */
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /**
<> 144:ef7eb2e8f9f7 1331 * @}
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1335 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1336 *
<> 144:ef7eb2e8f9f7 1337 @verbatim
<> 144:ef7eb2e8f9f7 1338 ===============================================================================
<> 144:ef7eb2e8f9f7 1339 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1340 ===============================================================================
<> 144:ef7eb2e8f9f7 1341 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1342 (+) Configure the DMA2D foreground or background layer parameters.
<> 144:ef7eb2e8f9f7 1343 (+) Configure the DMA2D CLUT transfer.
<> 144:ef7eb2e8f9f7 1344 (+) Configure the line watermark
<> 144:ef7eb2e8f9f7 1345 (+) Configure the dead time value.
<> 144:ef7eb2e8f9f7 1346 (+) Enable or disable the dead time value functionality.
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348
<> 144:ef7eb2e8f9f7 1349 @endverbatim
<> 144:ef7eb2e8f9f7 1350 * @{
<> 144:ef7eb2e8f9f7 1351 */
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /**
<> 144:ef7eb2e8f9f7 1354 * @brief Configure the DMA2D Layer according to the specified
<> 144:ef7eb2e8f9f7 1355 * parameters in the DMA2D_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1356 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1357 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1358 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 1359 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1360 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 1361 * @retval HAL status
<> 144:ef7eb2e8f9f7 1362 */
<> 144:ef7eb2e8f9f7 1363 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 1364 {
<> 144:ef7eb2e8f9f7 1365 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 uint32_t regMask = 0, regValue = 0;
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1370 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 1371 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
<> 144:ef7eb2e8f9f7 1372 if(hdma2d->Init.Mode != DMA2D_R2M)
<> 144:ef7eb2e8f9f7 1373 {
<> 144:ef7eb2e8f9f7 1374 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
<> 144:ef7eb2e8f9f7 1375 if(hdma2d->Init.Mode != DMA2D_M2M)
<> 144:ef7eb2e8f9f7 1376 {
<> 144:ef7eb2e8f9f7 1377 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
<> 144:ef7eb2e8f9f7 1378 }
<> 144:ef7eb2e8f9f7 1379 }
<> 144:ef7eb2e8f9f7 1380
<> 144:ef7eb2e8f9f7 1381 /* Process locked */
<> 144:ef7eb2e8f9f7 1382 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 1385 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* DMA2D BGPFCR register configuration -----------------------------------*/
<> 144:ef7eb2e8f9f7 1388 /* Prepare the value to be written to the BGPFCCR register */
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM);
<> 144:ef7eb2e8f9f7 1391 regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
<> 144:ef7eb2e8f9f7 1392
<> 144:ef7eb2e8f9f7 1393 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
<> 144:ef7eb2e8f9f7 1394 regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI);
<> 144:ef7eb2e8f9f7 1395 regMask |= DMA2D_BGPFCCR_AI;
<> 144:ef7eb2e8f9f7 1396 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
<> 144:ef7eb2e8f9f7 1397
<> 144:ef7eb2e8f9f7 1398 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
<> 144:ef7eb2e8f9f7 1399 regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);
<> 144:ef7eb2e8f9f7 1400 regMask |= DMA2D_BGPFCCR_RBS;
<> 144:ef7eb2e8f9f7 1401 #endif
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
<> 144:ef7eb2e8f9f7 1404 {
<> 144:ef7eb2e8f9f7 1405 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407 else
<> 144:ef7eb2e8f9f7 1408 {
<> 144:ef7eb2e8f9f7 1409 regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
<> 144:ef7eb2e8f9f7 1410 }
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 /* Configure the background DMA2D layer */
<> 144:ef7eb2e8f9f7 1413 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 1414 {
<> 144:ef7eb2e8f9f7 1415 /* Write DMA2D BGPFCCR register */
<> 144:ef7eb2e8f9f7 1416 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 /* DMA2D BGOR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1419 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
<> 144:ef7eb2e8f9f7 1420
<> 144:ef7eb2e8f9f7 1421 /* DMA2D BGCOLR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1422 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
<> 144:ef7eb2e8f9f7 1423 {
<> 144:ef7eb2e8f9f7 1424 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426 }
<> 144:ef7eb2e8f9f7 1427 /* Configure the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 1428 else
<> 144:ef7eb2e8f9f7 1429 {
<> 144:ef7eb2e8f9f7 1430 /* Write DMA2D FGPFCCR register */
<> 144:ef7eb2e8f9f7 1431 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
<> 144:ef7eb2e8f9f7 1432
<> 144:ef7eb2e8f9f7 1433 /* DMA2D FGOR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1434 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
<> 144:ef7eb2e8f9f7 1435
<> 144:ef7eb2e8f9f7 1436 /* DMA2D FGCOLR register configuration -------------------------------------*/
<> 144:ef7eb2e8f9f7 1437 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
<> 144:ef7eb2e8f9f7 1438 {
<> 144:ef7eb2e8f9f7 1439 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
<> 144:ef7eb2e8f9f7 1440 }
<> 144:ef7eb2e8f9f7 1441 }
<> 144:ef7eb2e8f9f7 1442 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 1443 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1444
<> 144:ef7eb2e8f9f7 1445 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1446 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 return HAL_OK;
<> 144:ef7eb2e8f9f7 1449 }
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /**
<> 144:ef7eb2e8f9f7 1452 * @brief Configure the DMA2D CLUT Transfer.
<> 144:ef7eb2e8f9f7 1453 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1454 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1455 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1456 * the configuration information for the color look up table.
<> 144:ef7eb2e8f9f7 1457 * @param LayerIdx: DMA2D Layer index.
<> 144:ef7eb2e8f9f7 1458 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1459 * 0(background) / 1(foreground)
<> 144:ef7eb2e8f9f7 1460 * @retval HAL status
<> 144:ef7eb2e8f9f7 1461 */
<> 144:ef7eb2e8f9f7 1462 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
<> 144:ef7eb2e8f9f7 1463 {
<> 144:ef7eb2e8f9f7 1464 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1465 assert_param(IS_DMA2D_LAYER(LayerIdx));
<> 144:ef7eb2e8f9f7 1466 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
<> 144:ef7eb2e8f9f7 1467 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 /* Process locked */
<> 144:ef7eb2e8f9f7 1470 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1471
<> 144:ef7eb2e8f9f7 1472 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 1473 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 /* Configure the CLUT of the background DMA2D layer */
<> 144:ef7eb2e8f9f7 1476 if(LayerIdx == 0)
<> 144:ef7eb2e8f9f7 1477 {
<> 144:ef7eb2e8f9f7 1478 /* Write background CLUT memory address */
<> 144:ef7eb2e8f9f7 1479 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /* Write background CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 1482 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 1483 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 1484 }
<> 144:ef7eb2e8f9f7 1485 /* Configure the CLUT of the foreground DMA2D layer */
<> 144:ef7eb2e8f9f7 1486 else
<> 144:ef7eb2e8f9f7 1487 {
<> 144:ef7eb2e8f9f7 1488 /* Write foreground CLUT memory address */
<> 144:ef7eb2e8f9f7 1489 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /* Write foreground CLUT size and CLUT color mode */
<> 144:ef7eb2e8f9f7 1492 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
<> 144:ef7eb2e8f9f7 1493 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
<> 144:ef7eb2e8f9f7 1494 }
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 /* Set the DMA2D state to Ready*/
<> 144:ef7eb2e8f9f7 1497 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1498
<> 144:ef7eb2e8f9f7 1499 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1500 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1501
<> 144:ef7eb2e8f9f7 1502 return HAL_OK;
<> 144:ef7eb2e8f9f7 1503 }
<> 144:ef7eb2e8f9f7 1504
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /**
<> 144:ef7eb2e8f9f7 1507 * @brief Configure the line watermark.
<> 144:ef7eb2e8f9f7 1508 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1509 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1510 * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
<> 144:ef7eb2e8f9f7 1511 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
<> 144:ef7eb2e8f9f7 1512 * @note The transfer watermark interrupt is disabled once it has occurred.
<> 144:ef7eb2e8f9f7 1513 * @retval HAL status
<> 144:ef7eb2e8f9f7 1514 */
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
<> 144:ef7eb2e8f9f7 1517 {
<> 144:ef7eb2e8f9f7 1518 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1519 assert_param(IS_DMA2D_LINEWATERMARK(Line));
<> 144:ef7eb2e8f9f7 1520
<> 144:ef7eb2e8f9f7 1521 if (Line > DMA2D_LWR_LW)
<> 144:ef7eb2e8f9f7 1522 {
<> 144:ef7eb2e8f9f7 1523 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1524 }
<> 144:ef7eb2e8f9f7 1525 else
<> 144:ef7eb2e8f9f7 1526 {
<> 144:ef7eb2e8f9f7 1527 /* Process locked */
<> 144:ef7eb2e8f9f7 1528 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /* Change DMA2D peripheral state */
<> 144:ef7eb2e8f9f7 1531 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1532
<> 144:ef7eb2e8f9f7 1533 /* Sets the Line watermark configuration */
<> 144:ef7eb2e8f9f7 1534 WRITE_REG(hdma2d->Instance->LWR, Line);
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536 /* Enable the Line interrupt */
<> 144:ef7eb2e8f9f7 1537 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
<> 144:ef7eb2e8f9f7 1538
<> 144:ef7eb2e8f9f7 1539 /* Initialize the DMA2D state*/
<> 144:ef7eb2e8f9f7 1540 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1543 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 return HAL_OK;
<> 144:ef7eb2e8f9f7 1546 }
<> 144:ef7eb2e8f9f7 1547 }
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 /**
<> 144:ef7eb2e8f9f7 1550 * @brief Enable DMA2D dead time feature.
<> 144:ef7eb2e8f9f7 1551 * @param hdma2d: DMA2D handle.
<> 144:ef7eb2e8f9f7 1552 * @retval HAL status
<> 144:ef7eb2e8f9f7 1553 */
<> 144:ef7eb2e8f9f7 1554 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1555 {
<> 144:ef7eb2e8f9f7 1556 /* Process Locked */
<> 144:ef7eb2e8f9f7 1557 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1558
<> 144:ef7eb2e8f9f7 1559 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 /* Set DMA2D_AMTCR EN bit */
<> 144:ef7eb2e8f9f7 1562 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1567 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 return HAL_OK;
<> 144:ef7eb2e8f9f7 1570 }
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 /**
<> 144:ef7eb2e8f9f7 1573 * @brief Disable DMA2D dead time feature.
<> 144:ef7eb2e8f9f7 1574 * @param hdma2d: DMA2D handle.
<> 144:ef7eb2e8f9f7 1575 * @retval HAL status
<> 144:ef7eb2e8f9f7 1576 */
<> 144:ef7eb2e8f9f7 1577 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1578 {
<> 144:ef7eb2e8f9f7 1579 /* Process Locked */
<> 144:ef7eb2e8f9f7 1580 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 /* Clear DMA2D_AMTCR EN bit */
<> 144:ef7eb2e8f9f7 1585 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1590 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 return HAL_OK;
<> 144:ef7eb2e8f9f7 1593 }
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /**
<> 144:ef7eb2e8f9f7 1596 * @brief Configure dead time.
<> 144:ef7eb2e8f9f7 1597 * @note The dead time value represents the guaranteed minimum number of cycles between
<> 144:ef7eb2e8f9f7 1598 * two consecutive transactions on the AHB bus.
<> 144:ef7eb2e8f9f7 1599 * @param hdma2d: DMA2D handle.
<> 144:ef7eb2e8f9f7 1600 * @param DeadTime: dead time value.
<> 144:ef7eb2e8f9f7 1601 * @retval HAL status
<> 144:ef7eb2e8f9f7 1602 */
<> 144:ef7eb2e8f9f7 1603 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
<> 144:ef7eb2e8f9f7 1604 {
<> 144:ef7eb2e8f9f7 1605 /* Process Locked */
<> 144:ef7eb2e8f9f7 1606 __HAL_LOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1607
<> 144:ef7eb2e8f9f7 1608 hdma2d->State = HAL_DMA2D_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /* Set DMA2D_AMTCR DT field */
<> 144:ef7eb2e8f9f7 1611 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613 hdma2d->State = HAL_DMA2D_STATE_READY;
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1616 __HAL_UNLOCK(hdma2d);
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 return HAL_OK;
<> 144:ef7eb2e8f9f7 1619 }
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /**
<> 144:ef7eb2e8f9f7 1622 * @}
<> 144:ef7eb2e8f9f7 1623 */
<> 144:ef7eb2e8f9f7 1624
<> 144:ef7eb2e8f9f7 1625
<> 144:ef7eb2e8f9f7 1626 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 1627 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 1628 *
<> 144:ef7eb2e8f9f7 1629 @verbatim
<> 144:ef7eb2e8f9f7 1630 ===============================================================================
<> 144:ef7eb2e8f9f7 1631 ##### Peripheral State and Errors functions #####
<> 144:ef7eb2e8f9f7 1632 ===============================================================================
<> 144:ef7eb2e8f9f7 1633 [..]
<> 144:ef7eb2e8f9f7 1634 This subsection provides functions allowing to :
<> 144:ef7eb2e8f9f7 1635 (+) Get the DMA2D state
<> 144:ef7eb2e8f9f7 1636 (+) Get the DMA2D error code
<> 144:ef7eb2e8f9f7 1637
<> 144:ef7eb2e8f9f7 1638 @endverbatim
<> 144:ef7eb2e8f9f7 1639 * @{
<> 144:ef7eb2e8f9f7 1640 */
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 /**
<> 144:ef7eb2e8f9f7 1643 * @brief Return the DMA2D state
<> 144:ef7eb2e8f9f7 1644 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1645 * the configuration information for the DMA2D.
<> 144:ef7eb2e8f9f7 1646 * @retval HAL state
<> 144:ef7eb2e8f9f7 1647 */
<> 144:ef7eb2e8f9f7 1648 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1649 {
<> 144:ef7eb2e8f9f7 1650 return hdma2d->State;
<> 144:ef7eb2e8f9f7 1651 }
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653 /**
<> 144:ef7eb2e8f9f7 1654 * @brief Return the DMA2D error code
<> 144:ef7eb2e8f9f7 1655 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1656 * the configuration information for DMA2D.
<> 144:ef7eb2e8f9f7 1657 * @retval DMA2D Error Code
<> 144:ef7eb2e8f9f7 1658 */
<> 144:ef7eb2e8f9f7 1659 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
<> 144:ef7eb2e8f9f7 1660 {
<> 144:ef7eb2e8f9f7 1661 return hdma2d->ErrorCode;
<> 144:ef7eb2e8f9f7 1662 }
<> 144:ef7eb2e8f9f7 1663
<> 144:ef7eb2e8f9f7 1664 /**
<> 144:ef7eb2e8f9f7 1665 * @}
<> 144:ef7eb2e8f9f7 1666 */
<> 144:ef7eb2e8f9f7 1667
<> 144:ef7eb2e8f9f7 1668 /**
<> 144:ef7eb2e8f9f7 1669 * @}
<> 144:ef7eb2e8f9f7 1670 */
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672
<> 144:ef7eb2e8f9f7 1673 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
<> 144:ef7eb2e8f9f7 1674 * @{
<> 144:ef7eb2e8f9f7 1675 */
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 /**
<> 144:ef7eb2e8f9f7 1678 * @brief Set the DMA2D transfer parameters.
<> 144:ef7eb2e8f9f7 1679 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1680 * the configuration information for the specified DMA2D.
<> 144:ef7eb2e8f9f7 1681 * @param pdata: The source memory Buffer address
<> 144:ef7eb2e8f9f7 1682 * @param DstAddress: The destination memory Buffer address
<> 144:ef7eb2e8f9f7 1683 * @param Width: The width of data to be transferred from source to destination.
<> 144:ef7eb2e8f9f7 1684 * @param Height: The height of data to be transferred from source to destination.
<> 144:ef7eb2e8f9f7 1685 * @retval HAL status
<> 144:ef7eb2e8f9f7 1686 */
<> 144:ef7eb2e8f9f7 1687 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
<> 144:ef7eb2e8f9f7 1688 {
<> 144:ef7eb2e8f9f7 1689 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 1690 uint32_t tmp1 = 0;
<> 144:ef7eb2e8f9f7 1691 uint32_t tmp2 = 0;
<> 144:ef7eb2e8f9f7 1692 uint32_t tmp3 = 0;
<> 144:ef7eb2e8f9f7 1693 uint32_t tmp4 = 0;
<> 144:ef7eb2e8f9f7 1694
<> 144:ef7eb2e8f9f7 1695 /* Configure DMA2D data size */
<> 144:ef7eb2e8f9f7 1696 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
<> 144:ef7eb2e8f9f7 1697
<> 144:ef7eb2e8f9f7 1698 /* Configure DMA2D destination address */
<> 144:ef7eb2e8f9f7 1699 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 /* Register to memory DMA2D mode selected */
<> 144:ef7eb2e8f9f7 1702 if (hdma2d->Init.Mode == DMA2D_R2M)
<> 144:ef7eb2e8f9f7 1703 {
<> 144:ef7eb2e8f9f7 1704 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
<> 144:ef7eb2e8f9f7 1705 tmp2 = pdata & DMA2D_OCOLR_RED_1;
<> 144:ef7eb2e8f9f7 1706 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
<> 144:ef7eb2e8f9f7 1707 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 /* Prepare the value to be written to the OCOLR register according to the color mode */
<> 144:ef7eb2e8f9f7 1710 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
<> 144:ef7eb2e8f9f7 1711 {
<> 144:ef7eb2e8f9f7 1712 tmp = (tmp3 | tmp2 | tmp1| tmp4);
<> 144:ef7eb2e8f9f7 1713 }
<> 144:ef7eb2e8f9f7 1714 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
<> 144:ef7eb2e8f9f7 1715 {
<> 144:ef7eb2e8f9f7 1716 tmp = (tmp3 | tmp2 | tmp4);
<> 144:ef7eb2e8f9f7 1717 }
<> 144:ef7eb2e8f9f7 1718 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
<> 144:ef7eb2e8f9f7 1719 {
<> 144:ef7eb2e8f9f7 1720 tmp2 = (tmp2 >> 19);
<> 144:ef7eb2e8f9f7 1721 tmp3 = (tmp3 >> 10);
<> 144:ef7eb2e8f9f7 1722 tmp4 = (tmp4 >> 3 );
<> 144:ef7eb2e8f9f7 1723 tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
<> 144:ef7eb2e8f9f7 1724 }
<> 144:ef7eb2e8f9f7 1725 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
<> 144:ef7eb2e8f9f7 1726 {
<> 144:ef7eb2e8f9f7 1727 tmp1 = (tmp1 >> 31);
<> 144:ef7eb2e8f9f7 1728 tmp2 = (tmp2 >> 19);
<> 144:ef7eb2e8f9f7 1729 tmp3 = (tmp3 >> 11);
<> 144:ef7eb2e8f9f7 1730 tmp4 = (tmp4 >> 3 );
<> 144:ef7eb2e8f9f7 1731 tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
<> 144:ef7eb2e8f9f7 1732 }
<> 144:ef7eb2e8f9f7 1733 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
<> 144:ef7eb2e8f9f7 1734 {
<> 144:ef7eb2e8f9f7 1735 tmp1 = (tmp1 >> 28);
<> 144:ef7eb2e8f9f7 1736 tmp2 = (tmp2 >> 20);
<> 144:ef7eb2e8f9f7 1737 tmp3 = (tmp3 >> 12);
<> 144:ef7eb2e8f9f7 1738 tmp4 = (tmp4 >> 4 );
<> 144:ef7eb2e8f9f7 1739 tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
<> 144:ef7eb2e8f9f7 1740 }
<> 144:ef7eb2e8f9f7 1741 /* Write to DMA2D OCOLR register */
<> 144:ef7eb2e8f9f7 1742 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
<> 144:ef7eb2e8f9f7 1743 }
<> 144:ef7eb2e8f9f7 1744 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
<> 144:ef7eb2e8f9f7 1745 {
<> 144:ef7eb2e8f9f7 1746 /* Configure DMA2D source address */
<> 144:ef7eb2e8f9f7 1747 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
<> 144:ef7eb2e8f9f7 1748 }
<> 144:ef7eb2e8f9f7 1749 }
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 /**
<> 144:ef7eb2e8f9f7 1752 * @}
<> 144:ef7eb2e8f9f7 1753 */
<> 157:ff67d9f36b67 1754 #endif /* DMA2D */
<> 144:ef7eb2e8f9f7 1755 #endif /* HAL_DMA2D_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1756 /**
<> 144:ef7eb2e8f9f7 1757 * @}
<> 144:ef7eb2e8f9f7 1758 */
<> 144:ef7eb2e8f9f7 1759
<> 144:ef7eb2e8f9f7 1760 /**
<> 144:ef7eb2e8f9f7 1761 * @}
<> 144:ef7eb2e8f9f7 1762 */
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/