mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
161:2cc1468da177
Child:
168:9672193075cf
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_dfsdm.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Digital Filter for Sigma-Delta Modulators
<> 144:ef7eb2e8f9f7 9 * (DFSDM) peripherals:
<> 144:ef7eb2e8f9f7 10 * + Initialization and configuration of channels and filters
<> 144:ef7eb2e8f9f7 11 * + Regular channels configuration
<> 144:ef7eb2e8f9f7 12 * + Injected channels configuration
<> 144:ef7eb2e8f9f7 13 * + Regular/Injected Channels DMA Configuration
<> 144:ef7eb2e8f9f7 14 * + Interrupts and flags management
<> 144:ef7eb2e8f9f7 15 * + Analog watchdog feature
<> 144:ef7eb2e8f9f7 16 * + Short-circuit detector feature
<> 144:ef7eb2e8f9f7 17 * + Extremes detector feature
<> 144:ef7eb2e8f9f7 18 * + Clock absence detector feature
<> 144:ef7eb2e8f9f7 19 * + Break generation on analog watchdog or short-circuit event
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 @verbatim
<> 144:ef7eb2e8f9f7 22 ==============================================================================
<> 144:ef7eb2e8f9f7 23 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 24 ==============================================================================
<> 144:ef7eb2e8f9f7 25 [..]
<> 144:ef7eb2e8f9f7 26 *** Channel initialization ***
<> 144:ef7eb2e8f9f7 27 ==============================
<> 144:ef7eb2e8f9f7 28 [..]
<> 144:ef7eb2e8f9f7 29 (#) User has first to initialize channels (before filters initialization).
<> 144:ef7eb2e8f9f7 30 (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
<> 144:ef7eb2e8f9f7 31 (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 32 (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 33 (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
<> 144:ef7eb2e8f9f7 34 (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
<> 144:ef7eb2e8f9f7 35 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 36 (#) Configure the output clock, input, serial interface, analog watchdog,
<> 144:ef7eb2e8f9f7 37 offset and data right bit shift parameters for this channel using the
<> 144:ef7eb2e8f9f7 38 HAL_DFSDM_ChannelInit() function.
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 *** Channel clock absence detector ***
<> 144:ef7eb2e8f9f7 41 ======================================
<> 144:ef7eb2e8f9f7 42 [..]
<> 144:ef7eb2e8f9f7 43 (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
<> 144:ef7eb2e8f9f7 44 HAL_DFSDM_ChannelCkabStart_IT().
<> 144:ef7eb2e8f9f7 45 (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
<> 144:ef7eb2e8f9f7 46 absence.
<> 144:ef7eb2e8f9f7 47 (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
<> 144:ef7eb2e8f9f7 48 clock absence is detected.
<> 144:ef7eb2e8f9f7 49 (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
<> 144:ef7eb2e8f9f7 50 HAL_DFSDM_ChannelCkabStop_IT().
<> 144:ef7eb2e8f9f7 51 (#) Please note that the same mode (polling or interrupt) has to be used
<> 144:ef7eb2e8f9f7 52 for all channels because the channels are sharing the same interrupt.
<> 144:ef7eb2e8f9f7 53 (#) Please note also that in interrupt mode, if clock absence detector is
<> 144:ef7eb2e8f9f7 54 stopped for one channel, interrupt will be disabled for all channels.
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 *** Channel short circuit detector ***
<> 144:ef7eb2e8f9f7 57 ======================================
<> 144:ef7eb2e8f9f7 58 [..]
<> 144:ef7eb2e8f9f7 59 (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
<> 144:ef7eb2e8f9f7 60 or HAL_DFSDM_ChannelScdStart_IT().
<> 144:ef7eb2e8f9f7 61 (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
<> 144:ef7eb2e8f9f7 62 circuit.
<> 144:ef7eb2e8f9f7 63 (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
<> 144:ef7eb2e8f9f7 64 short circuit is detected.
<> 144:ef7eb2e8f9f7 65 (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
<> 144:ef7eb2e8f9f7 66 or HAL_DFSDM_ChannelScdStop_IT().
<> 144:ef7eb2e8f9f7 67 (#) Please note that the same mode (polling or interrupt) has to be used
<> 144:ef7eb2e8f9f7 68 for all channels because the channels are sharing the same interrupt.
<> 144:ef7eb2e8f9f7 69 (#) Please note also that in interrupt mode, if short circuit detector is
<> 144:ef7eb2e8f9f7 70 stopped for one channel, interrupt will be disabled for all channels.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 *** Channel analog watchdog value ***
<> 144:ef7eb2e8f9f7 73 =====================================
<> 144:ef7eb2e8f9f7 74 [..]
<> 144:ef7eb2e8f9f7 75 (#) Get analog watchdog filter value of a channel using
<> 144:ef7eb2e8f9f7 76 HAL_DFSDM_ChannelGetAwdValue().
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 *** Channel offset value ***
<> 144:ef7eb2e8f9f7 79 =====================================
<> 144:ef7eb2e8f9f7 80 [..]
<> 144:ef7eb2e8f9f7 81 (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 *** Filter initialization ***
<> 144:ef7eb2e8f9f7 84 =============================
<> 144:ef7eb2e8f9f7 85 [..]
<> 144:ef7eb2e8f9f7 86 (#) After channel initialization, user has to init filters.
<> 144:ef7eb2e8f9f7 87 (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
<> 144:ef7eb2e8f9f7 88 (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
<> 144:ef7eb2e8f9f7 89 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 90 Please note that DFSDMz_FLT0 global interrupt could be already
<> 144:ef7eb2e8f9f7 91 enabled if interrupt is used for channel.
<> 144:ef7eb2e8f9f7 92 (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
<> 144:ef7eb2e8f9f7 93 with DFSDMz filter handle using __HAL_LINKDMA().
<> 144:ef7eb2e8f9f7 94 (#) Configure the regular conversion, injected conversion and filter
<> 144:ef7eb2e8f9f7 95 parameters for this filter using the HAL_DFSDM_FilterInit() function.
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 *** Filter regular channel conversion ***
<> 144:ef7eb2e8f9f7 98 =========================================
<> 144:ef7eb2e8f9f7 99 [..]
<> 144:ef7eb2e8f9f7 100 (#) Select regular channel and enable/disable continuous mode using
<> 144:ef7eb2e8f9f7 101 HAL_DFSDM_FilterConfigRegChannel().
<> 144:ef7eb2e8f9f7 102 (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
<> 144:ef7eb2e8f9f7 103 HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
<> 144:ef7eb2e8f9f7 104 HAL_DFSDM_FilterRegularMsbStart_DMA().
<> 144:ef7eb2e8f9f7 105 (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
<> 144:ef7eb2e8f9f7 106 the end of regular conversion.
<> 144:ef7eb2e8f9f7 107 (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
<> 144:ef7eb2e8f9f7 108 at the end of regular conversion.
<> 144:ef7eb2e8f9f7 109 (#) Get value of regular conversion and corresponding channel using
<> 144:ef7eb2e8f9f7 110 HAL_DFSDM_FilterGetRegularValue().
<> 144:ef7eb2e8f9f7 111 (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
<> 144:ef7eb2e8f9f7 112 HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
<> 144:ef7eb2e8f9f7 113 half transfer and at the transfer complete. Please note that
<> 144:ef7eb2e8f9f7 114 HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
<> 144:ef7eb2e8f9f7 115 circular mode.
<> 144:ef7eb2e8f9f7 116 (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
<> 144:ef7eb2e8f9f7 117 HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 *** Filter injected channels conversion ***
<> 144:ef7eb2e8f9f7 120 ===========================================
<> 144:ef7eb2e8f9f7 121 [..]
<> 144:ef7eb2e8f9f7 122 (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
<> 144:ef7eb2e8f9f7 123 (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
<> 144:ef7eb2e8f9f7 124 HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
<> 144:ef7eb2e8f9f7 125 HAL_DFSDM_FilterInjectedMsbStart_DMA().
<> 144:ef7eb2e8f9f7 126 (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
<> 144:ef7eb2e8f9f7 127 the end of injected conversion.
<> 144:ef7eb2e8f9f7 128 (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
<> 144:ef7eb2e8f9f7 129 at the end of injected conversion.
<> 144:ef7eb2e8f9f7 130 (#) Get value of injected conversion and corresponding channel using
<> 144:ef7eb2e8f9f7 131 HAL_DFSDM_FilterGetInjectedValue().
<> 144:ef7eb2e8f9f7 132 (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
<> 144:ef7eb2e8f9f7 133 HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
<> 144:ef7eb2e8f9f7 134 half transfer and at the transfer complete. Please note that
<> 144:ef7eb2e8f9f7 135 HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
<> 144:ef7eb2e8f9f7 136 circular mode.
<> 144:ef7eb2e8f9f7 137 (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
<> 144:ef7eb2e8f9f7 138 HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 *** Filter analog watchdog ***
<> 144:ef7eb2e8f9f7 141 ==============================
<> 144:ef7eb2e8f9f7 142 [..]
<> 144:ef7eb2e8f9f7 143 (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
<> 144:ef7eb2e8f9f7 144 (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
<> 144:ef7eb2e8f9f7 145 (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 *** Filter extreme detector ***
<> 144:ef7eb2e8f9f7 148 ===============================
<> 144:ef7eb2e8f9f7 149 [..]
<> 144:ef7eb2e8f9f7 150 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
<> 144:ef7eb2e8f9f7 151 (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
<> 144:ef7eb2e8f9f7 152 (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
<> 144:ef7eb2e8f9f7 153 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 *** Filter conversion time ***
<> 144:ef7eb2e8f9f7 156 ==============================
<> 144:ef7eb2e8f9f7 157 [..]
<> 144:ef7eb2e8f9f7 158 (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 @endverbatim
<> 144:ef7eb2e8f9f7 161 ******************************************************************************
<> 144:ef7eb2e8f9f7 162 * @attention
<> 144:ef7eb2e8f9f7 163 *
<> 144:ef7eb2e8f9f7 164 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 165 *
<> 144:ef7eb2e8f9f7 166 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 167 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 168 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 169 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 170 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 171 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 172 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 173 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 174 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 175 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 176 *
<> 144:ef7eb2e8f9f7 177 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 178 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 179 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 180 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 181 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 182 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 183 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 184 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 185 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 186 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 187 *
<> 144:ef7eb2e8f9f7 188 ******************************************************************************
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 192 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197 #ifdef HAL_DFSDM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 198 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 199 /** @defgroup DFSDM DFSDM
<> 144:ef7eb2e8f9f7 200 * @brief DFSDM HAL driver module
<> 144:ef7eb2e8f9f7 201 * @{
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 205 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 206 /** @defgroup DFSDM_Private_Define DFSDM Private Define
<> 144:ef7eb2e8f9f7 207 * @{
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 #define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
<> 144:ef7eb2e8f9f7 210 #define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
<> 144:ef7eb2e8f9f7 211 #define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
<> 144:ef7eb2e8f9f7 212 #define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
<> 144:ef7eb2e8f9f7 213 #define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
<> 144:ef7eb2e8f9f7 214 #define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
<> 144:ef7eb2e8f9f7 215 #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8
<> 144:ef7eb2e8f9f7 216 #define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
<> 144:ef7eb2e8f9f7 217 #define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
<> 144:ef7eb2e8f9f7 218 #define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
<> 144:ef7eb2e8f9f7 219 #define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
<> 144:ef7eb2e8f9f7 220 #define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
<> 144:ef7eb2e8f9f7 221 #define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
<> 144:ef7eb2e8f9f7 222 #define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
<> 144:ef7eb2e8f9f7 223 #define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
<> 144:ef7eb2e8f9f7 224 #define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
<> 144:ef7eb2e8f9f7 225 #define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
<> 144:ef7eb2e8f9f7 226 #define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
<> 144:ef7eb2e8f9f7 227 #define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
<> 144:ef7eb2e8f9f7 228 #define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
<> 144:ef7eb2e8f9f7 229 #define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
<> 144:ef7eb2e8f9f7 230 #define DFSDM_MSB_MASK 0xFFFF0000U
<> 144:ef7eb2e8f9f7 231 #define DFSDM_LSB_MASK 0x0000FFFFU
<> 144:ef7eb2e8f9f7 232 #define DFSDM_CKAB_TIMEOUT 5000U
<> 144:ef7eb2e8f9f7 233 #define DFSDM1_CHANNEL_NUMBER 8U
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @}
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 239 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 240 /** @defgroup DFSDM_Private_Variables DFSDM Private Variables
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t v_dfsdm1ChannelCounter = 0;
<> 144:ef7eb2e8f9f7 244 DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 250 /** @defgroup DFSDM_Private_Functions DFSDM Private Functions
<> 144:ef7eb2e8f9f7 251 * @{
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
<> 144:ef7eb2e8f9f7 254 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
<> 144:ef7eb2e8f9f7 255 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
<> 144:ef7eb2e8f9f7 256 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
<> 144:ef7eb2e8f9f7 257 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
<> 144:ef7eb2e8f9f7 258 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
<> 144:ef7eb2e8f9f7 259 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 260 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 261 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 262 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 263 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 269 /** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 274 * @brief Channel initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 275 *
<> 144:ef7eb2e8f9f7 276 @verbatim
<> 144:ef7eb2e8f9f7 277 ==============================================================================
<> 144:ef7eb2e8f9f7 278 ##### Channel initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 279 ==============================================================================
<> 144:ef7eb2e8f9f7 280 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 281 (+) Initialize the DFSDM channel.
<> 144:ef7eb2e8f9f7 282 (+) De-initialize the DFSDM channel.
<> 144:ef7eb2e8f9f7 283 @endverbatim
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @brief Initialize the DFSDM channel according to the specified parameters
<> 144:ef7eb2e8f9f7 289 * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
<> 144:ef7eb2e8f9f7 290 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 291 * @retval HAL status.
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /* Check DFSDM Channel handle */
<> 144:ef7eb2e8f9f7 296 if(hdfsdm_channel == NULL)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Check parameters */
<> 144:ef7eb2e8f9f7 302 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 303 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
<> 144:ef7eb2e8f9f7 304 assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
<> 144:ef7eb2e8f9f7 305 assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
<> 144:ef7eb2e8f9f7 306 assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
<> 144:ef7eb2e8f9f7 307 assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
<> 144:ef7eb2e8f9f7 308 assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
<> 144:ef7eb2e8f9f7 309 assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
<> 144:ef7eb2e8f9f7 310 assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
<> 144:ef7eb2e8f9f7 311 assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
<> 144:ef7eb2e8f9f7 312 assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Check that channel has not been already initialized */
<> 144:ef7eb2e8f9f7 315 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Call MSP init function */
<> 144:ef7eb2e8f9f7 321 HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /* Update the channel counter */
<> 144:ef7eb2e8f9f7 324 v_dfsdm1ChannelCounter++;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Configure output serial clock and enable global DFSDM interface only for first channel */
<> 144:ef7eb2e8f9f7 327 if(v_dfsdm1ChannelCounter == 1)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
<> 144:ef7eb2e8f9f7 330 /* Set the output serial clock source */
<> 144:ef7eb2e8f9f7 331 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
<> 144:ef7eb2e8f9f7 332 DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Reset clock divider */
<> 144:ef7eb2e8f9f7 335 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
<> 144:ef7eb2e8f9f7 336 if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
<> 144:ef7eb2e8f9f7 339 /* Set the output clock divider */
<> 144:ef7eb2e8f9f7 340 DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) <<
<> 144:ef7eb2e8f9f7 341 DFSDM_CHCFGR1_CLK_DIV_OFFSET);
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* enable the DFSDM global interface */
<> 144:ef7eb2e8f9f7 345 DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* Set channel input parameters */
<> 144:ef7eb2e8f9f7 349 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
<> 144:ef7eb2e8f9f7 350 DFSDM_CHCFGR1_CHINSEL);
<> 144:ef7eb2e8f9f7 351 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
<> 144:ef7eb2e8f9f7 352 hdfsdm_channel->Init.Input.DataPacking |
<> 144:ef7eb2e8f9f7 353 hdfsdm_channel->Init.Input.Pins);
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Set serial interface parameters */
<> 144:ef7eb2e8f9f7 356 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
<> 144:ef7eb2e8f9f7 357 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
<> 144:ef7eb2e8f9f7 358 hdfsdm_channel->Init.SerialInterface.SpiClock);
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /* Set analog watchdog parameters */
<> 144:ef7eb2e8f9f7 361 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
<> 144:ef7eb2e8f9f7 362 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
<> 144:ef7eb2e8f9f7 363 ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Set channel offset and right bit shift */
<> 144:ef7eb2e8f9f7 366 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
<> 144:ef7eb2e8f9f7 367 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
<> 144:ef7eb2e8f9f7 368 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Enable DFSDM channel */
<> 144:ef7eb2e8f9f7 371 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Set DFSDM Channel to ready state */
<> 144:ef7eb2e8f9f7 374 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Store channel handle in DFSDM channel handle table */
<> 144:ef7eb2e8f9f7 377 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 return HAL_OK;
<> 144:ef7eb2e8f9f7 380 }
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /**
<> 144:ef7eb2e8f9f7 383 * @brief De-initialize the DFSDM channel.
<> 144:ef7eb2e8f9f7 384 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 385 * @retval HAL status.
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Check DFSDM Channel handle */
<> 144:ef7eb2e8f9f7 390 if(hdfsdm_channel == NULL)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Check parameters */
<> 144:ef7eb2e8f9f7 396 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 /* Check that channel has not been already deinitialized */
<> 144:ef7eb2e8f9f7 399 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Disable the DFSDM channel */
<> 144:ef7eb2e8f9f7 405 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Update the channel counter */
<> 144:ef7eb2e8f9f7 408 v_dfsdm1ChannelCounter--;
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Disable global DFSDM at deinit of last channel */
<> 144:ef7eb2e8f9f7 411 if(v_dfsdm1ChannelCounter == 0)
<> 144:ef7eb2e8f9f7 412 {
<> 144:ef7eb2e8f9f7 413 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
<> 144:ef7eb2e8f9f7 414 }
<> 144:ef7eb2e8f9f7 415
<> 144:ef7eb2e8f9f7 416 /* Call MSP deinit function */
<> 144:ef7eb2e8f9f7 417 HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Set DFSDM Channel in reset state */
<> 144:ef7eb2e8f9f7 420 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Reset channel handle in DFSDM channel handle table */
<> 144:ef7eb2e8f9f7 423 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 return HAL_OK;
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @brief Initialize the DFSDM channel MSP.
<> 144:ef7eb2e8f9f7 430 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 431 * @retval None
<> 144:ef7eb2e8f9f7 432 */
<> 144:ef7eb2e8f9f7 433 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 436 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 439 the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 440 */
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /**
<> 144:ef7eb2e8f9f7 444 * @brief De-initialize the DFSDM channel MSP.
<> 144:ef7eb2e8f9f7 445 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 446 * @retval None
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 451 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 454 the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @}
<> 144:ef7eb2e8f9f7 460 */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
<> 144:ef7eb2e8f9f7 463 * @brief Channel operation functions
<> 144:ef7eb2e8f9f7 464 *
<> 144:ef7eb2e8f9f7 465 @verbatim
<> 144:ef7eb2e8f9f7 466 ==============================================================================
<> 144:ef7eb2e8f9f7 467 ##### Channel operation functions #####
<> 144:ef7eb2e8f9f7 468 ==============================================================================
<> 144:ef7eb2e8f9f7 469 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 470 (+) Manage clock absence detector feature.
<> 144:ef7eb2e8f9f7 471 (+) Manage short circuit detector feature.
<> 144:ef7eb2e8f9f7 472 (+) Get analog watchdog value.
<> 144:ef7eb2e8f9f7 473 (+) Modify offset value.
<> 144:ef7eb2e8f9f7 474 @endverbatim
<> 144:ef7eb2e8f9f7 475 * @{
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @brief This function allows to start clock absence detection in polling mode.
<> 144:ef7eb2e8f9f7 480 * @note Same mode has to be used for all channels.
<> 144:ef7eb2e8f9f7 481 * @note If clock is not available on this channel during 5 seconds,
<> 144:ef7eb2e8f9f7 482 * clock absence detection will not be activated and function
<> 144:ef7eb2e8f9f7 483 * will return HAL_TIMEOUT error.
<> 144:ef7eb2e8f9f7 484 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 485 * @retval HAL status
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 490 uint32_t channel;
<> 144:ef7eb2e8f9f7 491 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Check parameters */
<> 144:ef7eb2e8f9f7 494 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 497 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* Return error status */
<> 144:ef7eb2e8f9f7 500 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502 else
<> 144:ef7eb2e8f9f7 503 {
<> 144:ef7eb2e8f9f7 504 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 505 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* Get timeout */
<> 144:ef7eb2e8f9f7 508 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 511 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 516 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 /* Set timeout status */
<> 144:ef7eb2e8f9f7 519 status = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 520 break;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 /* Start clock absence detection */
<> 144:ef7eb2e8f9f7 527 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530 /* Return function status */
<> 144:ef7eb2e8f9f7 531 return status;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @brief This function allows to poll for the clock absence detection.
<> 144:ef7eb2e8f9f7 536 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 537 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 538 * @retval HAL status
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 541 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 544 uint32_t channel;
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Check parameters */
<> 144:ef7eb2e8f9f7 547 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 550 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 /* Return error status */
<> 144:ef7eb2e8f9f7 553 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555 else
<> 144:ef7eb2e8f9f7 556 {
<> 144:ef7eb2e8f9f7 557 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 558 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Get timeout */
<> 144:ef7eb2e8f9f7 561 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /* Wait clock absence detection */
<> 144:ef7eb2e8f9f7 564 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)
<> 144:ef7eb2e8f9f7 565 {
<> 144:ef7eb2e8f9f7 566 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 567 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 /* Return timeout status */
<> 144:ef7eb2e8f9f7 572 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* Clear clock absence detection flag */
<> 144:ef7eb2e8f9f7 578 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /* Return function status */
<> 144:ef7eb2e8f9f7 581 return HAL_OK;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /**
<> 144:ef7eb2e8f9f7 586 * @brief This function allows to stop clock absence detection in polling mode.
<> 144:ef7eb2e8f9f7 587 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 588 * @retval HAL status
<> 144:ef7eb2e8f9f7 589 */
<> 144:ef7eb2e8f9f7 590 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 593 uint32_t channel;
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Check parameters */
<> 144:ef7eb2e8f9f7 596 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 599 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Return error status */
<> 144:ef7eb2e8f9f7 602 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604 else
<> 144:ef7eb2e8f9f7 605 {
<> 144:ef7eb2e8f9f7 606 /* Stop clock absence detection */
<> 144:ef7eb2e8f9f7 607 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 610 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 611 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613 /* Return function status */
<> 144:ef7eb2e8f9f7 614 return status;
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @brief This function allows to start clock absence detection in interrupt mode.
<> 144:ef7eb2e8f9f7 619 * @note Same mode has to be used for all channels.
<> 144:ef7eb2e8f9f7 620 * @note If clock is not available on this channel during 5 seconds,
<> 144:ef7eb2e8f9f7 621 * clock absence detection will not be activated and function
<> 144:ef7eb2e8f9f7 622 * will return HAL_TIMEOUT error.
<> 144:ef7eb2e8f9f7 623 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 624 * @retval HAL status
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 627 {
<> 144:ef7eb2e8f9f7 628 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 629 uint32_t channel;
<> 144:ef7eb2e8f9f7 630 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Check parameters */
<> 144:ef7eb2e8f9f7 633 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 636 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 /* Return error status */
<> 144:ef7eb2e8f9f7 639 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 640 }
<> 144:ef7eb2e8f9f7 641 else
<> 144:ef7eb2e8f9f7 642 {
<> 144:ef7eb2e8f9f7 643 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 644 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Get timeout */
<> 144:ef7eb2e8f9f7 647 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 650 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 655 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 /* Set timeout status */
<> 144:ef7eb2e8f9f7 658 status = HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 659 break;
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 /* Activate clock absence detection interrupt */
<> 144:ef7eb2e8f9f7 666 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Start clock absence detection */
<> 144:ef7eb2e8f9f7 669 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
<> 144:ef7eb2e8f9f7 670 }
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672 /* Return function status */
<> 144:ef7eb2e8f9f7 673 return status;
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @brief Clock absence detection callback.
<> 144:ef7eb2e8f9f7 678 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 679 * @retval None
<> 144:ef7eb2e8f9f7 680 */
<> 144:ef7eb2e8f9f7 681 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 684 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 687 the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @brief This function allows to stop clock absence detection in interrupt mode.
<> 144:ef7eb2e8f9f7 693 * @note Interrupt will be disabled for all channels
<> 144:ef7eb2e8f9f7 694 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 695 * @retval HAL status
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 698 {
<> 144:ef7eb2e8f9f7 699 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 700 uint32_t channel;
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 /* Check parameters */
<> 144:ef7eb2e8f9f7 703 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 706 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 /* Return error status */
<> 144:ef7eb2e8f9f7 709 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 else
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* Stop clock absence detection */
<> 144:ef7eb2e8f9f7 714 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 717 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 718 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Disable clock absence detection interrupt */
<> 144:ef7eb2e8f9f7 721 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723 /* Return function status */
<> 144:ef7eb2e8f9f7 724 return status;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /**
<> 144:ef7eb2e8f9f7 728 * @brief This function allows to start short circuit detection in polling mode.
<> 144:ef7eb2e8f9f7 729 * @note Same mode has to be used for all channels
<> 144:ef7eb2e8f9f7 730 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 731 * @param Threshold : Short circuit detector threshold.
<> 144:ef7eb2e8f9f7 732 * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
<> 144:ef7eb2e8f9f7 733 * @param BreakSignal : Break signals assigned to short circuit event.
<> 144:ef7eb2e8f9f7 734 * This parameter can be a values combination of @ref DFSDM_BreakSignals.
<> 144:ef7eb2e8f9f7 735 * @retval HAL status
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 738 uint32_t Threshold,
<> 144:ef7eb2e8f9f7 739 uint32_t BreakSignal)
<> 144:ef7eb2e8f9f7 740 {
<> 144:ef7eb2e8f9f7 741 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Check parameters */
<> 144:ef7eb2e8f9f7 744 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 745 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
<> 144:ef7eb2e8f9f7 746 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 749 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 750 {
<> 144:ef7eb2e8f9f7 751 /* Return error status */
<> 144:ef7eb2e8f9f7 752 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 753 }
<> 144:ef7eb2e8f9f7 754 else
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 /* Configure threshold and break signals */
<> 144:ef7eb2e8f9f7 757 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
<> 144:ef7eb2e8f9f7 758 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
<> 144:ef7eb2e8f9f7 759 Threshold);
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Start short circuit detection */
<> 144:ef7eb2e8f9f7 762 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764 /* Return function status */
<> 144:ef7eb2e8f9f7 765 return status;
<> 144:ef7eb2e8f9f7 766 }
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /**
<> 144:ef7eb2e8f9f7 769 * @brief This function allows to poll for the short circuit detection.
<> 144:ef7eb2e8f9f7 770 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 771 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 772 * @retval HAL status
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 775 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 778 uint32_t channel;
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /* Check parameters */
<> 144:ef7eb2e8f9f7 781 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 784 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 785 {
<> 144:ef7eb2e8f9f7 786 /* Return error status */
<> 144:ef7eb2e8f9f7 787 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789 else
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 /* Get channel number from channel instance */
<> 144:ef7eb2e8f9f7 792 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 /* Get timeout */
<> 144:ef7eb2e8f9f7 795 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Wait short circuit detection */
<> 144:ef7eb2e8f9f7 798 while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)
<> 144:ef7eb2e8f9f7 799 {
<> 144:ef7eb2e8f9f7 800 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 801 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 804 {
<> 144:ef7eb2e8f9f7 805 /* Return timeout status */
<> 144:ef7eb2e8f9f7 806 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 807 }
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 812 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Return function status */
<> 144:ef7eb2e8f9f7 815 return HAL_OK;
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /**
<> 144:ef7eb2e8f9f7 820 * @brief This function allows to stop short circuit detection in polling mode.
<> 144:ef7eb2e8f9f7 821 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 822 * @retval HAL status
<> 144:ef7eb2e8f9f7 823 */
<> 144:ef7eb2e8f9f7 824 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 827 uint32_t channel;
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Check parameters */
<> 144:ef7eb2e8f9f7 830 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 833 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 /* Return error status */
<> 144:ef7eb2e8f9f7 836 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 else
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Stop short circuit detection */
<> 144:ef7eb2e8f9f7 841 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 844 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 845 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847 /* Return function status */
<> 144:ef7eb2e8f9f7 848 return status;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /**
<> 144:ef7eb2e8f9f7 852 * @brief This function allows to start short circuit detection in interrupt mode.
<> 144:ef7eb2e8f9f7 853 * @note Same mode has to be used for all channels
<> 144:ef7eb2e8f9f7 854 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 855 * @param Threshold : Short circuit detector threshold.
<> 144:ef7eb2e8f9f7 856 * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
<> 144:ef7eb2e8f9f7 857 * @param BreakSignal : Break signals assigned to short circuit event.
<> 144:ef7eb2e8f9f7 858 * This parameter can be a values combination of @ref DFSDM_BreakSignals.
<> 144:ef7eb2e8f9f7 859 * @retval HAL status
<> 144:ef7eb2e8f9f7 860 */
<> 144:ef7eb2e8f9f7 861 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 862 uint32_t Threshold,
<> 144:ef7eb2e8f9f7 863 uint32_t BreakSignal)
<> 144:ef7eb2e8f9f7 864 {
<> 144:ef7eb2e8f9f7 865 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /* Check parameters */
<> 144:ef7eb2e8f9f7 868 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 869 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
<> 144:ef7eb2e8f9f7 870 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 873 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 /* Return error status */
<> 144:ef7eb2e8f9f7 876 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878 else
<> 144:ef7eb2e8f9f7 879 {
<> 144:ef7eb2e8f9f7 880 /* Activate short circuit detection interrupt */
<> 144:ef7eb2e8f9f7 881 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /* Configure threshold and break signals */
<> 144:ef7eb2e8f9f7 884 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
<> 144:ef7eb2e8f9f7 885 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
<> 144:ef7eb2e8f9f7 886 Threshold);
<> 144:ef7eb2e8f9f7 887
<> 144:ef7eb2e8f9f7 888 /* Start short circuit detection */
<> 144:ef7eb2e8f9f7 889 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
<> 144:ef7eb2e8f9f7 890 }
<> 144:ef7eb2e8f9f7 891 /* Return function status */
<> 144:ef7eb2e8f9f7 892 return status;
<> 144:ef7eb2e8f9f7 893 }
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /**
<> 144:ef7eb2e8f9f7 896 * @brief Short circuit detection callback.
<> 144:ef7eb2e8f9f7 897 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 898 * @retval None
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 901 {
<> 144:ef7eb2e8f9f7 902 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 903 UNUSED(hdfsdm_channel);
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 906 the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908 }
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /**
<> 144:ef7eb2e8f9f7 911 * @brief This function allows to stop short circuit detection in interrupt mode.
<> 144:ef7eb2e8f9f7 912 * @note Interrupt will be disabled for all channels
<> 144:ef7eb2e8f9f7 913 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 914 * @retval HAL status
<> 144:ef7eb2e8f9f7 915 */
<> 144:ef7eb2e8f9f7 916 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 919 uint32_t channel;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Check parameters */
<> 144:ef7eb2e8f9f7 922 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 925 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 926 {
<> 144:ef7eb2e8f9f7 927 /* Return error status */
<> 144:ef7eb2e8f9f7 928 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 929 }
<> 144:ef7eb2e8f9f7 930 else
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* Stop short circuit detection */
<> 144:ef7eb2e8f9f7 933 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 936 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
<> 144:ef7eb2e8f9f7 937 DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /* Disable short circuit detection interrupt */
<> 144:ef7eb2e8f9f7 940 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942 /* Return function status */
<> 144:ef7eb2e8f9f7 943 return status;
<> 144:ef7eb2e8f9f7 944 }
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /**
<> 144:ef7eb2e8f9f7 947 * @brief This function allows to get channel analog watchdog value.
<> 144:ef7eb2e8f9f7 948 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 949 * @retval Channel analog watchdog value.
<> 144:ef7eb2e8f9f7 950 */
<> 144:ef7eb2e8f9f7 951 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
<> 144:ef7eb2e8f9f7 954 }
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 /**
<> 144:ef7eb2e8f9f7 957 * @brief This function allows to modify channel offset value.
<> 144:ef7eb2e8f9f7 958 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 959 * @param Offset : DFSDM channel offset.
<> 144:ef7eb2e8f9f7 960 * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
<> 144:ef7eb2e8f9f7 961 * @retval HAL status.
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
<> 144:ef7eb2e8f9f7 964 int32_t Offset)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /* Check parameters */
<> 144:ef7eb2e8f9f7 969 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
<> 144:ef7eb2e8f9f7 970 assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 /* Check DFSDM channel state */
<> 144:ef7eb2e8f9f7 973 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
<> 144:ef7eb2e8f9f7 974 {
<> 144:ef7eb2e8f9f7 975 /* Return error status */
<> 144:ef7eb2e8f9f7 976 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 977 }
<> 144:ef7eb2e8f9f7 978 else
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 /* Modify channel offset */
<> 144:ef7eb2e8f9f7 981 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
<> 144:ef7eb2e8f9f7 982 hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
<> 144:ef7eb2e8f9f7 983 }
<> 144:ef7eb2e8f9f7 984 /* Return function status */
<> 144:ef7eb2e8f9f7 985 return status;
<> 144:ef7eb2e8f9f7 986 }
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /**
<> 144:ef7eb2e8f9f7 989 * @}
<> 144:ef7eb2e8f9f7 990 */
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
<> 144:ef7eb2e8f9f7 993 * @brief Channel state function
<> 144:ef7eb2e8f9f7 994 *
<> 144:ef7eb2e8f9f7 995 @verbatim
<> 144:ef7eb2e8f9f7 996 ==============================================================================
<> 144:ef7eb2e8f9f7 997 ##### Channel state function #####
<> 144:ef7eb2e8f9f7 998 ==============================================================================
<> 144:ef7eb2e8f9f7 999 [..] This section provides function allowing to:
<> 144:ef7eb2e8f9f7 1000 (+) Get channel handle state.
<> 144:ef7eb2e8f9f7 1001 @endverbatim
<> 144:ef7eb2e8f9f7 1002 * @{
<> 144:ef7eb2e8f9f7 1003 */
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /**
<> 144:ef7eb2e8f9f7 1006 * @brief This function allows to get the current DFSDM channel handle state.
<> 144:ef7eb2e8f9f7 1007 * @param hdfsdm_channel : DFSDM channel handle.
<> 144:ef7eb2e8f9f7 1008 * @retval DFSDM channel state.
<> 144:ef7eb2e8f9f7 1009 */
<> 144:ef7eb2e8f9f7 1010 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
<> 144:ef7eb2e8f9f7 1011 {
<> 144:ef7eb2e8f9f7 1012 /* Return DFSDM channel handle state */
<> 144:ef7eb2e8f9f7 1013 return hdfsdm_channel->State;
<> 144:ef7eb2e8f9f7 1014 }
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /**
<> 144:ef7eb2e8f9f7 1017 * @}
<> 144:ef7eb2e8f9f7 1018 */
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 1021 * @brief Filter initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 1022 *
<> 144:ef7eb2e8f9f7 1023 @verbatim
<> 144:ef7eb2e8f9f7 1024 ==============================================================================
<> 144:ef7eb2e8f9f7 1025 ##### Filter initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 1026 ==============================================================================
<> 144:ef7eb2e8f9f7 1027 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1028 (+) Initialize the DFSDM filter.
<> 144:ef7eb2e8f9f7 1029 (+) De-initialize the DFSDM filter.
<> 144:ef7eb2e8f9f7 1030 @endverbatim
<> 144:ef7eb2e8f9f7 1031 * @{
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /**
<> 144:ef7eb2e8f9f7 1035 * @brief Initialize the DFSDM filter according to the specified parameters
<> 144:ef7eb2e8f9f7 1036 * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
<> 144:ef7eb2e8f9f7 1037 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1038 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1039 */
<> 144:ef7eb2e8f9f7 1040 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 /* Check DFSDM Channel handle */
<> 144:ef7eb2e8f9f7 1043 if(hdfsdm_filter == NULL)
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1046 }
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 /* Check parameters */
<> 144:ef7eb2e8f9f7 1049 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1050 assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
<> 144:ef7eb2e8f9f7 1051 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
<> 144:ef7eb2e8f9f7 1052 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
<> 144:ef7eb2e8f9f7 1053 assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
<> 144:ef7eb2e8f9f7 1054 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
<> 144:ef7eb2e8f9f7 1055 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
<> 144:ef7eb2e8f9f7 1056 assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
<> 144:ef7eb2e8f9f7 1057 assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
<> 144:ef7eb2e8f9f7 1058 assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1061 if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
<> 144:ef7eb2e8f9f7 1062 ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
<> 144:ef7eb2e8f9f7 1063 (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
<> 144:ef7eb2e8f9f7 1064 {
<> 144:ef7eb2e8f9f7 1065 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1066 }
<> 144:ef7eb2e8f9f7 1067
<> 144:ef7eb2e8f9f7 1068 /* Initialize DFSDM filter variables with default values */
<> 144:ef7eb2e8f9f7 1069 hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
<> 144:ef7eb2e8f9f7 1070 hdfsdm_filter->InjectedChannelsNbr = 1;
<> 144:ef7eb2e8f9f7 1071 hdfsdm_filter->InjConvRemaining = 1;
<> 144:ef7eb2e8f9f7 1072 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /* Call MSP init function */
<> 144:ef7eb2e8f9f7 1075 HAL_DFSDM_FilterMspInit(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Set regular parameters */
<> 144:ef7eb2e8f9f7 1078 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
<> 144:ef7eb2e8f9f7 1079 if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083 else
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
<> 144:ef7eb2e8f9f7 1089 {
<> 144:ef7eb2e8f9f7 1090 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
<> 144:ef7eb2e8f9f7 1091 }
<> 144:ef7eb2e8f9f7 1092 else
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
<> 144:ef7eb2e8f9f7 1095 }
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Set injected parameters */
<> 144:ef7eb2e8f9f7 1098 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
<> 144:ef7eb2e8f9f7 1099 if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
<> 144:ef7eb2e8f9f7 1100 {
<> 144:ef7eb2e8f9f7 1101 assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
<> 144:ef7eb2e8f9f7 1102 assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
<> 144:ef7eb2e8f9f7 1103 hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
<> 144:ef7eb2e8f9f7 1104 }
<> 144:ef7eb2e8f9f7 1105
<> 144:ef7eb2e8f9f7 1106 if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
<> 144:ef7eb2e8f9f7 1107 {
<> 144:ef7eb2e8f9f7 1108 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110 else
<> 144:ef7eb2e8f9f7 1111 {
<> 144:ef7eb2e8f9f7 1112 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
<> 144:ef7eb2e8f9f7 1113 }
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
<> 144:ef7eb2e8f9f7 1116 {
<> 144:ef7eb2e8f9f7 1117 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119 else
<> 144:ef7eb2e8f9f7 1120 {
<> 144:ef7eb2e8f9f7 1121 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /* Set filter parameters */
<> 144:ef7eb2e8f9f7 1125 hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
<> 144:ef7eb2e8f9f7 1126 hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
<> 144:ef7eb2e8f9f7 1127 ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |
<> 144:ef7eb2e8f9f7 1128 (hdfsdm_filter->Init.FilterParam.IntOversampling - 1));
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /* Store regular and injected triggers and injected scan mode*/
<> 144:ef7eb2e8f9f7 1131 hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
<> 144:ef7eb2e8f9f7 1132 hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
<> 144:ef7eb2e8f9f7 1133 hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
<> 144:ef7eb2e8f9f7 1134 hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 1137 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Set DFSDM filter to ready state */
<> 144:ef7eb2e8f9f7 1140 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 return HAL_OK;
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 /**
<> 144:ef7eb2e8f9f7 1146 * @brief De-initializes the DFSDM filter.
<> 144:ef7eb2e8f9f7 1147 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1148 * @retval HAL status.
<> 144:ef7eb2e8f9f7 1149 */
<> 144:ef7eb2e8f9f7 1150 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 /* Check DFSDM filter handle */
<> 144:ef7eb2e8f9f7 1153 if(hdfsdm_filter == NULL)
<> 144:ef7eb2e8f9f7 1154 {
<> 144:ef7eb2e8f9f7 1155 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1156 }
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Check parameters */
<> 144:ef7eb2e8f9f7 1159 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /* Disable the DFSDM filter */
<> 144:ef7eb2e8f9f7 1162 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Call MSP deinit function */
<> 144:ef7eb2e8f9f7 1165 HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /* Set DFSDM filter in reset state */
<> 144:ef7eb2e8f9f7 1168 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 return HAL_OK;
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /**
<> 144:ef7eb2e8f9f7 1174 * @brief Initializes the DFSDM filter MSP.
<> 144:ef7eb2e8f9f7 1175 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1176 * @retval None
<> 144:ef7eb2e8f9f7 1177 */
<> 144:ef7eb2e8f9f7 1178 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1181 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 1184 the HAL_DFSDM_FilterMspInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 1185 */
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 /**
<> 144:ef7eb2e8f9f7 1189 * @brief De-initializes the DFSDM filter MSP.
<> 144:ef7eb2e8f9f7 1190 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1191 * @retval None
<> 144:ef7eb2e8f9f7 1192 */
<> 144:ef7eb2e8f9f7 1193 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1194 {
<> 144:ef7eb2e8f9f7 1195 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1196 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1197
<> 144:ef7eb2e8f9f7 1198 /* NOTE : This function should not be modified, when the function is needed,
<> 144:ef7eb2e8f9f7 1199 the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
<> 144:ef7eb2e8f9f7 1200 */
<> 144:ef7eb2e8f9f7 1201 }
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /**
<> 144:ef7eb2e8f9f7 1204 * @}
<> 144:ef7eb2e8f9f7 1205 */
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
<> 144:ef7eb2e8f9f7 1208 * @brief Filter control functions
<> 144:ef7eb2e8f9f7 1209 *
<> 144:ef7eb2e8f9f7 1210 @verbatim
<> 144:ef7eb2e8f9f7 1211 ==============================================================================
<> 144:ef7eb2e8f9f7 1212 ##### Filter control functions #####
<> 144:ef7eb2e8f9f7 1213 ==============================================================================
<> 144:ef7eb2e8f9f7 1214 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1215 (+) Select channel and enable/disable continuous mode for regular conversion.
<> 144:ef7eb2e8f9f7 1216 (+) Select channels for injected conversion.
<> 144:ef7eb2e8f9f7 1217 @endverbatim
<> 144:ef7eb2e8f9f7 1218 * @{
<> 144:ef7eb2e8f9f7 1219 */
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /**
<> 144:ef7eb2e8f9f7 1222 * @brief This function allows to select channel and to enable/disable
<> 144:ef7eb2e8f9f7 1223 * continuous mode for regular conversion.
<> 144:ef7eb2e8f9f7 1224 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1225 * @param Channel : Channel for regular conversion.
<> 144:ef7eb2e8f9f7 1226 * This parameter can be a value of @ref DFSDM_Channel_Selection.
<> 144:ef7eb2e8f9f7 1227 * @param ContinuousMode : Enable/disable continuous mode for regular conversion.
<> 144:ef7eb2e8f9f7 1228 * This parameter can be a value of @ref DFSDM_ContinuousMode.
<> 144:ef7eb2e8f9f7 1229 * @retval HAL status
<> 144:ef7eb2e8f9f7 1230 */
<> 144:ef7eb2e8f9f7 1231 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1232 uint32_t Channel,
<> 144:ef7eb2e8f9f7 1233 uint32_t ContinuousMode)
<> 144:ef7eb2e8f9f7 1234 {
<> 144:ef7eb2e8f9f7 1235 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1236
<> 144:ef7eb2e8f9f7 1237 /* Check parameters */
<> 144:ef7eb2e8f9f7 1238 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1239 assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 1240 assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
<> 144:ef7eb2e8f9f7 1241
<> 144:ef7eb2e8f9f7 1242 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1243 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
<> 144:ef7eb2e8f9f7 1244 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 1245 {
<> 144:ef7eb2e8f9f7 1246 /* Configure channel and continuous mode for regular conversion */
<> 144:ef7eb2e8f9f7 1247 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
<> 144:ef7eb2e8f9f7 1248 if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
<> 144:ef7eb2e8f9f7 1249 {
<> 144:ef7eb2e8f9f7 1250 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
<> 144:ef7eb2e8f9f7 1251 DFSDM_FLTCR1_RCONT);
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253 else
<> 144:ef7eb2e8f9f7 1254 {
<> 144:ef7eb2e8f9f7 1255 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
<> 144:ef7eb2e8f9f7 1256 }
<> 144:ef7eb2e8f9f7 1257 /* Store continuous mode information */
<> 144:ef7eb2e8f9f7 1258 hdfsdm_filter->RegularContMode = ContinuousMode;
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 else
<> 144:ef7eb2e8f9f7 1261 {
<> 144:ef7eb2e8f9f7 1262 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1263 }
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265 /* Return function status */
<> 144:ef7eb2e8f9f7 1266 return status;
<> 144:ef7eb2e8f9f7 1267 }
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 /**
<> 144:ef7eb2e8f9f7 1270 * @brief This function allows to select channels for injected conversion.
<> 144:ef7eb2e8f9f7 1271 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1272 * @param Channel : Channels for injected conversion.
<> 144:ef7eb2e8f9f7 1273 * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
<> 144:ef7eb2e8f9f7 1274 * @retval HAL status
<> 144:ef7eb2e8f9f7 1275 */
<> 144:ef7eb2e8f9f7 1276 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1277 uint32_t Channel)
<> 144:ef7eb2e8f9f7 1278 {
<> 144:ef7eb2e8f9f7 1279 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /* Check parameters */
<> 144:ef7eb2e8f9f7 1282 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1283 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 1284
<> 144:ef7eb2e8f9f7 1285 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1286 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
<> 144:ef7eb2e8f9f7 1287 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 1288 {
<> 144:ef7eb2e8f9f7 1289 /* Configure channel for injected conversion */
<> 144:ef7eb2e8f9f7 1290 hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
<> 144:ef7eb2e8f9f7 1291 /* Store number of injected channels */
<> 144:ef7eb2e8f9f7 1292 hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
<> 144:ef7eb2e8f9f7 1293 /* Update number of injected channels remaining */
<> 144:ef7eb2e8f9f7 1294 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 1295 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 1296 }
<> 144:ef7eb2e8f9f7 1297 else
<> 144:ef7eb2e8f9f7 1298 {
<> 144:ef7eb2e8f9f7 1299 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301 /* Return function status */
<> 144:ef7eb2e8f9f7 1302 return status;
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /**
<> 144:ef7eb2e8f9f7 1306 * @}
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308
<> 144:ef7eb2e8f9f7 1309 /** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
<> 144:ef7eb2e8f9f7 1310 * @brief Filter operation functions
<> 144:ef7eb2e8f9f7 1311 *
<> 144:ef7eb2e8f9f7 1312 @verbatim
<> 144:ef7eb2e8f9f7 1313 ==============================================================================
<> 144:ef7eb2e8f9f7 1314 ##### Filter operation functions #####
<> 144:ef7eb2e8f9f7 1315 ==============================================================================
<> 144:ef7eb2e8f9f7 1316 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1317 (+) Start conversion of regular/injected channel.
<> 144:ef7eb2e8f9f7 1318 (+) Poll for the end of regular/injected conversion.
<> 144:ef7eb2e8f9f7 1319 (+) Stop conversion of regular/injected channel.
<> 144:ef7eb2e8f9f7 1320 (+) Start conversion of regular/injected channel and enable interrupt.
<> 144:ef7eb2e8f9f7 1321 (+) Call the callback functions at the end of regular/injected conversions.
<> 144:ef7eb2e8f9f7 1322 (+) Stop conversion of regular/injected channel and disable interrupt.
<> 144:ef7eb2e8f9f7 1323 (+) Start conversion of regular/injected channel and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1324 (+) Stop conversion of regular/injected channel and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1325 (+) Start analog watchdog and enable interrupt.
<> 144:ef7eb2e8f9f7 1326 (+) Call the callback function when analog watchdog occurs.
<> 144:ef7eb2e8f9f7 1327 (+) Stop analog watchdog and disable interrupt.
<> 144:ef7eb2e8f9f7 1328 (+) Start extreme detector.
<> 144:ef7eb2e8f9f7 1329 (+) Stop extreme detector.
<> 144:ef7eb2e8f9f7 1330 (+) Get result of regular channel conversion.
<> 144:ef7eb2e8f9f7 1331 (+) Get result of injected channel conversion.
<> 144:ef7eb2e8f9f7 1332 (+) Get extreme detector maximum and minimum values.
<> 144:ef7eb2e8f9f7 1333 (+) Get conversion time.
<> 144:ef7eb2e8f9f7 1334 (+) Handle DFSDM interrupt request.
<> 144:ef7eb2e8f9f7 1335 @endverbatim
<> 144:ef7eb2e8f9f7 1336 * @{
<> 144:ef7eb2e8f9f7 1337 */
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /**
<> 144:ef7eb2e8f9f7 1340 * @brief This function allows to start regular conversion in polling mode.
<> 144:ef7eb2e8f9f7 1341 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1342 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1343 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1344 * @retval HAL status
<> 144:ef7eb2e8f9f7 1345 */
<> 144:ef7eb2e8f9f7 1346 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1347 {
<> 144:ef7eb2e8f9f7 1348 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /* Check parameters */
<> 144:ef7eb2e8f9f7 1351 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1354 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1355 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1356 {
<> 144:ef7eb2e8f9f7 1357 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1358 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1359 }
<> 144:ef7eb2e8f9f7 1360 else
<> 144:ef7eb2e8f9f7 1361 {
<> 144:ef7eb2e8f9f7 1362 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1363 }
<> 144:ef7eb2e8f9f7 1364 /* Return function status */
<> 144:ef7eb2e8f9f7 1365 return status;
<> 144:ef7eb2e8f9f7 1366 }
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /**
<> 144:ef7eb2e8f9f7 1369 * @brief This function allows to poll for the end of regular conversion.
<> 144:ef7eb2e8f9f7 1370 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1371 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1372 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 1373 * @retval HAL status
<> 144:ef7eb2e8f9f7 1374 */
<> 144:ef7eb2e8f9f7 1375 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1376 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1377 {
<> 144:ef7eb2e8f9f7 1378 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1379
<> 144:ef7eb2e8f9f7 1380 /* Check parameters */
<> 144:ef7eb2e8f9f7 1381 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1384 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1385 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1386 {
<> 144:ef7eb2e8f9f7 1387 /* Return error status */
<> 144:ef7eb2e8f9f7 1388 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1389 }
<> 144:ef7eb2e8f9f7 1390 else
<> 144:ef7eb2e8f9f7 1391 {
<> 144:ef7eb2e8f9f7 1392 /* Get timeout */
<> 144:ef7eb2e8f9f7 1393 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 /* Wait end of regular conversion */
<> 144:ef7eb2e8f9f7 1396 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
<> 144:ef7eb2e8f9f7 1397 {
<> 144:ef7eb2e8f9f7 1398 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 1399 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1400 {
<> 144:ef7eb2e8f9f7 1401 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1402 {
<> 144:ef7eb2e8f9f7 1403 /* Return timeout status */
<> 144:ef7eb2e8f9f7 1404 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1405 }
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407 }
<> 144:ef7eb2e8f9f7 1408 /* Check if overrun occurs */
<> 144:ef7eb2e8f9f7 1409 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
<> 144:ef7eb2e8f9f7 1410 {
<> 144:ef7eb2e8f9f7 1411 /* Update error code and call error callback */
<> 144:ef7eb2e8f9f7 1412 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
<> 144:ef7eb2e8f9f7 1413 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /* Clear regular overrun flag */
<> 144:ef7eb2e8f9f7 1416 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
<> 144:ef7eb2e8f9f7 1417 }
<> 144:ef7eb2e8f9f7 1418 /* Update DFSDM filter state only if not continuous conversion and SW trigger */
<> 144:ef7eb2e8f9f7 1419 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1420 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 1421 {
<> 144:ef7eb2e8f9f7 1422 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
<> 144:ef7eb2e8f9f7 1423 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
<> 144:ef7eb2e8f9f7 1424 }
<> 144:ef7eb2e8f9f7 1425 /* Return function status */
<> 144:ef7eb2e8f9f7 1426 return HAL_OK;
<> 144:ef7eb2e8f9f7 1427 }
<> 144:ef7eb2e8f9f7 1428 }
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 /**
<> 144:ef7eb2e8f9f7 1431 * @brief This function allows to stop regular conversion in polling mode.
<> 144:ef7eb2e8f9f7 1432 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1433 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1434 * @retval HAL status
<> 144:ef7eb2e8f9f7 1435 */
<> 144:ef7eb2e8f9f7 1436 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1437 {
<> 144:ef7eb2e8f9f7 1438 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 /* Check parameters */
<> 144:ef7eb2e8f9f7 1441 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1442
<> 144:ef7eb2e8f9f7 1443 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1444 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1445 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1446 {
<> 144:ef7eb2e8f9f7 1447 /* Return error status */
<> 144:ef7eb2e8f9f7 1448 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1449 }
<> 144:ef7eb2e8f9f7 1450 else
<> 144:ef7eb2e8f9f7 1451 {
<> 144:ef7eb2e8f9f7 1452 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 1453 DFSDM_RegConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1454 }
<> 144:ef7eb2e8f9f7 1455 /* Return function status */
<> 144:ef7eb2e8f9f7 1456 return status;
<> 144:ef7eb2e8f9f7 1457 }
<> 144:ef7eb2e8f9f7 1458
<> 144:ef7eb2e8f9f7 1459 /**
<> 144:ef7eb2e8f9f7 1460 * @brief This function allows to start regular conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1461 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1462 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1463 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1464 * @retval HAL status
<> 144:ef7eb2e8f9f7 1465 */
<> 144:ef7eb2e8f9f7 1466 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1467 {
<> 144:ef7eb2e8f9f7 1468 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 /* Check parameters */
<> 144:ef7eb2e8f9f7 1471 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1474 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1475 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1476 {
<> 144:ef7eb2e8f9f7 1477 /* Enable interrupts for regular conversions */
<> 144:ef7eb2e8f9f7 1478 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1481 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1482 }
<> 144:ef7eb2e8f9f7 1483 else
<> 144:ef7eb2e8f9f7 1484 {
<> 144:ef7eb2e8f9f7 1485 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1486 }
<> 144:ef7eb2e8f9f7 1487 /* Return function status */
<> 144:ef7eb2e8f9f7 1488 return status;
<> 144:ef7eb2e8f9f7 1489 }
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /**
<> 144:ef7eb2e8f9f7 1492 * @brief This function allows to stop regular conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1493 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1494 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1495 * @retval HAL status
<> 144:ef7eb2e8f9f7 1496 */
<> 144:ef7eb2e8f9f7 1497 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1498 {
<> 144:ef7eb2e8f9f7 1499 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1500
<> 144:ef7eb2e8f9f7 1501 /* Check parameters */
<> 144:ef7eb2e8f9f7 1502 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1505 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1506 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1507 {
<> 144:ef7eb2e8f9f7 1508 /* Return error status */
<> 144:ef7eb2e8f9f7 1509 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1510 }
<> 144:ef7eb2e8f9f7 1511 else
<> 144:ef7eb2e8f9f7 1512 {
<> 144:ef7eb2e8f9f7 1513 /* Disable interrupts for regular conversions */
<> 144:ef7eb2e8f9f7 1514 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 1517 DFSDM_RegConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1518 }
<> 144:ef7eb2e8f9f7 1519 /* Return function status */
<> 144:ef7eb2e8f9f7 1520 return status;
<> 144:ef7eb2e8f9f7 1521 }
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /**
<> 144:ef7eb2e8f9f7 1524 * @brief This function allows to start regular conversion in DMA mode.
<> 144:ef7eb2e8f9f7 1525 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1526 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1527 * Please note that data on buffer will contain signed regular conversion
<> 144:ef7eb2e8f9f7 1528 * value on 24 most significant bits and corresponding channel on 3 least
<> 144:ef7eb2e8f9f7 1529 * significant bits.
<> 144:ef7eb2e8f9f7 1530 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1531 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 1532 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 1533 * @retval HAL status
<> 144:ef7eb2e8f9f7 1534 */
<> 144:ef7eb2e8f9f7 1535 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1536 int32_t *pData,
<> 144:ef7eb2e8f9f7 1537 uint32_t Length)
<> 144:ef7eb2e8f9f7 1538 {
<> 144:ef7eb2e8f9f7 1539 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /* Check parameters */
<> 144:ef7eb2e8f9f7 1542 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 1545 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 1546 {
<> 144:ef7eb2e8f9f7 1547 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1548 }
<> 144:ef7eb2e8f9f7 1549 /* Check that DMA is enabled for regular conversion */
<> 144:ef7eb2e8f9f7 1550 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
<> 144:ef7eb2e8f9f7 1551 {
<> 144:ef7eb2e8f9f7 1552 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1553 }
<> 144:ef7eb2e8f9f7 1554 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1555 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1556 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1557 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 1558 (Length != 1))
<> 144:ef7eb2e8f9f7 1559 {
<> 144:ef7eb2e8f9f7 1560 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1561 }
<> 144:ef7eb2e8f9f7 1562 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1563 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1564 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 1565 {
<> 144:ef7eb2e8f9f7 1566 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1567 }
<> 144:ef7eb2e8f9f7 1568 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1569 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1570 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1571 {
<> 144:ef7eb2e8f9f7 1572 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 1573 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
<> 144:ef7eb2e8f9f7 1574 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 1575 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 1576 DFSDM_DMARegularHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 1579 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
<> 144:ef7eb2e8f9f7 1580 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 1581 {
<> 144:ef7eb2e8f9f7 1582 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 1583 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1584 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1585 }
<> 144:ef7eb2e8f9f7 1586 else
<> 144:ef7eb2e8f9f7 1587 {
<> 144:ef7eb2e8f9f7 1588 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1589 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1590 }
<> 144:ef7eb2e8f9f7 1591 }
<> 144:ef7eb2e8f9f7 1592 else
<> 144:ef7eb2e8f9f7 1593 {
<> 144:ef7eb2e8f9f7 1594 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1595 }
<> 144:ef7eb2e8f9f7 1596 /* Return function status */
<> 144:ef7eb2e8f9f7 1597 return status;
<> 144:ef7eb2e8f9f7 1598 }
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 /**
<> 144:ef7eb2e8f9f7 1601 * @brief This function allows to start regular conversion in DMA mode and to get
<> 144:ef7eb2e8f9f7 1602 * only the 16 most significant bits of conversion.
<> 144:ef7eb2e8f9f7 1603 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1604 * in idle state or if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1605 * Please note that data on buffer will contain signed 16 most significant
<> 144:ef7eb2e8f9f7 1606 * bits of regular conversion.
<> 144:ef7eb2e8f9f7 1607 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1608 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 1609 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 1610 * @retval HAL status
<> 144:ef7eb2e8f9f7 1611 */
<> 144:ef7eb2e8f9f7 1612 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1613 int16_t *pData,
<> 144:ef7eb2e8f9f7 1614 uint32_t Length)
<> 144:ef7eb2e8f9f7 1615 {
<> 144:ef7eb2e8f9f7 1616 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 /* Check parameters */
<> 144:ef7eb2e8f9f7 1619 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 1622 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 1623 {
<> 144:ef7eb2e8f9f7 1624 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1625 }
<> 144:ef7eb2e8f9f7 1626 /* Check that DMA is enabled for regular conversion */
<> 144:ef7eb2e8f9f7 1627 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
<> 144:ef7eb2e8f9f7 1628 {
<> 144:ef7eb2e8f9f7 1629 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1630 }
<> 144:ef7eb2e8f9f7 1631 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1632 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1633 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1634 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 1635 (Length != 1))
<> 144:ef7eb2e8f9f7 1636 {
<> 144:ef7eb2e8f9f7 1637 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1638 }
<> 144:ef7eb2e8f9f7 1639 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1640 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 1641 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 1642 {
<> 144:ef7eb2e8f9f7 1643 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1644 }
<> 144:ef7eb2e8f9f7 1645 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1646 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1647 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
<> 144:ef7eb2e8f9f7 1648 {
<> 144:ef7eb2e8f9f7 1649 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 1650 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
<> 144:ef7eb2e8f9f7 1651 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 1652 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 1653 DFSDM_DMARegularHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 1654
<> 144:ef7eb2e8f9f7 1655 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 1656 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \
<> 144:ef7eb2e8f9f7 1657 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 1658 {
<> 144:ef7eb2e8f9f7 1659 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 1660 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1661 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1662 }
<> 144:ef7eb2e8f9f7 1663 else
<> 144:ef7eb2e8f9f7 1664 {
<> 144:ef7eb2e8f9f7 1665 /* Start regular conversion */
<> 144:ef7eb2e8f9f7 1666 DFSDM_RegConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1667 }
<> 144:ef7eb2e8f9f7 1668 }
<> 144:ef7eb2e8f9f7 1669 else
<> 144:ef7eb2e8f9f7 1670 {
<> 144:ef7eb2e8f9f7 1671 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1672 }
<> 144:ef7eb2e8f9f7 1673 /* Return function status */
<> 144:ef7eb2e8f9f7 1674 return status;
<> 144:ef7eb2e8f9f7 1675 }
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 /**
<> 144:ef7eb2e8f9f7 1678 * @brief This function allows to stop regular conversion in DMA mode.
<> 144:ef7eb2e8f9f7 1679 * @note This function should be called only if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1680 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1681 * @retval HAL status
<> 144:ef7eb2e8f9f7 1682 */
<> 144:ef7eb2e8f9f7 1683 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1684 {
<> 144:ef7eb2e8f9f7 1685 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /* Check parameters */
<> 144:ef7eb2e8f9f7 1688 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1689
<> 144:ef7eb2e8f9f7 1690 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1691 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 1692 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1693 {
<> 144:ef7eb2e8f9f7 1694 /* Return error status */
<> 144:ef7eb2e8f9f7 1695 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1696 }
<> 144:ef7eb2e8f9f7 1697 else
<> 144:ef7eb2e8f9f7 1698 {
<> 144:ef7eb2e8f9f7 1699 /* Stop current DMA transfer */
<> 144:ef7eb2e8f9f7 1700 if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
<> 144:ef7eb2e8f9f7 1701 {
<> 144:ef7eb2e8f9f7 1702 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 1703 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1704 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1705 }
<> 144:ef7eb2e8f9f7 1706 else
<> 144:ef7eb2e8f9f7 1707 {
<> 144:ef7eb2e8f9f7 1708 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 1709 DFSDM_RegConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1710 }
<> 144:ef7eb2e8f9f7 1711 }
<> 144:ef7eb2e8f9f7 1712 /* Return function status */
<> 144:ef7eb2e8f9f7 1713 return status;
<> 144:ef7eb2e8f9f7 1714 }
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /**
<> 144:ef7eb2e8f9f7 1717 * @brief This function allows to get regular conversion value.
<> 144:ef7eb2e8f9f7 1718 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1719 * @param Channel : Corresponding channel of regular conversion.
<> 144:ef7eb2e8f9f7 1720 * @retval Regular conversion value
<> 144:ef7eb2e8f9f7 1721 */
<> 144:ef7eb2e8f9f7 1722 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1723 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 1724 {
<> 144:ef7eb2e8f9f7 1725 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 1726 int32_t value = 0;
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 /* Check parameters */
<> 144:ef7eb2e8f9f7 1729 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1730 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732 /* Get value of data register for regular channel */
<> 144:ef7eb2e8f9f7 1733 reg = hdfsdm_filter->Instance->FLTRDATAR;
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 /* Extract channel and regular conversion value */
<> 144:ef7eb2e8f9f7 1736 *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
<> 144:ef7eb2e8f9f7 1737 value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 /* return regular conversion value */
<> 144:ef7eb2e8f9f7 1740 return value;
<> 144:ef7eb2e8f9f7 1741 }
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /**
<> 144:ef7eb2e8f9f7 1744 * @brief This function allows to start injected conversion in polling mode.
<> 144:ef7eb2e8f9f7 1745 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1746 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1747 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1748 * @retval HAL status
<> 144:ef7eb2e8f9f7 1749 */
<> 144:ef7eb2e8f9f7 1750 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1751 {
<> 144:ef7eb2e8f9f7 1752 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1753
<> 144:ef7eb2e8f9f7 1754 /* Check parameters */
<> 144:ef7eb2e8f9f7 1755 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1758 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1759 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 1760 {
<> 144:ef7eb2e8f9f7 1761 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 1762 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1763 }
<> 144:ef7eb2e8f9f7 1764 else
<> 144:ef7eb2e8f9f7 1765 {
<> 144:ef7eb2e8f9f7 1766 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1767 }
<> 144:ef7eb2e8f9f7 1768 /* Return function status */
<> 144:ef7eb2e8f9f7 1769 return status;
<> 144:ef7eb2e8f9f7 1770 }
<> 144:ef7eb2e8f9f7 1771
<> 144:ef7eb2e8f9f7 1772 /**
<> 144:ef7eb2e8f9f7 1773 * @brief This function allows to poll for the end of injected conversion.
<> 144:ef7eb2e8f9f7 1774 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1775 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1776 * @param Timeout : Timeout value in milliseconds.
<> 144:ef7eb2e8f9f7 1777 * @retval HAL status
<> 144:ef7eb2e8f9f7 1778 */
<> 144:ef7eb2e8f9f7 1779 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1780 uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1781 {
<> 144:ef7eb2e8f9f7 1782 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 1783
<> 144:ef7eb2e8f9f7 1784 /* Check parameters */
<> 144:ef7eb2e8f9f7 1785 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1788 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 1789 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1790 {
<> 144:ef7eb2e8f9f7 1791 /* Return error status */
<> 144:ef7eb2e8f9f7 1792 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1793 }
<> 144:ef7eb2e8f9f7 1794 else
<> 144:ef7eb2e8f9f7 1795 {
<> 144:ef7eb2e8f9f7 1796 /* Get timeout */
<> 144:ef7eb2e8f9f7 1797 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 /* Wait end of injected conversions */
<> 144:ef7eb2e8f9f7 1800 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
<> 144:ef7eb2e8f9f7 1801 {
<> 144:ef7eb2e8f9f7 1802 /* Check the Timeout */
<> 144:ef7eb2e8f9f7 1803 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1804 {
<> 144:ef7eb2e8f9f7 1805 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
<> 144:ef7eb2e8f9f7 1806 {
<> 144:ef7eb2e8f9f7 1807 /* Return timeout status */
<> 144:ef7eb2e8f9f7 1808 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1809 }
<> 144:ef7eb2e8f9f7 1810 }
<> 144:ef7eb2e8f9f7 1811 }
<> 144:ef7eb2e8f9f7 1812 /* Check if overrun occurs */
<> 144:ef7eb2e8f9f7 1813 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
<> 144:ef7eb2e8f9f7 1814 {
<> 144:ef7eb2e8f9f7 1815 /* Update error code and call error callback */
<> 144:ef7eb2e8f9f7 1816 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
<> 144:ef7eb2e8f9f7 1817 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1818
<> 144:ef7eb2e8f9f7 1819 /* Clear injected overrun flag */
<> 144:ef7eb2e8f9f7 1820 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
<> 144:ef7eb2e8f9f7 1821 }
<> 144:ef7eb2e8f9f7 1822
<> 144:ef7eb2e8f9f7 1823 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 1824 hdfsdm_filter->InjConvRemaining--;
<> 144:ef7eb2e8f9f7 1825 if(hdfsdm_filter->InjConvRemaining == 0)
<> 144:ef7eb2e8f9f7 1826 {
<> 144:ef7eb2e8f9f7 1827 /* Update DFSDM filter state only if trigger is software */
<> 144:ef7eb2e8f9f7 1828 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 1829 {
<> 144:ef7eb2e8f9f7 1830 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
<> 144:ef7eb2e8f9f7 1831 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
<> 144:ef7eb2e8f9f7 1832 }
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 /* end of injected sequence, reset the value */
<> 144:ef7eb2e8f9f7 1835 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 1836 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 1837 }
<> 144:ef7eb2e8f9f7 1838
<> 144:ef7eb2e8f9f7 1839 /* Return function status */
<> 144:ef7eb2e8f9f7 1840 return HAL_OK;
<> 144:ef7eb2e8f9f7 1841 }
<> 144:ef7eb2e8f9f7 1842 }
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 /**
<> 144:ef7eb2e8f9f7 1845 * @brief This function allows to stop injected conversion in polling mode.
<> 144:ef7eb2e8f9f7 1846 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1847 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1848 * @retval HAL status
<> 144:ef7eb2e8f9f7 1849 */
<> 144:ef7eb2e8f9f7 1850 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1851 {
<> 144:ef7eb2e8f9f7 1852 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1853
<> 144:ef7eb2e8f9f7 1854 /* Check parameters */
<> 144:ef7eb2e8f9f7 1855 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1858 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 1859 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1860 {
<> 144:ef7eb2e8f9f7 1861 /* Return error status */
<> 144:ef7eb2e8f9f7 1862 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1863 }
<> 144:ef7eb2e8f9f7 1864 else
<> 144:ef7eb2e8f9f7 1865 {
<> 144:ef7eb2e8f9f7 1866 /* Stop injected conversion */
<> 144:ef7eb2e8f9f7 1867 DFSDM_InjConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1868 }
<> 144:ef7eb2e8f9f7 1869 /* Return function status */
<> 144:ef7eb2e8f9f7 1870 return status;
<> 144:ef7eb2e8f9f7 1871 }
<> 144:ef7eb2e8f9f7 1872
<> 144:ef7eb2e8f9f7 1873 /**
<> 144:ef7eb2e8f9f7 1874 * @brief This function allows to start injected conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1875 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1876 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1877 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1878 * @retval HAL status
<> 144:ef7eb2e8f9f7 1879 */
<> 144:ef7eb2e8f9f7 1880 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1881 {
<> 144:ef7eb2e8f9f7 1882 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1883
<> 144:ef7eb2e8f9f7 1884 /* Check parameters */
<> 144:ef7eb2e8f9f7 1885 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1886
<> 144:ef7eb2e8f9f7 1887 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1888 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1889 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 1890 {
<> 144:ef7eb2e8f9f7 1891 /* Enable interrupts for injected conversions */
<> 144:ef7eb2e8f9f7 1892 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
<> 144:ef7eb2e8f9f7 1893
<> 144:ef7eb2e8f9f7 1894 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 1895 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1896 }
<> 144:ef7eb2e8f9f7 1897 else
<> 144:ef7eb2e8f9f7 1898 {
<> 144:ef7eb2e8f9f7 1899 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1900 }
<> 144:ef7eb2e8f9f7 1901 /* Return function status */
<> 144:ef7eb2e8f9f7 1902 return status;
<> 144:ef7eb2e8f9f7 1903 }
<> 144:ef7eb2e8f9f7 1904
<> 144:ef7eb2e8f9f7 1905 /**
<> 144:ef7eb2e8f9f7 1906 * @brief This function allows to stop injected conversion in interrupt mode.
<> 144:ef7eb2e8f9f7 1907 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 1908 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1909 * @retval HAL status
<> 144:ef7eb2e8f9f7 1910 */
<> 144:ef7eb2e8f9f7 1911 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 1912 {
<> 144:ef7eb2e8f9f7 1913 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1914
<> 144:ef7eb2e8f9f7 1915 /* Check parameters */
<> 144:ef7eb2e8f9f7 1916 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1917
<> 144:ef7eb2e8f9f7 1918 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1919 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 1920 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 1921 {
<> 144:ef7eb2e8f9f7 1922 /* Return error status */
<> 144:ef7eb2e8f9f7 1923 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1924 }
<> 144:ef7eb2e8f9f7 1925 else
<> 144:ef7eb2e8f9f7 1926 {
<> 144:ef7eb2e8f9f7 1927 /* Disable interrupts for injected conversions */
<> 144:ef7eb2e8f9f7 1928 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 /* Stop injected conversion */
<> 144:ef7eb2e8f9f7 1931 DFSDM_InjConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 1932 }
<> 144:ef7eb2e8f9f7 1933 /* Return function status */
<> 144:ef7eb2e8f9f7 1934 return status;
<> 144:ef7eb2e8f9f7 1935 }
<> 144:ef7eb2e8f9f7 1936
<> 144:ef7eb2e8f9f7 1937 /**
<> 144:ef7eb2e8f9f7 1938 * @brief This function allows to start injected conversion in DMA mode.
<> 144:ef7eb2e8f9f7 1939 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 1940 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 1941 * Please note that data on buffer will contain signed injected conversion
<> 144:ef7eb2e8f9f7 1942 * value on 24 most significant bits and corresponding channel on 3 least
<> 144:ef7eb2e8f9f7 1943 * significant bits.
<> 144:ef7eb2e8f9f7 1944 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 1945 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 1946 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 1947 * @retval HAL status
<> 144:ef7eb2e8f9f7 1948 */
<> 144:ef7eb2e8f9f7 1949 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 1950 int32_t *pData,
<> 144:ef7eb2e8f9f7 1951 uint32_t Length)
<> 144:ef7eb2e8f9f7 1952 {
<> 144:ef7eb2e8f9f7 1953 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 1954
<> 144:ef7eb2e8f9f7 1955 /* Check parameters */
<> 144:ef7eb2e8f9f7 1956 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 1957
<> 144:ef7eb2e8f9f7 1958 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 1959 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 1960 {
<> 144:ef7eb2e8f9f7 1961 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1962 }
<> 144:ef7eb2e8f9f7 1963 /* Check that DMA is enabled for injected conversion */
<> 144:ef7eb2e8f9f7 1964 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
<> 144:ef7eb2e8f9f7 1965 {
<> 144:ef7eb2e8f9f7 1966 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1967 }
<> 144:ef7eb2e8f9f7 1968 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 1969 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1970 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 1971 (Length > hdfsdm_filter->InjConvRemaining))
<> 144:ef7eb2e8f9f7 1972 {
<> 144:ef7eb2e8f9f7 1973 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1974 }
<> 144:ef7eb2e8f9f7 1975 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 1976 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 1977 {
<> 144:ef7eb2e8f9f7 1978 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1979 }
<> 144:ef7eb2e8f9f7 1980 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 1981 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 1982 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 1983 {
<> 144:ef7eb2e8f9f7 1984 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 1985 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
<> 144:ef7eb2e8f9f7 1986 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 1987 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 1988 DFSDM_DMAInjectedHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 1989
<> 144:ef7eb2e8f9f7 1990 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 1991 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
<> 144:ef7eb2e8f9f7 1992 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 1993 {
<> 144:ef7eb2e8f9f7 1994 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 1995 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 1996 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 1997 }
<> 144:ef7eb2e8f9f7 1998 else
<> 144:ef7eb2e8f9f7 1999 {
<> 144:ef7eb2e8f9f7 2000 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 2001 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2002 }
<> 144:ef7eb2e8f9f7 2003 }
<> 144:ef7eb2e8f9f7 2004 else
<> 144:ef7eb2e8f9f7 2005 {
<> 144:ef7eb2e8f9f7 2006 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2007 }
<> 144:ef7eb2e8f9f7 2008 /* Return function status */
<> 144:ef7eb2e8f9f7 2009 return status;
<> 144:ef7eb2e8f9f7 2010 }
<> 144:ef7eb2e8f9f7 2011
<> 144:ef7eb2e8f9f7 2012 /**
<> 144:ef7eb2e8f9f7 2013 * @brief This function allows to start injected conversion in DMA mode and to get
<> 144:ef7eb2e8f9f7 2014 * only the 16 most significant bits of conversion.
<> 144:ef7eb2e8f9f7 2015 * @note This function should be called only when DFSDM filter instance is
<> 144:ef7eb2e8f9f7 2016 * in idle state or if regular conversion is ongoing.
<> 144:ef7eb2e8f9f7 2017 * Please note that data on buffer will contain signed 16 most significant
<> 144:ef7eb2e8f9f7 2018 * bits of injected conversion.
<> 144:ef7eb2e8f9f7 2019 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2020 * @param pData : The destination buffer address.
<> 144:ef7eb2e8f9f7 2021 * @param Length : The length of data to be transferred from DFSDM filter to memory.
<> 144:ef7eb2e8f9f7 2022 * @retval HAL status
<> 144:ef7eb2e8f9f7 2023 */
<> 144:ef7eb2e8f9f7 2024 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2025 int16_t *pData,
<> 144:ef7eb2e8f9f7 2026 uint32_t Length)
<> 144:ef7eb2e8f9f7 2027 {
<> 144:ef7eb2e8f9f7 2028 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2029
<> 144:ef7eb2e8f9f7 2030 /* Check parameters */
<> 144:ef7eb2e8f9f7 2031 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 /* Check destination address and length */
<> 144:ef7eb2e8f9f7 2034 if((pData == NULL) || (Length == 0))
<> 144:ef7eb2e8f9f7 2035 {
<> 144:ef7eb2e8f9f7 2036 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2037 }
<> 144:ef7eb2e8f9f7 2038 /* Check that DMA is enabled for injected conversion */
<> 144:ef7eb2e8f9f7 2039 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
<> 144:ef7eb2e8f9f7 2040 {
<> 144:ef7eb2e8f9f7 2041 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2042 }
<> 144:ef7eb2e8f9f7 2043 /* Check parameters compatibility */
<> 144:ef7eb2e8f9f7 2044 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 2045 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
<> 144:ef7eb2e8f9f7 2046 (Length > hdfsdm_filter->InjConvRemaining))
<> 144:ef7eb2e8f9f7 2047 {
<> 144:ef7eb2e8f9f7 2048 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2049 }
<> 144:ef7eb2e8f9f7 2050 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
<> 144:ef7eb2e8f9f7 2051 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
<> 144:ef7eb2e8f9f7 2052 {
<> 144:ef7eb2e8f9f7 2053 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2054 }
<> 144:ef7eb2e8f9f7 2055 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2056 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
<> 144:ef7eb2e8f9f7 2057 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
<> 144:ef7eb2e8f9f7 2058 {
<> 144:ef7eb2e8f9f7 2059 /* Set callbacks on DMA handler */
<> 144:ef7eb2e8f9f7 2060 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
<> 144:ef7eb2e8f9f7 2061 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
<> 144:ef7eb2e8f9f7 2062 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
<> 144:ef7eb2e8f9f7 2063 DFSDM_DMAInjectedHalfConvCplt : NULL;
<> 144:ef7eb2e8f9f7 2064
<> 144:ef7eb2e8f9f7 2065 /* Start DMA in interrupt mode */
<> 144:ef7eb2e8f9f7 2066 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \
<> 144:ef7eb2e8f9f7 2067 (uint32_t) pData, Length) != HAL_OK)
<> 144:ef7eb2e8f9f7 2068 {
<> 144:ef7eb2e8f9f7 2069 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 2070 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 2071 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2072 }
<> 144:ef7eb2e8f9f7 2073 else
<> 144:ef7eb2e8f9f7 2074 {
<> 144:ef7eb2e8f9f7 2075 /* Start injected conversion */
<> 144:ef7eb2e8f9f7 2076 DFSDM_InjConvStart(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2077 }
<> 144:ef7eb2e8f9f7 2078 }
<> 144:ef7eb2e8f9f7 2079 else
<> 144:ef7eb2e8f9f7 2080 {
<> 144:ef7eb2e8f9f7 2081 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2082 }
<> 144:ef7eb2e8f9f7 2083 /* Return function status */
<> 144:ef7eb2e8f9f7 2084 return status;
<> 144:ef7eb2e8f9f7 2085 }
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 /**
<> 144:ef7eb2e8f9f7 2088 * @brief This function allows to stop injected conversion in DMA mode.
<> 144:ef7eb2e8f9f7 2089 * @note This function should be called only if injected conversion is ongoing.
<> 144:ef7eb2e8f9f7 2090 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2091 * @retval HAL status
<> 144:ef7eb2e8f9f7 2092 */
<> 144:ef7eb2e8f9f7 2093 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2094 {
<> 144:ef7eb2e8f9f7 2095 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2096
<> 144:ef7eb2e8f9f7 2097 /* Check parameters */
<> 144:ef7eb2e8f9f7 2098 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2101 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
<> 144:ef7eb2e8f9f7 2102 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
<> 144:ef7eb2e8f9f7 2103 {
<> 144:ef7eb2e8f9f7 2104 /* Return error status */
<> 144:ef7eb2e8f9f7 2105 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2106 }
<> 144:ef7eb2e8f9f7 2107 else
<> 144:ef7eb2e8f9f7 2108 {
<> 144:ef7eb2e8f9f7 2109 /* Stop current DMA transfer */
<> 144:ef7eb2e8f9f7 2110 if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
<> 144:ef7eb2e8f9f7 2111 {
<> 144:ef7eb2e8f9f7 2112 /* Set DFSDM filter in error state */
<> 144:ef7eb2e8f9f7 2113 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
<> 144:ef7eb2e8f9f7 2114 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2115 }
<> 144:ef7eb2e8f9f7 2116 else
<> 144:ef7eb2e8f9f7 2117 {
<> 144:ef7eb2e8f9f7 2118 /* Stop regular conversion */
<> 144:ef7eb2e8f9f7 2119 DFSDM_InjConvStop(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2120 }
<> 144:ef7eb2e8f9f7 2121 }
<> 144:ef7eb2e8f9f7 2122 /* Return function status */
<> 144:ef7eb2e8f9f7 2123 return status;
<> 144:ef7eb2e8f9f7 2124 }
<> 144:ef7eb2e8f9f7 2125
<> 144:ef7eb2e8f9f7 2126 /**
<> 144:ef7eb2e8f9f7 2127 * @brief This function allows to get injected conversion value.
<> 144:ef7eb2e8f9f7 2128 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2129 * @param Channel : Corresponding channel of injected conversion.
<> 144:ef7eb2e8f9f7 2130 * @retval Injected conversion value
<> 144:ef7eb2e8f9f7 2131 */
<> 144:ef7eb2e8f9f7 2132 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2133 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 2134 {
<> 144:ef7eb2e8f9f7 2135 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2136 int32_t value = 0;
<> 144:ef7eb2e8f9f7 2137
<> 144:ef7eb2e8f9f7 2138 /* Check parameters */
<> 144:ef7eb2e8f9f7 2139 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2140 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 2141
<> 144:ef7eb2e8f9f7 2142 /* Get value of data register for injected channel */
<> 144:ef7eb2e8f9f7 2143 reg = hdfsdm_filter->Instance->FLTJDATAR;
<> 144:ef7eb2e8f9f7 2144
<> 144:ef7eb2e8f9f7 2145 /* Extract channel and injected conversion value */
<> 144:ef7eb2e8f9f7 2146 *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
<> 144:ef7eb2e8f9f7 2147 value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2148
<> 144:ef7eb2e8f9f7 2149 /* return regular conversion value */
<> 144:ef7eb2e8f9f7 2150 return value;
<> 144:ef7eb2e8f9f7 2151 }
<> 144:ef7eb2e8f9f7 2152
<> 144:ef7eb2e8f9f7 2153 /**
<> 144:ef7eb2e8f9f7 2154 * @brief This function allows to start filter analog watchdog in interrupt mode.
<> 144:ef7eb2e8f9f7 2155 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2156 * @param awdParam : DFSDM filter analog watchdog parameters.
<> 144:ef7eb2e8f9f7 2157 * @retval HAL status
<> 144:ef7eb2e8f9f7 2158 */
<> 144:ef7eb2e8f9f7 2159 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2160 DFSDM_Filter_AwdParamTypeDef *awdParam)
<> 144:ef7eb2e8f9f7 2161 {
<> 144:ef7eb2e8f9f7 2162 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2163
<> 144:ef7eb2e8f9f7 2164 /* Check parameters */
<> 144:ef7eb2e8f9f7 2165 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2166 assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
<> 144:ef7eb2e8f9f7 2167 assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
<> 144:ef7eb2e8f9f7 2168 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
<> 144:ef7eb2e8f9f7 2169 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
<> 144:ef7eb2e8f9f7 2170 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
<> 144:ef7eb2e8f9f7 2171 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
<> 144:ef7eb2e8f9f7 2172
<> 144:ef7eb2e8f9f7 2173 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2174 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2175 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2176 {
<> 144:ef7eb2e8f9f7 2177 /* Return error status */
<> 144:ef7eb2e8f9f7 2178 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2179 }
<> 144:ef7eb2e8f9f7 2180 else
<> 144:ef7eb2e8f9f7 2181 {
<> 144:ef7eb2e8f9f7 2182 /* Set analog watchdog data source */
<> 144:ef7eb2e8f9f7 2183 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
<> 144:ef7eb2e8f9f7 2184 hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
<> 144:ef7eb2e8f9f7 2185
<> 144:ef7eb2e8f9f7 2186 /* Set thresholds and break signals */
<> 144:ef7eb2e8f9f7 2187 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
<> 144:ef7eb2e8f9f7 2188 hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
<> 144:ef7eb2e8f9f7 2189 awdParam->HighBreakSignal);
<> 144:ef7eb2e8f9f7 2190 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
<> 144:ef7eb2e8f9f7 2191 hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
<> 144:ef7eb2e8f9f7 2192 awdParam->LowBreakSignal);
<> 144:ef7eb2e8f9f7 2193
<> 144:ef7eb2e8f9f7 2194 /* Set channels and interrupt for analog watchdog */
<> 144:ef7eb2e8f9f7 2195 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
<> 144:ef7eb2e8f9f7 2196 hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
<> 144:ef7eb2e8f9f7 2197 DFSDM_FLTCR2_AWDIE);
<> 144:ef7eb2e8f9f7 2198 }
<> 144:ef7eb2e8f9f7 2199 /* Return function status */
<> 144:ef7eb2e8f9f7 2200 return status;
<> 144:ef7eb2e8f9f7 2201 }
<> 144:ef7eb2e8f9f7 2202
<> 144:ef7eb2e8f9f7 2203 /**
<> 144:ef7eb2e8f9f7 2204 * @brief This function allows to stop filter analog watchdog in interrupt mode.
<> 144:ef7eb2e8f9f7 2205 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2206 * @retval HAL status
<> 144:ef7eb2e8f9f7 2207 */
<> 144:ef7eb2e8f9f7 2208 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2209 {
<> 144:ef7eb2e8f9f7 2210 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2211
<> 144:ef7eb2e8f9f7 2212 /* Check parameters */
<> 144:ef7eb2e8f9f7 2213 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2214
<> 144:ef7eb2e8f9f7 2215 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2216 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2217 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2218 {
<> 144:ef7eb2e8f9f7 2219 /* Return error status */
<> 144:ef7eb2e8f9f7 2220 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2221 }
<> 144:ef7eb2e8f9f7 2222 else
<> 144:ef7eb2e8f9f7 2223 {
<> 144:ef7eb2e8f9f7 2224 /* Reset channels for analog watchdog and deactivate interrupt */
<> 144:ef7eb2e8f9f7 2225 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
<> 144:ef7eb2e8f9f7 2226
<> 144:ef7eb2e8f9f7 2227 /* Clear all analog watchdog flags */
<> 144:ef7eb2e8f9f7 2228 hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
<> 144:ef7eb2e8f9f7 2229
<> 144:ef7eb2e8f9f7 2230 /* Reset thresholds and break signals */
<> 144:ef7eb2e8f9f7 2231 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
<> 144:ef7eb2e8f9f7 2232 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
<> 144:ef7eb2e8f9f7 2233
<> 144:ef7eb2e8f9f7 2234 /* Reset analog watchdog data source */
<> 144:ef7eb2e8f9f7 2235 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
<> 144:ef7eb2e8f9f7 2236 }
<> 144:ef7eb2e8f9f7 2237 /* Return function status */
<> 144:ef7eb2e8f9f7 2238 return status;
<> 144:ef7eb2e8f9f7 2239 }
<> 144:ef7eb2e8f9f7 2240
<> 144:ef7eb2e8f9f7 2241 /**
<> 144:ef7eb2e8f9f7 2242 * @brief This function allows to start extreme detector feature.
<> 144:ef7eb2e8f9f7 2243 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2244 * @param Channel : Channels where extreme detector is enabled.
<> 144:ef7eb2e8f9f7 2245 * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
<> 144:ef7eb2e8f9f7 2246 * @retval HAL status
<> 144:ef7eb2e8f9f7 2247 */
<> 144:ef7eb2e8f9f7 2248 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2249 uint32_t Channel)
<> 144:ef7eb2e8f9f7 2250 {
<> 144:ef7eb2e8f9f7 2251 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2252
<> 144:ef7eb2e8f9f7 2253 /* Check parameters */
<> 144:ef7eb2e8f9f7 2254 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2255 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 2256
<> 144:ef7eb2e8f9f7 2257 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2258 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2259 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2260 {
<> 144:ef7eb2e8f9f7 2261 /* Return error status */
<> 144:ef7eb2e8f9f7 2262 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2263 }
<> 144:ef7eb2e8f9f7 2264 else
<> 144:ef7eb2e8f9f7 2265 {
<> 144:ef7eb2e8f9f7 2266 /* Set channels for extreme detector */
<> 144:ef7eb2e8f9f7 2267 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
<> 144:ef7eb2e8f9f7 2268 hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);
<> 144:ef7eb2e8f9f7 2269 }
<> 144:ef7eb2e8f9f7 2270 /* Return function status */
<> 144:ef7eb2e8f9f7 2271 return status;
<> 144:ef7eb2e8f9f7 2272 }
<> 144:ef7eb2e8f9f7 2273
<> 144:ef7eb2e8f9f7 2274 /**
<> 144:ef7eb2e8f9f7 2275 * @brief This function allows to stop extreme detector feature.
<> 144:ef7eb2e8f9f7 2276 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2277 * @retval HAL status
<> 144:ef7eb2e8f9f7 2278 */
<> 144:ef7eb2e8f9f7 2279 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2280 {
<> 144:ef7eb2e8f9f7 2281 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 2282 __IO uint32_t reg1;
<> 144:ef7eb2e8f9f7 2283 __IO uint32_t reg2;
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 /* Check parameters */
<> 144:ef7eb2e8f9f7 2286 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2287
<> 144:ef7eb2e8f9f7 2288 /* Check DFSDM filter state */
<> 144:ef7eb2e8f9f7 2289 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
<> 144:ef7eb2e8f9f7 2290 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
<> 144:ef7eb2e8f9f7 2291 {
<> 144:ef7eb2e8f9f7 2292 /* Return error status */
<> 144:ef7eb2e8f9f7 2293 status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 2294 }
<> 144:ef7eb2e8f9f7 2295 else
<> 144:ef7eb2e8f9f7 2296 {
<> 144:ef7eb2e8f9f7 2297 /* Reset channels for extreme detector */
<> 144:ef7eb2e8f9f7 2298 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
<> 144:ef7eb2e8f9f7 2299
<> 144:ef7eb2e8f9f7 2300 /* Clear extreme detector values */
<> 144:ef7eb2e8f9f7 2301 reg1 = hdfsdm_filter->Instance->FLTEXMAX;
<> 144:ef7eb2e8f9f7 2302 reg2 = hdfsdm_filter->Instance->FLTEXMIN;
<> 144:ef7eb2e8f9f7 2303 UNUSED(reg1); /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2304 UNUSED(reg2); /* To avoid GCC warning */
<> 144:ef7eb2e8f9f7 2305 }
<> 144:ef7eb2e8f9f7 2306 /* Return function status */
<> 144:ef7eb2e8f9f7 2307 return status;
<> 144:ef7eb2e8f9f7 2308 }
<> 144:ef7eb2e8f9f7 2309
<> 144:ef7eb2e8f9f7 2310 /**
<> 144:ef7eb2e8f9f7 2311 * @brief This function allows to get extreme detector maximum value.
<> 144:ef7eb2e8f9f7 2312 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2313 * @param Channel : Corresponding channel.
<> 144:ef7eb2e8f9f7 2314 * @retval Extreme detector maximum value
<> 144:ef7eb2e8f9f7 2315 * This value is between Min_Data = -8388608 and Max_Data = 8388607.
<> 144:ef7eb2e8f9f7 2316 */
<> 144:ef7eb2e8f9f7 2317 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2318 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 2319 {
<> 144:ef7eb2e8f9f7 2320 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2321 int32_t value = 0;
<> 144:ef7eb2e8f9f7 2322
<> 144:ef7eb2e8f9f7 2323 /* Check parameters */
<> 144:ef7eb2e8f9f7 2324 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2325 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 /* Get value of extreme detector maximum register */
<> 144:ef7eb2e8f9f7 2328 reg = hdfsdm_filter->Instance->FLTEXMAX;
<> 144:ef7eb2e8f9f7 2329
<> 144:ef7eb2e8f9f7 2330 /* Extract channel and extreme detector maximum value */
<> 144:ef7eb2e8f9f7 2331 *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
<> 144:ef7eb2e8f9f7 2332 value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2333
<> 144:ef7eb2e8f9f7 2334 /* return extreme detector maximum value */
<> 144:ef7eb2e8f9f7 2335 return value;
<> 144:ef7eb2e8f9f7 2336 }
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 /**
<> 144:ef7eb2e8f9f7 2339 * @brief This function allows to get extreme detector minimum value.
<> 144:ef7eb2e8f9f7 2340 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2341 * @param Channel : Corresponding channel.
<> 144:ef7eb2e8f9f7 2342 * @retval Extreme detector minimum value
<> 144:ef7eb2e8f9f7 2343 * This value is between Min_Data = -8388608 and Max_Data = 8388607.
<> 144:ef7eb2e8f9f7 2344 */
<> 144:ef7eb2e8f9f7 2345 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2346 uint32_t *Channel)
<> 144:ef7eb2e8f9f7 2347 {
<> 144:ef7eb2e8f9f7 2348 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2349 int32_t value = 0;
<> 144:ef7eb2e8f9f7 2350
<> 144:ef7eb2e8f9f7 2351 /* Check parameters */
<> 144:ef7eb2e8f9f7 2352 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2353 assert_param(Channel != NULL);
<> 144:ef7eb2e8f9f7 2354
<> 144:ef7eb2e8f9f7 2355 /* Get value of extreme detector minimum register */
<> 144:ef7eb2e8f9f7 2356 reg = hdfsdm_filter->Instance->FLTEXMIN;
<> 144:ef7eb2e8f9f7 2357
<> 144:ef7eb2e8f9f7 2358 /* Extract channel and extreme detector minimum value */
<> 144:ef7eb2e8f9f7 2359 *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
<> 144:ef7eb2e8f9f7 2360 value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 /* return extreme detector minimum value */
<> 144:ef7eb2e8f9f7 2363 return value;
<> 144:ef7eb2e8f9f7 2364 }
<> 144:ef7eb2e8f9f7 2365
<> 144:ef7eb2e8f9f7 2366 /**
<> 144:ef7eb2e8f9f7 2367 * @brief This function allows to get conversion time value.
<> 144:ef7eb2e8f9f7 2368 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2369 * @retval Conversion time value
<> 144:ef7eb2e8f9f7 2370 * @note To get time in second, this value has to be divided by DFSDM clock frequency.
<> 144:ef7eb2e8f9f7 2371 */
<> 144:ef7eb2e8f9f7 2372 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2373 {
<> 144:ef7eb2e8f9f7 2374 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2375 uint32_t value = 0;
<> 144:ef7eb2e8f9f7 2376
<> 144:ef7eb2e8f9f7 2377 /* Check parameters */
<> 144:ef7eb2e8f9f7 2378 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
<> 144:ef7eb2e8f9f7 2379
<> 144:ef7eb2e8f9f7 2380 /* Get value of conversion timer register */
<> 144:ef7eb2e8f9f7 2381 reg = hdfsdm_filter->Instance->FLTCNVTIMR;
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 /* Extract conversion time value */
<> 144:ef7eb2e8f9f7 2384 value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
<> 144:ef7eb2e8f9f7 2385
<> 144:ef7eb2e8f9f7 2386 /* return extreme detector minimum value */
<> 144:ef7eb2e8f9f7 2387 return value;
<> 144:ef7eb2e8f9f7 2388 }
<> 144:ef7eb2e8f9f7 2389
<> 144:ef7eb2e8f9f7 2390 /**
<> 144:ef7eb2e8f9f7 2391 * @brief This function handles the DFSDM interrupts.
<> 144:ef7eb2e8f9f7 2392 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2393 * @retval None
<> 144:ef7eb2e8f9f7 2394 */
<> 144:ef7eb2e8f9f7 2395 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2396 {
<> 144:ef7eb2e8f9f7 2397 /* Check if overrun occurs during regular conversion */
<> 144:ef7eb2e8f9f7 2398 if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \
<> 144:ef7eb2e8f9f7 2399 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0))
<> 144:ef7eb2e8f9f7 2400 {
<> 144:ef7eb2e8f9f7 2401 /* Clear regular overrun flag */
<> 144:ef7eb2e8f9f7 2402 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
<> 144:ef7eb2e8f9f7 2403
<> 144:ef7eb2e8f9f7 2404 /* Update error code */
<> 144:ef7eb2e8f9f7 2405 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
<> 144:ef7eb2e8f9f7 2406
<> 144:ef7eb2e8f9f7 2407 /* Call error callback */
<> 144:ef7eb2e8f9f7 2408 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2409 }
<> 144:ef7eb2e8f9f7 2410 /* Check if overrun occurs during injected conversion */
<> 144:ef7eb2e8f9f7 2411 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \
<> 144:ef7eb2e8f9f7 2412 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0))
<> 144:ef7eb2e8f9f7 2413 {
<> 144:ef7eb2e8f9f7 2414 /* Clear injected overrun flag */
<> 144:ef7eb2e8f9f7 2415 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
<> 144:ef7eb2e8f9f7 2416
<> 144:ef7eb2e8f9f7 2417 /* Update error code */
<> 144:ef7eb2e8f9f7 2418 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
<> 144:ef7eb2e8f9f7 2419
<> 144:ef7eb2e8f9f7 2420 /* Call error callback */
<> 144:ef7eb2e8f9f7 2421 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2422 }
<> 144:ef7eb2e8f9f7 2423 /* Check if end of regular conversion */
<> 144:ef7eb2e8f9f7 2424 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \
<> 144:ef7eb2e8f9f7 2425 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0))
<> 144:ef7eb2e8f9f7 2426 {
<> 144:ef7eb2e8f9f7 2427 /* Call regular conversion complete callback */
<> 144:ef7eb2e8f9f7 2428 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2429
<> 144:ef7eb2e8f9f7 2430 /* End of conversion if mode is not continuous and software trigger */
<> 144:ef7eb2e8f9f7 2431 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
<> 144:ef7eb2e8f9f7 2432 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 2433 {
<> 144:ef7eb2e8f9f7 2434 /* Disable interrupts for regular conversions */
<> 144:ef7eb2e8f9f7 2435 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
<> 144:ef7eb2e8f9f7 2436
<> 144:ef7eb2e8f9f7 2437 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2438 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
<> 144:ef7eb2e8f9f7 2439 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
<> 144:ef7eb2e8f9f7 2440 }
<> 144:ef7eb2e8f9f7 2441 }
<> 144:ef7eb2e8f9f7 2442 /* Check if end of injected conversion */
<> 144:ef7eb2e8f9f7 2443 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \
<> 144:ef7eb2e8f9f7 2444 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0))
<> 144:ef7eb2e8f9f7 2445 {
<> 144:ef7eb2e8f9f7 2446 /* Call injected conversion complete callback */
<> 144:ef7eb2e8f9f7 2447 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2448
<> 144:ef7eb2e8f9f7 2449 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 2450 hdfsdm_filter->InjConvRemaining--;
<> 144:ef7eb2e8f9f7 2451 if(hdfsdm_filter->InjConvRemaining == 0)
<> 144:ef7eb2e8f9f7 2452 {
<> 144:ef7eb2e8f9f7 2453 /* End of conversion if trigger is software */
<> 144:ef7eb2e8f9f7 2454 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2455 {
<> 144:ef7eb2e8f9f7 2456 /* Disable interrupts for injected conversions */
<> 144:ef7eb2e8f9f7 2457 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
<> 144:ef7eb2e8f9f7 2458
<> 144:ef7eb2e8f9f7 2459 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2460 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
<> 144:ef7eb2e8f9f7 2461 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
<> 144:ef7eb2e8f9f7 2462 }
<> 144:ef7eb2e8f9f7 2463 /* end of injected sequence, reset the value */
<> 144:ef7eb2e8f9f7 2464 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 2465 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 2466 }
<> 144:ef7eb2e8f9f7 2467 }
<> 144:ef7eb2e8f9f7 2468 /* Check if analog watchdog occurs */
<> 144:ef7eb2e8f9f7 2469 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \
<> 144:ef7eb2e8f9f7 2470 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0))
<> 144:ef7eb2e8f9f7 2471 {
<> 144:ef7eb2e8f9f7 2472 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2473 uint32_t threshold = 0;
<> 144:ef7eb2e8f9f7 2474 uint32_t channel = 0;
<> 144:ef7eb2e8f9f7 2475
<> 144:ef7eb2e8f9f7 2476 /* Get channel and threshold */
<> 144:ef7eb2e8f9f7 2477 reg = hdfsdm_filter->Instance->FLTAWSR;
<> 144:ef7eb2e8f9f7 2478 threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
<> 144:ef7eb2e8f9f7 2479 if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
<> 144:ef7eb2e8f9f7 2480 {
<> 144:ef7eb2e8f9f7 2481 reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
<> 144:ef7eb2e8f9f7 2482 }
<> 144:ef7eb2e8f9f7 2483 while((reg & 1) == 0)
<> 144:ef7eb2e8f9f7 2484 {
<> 144:ef7eb2e8f9f7 2485 channel++;
<> 144:ef7eb2e8f9f7 2486 reg = reg >> 1;
<> 144:ef7eb2e8f9f7 2487 }
<> 144:ef7eb2e8f9f7 2488 /* Clear analog watchdog flag */
<> 144:ef7eb2e8f9f7 2489 hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
<> 144:ef7eb2e8f9f7 2490 (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
<> 144:ef7eb2e8f9f7 2491 (1 << channel);
<> 144:ef7eb2e8f9f7 2492
<> 144:ef7eb2e8f9f7 2493 /* Call analog watchdog callback */
<> 144:ef7eb2e8f9f7 2494 HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
<> 144:ef7eb2e8f9f7 2495 }
<> 144:ef7eb2e8f9f7 2496 /* Check if clock absence occurs */
<> 144:ef7eb2e8f9f7 2497 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
<> 144:ef7eb2e8f9f7 2498 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \
<> 144:ef7eb2e8f9f7 2499 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0))
<> 144:ef7eb2e8f9f7 2500 {
<> 144:ef7eb2e8f9f7 2501 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2502 uint32_t channel = 0;
<> 144:ef7eb2e8f9f7 2503
<> 144:ef7eb2e8f9f7 2504 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
<> 144:ef7eb2e8f9f7 2505
<> 144:ef7eb2e8f9f7 2506 while(channel < DFSDM1_CHANNEL_NUMBER)
<> 144:ef7eb2e8f9f7 2507 {
<> 144:ef7eb2e8f9f7 2508 /* Check if flag is set and corresponding channel is enabled */
<> 144:ef7eb2e8f9f7 2509 if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL))
<> 144:ef7eb2e8f9f7 2510 {
<> 144:ef7eb2e8f9f7 2511 /* Check clock absence has been enabled for this channel */
<> 144:ef7eb2e8f9f7 2512 if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)
<> 144:ef7eb2e8f9f7 2513 {
<> 144:ef7eb2e8f9f7 2514 /* Clear clock absence flag */
<> 144:ef7eb2e8f9f7 2515 hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 2516
<> 144:ef7eb2e8f9f7 2517 /* Call clock absence callback */
<> 144:ef7eb2e8f9f7 2518 HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
<> 144:ef7eb2e8f9f7 2519 }
<> 144:ef7eb2e8f9f7 2520 }
<> 144:ef7eb2e8f9f7 2521 channel++;
<> 144:ef7eb2e8f9f7 2522 reg = reg >> 1;
<> 144:ef7eb2e8f9f7 2523 }
<> 144:ef7eb2e8f9f7 2524 }
<> 144:ef7eb2e8f9f7 2525 /* Check if short circuit detection occurs */
<> 144:ef7eb2e8f9f7 2526 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
<> 144:ef7eb2e8f9f7 2527 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \
<> 144:ef7eb2e8f9f7 2528 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0))
<> 144:ef7eb2e8f9f7 2529 {
<> 144:ef7eb2e8f9f7 2530 uint32_t reg = 0;
<> 144:ef7eb2e8f9f7 2531 uint32_t channel = 0;
<> 144:ef7eb2e8f9f7 2532
<> 144:ef7eb2e8f9f7 2533 /* Get channel */
<> 144:ef7eb2e8f9f7 2534 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
<> 144:ef7eb2e8f9f7 2535 while((reg & 1) == 0)
<> 144:ef7eb2e8f9f7 2536 {
<> 144:ef7eb2e8f9f7 2537 channel++;
<> 144:ef7eb2e8f9f7 2538 reg = reg >> 1;
<> 144:ef7eb2e8f9f7 2539 }
<> 144:ef7eb2e8f9f7 2540
<> 144:ef7eb2e8f9f7 2541 /* Clear short circuit detection flag */
<> 144:ef7eb2e8f9f7 2542 hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
<> 144:ef7eb2e8f9f7 2543
<> 144:ef7eb2e8f9f7 2544 /* Call short circuit detection callback */
<> 144:ef7eb2e8f9f7 2545 HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
<> 144:ef7eb2e8f9f7 2546 }
<> 144:ef7eb2e8f9f7 2547 }
<> 144:ef7eb2e8f9f7 2548
<> 144:ef7eb2e8f9f7 2549 /**
<> 144:ef7eb2e8f9f7 2550 * @brief Regular conversion complete callback.
<> 144:ef7eb2e8f9f7 2551 * @note In interrupt mode, user has to read conversion value in this function
<> 144:ef7eb2e8f9f7 2552 * using HAL_DFSDM_FilterGetRegularValue.
<> 144:ef7eb2e8f9f7 2553 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2554 * @retval None
<> 144:ef7eb2e8f9f7 2555 */
<> 144:ef7eb2e8f9f7 2556 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2557 {
<> 144:ef7eb2e8f9f7 2558 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2559 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2560
<> 144:ef7eb2e8f9f7 2561 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2562 the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2563 */
<> 144:ef7eb2e8f9f7 2564 }
<> 144:ef7eb2e8f9f7 2565
<> 144:ef7eb2e8f9f7 2566 /**
<> 144:ef7eb2e8f9f7 2567 * @brief Half regular conversion complete callback.
<> 144:ef7eb2e8f9f7 2568 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2569 * @retval None
<> 144:ef7eb2e8f9f7 2570 */
<> 144:ef7eb2e8f9f7 2571 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2572 {
<> 144:ef7eb2e8f9f7 2573 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2574 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2575
<> 144:ef7eb2e8f9f7 2576 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2577 the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2578 */
<> 144:ef7eb2e8f9f7 2579 }
<> 144:ef7eb2e8f9f7 2580
<> 144:ef7eb2e8f9f7 2581 /**
<> 144:ef7eb2e8f9f7 2582 * @brief Injected conversion complete callback.
<> 144:ef7eb2e8f9f7 2583 * @note In interrupt mode, user has to read conversion value in this function
<> 144:ef7eb2e8f9f7 2584 * using HAL_DFSDM_FilterGetInjectedValue.
<> 144:ef7eb2e8f9f7 2585 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2586 * @retval None
<> 144:ef7eb2e8f9f7 2587 */
<> 144:ef7eb2e8f9f7 2588 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2589 {
<> 144:ef7eb2e8f9f7 2590 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2591 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2592
<> 144:ef7eb2e8f9f7 2593 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2594 the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2595 */
<> 144:ef7eb2e8f9f7 2596 }
<> 144:ef7eb2e8f9f7 2597
<> 144:ef7eb2e8f9f7 2598 /**
<> 144:ef7eb2e8f9f7 2599 * @brief Half injected conversion complete callback.
<> 144:ef7eb2e8f9f7 2600 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2601 * @retval None
<> 144:ef7eb2e8f9f7 2602 */
<> 144:ef7eb2e8f9f7 2603 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2604 {
<> 144:ef7eb2e8f9f7 2605 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2606 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2607
<> 144:ef7eb2e8f9f7 2608 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2609 the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2610 */
<> 144:ef7eb2e8f9f7 2611 }
<> 144:ef7eb2e8f9f7 2612
<> 144:ef7eb2e8f9f7 2613 /**
<> 144:ef7eb2e8f9f7 2614 * @brief Filter analog watchdog callback.
<> 144:ef7eb2e8f9f7 2615 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2616 * @param Channel : Corresponding channel.
<> 144:ef7eb2e8f9f7 2617 * @param Threshold : Low or high threshold has been reached.
<> 144:ef7eb2e8f9f7 2618 * @retval None
<> 144:ef7eb2e8f9f7 2619 */
<> 144:ef7eb2e8f9f7 2620 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
<> 144:ef7eb2e8f9f7 2621 uint32_t Channel, uint32_t Threshold)
<> 144:ef7eb2e8f9f7 2622 {
<> 144:ef7eb2e8f9f7 2623 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2624 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2625 UNUSED(Channel);
<> 144:ef7eb2e8f9f7 2626 UNUSED(Threshold);
<> 144:ef7eb2e8f9f7 2627
<> 144:ef7eb2e8f9f7 2628 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2629 the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2630 */
<> 144:ef7eb2e8f9f7 2631 }
<> 144:ef7eb2e8f9f7 2632
<> 144:ef7eb2e8f9f7 2633 /**
<> 144:ef7eb2e8f9f7 2634 * @brief Error callback.
<> 144:ef7eb2e8f9f7 2635 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2636 * @retval None
<> 144:ef7eb2e8f9f7 2637 */
<> 144:ef7eb2e8f9f7 2638 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2639 {
<> 144:ef7eb2e8f9f7 2640 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2641 UNUSED(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2642
<> 144:ef7eb2e8f9f7 2643 /* NOTE : This function should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2644 the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
<> 144:ef7eb2e8f9f7 2645 */
<> 144:ef7eb2e8f9f7 2646 }
<> 144:ef7eb2e8f9f7 2647
<> 144:ef7eb2e8f9f7 2648 /**
<> 144:ef7eb2e8f9f7 2649 * @}
<> 144:ef7eb2e8f9f7 2650 */
<> 144:ef7eb2e8f9f7 2651
<> 144:ef7eb2e8f9f7 2652 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
<> 144:ef7eb2e8f9f7 2653 * @brief Filter state functions
<> 144:ef7eb2e8f9f7 2654 *
<> 144:ef7eb2e8f9f7 2655 @verbatim
<> 144:ef7eb2e8f9f7 2656 ==============================================================================
<> 144:ef7eb2e8f9f7 2657 ##### Filter state functions #####
<> 144:ef7eb2e8f9f7 2658 ==============================================================================
<> 144:ef7eb2e8f9f7 2659 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2660 (+) Get the DFSDM filter state.
<> 144:ef7eb2e8f9f7 2661 (+) Get the DFSDM filter error.
<> 144:ef7eb2e8f9f7 2662 @endverbatim
<> 144:ef7eb2e8f9f7 2663 * @{
<> 144:ef7eb2e8f9f7 2664 */
<> 144:ef7eb2e8f9f7 2665
<> 144:ef7eb2e8f9f7 2666 /**
<> 144:ef7eb2e8f9f7 2667 * @brief This function allows to get the current DFSDM filter handle state.
<> 144:ef7eb2e8f9f7 2668 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2669 * @retval DFSDM filter state.
<> 144:ef7eb2e8f9f7 2670 */
<> 144:ef7eb2e8f9f7 2671 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2672 {
<> 144:ef7eb2e8f9f7 2673 /* Return DFSDM filter handle state */
<> 144:ef7eb2e8f9f7 2674 return hdfsdm_filter->State;
<> 144:ef7eb2e8f9f7 2675 }
<> 144:ef7eb2e8f9f7 2676
<> 144:ef7eb2e8f9f7 2677 /**
<> 144:ef7eb2e8f9f7 2678 * @brief This function allows to get the current DFSDM filter error.
<> 144:ef7eb2e8f9f7 2679 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2680 * @retval DFSDM filter error code.
<> 144:ef7eb2e8f9f7 2681 */
<> 144:ef7eb2e8f9f7 2682 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2683 {
<> 144:ef7eb2e8f9f7 2684 return hdfsdm_filter->ErrorCode;
<> 144:ef7eb2e8f9f7 2685 }
<> 144:ef7eb2e8f9f7 2686
<> 144:ef7eb2e8f9f7 2687 /**
<> 144:ef7eb2e8f9f7 2688 * @}
<> 144:ef7eb2e8f9f7 2689 */
<> 144:ef7eb2e8f9f7 2690
<> 144:ef7eb2e8f9f7 2691 /**
<> 144:ef7eb2e8f9f7 2692 * @}
<> 144:ef7eb2e8f9f7 2693 */
<> 144:ef7eb2e8f9f7 2694 /* End of exported functions -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2695
<> 144:ef7eb2e8f9f7 2696 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2697 /** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
<> 144:ef7eb2e8f9f7 2698 * @{
<> 144:ef7eb2e8f9f7 2699 */
<> 144:ef7eb2e8f9f7 2700
<> 144:ef7eb2e8f9f7 2701 /**
<> 144:ef7eb2e8f9f7 2702 * @brief DMA half transfer complete callback for regular conversion.
<> 144:ef7eb2e8f9f7 2703 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2704 * @retval None
<> 144:ef7eb2e8f9f7 2705 */
<> 144:ef7eb2e8f9f7 2706 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2707 {
<> 144:ef7eb2e8f9f7 2708 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2709 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2710
<> 144:ef7eb2e8f9f7 2711 /* Call regular half conversion complete callback */
<> 144:ef7eb2e8f9f7 2712 HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2713 }
<> 144:ef7eb2e8f9f7 2714
<> 144:ef7eb2e8f9f7 2715 /**
<> 144:ef7eb2e8f9f7 2716 * @brief DMA transfer complete callback for regular conversion.
<> 144:ef7eb2e8f9f7 2717 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2718 * @retval None
<> 144:ef7eb2e8f9f7 2719 */
<> 144:ef7eb2e8f9f7 2720 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2721 {
<> 144:ef7eb2e8f9f7 2722 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2723 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2724
<> 144:ef7eb2e8f9f7 2725 /* Call regular conversion complete callback */
<> 144:ef7eb2e8f9f7 2726 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2727 }
<> 144:ef7eb2e8f9f7 2728
<> 144:ef7eb2e8f9f7 2729 /**
<> 144:ef7eb2e8f9f7 2730 * @brief DMA half transfer complete callback for injected conversion.
<> 144:ef7eb2e8f9f7 2731 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2732 * @retval None
<> 144:ef7eb2e8f9f7 2733 */
<> 144:ef7eb2e8f9f7 2734 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2735 {
<> 144:ef7eb2e8f9f7 2736 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2737 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2738
<> 144:ef7eb2e8f9f7 2739 /* Call injected half conversion complete callback */
<> 144:ef7eb2e8f9f7 2740 HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2741 }
<> 144:ef7eb2e8f9f7 2742
<> 144:ef7eb2e8f9f7 2743 /**
<> 144:ef7eb2e8f9f7 2744 * @brief DMA transfer complete callback for injected conversion.
<> 144:ef7eb2e8f9f7 2745 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2746 * @retval None
<> 144:ef7eb2e8f9f7 2747 */
<> 144:ef7eb2e8f9f7 2748 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2749 {
<> 144:ef7eb2e8f9f7 2750 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2751 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2752
<> 144:ef7eb2e8f9f7 2753 /* Call injected conversion complete callback */
<> 144:ef7eb2e8f9f7 2754 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2755 }
<> 144:ef7eb2e8f9f7 2756
<> 144:ef7eb2e8f9f7 2757 /**
<> 144:ef7eb2e8f9f7 2758 * @brief DMA error callback.
<> 144:ef7eb2e8f9f7 2759 * @param hdma : DMA handle.
<> 144:ef7eb2e8f9f7 2760 * @retval None
<> 144:ef7eb2e8f9f7 2761 */
<> 144:ef7eb2e8f9f7 2762 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 2763 {
<> 144:ef7eb2e8f9f7 2764 /* Get DFSDM filter handle */
<> 144:ef7eb2e8f9f7 2765 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
<> 144:ef7eb2e8f9f7 2766
<> 144:ef7eb2e8f9f7 2767 /* Update error code */
<> 144:ef7eb2e8f9f7 2768 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
<> 144:ef7eb2e8f9f7 2769
<> 144:ef7eb2e8f9f7 2770 /* Call error callback */
<> 144:ef7eb2e8f9f7 2771 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
<> 144:ef7eb2e8f9f7 2772 }
<> 144:ef7eb2e8f9f7 2773
<> 144:ef7eb2e8f9f7 2774 /**
<> 144:ef7eb2e8f9f7 2775 * @brief This function allows to get the number of injected channels.
<> 144:ef7eb2e8f9f7 2776 * @param Channels : bitfield of injected channels.
<> 144:ef7eb2e8f9f7 2777 * @retval Number of injected channels.
<> 144:ef7eb2e8f9f7 2778 */
<> 144:ef7eb2e8f9f7 2779 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
<> 144:ef7eb2e8f9f7 2780 {
<> 144:ef7eb2e8f9f7 2781 uint32_t nbChannels = 0;
<> 144:ef7eb2e8f9f7 2782 uint32_t tmp;
<> 144:ef7eb2e8f9f7 2783
<> 144:ef7eb2e8f9f7 2784 /* Get the number of channels from bitfield */
<> 144:ef7eb2e8f9f7 2785 tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
<> 144:ef7eb2e8f9f7 2786 while(tmp != 0)
<> 144:ef7eb2e8f9f7 2787 {
<> 144:ef7eb2e8f9f7 2788 if((tmp & 1) != 0)
<> 144:ef7eb2e8f9f7 2789 {
<> 144:ef7eb2e8f9f7 2790 nbChannels++;
<> 144:ef7eb2e8f9f7 2791 }
<> 144:ef7eb2e8f9f7 2792 tmp = (uint32_t) (tmp >> 1);
<> 144:ef7eb2e8f9f7 2793 }
<> 144:ef7eb2e8f9f7 2794 return nbChannels;
<> 144:ef7eb2e8f9f7 2795 }
<> 144:ef7eb2e8f9f7 2796
<> 144:ef7eb2e8f9f7 2797 /**
<> 144:ef7eb2e8f9f7 2798 * @brief This function allows to get the channel number from channel instance.
<> 144:ef7eb2e8f9f7 2799 * @param Instance : DFSDM channel instance.
<> 144:ef7eb2e8f9f7 2800 * @retval Channel number.
<> 144:ef7eb2e8f9f7 2801 */
<> 144:ef7eb2e8f9f7 2802 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
<> 144:ef7eb2e8f9f7 2803 {
<> 144:ef7eb2e8f9f7 2804 uint32_t channel = 0xFF;
<> 144:ef7eb2e8f9f7 2805
<> 144:ef7eb2e8f9f7 2806 /* Get channel from instance */
<> 144:ef7eb2e8f9f7 2807 if(Instance == DFSDM1_Channel0)
<> 144:ef7eb2e8f9f7 2808 {
<> 144:ef7eb2e8f9f7 2809 channel = 0;
<> 144:ef7eb2e8f9f7 2810 }
<> 144:ef7eb2e8f9f7 2811 else if(Instance == DFSDM1_Channel1)
<> 144:ef7eb2e8f9f7 2812 {
<> 144:ef7eb2e8f9f7 2813 channel = 1;
<> 144:ef7eb2e8f9f7 2814 }
<> 144:ef7eb2e8f9f7 2815 else if(Instance == DFSDM1_Channel2)
<> 144:ef7eb2e8f9f7 2816 {
<> 144:ef7eb2e8f9f7 2817 channel = 2;
<> 144:ef7eb2e8f9f7 2818 }
<> 144:ef7eb2e8f9f7 2819 else if(Instance == DFSDM1_Channel3)
<> 144:ef7eb2e8f9f7 2820 {
<> 144:ef7eb2e8f9f7 2821 channel = 3;
<> 144:ef7eb2e8f9f7 2822 }
<> 144:ef7eb2e8f9f7 2823 else if(Instance == DFSDM1_Channel4)
<> 144:ef7eb2e8f9f7 2824 {
<> 144:ef7eb2e8f9f7 2825 channel = 4;
<> 144:ef7eb2e8f9f7 2826 }
<> 144:ef7eb2e8f9f7 2827 else if(Instance == DFSDM1_Channel5)
<> 144:ef7eb2e8f9f7 2828 {
<> 144:ef7eb2e8f9f7 2829 channel = 5;
<> 144:ef7eb2e8f9f7 2830 }
<> 144:ef7eb2e8f9f7 2831 else if(Instance == DFSDM1_Channel6)
<> 144:ef7eb2e8f9f7 2832 {
<> 144:ef7eb2e8f9f7 2833 channel = 6;
<> 144:ef7eb2e8f9f7 2834 }
<> 144:ef7eb2e8f9f7 2835 else if(Instance == DFSDM1_Channel7)
<> 144:ef7eb2e8f9f7 2836 {
<> 144:ef7eb2e8f9f7 2837 channel = 7;
<> 144:ef7eb2e8f9f7 2838 }
<> 144:ef7eb2e8f9f7 2839
<> 144:ef7eb2e8f9f7 2840 return channel;
<> 144:ef7eb2e8f9f7 2841 }
<> 144:ef7eb2e8f9f7 2842
<> 144:ef7eb2e8f9f7 2843 /**
<> 144:ef7eb2e8f9f7 2844 * @brief This function allows to really start regular conversion.
<> 144:ef7eb2e8f9f7 2845 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2846 * @retval None
<> 144:ef7eb2e8f9f7 2847 */
<> 144:ef7eb2e8f9f7 2848 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2849 {
<> 144:ef7eb2e8f9f7 2850 /* Check regular trigger */
<> 144:ef7eb2e8f9f7 2851 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2852 {
<> 144:ef7eb2e8f9f7 2853 /* Software start of regular conversion */
<> 144:ef7eb2e8f9f7 2854 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
<> 144:ef7eb2e8f9f7 2855 }
<> 144:ef7eb2e8f9f7 2856 else /* synchronous trigger */
<> 144:ef7eb2e8f9f7 2857 {
<> 144:ef7eb2e8f9f7 2858 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2859 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2860
<> 144:ef7eb2e8f9f7 2861 /* Set RSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2862 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
<> 144:ef7eb2e8f9f7 2863
<> 144:ef7eb2e8f9f7 2864 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2865 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2866
<> 144:ef7eb2e8f9f7 2867 /* If injected conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2868 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
<> 144:ef7eb2e8f9f7 2869 {
<> 144:ef7eb2e8f9f7 2870 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2871 {
<> 144:ef7eb2e8f9f7 2872 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
<> 144:ef7eb2e8f9f7 2873 }
<> 144:ef7eb2e8f9f7 2874 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 2875 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 2876 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 2877 }
<> 144:ef7eb2e8f9f7 2878 }
<> 144:ef7eb2e8f9f7 2879 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2880 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
<> 144:ef7eb2e8f9f7 2881 HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
<> 144:ef7eb2e8f9f7 2882 }
<> 144:ef7eb2e8f9f7 2883
<> 144:ef7eb2e8f9f7 2884 /**
<> 144:ef7eb2e8f9f7 2885 * @brief This function allows to really stop regular conversion.
<> 144:ef7eb2e8f9f7 2886 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2887 * @retval None
<> 144:ef7eb2e8f9f7 2888 */
<> 144:ef7eb2e8f9f7 2889 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2890 {
<> 144:ef7eb2e8f9f7 2891 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2892 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2893
<> 144:ef7eb2e8f9f7 2894 /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2895 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
<> 144:ef7eb2e8f9f7 2896 {
<> 144:ef7eb2e8f9f7 2897 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
<> 144:ef7eb2e8f9f7 2898 }
<> 144:ef7eb2e8f9f7 2899
<> 144:ef7eb2e8f9f7 2900 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2901 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2902
<> 144:ef7eb2e8f9f7 2903 /* If injected conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2904 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
<> 144:ef7eb2e8f9f7 2905 {
<> 144:ef7eb2e8f9f7 2906 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2907 {
<> 144:ef7eb2e8f9f7 2908 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
<> 144:ef7eb2e8f9f7 2909 }
<> 144:ef7eb2e8f9f7 2910 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 2911 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 2912 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 2913 }
<> 144:ef7eb2e8f9f7 2914
<> 144:ef7eb2e8f9f7 2915 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2916 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
<> 144:ef7eb2e8f9f7 2917 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
<> 144:ef7eb2e8f9f7 2918 }
<> 144:ef7eb2e8f9f7 2919
<> 144:ef7eb2e8f9f7 2920 /**
<> 144:ef7eb2e8f9f7 2921 * @brief This function allows to really start injected conversion.
<> 144:ef7eb2e8f9f7 2922 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2923 * @retval None
<> 144:ef7eb2e8f9f7 2924 */
<> 144:ef7eb2e8f9f7 2925 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2926 {
<> 144:ef7eb2e8f9f7 2927 /* Check injected trigger */
<> 144:ef7eb2e8f9f7 2928 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
<> 144:ef7eb2e8f9f7 2929 {
<> 144:ef7eb2e8f9f7 2930 /* Software start of injected conversion */
<> 144:ef7eb2e8f9f7 2931 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
<> 144:ef7eb2e8f9f7 2932 }
<> 144:ef7eb2e8f9f7 2933 else /* external or synchronous trigger */
<> 144:ef7eb2e8f9f7 2934 {
<> 144:ef7eb2e8f9f7 2935 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2936 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2937
<> 144:ef7eb2e8f9f7 2938 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
<> 144:ef7eb2e8f9f7 2939 {
<> 144:ef7eb2e8f9f7 2940 /* Set JSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2941 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
<> 144:ef7eb2e8f9f7 2942 }
<> 144:ef7eb2e8f9f7 2943 else /* external trigger */
<> 144:ef7eb2e8f9f7 2944 {
<> 144:ef7eb2e8f9f7 2945 /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2946 hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
<> 144:ef7eb2e8f9f7 2947 }
<> 144:ef7eb2e8f9f7 2948
<> 144:ef7eb2e8f9f7 2949 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2950 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2951
<> 144:ef7eb2e8f9f7 2952 /* If regular conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2953 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
<> 144:ef7eb2e8f9f7 2954 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 2955 {
<> 144:ef7eb2e8f9f7 2956 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
<> 144:ef7eb2e8f9f7 2957 }
<> 144:ef7eb2e8f9f7 2958 }
<> 144:ef7eb2e8f9f7 2959 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 2960 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
<> 144:ef7eb2e8f9f7 2961 HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
<> 144:ef7eb2e8f9f7 2962 }
<> 144:ef7eb2e8f9f7 2963
<> 144:ef7eb2e8f9f7 2964 /**
<> 144:ef7eb2e8f9f7 2965 * @brief This function allows to really stop injected conversion.
<> 144:ef7eb2e8f9f7 2966 * @param hdfsdm_filter : DFSDM filter handle.
<> 144:ef7eb2e8f9f7 2967 * @retval None
<> 144:ef7eb2e8f9f7 2968 */
<> 144:ef7eb2e8f9f7 2969 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
<> 144:ef7eb2e8f9f7 2970 {
<> 144:ef7eb2e8f9f7 2971 /* Disable DFSDM filter */
<> 144:ef7eb2e8f9f7 2972 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
<> 144:ef7eb2e8f9f7 2973
<> 144:ef7eb2e8f9f7 2974 /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2975 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
<> 144:ef7eb2e8f9f7 2976 {
<> 144:ef7eb2e8f9f7 2977 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
<> 144:ef7eb2e8f9f7 2978 }
<> 144:ef7eb2e8f9f7 2979 else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
<> 144:ef7eb2e8f9f7 2980 {
<> 144:ef7eb2e8f9f7 2981 /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
<> 144:ef7eb2e8f9f7 2982 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
<> 144:ef7eb2e8f9f7 2983 }
<> 144:ef7eb2e8f9f7 2984
<> 144:ef7eb2e8f9f7 2985 /* Enable DFSDM filter */
<> 144:ef7eb2e8f9f7 2986 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
<> 144:ef7eb2e8f9f7 2987
<> 144:ef7eb2e8f9f7 2988 /* If regular conversion was in progress, restart it */
<> 144:ef7eb2e8f9f7 2989 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
<> 144:ef7eb2e8f9f7 2990 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
<> 144:ef7eb2e8f9f7 2991 {
<> 144:ef7eb2e8f9f7 2992 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
<> 144:ef7eb2e8f9f7 2993 }
<> 144:ef7eb2e8f9f7 2994
<> 144:ef7eb2e8f9f7 2995 /* Update remaining injected conversions */
<> 144:ef7eb2e8f9f7 2996 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
<> 144:ef7eb2e8f9f7 2997 hdfsdm_filter->InjectedChannelsNbr : 1;
<> 144:ef7eb2e8f9f7 2998
<> 144:ef7eb2e8f9f7 2999 /* Update DFSDM filter state */
<> 144:ef7eb2e8f9f7 3000 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
<> 144:ef7eb2e8f9f7 3001 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
<> 144:ef7eb2e8f9f7 3002 }
<> 144:ef7eb2e8f9f7 3003
<> 144:ef7eb2e8f9f7 3004 /**
<> 144:ef7eb2e8f9f7 3005 * @}
<> 144:ef7eb2e8f9f7 3006 */
<> 144:ef7eb2e8f9f7 3007 /* End of private functions --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 3008
<> 144:ef7eb2e8f9f7 3009 /**
<> 144:ef7eb2e8f9f7 3010 * @}
<> 144:ef7eb2e8f9f7 3011 */
<> 144:ef7eb2e8f9f7 3012 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 3013 #endif /* HAL_DFSDM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 3014 /**
<> 144:ef7eb2e8f9f7 3015 * @}
<> 144:ef7eb2e8f9f7 3016 */
<> 144:ef7eb2e8f9f7 3017
<> 144:ef7eb2e8f9f7 3018 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/