mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c@169:e3b6fe271b81, 2017-07-19 (annotated)
- Committer:
- Kojto
- Date:
- Wed Jul 19 17:31:21 2017 +0100
- Revision:
- 169:e3b6fe271b81
- Parent:
- 156:95d6b41a828b
- Child:
- 180:96ed750bd169
This updates the lib to the mbed lib v 147
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include "mbed_assert.h" |
<> | 144:ef7eb2e8f9f7 | 17 | #include "dma_api.h" |
<> | 144:ef7eb2e8f9f7 | 18 | #include "i2c_api.h" |
<> | 144:ef7eb2e8f9f7 | 19 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 21 | #include "r_typedefs.h" |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | #include "riic_iodefine.h" |
<> | 144:ef7eb2e8f9f7 | 24 | #include "RZ_A1_Init.h" |
<> | 144:ef7eb2e8f9f7 | 25 | #include "MBRZA1H.h" |
<> | 144:ef7eb2e8f9f7 | 26 | |
<> | 144:ef7eb2e8f9f7 | 27 | volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | #define REG(N) \ |
<> | 144:ef7eb2e8f9f7 | 30 | RIIC[obj->i2c.i2c]->RIICn##N |
<> | 144:ef7eb2e8f9f7 | 31 | |
<> | 144:ef7eb2e8f9f7 | 32 | /* RIICnCR1 */ |
<> | 144:ef7eb2e8f9f7 | 33 | #define CR1_RST (1 << 6) |
<> | 144:ef7eb2e8f9f7 | 34 | #define CR1_ICE (1 << 7) |
<> | 144:ef7eb2e8f9f7 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | /* RIICnCR2 */ |
<> | 144:ef7eb2e8f9f7 | 37 | #define CR2_ST (1 << 1) |
<> | 144:ef7eb2e8f9f7 | 38 | #define CR2_RS (1 << 2) |
<> | 144:ef7eb2e8f9f7 | 39 | #define CR2_SP (1 << 3) |
<> | 144:ef7eb2e8f9f7 | 40 | #define CR2_TRS (1 << 5) |
<> | 144:ef7eb2e8f9f7 | 41 | #define CR2_BBSY (1 << 7) |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | /* RIICnMR3 */ |
<> | 144:ef7eb2e8f9f7 | 44 | #define MR3_ACKBT (1 << 3) |
<> | 144:ef7eb2e8f9f7 | 45 | #define MR3_ACKWP (1 << 4) |
<> | 144:ef7eb2e8f9f7 | 46 | #define MR3_WAIT (1 << 6) |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | /* RIICnSER */ |
<> | 144:ef7eb2e8f9f7 | 49 | #define SER_SAR0E (1 << 0) |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | /* RIICnSR1 */ |
<> | 144:ef7eb2e8f9f7 | 52 | #define SR1_AAS0 (1 << 0) |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | /* RIICnSR2 */ |
<> | 144:ef7eb2e8f9f7 | 55 | #define SR2_START (1 << 2) |
<> | 144:ef7eb2e8f9f7 | 56 | #define SR2_STOP (1 << 3) |
<> | 144:ef7eb2e8f9f7 | 57 | #define SR2_NACKF (1 << 4) |
<> | 144:ef7eb2e8f9f7 | 58 | #define SR2_RDRF (1 << 5) |
<> | 144:ef7eb2e8f9f7 | 59 | #define SR2_TEND (1 << 6) |
<> | 144:ef7eb2e8f9f7 | 60 | #define SR2_TDRE (1 << 7) |
<> | 144:ef7eb2e8f9f7 | 61 | |
<> | 144:ef7eb2e8f9f7 | 62 | #define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | static const PinMap PinMap_I2C_SDA[] = { |
<> | 144:ef7eb2e8f9f7 | 65 | {P1_1 , I2C_0, 1}, |
<> | 144:ef7eb2e8f9f7 | 66 | {P1_3 , I2C_1, 1}, |
<> | 144:ef7eb2e8f9f7 | 67 | {P1_7 , I2C_3, 1}, |
<> | 144:ef7eb2e8f9f7 | 68 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 69 | }; |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | static const PinMap PinMap_I2C_SCL[] = { |
<> | 144:ef7eb2e8f9f7 | 72 | {P1_0 , I2C_0, 1}, |
<> | 144:ef7eb2e8f9f7 | 73 | {P1_2 , I2C_1, 1}, |
<> | 144:ef7eb2e8f9f7 | 74 | {P1_6 , I2C_3, 1}, |
<> | 144:ef7eb2e8f9f7 | 75 | {NC , NC, 0} |
<> | 144:ef7eb2e8f9f7 | 76 | }; |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | static inline int i2c_status(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 79 | return REG(SR2.UINT8[0]); |
<> | 144:ef7eb2e8f9f7 | 80 | } |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | static void i2c_reg_reset(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 83 | /* full reset */ |
<> | 144:ef7eb2e8f9f7 | 84 | REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off |
<> | 144:ef7eb2e8f9f7 | 85 | REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on |
<> | 144:ef7eb2e8f9f7 | 86 | REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack) |
<> | 144:ef7eb2e8f9f7 | 89 | REG(SER.UINT8[0]) = 0x00; // no slave addr enabled |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | /* set frequency */ |
<> | 144:ef7eb2e8f9f7 | 92 | REG(MR1.UINT8[0]) |= obj->i2c.pclk_bit; |
<> | 144:ef7eb2e8f9f7 | 93 | REG(BRL.UINT8[0]) = obj->i2c.width_low; |
<> | 144:ef7eb2e8f9f7 | 94 | REG(BRH.UINT8[0]) = obj->i2c.width_hi; |
<> | 144:ef7eb2e8f9f7 | 95 | |
<> | 144:ef7eb2e8f9f7 | 96 | REG(MR2.UINT8[0]) = 0x07; |
<> | 144:ef7eb2e8f9f7 | 97 | REG(MR3.UINT8[0]) = 0x00; |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT |
<> | 144:ef7eb2e8f9f7 | 100 | REG(IER.UINT8[0]) = 0x00; // no interrupt |
<> | 144:ef7eb2e8f9f7 | 101 | |
<> | 144:ef7eb2e8f9f7 | 102 | REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset |
<> | 144:ef7eb2e8f9f7 | 103 | } |
<> | 144:ef7eb2e8f9f7 | 104 | |
<> | 144:ef7eb2e8f9f7 | 105 | static inline int i2c_wait_RDRF(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 106 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
<> | 144:ef7eb2e8f9f7 | 109 | while ((i2c_status(obj) & SR2_RDRF) == 0) { |
<> | 144:ef7eb2e8f9f7 | 110 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 111 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 112 | return -1; |
<> | 144:ef7eb2e8f9f7 | 113 | } |
<> | 144:ef7eb2e8f9f7 | 114 | } |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | return 0; |
<> | 144:ef7eb2e8f9f7 | 117 | } |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | static int i2c_wait_TDRE(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 120 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
<> | 144:ef7eb2e8f9f7 | 123 | while ((i2c_status(obj) & SR2_TDRE) == 0) { |
<> | 144:ef7eb2e8f9f7 | 124 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 125 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 126 | return -1; |
<> | 144:ef7eb2e8f9f7 | 127 | } |
<> | 144:ef7eb2e8f9f7 | 128 | } |
<> | 144:ef7eb2e8f9f7 | 129 | |
<> | 144:ef7eb2e8f9f7 | 130 | return 0; |
<> | 144:ef7eb2e8f9f7 | 131 | } |
<> | 144:ef7eb2e8f9f7 | 132 | |
<> | 144:ef7eb2e8f9f7 | 133 | static int i2c_wait_TEND(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 134 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
<> | 144:ef7eb2e8f9f7 | 137 | while ((i2c_status(obj) & SR2_TEND) == 0) { |
<> | 144:ef7eb2e8f9f7 | 138 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 139 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 140 | return -1; |
<> | 144:ef7eb2e8f9f7 | 141 | } |
<> | 144:ef7eb2e8f9f7 | 142 | } |
<> | 144:ef7eb2e8f9f7 | 143 | |
<> | 144:ef7eb2e8f9f7 | 144 | return 0; |
<> | 144:ef7eb2e8f9f7 | 145 | } |
<> | 144:ef7eb2e8f9f7 | 146 | |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | static int i2c_wait_START(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 149 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 150 | |
<> | 144:ef7eb2e8f9f7 | 151 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
<> | 144:ef7eb2e8f9f7 | 152 | while ((i2c_status(obj) & SR2_START) == 0) { |
<> | 144:ef7eb2e8f9f7 | 153 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 154 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 155 | return -1; |
<> | 144:ef7eb2e8f9f7 | 156 | } |
<> | 144:ef7eb2e8f9f7 | 157 | } |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | return 0; |
<> | 144:ef7eb2e8f9f7 | 160 | } |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | static int i2c_wait_STOP(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 163 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
<> | 144:ef7eb2e8f9f7 | 166 | while ((i2c_status(obj) & SR2_STOP) == 0) { |
<> | 144:ef7eb2e8f9f7 | 167 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 168 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 169 | return -1; |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | } |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | return 0; |
<> | 144:ef7eb2e8f9f7 | 174 | } |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | static int i2c_set_STOP(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 177 | /* SR2.STOP = 0 */ |
<> | 144:ef7eb2e8f9f7 | 178 | REG(SR2.UINT32) &= ~SR2_STOP; |
<> | 144:ef7eb2e8f9f7 | 179 | /* Stop condition */ |
<> | 144:ef7eb2e8f9f7 | 180 | REG(CR2.UINT32) |= CR2_SP; |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | return 0; |
<> | 144:ef7eb2e8f9f7 | 183 | } |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 186 | /* SR2.NACKF = 0 */ |
<> | 144:ef7eb2e8f9f7 | 187 | REG(SR2.UINT32) &= ~SR2_NACKF; |
<> | 144:ef7eb2e8f9f7 | 188 | /* SR2.STOP = 0 */ |
<> | 144:ef7eb2e8f9f7 | 189 | REG(SR2.UINT32) &= ~SR2_STOP; |
<> | 144:ef7eb2e8f9f7 | 190 | } |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | static void i2c_set_MR3_NACK(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 193 | /* send a NOT ACK */ |
<> | 144:ef7eb2e8f9f7 | 194 | REG(MR3.UINT32) |= MR3_ACKWP; |
<> | 144:ef7eb2e8f9f7 | 195 | REG(MR3.UINT32) |= MR3_ACKBT; |
<> | 144:ef7eb2e8f9f7 | 196 | REG(MR3.UINT32) &= ~MR3_ACKWP; |
<> | 144:ef7eb2e8f9f7 | 197 | } |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | static void i2c_set_MR3_ACK(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 200 | /* send a ACK */ |
<> | 144:ef7eb2e8f9f7 | 201 | REG(MR3.UINT32) |= MR3_ACKWP; |
<> | 144:ef7eb2e8f9f7 | 202 | REG(MR3.UINT32) &= ~MR3_ACKBT; |
<> | 144:ef7eb2e8f9f7 | 203 | REG(MR3.UINT32) &= ~MR3_ACKWP; |
<> | 144:ef7eb2e8f9f7 | 204 | } |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | static inline void i2c_power_enable(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 207 | volatile uint8_t dummy; |
<> | 144:ef7eb2e8f9f7 | 208 | switch ((int)obj->i2c.i2c) { |
<> | 144:ef7eb2e8f9f7 | 209 | case I2C_0: |
<> | 144:ef7eb2e8f9f7 | 210 | CPGSTBCR9 &= ~(0x80); |
<> | 144:ef7eb2e8f9f7 | 211 | break; |
<> | 144:ef7eb2e8f9f7 | 212 | case I2C_1: |
<> | 144:ef7eb2e8f9f7 | 213 | CPGSTBCR9 &= ~(0x40); |
<> | 144:ef7eb2e8f9f7 | 214 | break; |
<> | 144:ef7eb2e8f9f7 | 215 | case I2C_2: |
<> | 144:ef7eb2e8f9f7 | 216 | CPGSTBCR9 &= ~(0x20); |
<> | 144:ef7eb2e8f9f7 | 217 | break; |
<> | 144:ef7eb2e8f9f7 | 218 | case I2C_3: |
<> | 144:ef7eb2e8f9f7 | 219 | CPGSTBCR9 &= ~(0x10); |
<> | 144:ef7eb2e8f9f7 | 220 | break; |
<> | 144:ef7eb2e8f9f7 | 221 | } |
<> | 144:ef7eb2e8f9f7 | 222 | dummy = CPGSTBCR9; |
<> | 144:ef7eb2e8f9f7 | 223 | } |
<> | 144:ef7eb2e8f9f7 | 224 | |
<> | 144:ef7eb2e8f9f7 | 225 | void i2c_init(i2c_t *obj, PinName sda, PinName scl) { |
<> | 144:ef7eb2e8f9f7 | 226 | /* determine the I2C to use */ |
<> | 144:ef7eb2e8f9f7 | 227 | I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); |
<> | 144:ef7eb2e8f9f7 | 228 | I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); |
<> | 144:ef7eb2e8f9f7 | 229 | obj->i2c.i2c = pinmap_merge(i2c_sda, i2c_scl); |
<> | 144:ef7eb2e8f9f7 | 230 | MBED_ASSERT((int)obj->i2c.i2c != NC); |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | /* enable power */ |
<> | 144:ef7eb2e8f9f7 | 233 | i2c_power_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 234 | |
<> | 144:ef7eb2e8f9f7 | 235 | /* set default frequency at 100k */ |
<> | 144:ef7eb2e8f9f7 | 236 | i2c_frequency(obj, 100000); |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | pinmap_pinout(sda, PinMap_I2C_SDA); |
<> | 144:ef7eb2e8f9f7 | 239 | pinmap_pinout(scl, PinMap_I2C_SCL); |
<> | 144:ef7eb2e8f9f7 | 240 | |
<> | 144:ef7eb2e8f9f7 | 241 | obj->i2c.last_stop_flag = 1; |
<> | 144:ef7eb2e8f9f7 | 242 | } |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | inline int i2c_start(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 245 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | while ((REG(CR2.UINT32) & CR2_BBSY) != 0) { |
<> | 144:ef7eb2e8f9f7 | 248 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 249 | if (timeout >= obj->i2c.bbsy_wait_cnt) { |
<> | 144:ef7eb2e8f9f7 | 250 | break; |
<> | 144:ef7eb2e8f9f7 | 251 | } |
<> | 144:ef7eb2e8f9f7 | 252 | } |
<> | 144:ef7eb2e8f9f7 | 253 | /* Start Condition */ |
<> | 144:ef7eb2e8f9f7 | 254 | REG(CR2.UINT8[0]) |= CR2_ST; |
<> | 144:ef7eb2e8f9f7 | 255 | |
<> | 144:ef7eb2e8f9f7 | 256 | return 0; |
<> | 144:ef7eb2e8f9f7 | 257 | } |
<> | 144:ef7eb2e8f9f7 | 258 | |
<> | 144:ef7eb2e8f9f7 | 259 | static inline int i2c_restart(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 260 | /* SR2.START = 0 */ |
<> | 144:ef7eb2e8f9f7 | 261 | REG(SR2.UINT32) &= ~SR2_START; |
<> | 144:ef7eb2e8f9f7 | 262 | /* ReStart condition */ |
<> | 144:ef7eb2e8f9f7 | 263 | REG(CR2.UINT32) |= CR2_RS; |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | return 0; |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | inline int i2c_stop(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 269 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 270 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 271 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 272 | |
<> | 144:ef7eb2e8f9f7 | 273 | return 0; |
<> | 144:ef7eb2e8f9f7 | 274 | } |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | static void i2c_set_err_noslave(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 277 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 278 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 279 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 280 | obj->i2c.last_stop_flag = 1; |
<> | 144:ef7eb2e8f9f7 | 281 | } |
<> | 144:ef7eb2e8f9f7 | 282 | |
<> | 144:ef7eb2e8f9f7 | 283 | static inline int i2c_do_write(i2c_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 284 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
<> | 144:ef7eb2e8f9f7 | 287 | while ((i2c_status(obj) & SR2_TDRE) == 0) { |
<> | 144:ef7eb2e8f9f7 | 288 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 289 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 290 | return -1; |
<> | 144:ef7eb2e8f9f7 | 291 | } |
<> | 144:ef7eb2e8f9f7 | 292 | } |
<> | 144:ef7eb2e8f9f7 | 293 | /* write the data */ |
<> | 144:ef7eb2e8f9f7 | 294 | REG(DRT.UINT32) = value; |
<> | 144:ef7eb2e8f9f7 | 295 | |
<> | 144:ef7eb2e8f9f7 | 296 | return 0; |
<> | 144:ef7eb2e8f9f7 | 297 | } |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | static inline int i2c_read_address_write(i2c_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 300 | int status; |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | status = i2c_wait_TDRE(obj); |
<> | 144:ef7eb2e8f9f7 | 303 | if (status == 0) { |
<> | 144:ef7eb2e8f9f7 | 304 | /* write the data */ |
<> | 144:ef7eb2e8f9f7 | 305 | REG(DRT.UINT32) = value; |
<> | 144:ef7eb2e8f9f7 | 306 | } |
<> | 144:ef7eb2e8f9f7 | 307 | |
<> | 144:ef7eb2e8f9f7 | 308 | return status; |
<> | 144:ef7eb2e8f9f7 | 309 | |
<> | 144:ef7eb2e8f9f7 | 310 | } |
<> | 144:ef7eb2e8f9f7 | 311 | |
<> | 144:ef7eb2e8f9f7 | 312 | static inline int i2c_do_read(i2c_t *obj, int last) { |
<> | 144:ef7eb2e8f9f7 | 313 | if (last == 2) { |
<> | 144:ef7eb2e8f9f7 | 314 | /* this time is befor last byte read */ |
<> | 144:ef7eb2e8f9f7 | 315 | /* Set MR3 WAIT bit is 1 */; |
<> | 144:ef7eb2e8f9f7 | 316 | REG(MR3.UINT32) |= MR3_WAIT; |
<> | 144:ef7eb2e8f9f7 | 317 | } else if (last == 1) { |
<> | 144:ef7eb2e8f9f7 | 318 | i2c_set_MR3_NACK(obj); |
<> | 144:ef7eb2e8f9f7 | 319 | } else { |
<> | 144:ef7eb2e8f9f7 | 320 | i2c_set_MR3_ACK(obj); |
<> | 144:ef7eb2e8f9f7 | 321 | } |
<> | 144:ef7eb2e8f9f7 | 322 | |
<> | 144:ef7eb2e8f9f7 | 323 | /* return the data */ |
<> | 144:ef7eb2e8f9f7 | 324 | return (REG(DRR.UINT32) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 325 | } |
<> | 144:ef7eb2e8f9f7 | 326 | |
<> | 144:ef7eb2e8f9f7 | 327 | void i2c_frequency(i2c_t *obj, int hz) { |
<> | 144:ef7eb2e8f9f7 | 328 | float64_t pclk_val; |
<> | 144:ef7eb2e8f9f7 | 329 | float64_t wait_utime; |
<> | 144:ef7eb2e8f9f7 | 330 | volatile float64_t bps; |
<> | 144:ef7eb2e8f9f7 | 331 | volatile float64_t L_time; /* H Width period */ |
<> | 144:ef7eb2e8f9f7 | 332 | volatile float64_t H_time; /* L Width period */ |
<> | 144:ef7eb2e8f9f7 | 333 | uint32_t tmp_L_width; |
<> | 144:ef7eb2e8f9f7 | 334 | uint32_t tmp_H_width; |
<> | 144:ef7eb2e8f9f7 | 335 | uint32_t remainder; |
<> | 144:ef7eb2e8f9f7 | 336 | uint32_t wk_cks = 0; |
<> | 144:ef7eb2e8f9f7 | 337 | |
<> | 144:ef7eb2e8f9f7 | 338 | /* set PCLK */ |
<> | 144:ef7eb2e8f9f7 | 339 | if (false == RZ_A1_IsClockMode0()) { |
<> | 144:ef7eb2e8f9f7 | 340 | pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK; |
<> | 144:ef7eb2e8f9f7 | 341 | } else { |
<> | 144:ef7eb2e8f9f7 | 342 | pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK; |
<> | 144:ef7eb2e8f9f7 | 343 | } |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | /* Min 10kHz, Max 400kHz */ |
<> | 144:ef7eb2e8f9f7 | 346 | if (hz < 10000) { |
<> | 144:ef7eb2e8f9f7 | 347 | bps = 10000; |
<> | 144:ef7eb2e8f9f7 | 348 | } else if (hz > 400000) { |
<> | 144:ef7eb2e8f9f7 | 349 | bps = 400000; |
<> | 144:ef7eb2e8f9f7 | 350 | } else { |
<> | 144:ef7eb2e8f9f7 | 351 | bps = (float64_t)hz; |
<> | 144:ef7eb2e8f9f7 | 352 | } |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | /* Calculation L width time */ |
<> | 144:ef7eb2e8f9f7 | 355 | L_time = (1 / (2 * bps)); /* Harf period of frequency */ |
<> | 144:ef7eb2e8f9f7 | 356 | H_time = L_time; |
<> | 144:ef7eb2e8f9f7 | 357 | |
<> | 144:ef7eb2e8f9f7 | 358 | /* Check I2C mode of Speed */ |
<> | 144:ef7eb2e8f9f7 | 359 | if (bps > 100000) { |
<> | 144:ef7eb2e8f9f7 | 360 | /* Fast-mode */ |
<> | 144:ef7eb2e8f9f7 | 361 | L_time -= 102E-9; /* Falling time of SCL clock. */ |
<> | 144:ef7eb2e8f9f7 | 362 | H_time -= 138E-9; /* Rising time of SCL clock. */ |
<> | 144:ef7eb2e8f9f7 | 363 | /* Check L wideth */ |
<> | 144:ef7eb2e8f9f7 | 364 | if (L_time < 1.3E-6) { |
<> | 144:ef7eb2e8f9f7 | 365 | /* Wnen L width less than 1.3us */ |
<> | 144:ef7eb2e8f9f7 | 366 | /* Subtract Rise up and down time for SCL from H/L width */ |
<> | 144:ef7eb2e8f9f7 | 367 | L_time = 1.3E-6; |
<> | 144:ef7eb2e8f9f7 | 368 | H_time = (1 / bps) - L_time - 138E-9 - 102E-9; |
<> | 144:ef7eb2e8f9f7 | 369 | } |
<> | 144:ef7eb2e8f9f7 | 370 | } |
<> | 144:ef7eb2e8f9f7 | 371 | |
<> | 144:ef7eb2e8f9f7 | 372 | tmp_L_width = (uint32_t)(L_time * pclk_val * 10); |
<> | 144:ef7eb2e8f9f7 | 373 | tmp_L_width >>= 1; |
<> | 144:ef7eb2e8f9f7 | 374 | wk_cks++; |
<> | 144:ef7eb2e8f9f7 | 375 | while (tmp_L_width >= 341) { |
<> | 144:ef7eb2e8f9f7 | 376 | tmp_L_width >>= 1; |
<> | 144:ef7eb2e8f9f7 | 377 | wk_cks++; |
<> | 144:ef7eb2e8f9f7 | 378 | } |
<> | 144:ef7eb2e8f9f7 | 379 | remainder = tmp_L_width % 10; |
<> | 144:ef7eb2e8f9f7 | 380 | tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */ |
<> | 144:ef7eb2e8f9f7 | 381 | |
<> | 144:ef7eb2e8f9f7 | 382 | tmp_H_width = (uint32_t)(H_time * pclk_val * 10); |
<> | 144:ef7eb2e8f9f7 | 383 | tmp_H_width >>= wk_cks; |
<> | 144:ef7eb2e8f9f7 | 384 | if (remainder == 0) { |
<> | 144:ef7eb2e8f9f7 | 385 | tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */ |
<> | 144:ef7eb2e8f9f7 | 386 | } else { |
<> | 144:ef7eb2e8f9f7 | 387 | remainder += tmp_H_width % 10; |
<> | 144:ef7eb2e8f9f7 | 388 | tmp_H_width = (tmp_H_width / 10) - 3; |
<> | 144:ef7eb2e8f9f7 | 389 | if (remainder > 10) { |
<> | 144:ef7eb2e8f9f7 | 390 | tmp_H_width += 1; /* fine adjustment */ |
<> | 144:ef7eb2e8f9f7 | 391 | } |
<> | 144:ef7eb2e8f9f7 | 392 | } |
<> | 144:ef7eb2e8f9f7 | 393 | /* timeout of BBSY bit is minimum low width by frequency */ |
<> | 144:ef7eb2e8f9f7 | 394 | /* so timeout calculates "(low width) * 2" by frequency */ |
<> | 144:ef7eb2e8f9f7 | 395 | wait_utime = (L_time * 2) * 1000000; |
<> | 144:ef7eb2e8f9f7 | 396 | /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */ |
<> | 144:ef7eb2e8f9f7 | 397 | if (wait_utime <= 0.3) { |
<> | 144:ef7eb2e8f9f7 | 398 | obj->i2c.bbsy_wait_cnt = 1; |
<> | 144:ef7eb2e8f9f7 | 399 | } else { |
<> | 144:ef7eb2e8f9f7 | 400 | obj->i2c.bbsy_wait_cnt = (int)(wait_utime / 0.3); |
<> | 144:ef7eb2e8f9f7 | 401 | } |
<> | 144:ef7eb2e8f9f7 | 402 | |
<> | 144:ef7eb2e8f9f7 | 403 | |
<> | 144:ef7eb2e8f9f7 | 404 | /* I2C Rate */ |
<> | 144:ef7eb2e8f9f7 | 405 | obj->i2c.pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ |
<> | 144:ef7eb2e8f9f7 | 406 | obj->i2c.width_low = (uint8_t)(tmp_L_width | 0x000000E0); |
<> | 144:ef7eb2e8f9f7 | 407 | obj->i2c.width_hi = (uint8_t)(tmp_H_width | 0x000000E0); |
<> | 144:ef7eb2e8f9f7 | 408 | |
<> | 144:ef7eb2e8f9f7 | 409 | /* full reset */ |
<> | 144:ef7eb2e8f9f7 | 410 | i2c_reg_reset(obj); |
<> | 144:ef7eb2e8f9f7 | 411 | } |
<> | 144:ef7eb2e8f9f7 | 412 | |
<> | 144:ef7eb2e8f9f7 | 413 | int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { |
<> | 144:ef7eb2e8f9f7 | 414 | int count = 0; |
<> | 144:ef7eb2e8f9f7 | 415 | int status; |
<> | 144:ef7eb2e8f9f7 | 416 | int value; |
<> | 144:ef7eb2e8f9f7 | 417 | volatile uint32_t work_reg = 0; |
<> | 144:ef7eb2e8f9f7 | 418 | |
<> | 144:ef7eb2e8f9f7 | 419 | i2c_set_MR3_ACK(obj); |
<> | 144:ef7eb2e8f9f7 | 420 | /* There is a STOP condition for last processing */ |
<> | 144:ef7eb2e8f9f7 | 421 | if (obj->i2c.last_stop_flag != 0) { |
<> | 144:ef7eb2e8f9f7 | 422 | status = i2c_start(obj); |
<> | 144:ef7eb2e8f9f7 | 423 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 424 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 425 | return I2C_ERROR_BUS_BUSY; |
<> | 144:ef7eb2e8f9f7 | 426 | } |
<> | 144:ef7eb2e8f9f7 | 427 | } |
<> | 144:ef7eb2e8f9f7 | 428 | obj->i2c.last_stop_flag = stop; |
<> | 144:ef7eb2e8f9f7 | 429 | /* Send Slave address */ |
<> | 144:ef7eb2e8f9f7 | 430 | status = i2c_read_address_write(obj, (address | 0x01)); |
<> | 144:ef7eb2e8f9f7 | 431 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 432 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 433 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 434 | } |
<> | 144:ef7eb2e8f9f7 | 435 | /* wait RDRF */ |
<> | 144:ef7eb2e8f9f7 | 436 | status = i2c_wait_RDRF(obj); |
<> | 144:ef7eb2e8f9f7 | 437 | /* check ACK/NACK */ |
<> | 144:ef7eb2e8f9f7 | 438 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { |
<> | 144:ef7eb2e8f9f7 | 439 | /* Slave sends NACK */ |
<> | 144:ef7eb2e8f9f7 | 440 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 441 | /* dummy read */ |
<> | 144:ef7eb2e8f9f7 | 442 | value = REG(DRR.UINT32); |
<> | 144:ef7eb2e8f9f7 | 443 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 444 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 445 | obj->i2c.last_stop_flag = 1; |
<> | 144:ef7eb2e8f9f7 | 446 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 447 | } |
<> | 156:95d6b41a828b | 448 | if (length != 0) { |
<> | 156:95d6b41a828b | 449 | /* Read in all except last byte */ |
<> | 156:95d6b41a828b | 450 | if (length > 2) { |
<> | 156:95d6b41a828b | 451 | /* dummy read */ |
<> | 156:95d6b41a828b | 452 | value = REG(DRR.UINT32); |
<> | 156:95d6b41a828b | 453 | for (count = 0; count < (length - 1); count++) { |
<> | 156:95d6b41a828b | 454 | /* wait for it to arrive */ |
<> | 156:95d6b41a828b | 455 | status = i2c_wait_RDRF(obj); |
<> | 156:95d6b41a828b | 456 | if (status != 0) { |
<> | 156:95d6b41a828b | 457 | i2c_set_err_noslave(obj); |
<> | 156:95d6b41a828b | 458 | return I2C_ERROR_NO_SLAVE; |
<> | 156:95d6b41a828b | 459 | } |
<> | 156:95d6b41a828b | 460 | /* Recieve the data */ |
<> | 156:95d6b41a828b | 461 | if (count == (length - 2)) { |
<> | 156:95d6b41a828b | 462 | value = i2c_do_read(obj, 1); |
<> | 156:95d6b41a828b | 463 | } else if ((length >= 3) && (count == (length - 3))) { |
<> | 156:95d6b41a828b | 464 | value = i2c_do_read(obj, 2); |
<> | 156:95d6b41a828b | 465 | } else { |
<> | 156:95d6b41a828b | 466 | value = i2c_do_read(obj, 0); |
<> | 156:95d6b41a828b | 467 | } |
<> | 156:95d6b41a828b | 468 | data[count] = (char)value; |
<> | 156:95d6b41a828b | 469 | } |
<> | 156:95d6b41a828b | 470 | } else if (length == 2) { |
<> | 156:95d6b41a828b | 471 | /* Set MR3 WAIT bit is 1 */ |
<> | 156:95d6b41a828b | 472 | REG(MR3.UINT32) |= MR3_WAIT; |
<> | 156:95d6b41a828b | 473 | /* dummy read */ |
<> | 156:95d6b41a828b | 474 | value = REG(DRR.UINT32); |
<> | 144:ef7eb2e8f9f7 | 475 | /* wait for it to arrive */ |
<> | 144:ef7eb2e8f9f7 | 476 | status = i2c_wait_RDRF(obj); |
<> | 144:ef7eb2e8f9f7 | 477 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 478 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 479 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 480 | } |
<> | 156:95d6b41a828b | 481 | i2c_set_MR3_NACK(obj); |
<> | 156:95d6b41a828b | 482 | data[count] = (char)REG(DRR.UINT32); |
<> | 156:95d6b41a828b | 483 | count++; |
<> | 156:95d6b41a828b | 484 | } else { |
<> | 156:95d6b41a828b | 485 | /* length == 1 */ |
<> | 156:95d6b41a828b | 486 | /* Set MR3 WAIT bit is 1 */; |
<> | 156:95d6b41a828b | 487 | REG(MR3.UINT32) |= MR3_WAIT; |
<> | 156:95d6b41a828b | 488 | i2c_set_MR3_NACK(obj); |
<> | 156:95d6b41a828b | 489 | /* dummy read */ |
<> | 156:95d6b41a828b | 490 | value = REG(DRR.UINT32); |
<> | 144:ef7eb2e8f9f7 | 491 | } |
<> | 144:ef7eb2e8f9f7 | 492 | /* wait for it to arrive */ |
<> | 144:ef7eb2e8f9f7 | 493 | status = i2c_wait_RDRF(obj); |
<> | 144:ef7eb2e8f9f7 | 494 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 495 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 496 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 497 | } |
<> | 156:95d6b41a828b | 498 | |
<> | 156:95d6b41a828b | 499 | /* If not repeated start, send stop. */ |
<> | 156:95d6b41a828b | 500 | if (stop) { |
<> | 156:95d6b41a828b | 501 | (void)i2c_set_STOP(obj); |
<> | 156:95d6b41a828b | 502 | /* RIICnDRR read */ |
<> | 156:95d6b41a828b | 503 | value = (REG(DRR.UINT32) & 0xFF); |
<> | 156:95d6b41a828b | 504 | data[count] = (char)value; |
<> | 156:95d6b41a828b | 505 | /* RIICnMR3.WAIT = 0 */ |
<> | 156:95d6b41a828b | 506 | REG(MR3.UINT32) &= ~MR3_WAIT; |
<> | 156:95d6b41a828b | 507 | (void)i2c_wait_STOP(obj); |
<> | 156:95d6b41a828b | 508 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 156:95d6b41a828b | 509 | } else { |
<> | 156:95d6b41a828b | 510 | (void)i2c_restart(obj); |
<> | 156:95d6b41a828b | 511 | /* RIICnDRR read */ |
<> | 156:95d6b41a828b | 512 | value = (REG(DRR.UINT32) & 0xFF); |
<> | 156:95d6b41a828b | 513 | data[count] = (char)value; |
<> | 156:95d6b41a828b | 514 | /* RIICnMR3.WAIT = 0 */ |
<> | 156:95d6b41a828b | 515 | REG(MR3.UINT32) &= ~MR3_WAIT; |
<> | 156:95d6b41a828b | 516 | (void)i2c_wait_START(obj); |
<> | 156:95d6b41a828b | 517 | /* SR2.START = 0 */ |
<> | 156:95d6b41a828b | 518 | REG(SR2.UINT32) &= ~SR2_START; |
<> | 156:95d6b41a828b | 519 | } |
<> | 144:ef7eb2e8f9f7 | 520 | } else { |
<> | 156:95d6b41a828b | 521 | /* If not repeated start, send stop. */ |
<> | 156:95d6b41a828b | 522 | if (stop) { |
<> | 156:95d6b41a828b | 523 | (void)i2c_set_STOP(obj); |
<> | 156:95d6b41a828b | 524 | (void)i2c_wait_STOP(obj); |
<> | 156:95d6b41a828b | 525 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 156:95d6b41a828b | 526 | } else { |
<> | 156:95d6b41a828b | 527 | (void)i2c_restart(obj); |
<> | 156:95d6b41a828b | 528 | (void)i2c_wait_START(obj); |
<> | 156:95d6b41a828b | 529 | /* SR2.START = 0 */ |
<> | 156:95d6b41a828b | 530 | REG(SR2.UINT32) &= ~SR2_START; |
<> | 156:95d6b41a828b | 531 | } |
<> | 144:ef7eb2e8f9f7 | 532 | } |
<> | 144:ef7eb2e8f9f7 | 533 | |
<> | 144:ef7eb2e8f9f7 | 534 | return length; |
<> | 144:ef7eb2e8f9f7 | 535 | } |
<> | 144:ef7eb2e8f9f7 | 536 | |
<> | 144:ef7eb2e8f9f7 | 537 | int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { |
<> | 144:ef7eb2e8f9f7 | 538 | int cnt; |
<> | 144:ef7eb2e8f9f7 | 539 | int status; |
<> | 144:ef7eb2e8f9f7 | 540 | |
<> | 144:ef7eb2e8f9f7 | 541 | /* There is a STOP condition for last processing */ |
<> | 144:ef7eb2e8f9f7 | 542 | if (obj->i2c.last_stop_flag != 0) { |
<> | 144:ef7eb2e8f9f7 | 543 | status = i2c_start(obj); |
<> | 144:ef7eb2e8f9f7 | 544 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 545 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 546 | return I2C_ERROR_BUS_BUSY; |
<> | 144:ef7eb2e8f9f7 | 547 | } |
<> | 144:ef7eb2e8f9f7 | 548 | } |
<> | 144:ef7eb2e8f9f7 | 549 | obj->i2c.last_stop_flag = stop; |
<> | 144:ef7eb2e8f9f7 | 550 | /* Send Slave address */ |
<> | 144:ef7eb2e8f9f7 | 551 | status = i2c_do_write(obj, address); |
<> | 144:ef7eb2e8f9f7 | 552 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 553 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 554 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 555 | } |
<> | 144:ef7eb2e8f9f7 | 556 | /* Wait send end */ |
<> | 144:ef7eb2e8f9f7 | 557 | status = i2c_wait_TEND(obj); |
<> | 144:ef7eb2e8f9f7 | 558 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { |
<> | 144:ef7eb2e8f9f7 | 559 | /* Slave sends NACK */ |
<> | 144:ef7eb2e8f9f7 | 560 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 561 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 562 | } |
<> | 144:ef7eb2e8f9f7 | 563 | /* Send Write data */ |
<> | 144:ef7eb2e8f9f7 | 564 | for (cnt=0; cnt<length; cnt++) { |
<> | 144:ef7eb2e8f9f7 | 565 | status = i2c_do_write(obj, data[cnt]); |
<> | 144:ef7eb2e8f9f7 | 566 | if(status != 0) { |
<> | 144:ef7eb2e8f9f7 | 567 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 568 | return cnt; |
<> | 144:ef7eb2e8f9f7 | 569 | } else { |
<> | 144:ef7eb2e8f9f7 | 570 | /* Wait send end */ |
<> | 144:ef7eb2e8f9f7 | 571 | status = i2c_wait_TEND(obj); |
<> | 144:ef7eb2e8f9f7 | 572 | if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) { |
<> | 144:ef7eb2e8f9f7 | 573 | /* Slave sends NACK */ |
<> | 144:ef7eb2e8f9f7 | 574 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 575 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 576 | } |
<> | 144:ef7eb2e8f9f7 | 577 | } |
<> | 144:ef7eb2e8f9f7 | 578 | } |
<> | 144:ef7eb2e8f9f7 | 579 | /* If not repeated start, send stop. */ |
<> | 144:ef7eb2e8f9f7 | 580 | if (stop) { |
<> | 144:ef7eb2e8f9f7 | 581 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 582 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 583 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 584 | } else { |
<> | 144:ef7eb2e8f9f7 | 585 | (void)i2c_restart(obj); |
<> | 144:ef7eb2e8f9f7 | 586 | (void)i2c_wait_START(obj); |
<> | 144:ef7eb2e8f9f7 | 587 | /* SR2.START = 0 */ |
<> | 144:ef7eb2e8f9f7 | 588 | REG(SR2.UINT32) &= ~SR2_START; |
<> | 144:ef7eb2e8f9f7 | 589 | |
<> | 144:ef7eb2e8f9f7 | 590 | } |
<> | 144:ef7eb2e8f9f7 | 591 | |
<> | 144:ef7eb2e8f9f7 | 592 | return length; |
<> | 144:ef7eb2e8f9f7 | 593 | } |
<> | 144:ef7eb2e8f9f7 | 594 | |
<> | 144:ef7eb2e8f9f7 | 595 | void i2c_reset(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 596 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 597 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 598 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 599 | } |
<> | 144:ef7eb2e8f9f7 | 600 | |
<> | 144:ef7eb2e8f9f7 | 601 | int i2c_byte_read(i2c_t *obj, int last) { |
<> | 144:ef7eb2e8f9f7 | 602 | int status; |
<> | 144:ef7eb2e8f9f7 | 603 | int data; |
<> | 144:ef7eb2e8f9f7 | 604 | |
<> | 144:ef7eb2e8f9f7 | 605 | data = i2c_do_read(obj, last); |
<> | 144:ef7eb2e8f9f7 | 606 | /* wait for it to arrive */ |
<> | 144:ef7eb2e8f9f7 | 607 | status = i2c_wait_RDRF(obj); |
<> | 144:ef7eb2e8f9f7 | 608 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 609 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 610 | return I2C_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 611 | } |
<> | 144:ef7eb2e8f9f7 | 612 | |
<> | 144:ef7eb2e8f9f7 | 613 | return data; |
<> | 144:ef7eb2e8f9f7 | 614 | } |
<> | 144:ef7eb2e8f9f7 | 615 | |
<> | 144:ef7eb2e8f9f7 | 616 | int i2c_byte_write(i2c_t *obj, int data) { |
<> | 144:ef7eb2e8f9f7 | 617 | int ack = 0; |
<> | 144:ef7eb2e8f9f7 | 618 | int status; |
<> | 144:ef7eb2e8f9f7 | 619 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 620 | |
<> | 144:ef7eb2e8f9f7 | 621 | status = i2c_do_write(obj, (data & 0xFF)); |
<> | 144:ef7eb2e8f9f7 | 622 | if (status != 0) { |
<> | 144:ef7eb2e8f9f7 | 623 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 624 | } else { |
<> | 144:ef7eb2e8f9f7 | 625 | while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) { |
<> | 144:ef7eb2e8f9f7 | 626 | timeout++; |
<> | 144:ef7eb2e8f9f7 | 627 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 628 | return ack; |
<> | 144:ef7eb2e8f9f7 | 629 | } |
<> | 144:ef7eb2e8f9f7 | 630 | } |
<> | 144:ef7eb2e8f9f7 | 631 | /* check ACK/NACK */ |
<> | 144:ef7eb2e8f9f7 | 632 | if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { |
<> | 144:ef7eb2e8f9f7 | 633 | /* NACK */ |
<> | 144:ef7eb2e8f9f7 | 634 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 635 | } else { |
<> | 144:ef7eb2e8f9f7 | 636 | ack = 1; |
<> | 144:ef7eb2e8f9f7 | 637 | } |
<> | 144:ef7eb2e8f9f7 | 638 | } |
<> | 144:ef7eb2e8f9f7 | 639 | |
<> | 144:ef7eb2e8f9f7 | 640 | return ack; |
<> | 144:ef7eb2e8f9f7 | 641 | } |
<> | 144:ef7eb2e8f9f7 | 642 | |
<> | 144:ef7eb2e8f9f7 | 643 | void i2c_slave_mode(i2c_t *obj, int enable_slave) { |
<> | 144:ef7eb2e8f9f7 | 644 | if (enable_slave != 0) { |
<> | 144:ef7eb2e8f9f7 | 645 | REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled |
<> | 144:ef7eb2e8f9f7 | 646 | } else { |
<> | 144:ef7eb2e8f9f7 | 647 | REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled |
<> | 144:ef7eb2e8f9f7 | 648 | } |
<> | 144:ef7eb2e8f9f7 | 649 | } |
<> | 144:ef7eb2e8f9f7 | 650 | |
<> | 144:ef7eb2e8f9f7 | 651 | int i2c_slave_receive(i2c_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 652 | int status; |
<> | 144:ef7eb2e8f9f7 | 653 | int retval; |
<> | 144:ef7eb2e8f9f7 | 654 | |
<> | 144:ef7eb2e8f9f7 | 655 | status = (REG(SR1.UINT8[0]) & SR1_AAS0); |
<> | 144:ef7eb2e8f9f7 | 656 | status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4; |
<> | 144:ef7eb2e8f9f7 | 657 | |
<> | 144:ef7eb2e8f9f7 | 658 | switch(status) { |
<> | 144:ef7eb2e8f9f7 | 659 | case 0x01: |
<> | 144:ef7eb2e8f9f7 | 660 | /* the master is writing to this slave */ |
<> | 144:ef7eb2e8f9f7 | 661 | retval = 3; |
<> | 144:ef7eb2e8f9f7 | 662 | break; |
<> | 144:ef7eb2e8f9f7 | 663 | case 0x02: |
<> | 144:ef7eb2e8f9f7 | 664 | /* the master is writing to all slave */ |
<> | 144:ef7eb2e8f9f7 | 665 | retval = 2; |
<> | 144:ef7eb2e8f9f7 | 666 | break; |
<> | 144:ef7eb2e8f9f7 | 667 | case 0x03: |
<> | 144:ef7eb2e8f9f7 | 668 | /* the master has requested a read from this slave */ |
<> | 144:ef7eb2e8f9f7 | 669 | retval = 1; |
<> | 144:ef7eb2e8f9f7 | 670 | break; |
<> | 144:ef7eb2e8f9f7 | 671 | default : |
<> | 144:ef7eb2e8f9f7 | 672 | /* no data */ |
<> | 144:ef7eb2e8f9f7 | 673 | retval = 0; |
<> | 144:ef7eb2e8f9f7 | 674 | break; |
<> | 144:ef7eb2e8f9f7 | 675 | } |
<> | 144:ef7eb2e8f9f7 | 676 | |
<> | 144:ef7eb2e8f9f7 | 677 | return retval; |
<> | 144:ef7eb2e8f9f7 | 678 | } |
<> | 144:ef7eb2e8f9f7 | 679 | |
<> | 144:ef7eb2e8f9f7 | 680 | int i2c_slave_read(i2c_t *obj, char *data, int length) { |
<> | 144:ef7eb2e8f9f7 | 681 | int timeout = 0; |
<> | 144:ef7eb2e8f9f7 | 682 | int count; |
<> | 144:ef7eb2e8f9f7 | 683 | int break_flg = 0; |
<> | 144:ef7eb2e8f9f7 | 684 | |
<> | 144:ef7eb2e8f9f7 | 685 | if(length <= 0) { |
<> | 144:ef7eb2e8f9f7 | 686 | return 0; |
<> | 144:ef7eb2e8f9f7 | 687 | } |
<> | 144:ef7eb2e8f9f7 | 688 | for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { |
<> | 144:ef7eb2e8f9f7 | 689 | /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ |
<> | 144:ef7eb2e8f9f7 | 690 | while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) { |
<> | 144:ef7eb2e8f9f7 | 691 | if ((i2c_status(obj) & SR2_STOP) != 0) { |
<> | 144:ef7eb2e8f9f7 | 692 | break_flg = 1; |
<> | 144:ef7eb2e8f9f7 | 693 | break; |
<> | 144:ef7eb2e8f9f7 | 694 | } |
<> | 144:ef7eb2e8f9f7 | 695 | timeout ++; |
<> | 144:ef7eb2e8f9f7 | 696 | if (timeout >= WAIT_TIMEOUT) { |
<> | 144:ef7eb2e8f9f7 | 697 | return -1; |
<> | 144:ef7eb2e8f9f7 | 698 | } |
<> | 144:ef7eb2e8f9f7 | 699 | } |
<> | 144:ef7eb2e8f9f7 | 700 | if (break_flg == 0) { |
<> | 144:ef7eb2e8f9f7 | 701 | if (count == 0) { |
<> | 144:ef7eb2e8f9f7 | 702 | /* dummy read */ |
<> | 144:ef7eb2e8f9f7 | 703 | (void)REG(DRR.UINT32); |
<> | 144:ef7eb2e8f9f7 | 704 | } else { |
<> | 144:ef7eb2e8f9f7 | 705 | data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 706 | } |
<> | 144:ef7eb2e8f9f7 | 707 | } |
<> | 144:ef7eb2e8f9f7 | 708 | } |
<> | 144:ef7eb2e8f9f7 | 709 | if (break_flg == 0) { |
<> | 144:ef7eb2e8f9f7 | 710 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 711 | } else { |
<> | 144:ef7eb2e8f9f7 | 712 | if ((i2c_status(obj) & SR2_RDRF) != 0) { |
<> | 144:ef7eb2e8f9f7 | 713 | if (count <= 1) { |
<> | 144:ef7eb2e8f9f7 | 714 | /* fail safe */ |
<> | 144:ef7eb2e8f9f7 | 715 | /* dummy read */ |
<> | 144:ef7eb2e8f9f7 | 716 | (void)REG(DRR.UINT32); |
<> | 144:ef7eb2e8f9f7 | 717 | } else { |
<> | 144:ef7eb2e8f9f7 | 718 | data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 719 | } |
<> | 144:ef7eb2e8f9f7 | 720 | } |
<> | 144:ef7eb2e8f9f7 | 721 | } |
<> | 144:ef7eb2e8f9f7 | 722 | /* SR2.STOP = 0 */ |
<> | 144:ef7eb2e8f9f7 | 723 | REG(SR2.UINT32) &= ~SR2_STOP; |
<> | 144:ef7eb2e8f9f7 | 724 | |
<> | 144:ef7eb2e8f9f7 | 725 | return (count - 1); |
<> | 144:ef7eb2e8f9f7 | 726 | } |
<> | 144:ef7eb2e8f9f7 | 727 | |
<> | 144:ef7eb2e8f9f7 | 728 | int i2c_slave_write(i2c_t *obj, const char *data, int length) { |
<> | 144:ef7eb2e8f9f7 | 729 | int count = 0; |
<> | 144:ef7eb2e8f9f7 | 730 | int status = 0; |
<> | 144:ef7eb2e8f9f7 | 731 | |
<> | 144:ef7eb2e8f9f7 | 732 | if(length <= 0) { |
<> | 144:ef7eb2e8f9f7 | 733 | return 0; |
<> | 144:ef7eb2e8f9f7 | 734 | } |
<> | 144:ef7eb2e8f9f7 | 735 | |
<> | 144:ef7eb2e8f9f7 | 736 | while ((count < length) && (status == 0)) { |
<> | 144:ef7eb2e8f9f7 | 737 | status = i2c_do_write(obj, data[count]); |
<> | 144:ef7eb2e8f9f7 | 738 | if(status == 0) { |
<> | 144:ef7eb2e8f9f7 | 739 | /* Wait send end */ |
<> | 144:ef7eb2e8f9f7 | 740 | status = i2c_wait_TEND(obj); |
<> | 144:ef7eb2e8f9f7 | 741 | if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) { |
<> | 144:ef7eb2e8f9f7 | 742 | /* NACK */ |
<> | 144:ef7eb2e8f9f7 | 743 | break; |
<> | 144:ef7eb2e8f9f7 | 744 | } |
<> | 144:ef7eb2e8f9f7 | 745 | } |
<> | 144:ef7eb2e8f9f7 | 746 | count++; |
<> | 144:ef7eb2e8f9f7 | 747 | } |
<> | 144:ef7eb2e8f9f7 | 748 | /* dummy read */ |
<> | 144:ef7eb2e8f9f7 | 749 | (void)REG(DRR.UINT32); |
<> | 144:ef7eb2e8f9f7 | 750 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 751 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 752 | |
<> | 144:ef7eb2e8f9f7 | 753 | return count; |
<> | 144:ef7eb2e8f9f7 | 754 | } |
<> | 144:ef7eb2e8f9f7 | 755 | |
<> | 144:ef7eb2e8f9f7 | 756 | void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { |
<> | 144:ef7eb2e8f9f7 | 757 | REG(SAR0.UINT32) = (address & 0xfffffffe); |
<> | 144:ef7eb2e8f9f7 | 758 | } |
<> | 144:ef7eb2e8f9f7 | 759 | |
<> | 144:ef7eb2e8f9f7 | 760 | #if DEVICE_I2C_ASYNCH |
<> | 144:ef7eb2e8f9f7 | 761 | |
<> | 144:ef7eb2e8f9f7 | 762 | #define IRQ_NUM 4 |
<> | 144:ef7eb2e8f9f7 | 763 | #define IRQ_TX 0 |
<> | 144:ef7eb2e8f9f7 | 764 | #define IRQ_RX 1 |
<> | 144:ef7eb2e8f9f7 | 765 | #define IRQ_ERR1 2 |
<> | 144:ef7eb2e8f9f7 | 766 | #define IRQ_ERR2 3 |
<> | 144:ef7eb2e8f9f7 | 767 | |
<> | 144:ef7eb2e8f9f7 | 768 | static void i2c_irqs_set(i2c_t *obj, uint32_t enable); |
<> | 144:ef7eb2e8f9f7 | 769 | |
<> | 144:ef7eb2e8f9f7 | 770 | static void i2c0_tx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 771 | static void i2c1_tx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 772 | static void i2c2_tx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 773 | static void i2c3_tx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 774 | static void i2c0_rx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 775 | static void i2c1_rx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 776 | static void i2c2_rx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 777 | static void i2c3_rx_irq(void); |
<> | 144:ef7eb2e8f9f7 | 778 | static void i2c0_al_irq(void); |
<> | 144:ef7eb2e8f9f7 | 779 | static void i2c1_al_irq(void); |
<> | 144:ef7eb2e8f9f7 | 780 | static void i2c2_al_irq(void); |
<> | 144:ef7eb2e8f9f7 | 781 | static void i2c3_al_irq(void); |
<> | 144:ef7eb2e8f9f7 | 782 | static void i2c0_to_irq(void); |
<> | 144:ef7eb2e8f9f7 | 783 | static void i2c1_to_irq(void); |
<> | 144:ef7eb2e8f9f7 | 784 | static void i2c2_to_irq(void); |
<> | 144:ef7eb2e8f9f7 | 785 | static void i2c3_to_irq(void); |
<> | 144:ef7eb2e8f9f7 | 786 | |
<> | 144:ef7eb2e8f9f7 | 787 | static const IRQn_Type irq_set_tbl[RIIC_COUNT][IRQ_NUM] = { |
<> | 144:ef7eb2e8f9f7 | 788 | {INTIICTEI0_IRQn, INTIICRI0_IRQn, INTIICALI0_IRQn, INTIICTMOI0_IRQn}, |
<> | 144:ef7eb2e8f9f7 | 789 | {INTIICTEI1_IRQn, INTIICRI1_IRQn, INTIICALI1_IRQn, INTIICTMOI1_IRQn}, |
<> | 144:ef7eb2e8f9f7 | 790 | {INTIICTEI2_IRQn, INTIICRI2_IRQn, INTIICALI2_IRQn, INTIICTMOI2_IRQn}, |
<> | 144:ef7eb2e8f9f7 | 791 | {INTIICTEI3_IRQn, INTIICRI3_IRQn, INTIICALI3_IRQn, INTIICTMOI3_IRQn}, |
<> | 144:ef7eb2e8f9f7 | 792 | }; |
<> | 144:ef7eb2e8f9f7 | 793 | |
<> | 144:ef7eb2e8f9f7 | 794 | static const IRQHandler hander_set_tbl[RIIC_COUNT][IRQ_NUM] = { |
<> | 144:ef7eb2e8f9f7 | 795 | {i2c0_tx_irq, i2c0_rx_irq, i2c0_al_irq, i2c0_to_irq}, |
<> | 144:ef7eb2e8f9f7 | 796 | {i2c1_tx_irq, i2c1_rx_irq, i2c1_al_irq, i2c1_to_irq}, |
<> | 144:ef7eb2e8f9f7 | 797 | {i2c2_tx_irq, i2c2_rx_irq, i2c2_al_irq, i2c2_to_irq}, |
<> | 144:ef7eb2e8f9f7 | 798 | {i2c3_tx_irq, i2c3_rx_irq, i2c3_al_irq, i2c3_to_irq}, |
<> | 144:ef7eb2e8f9f7 | 799 | }; |
<> | 144:ef7eb2e8f9f7 | 800 | |
<> | 144:ef7eb2e8f9f7 | 801 | struct i2c_global_data_s { |
<> | 144:ef7eb2e8f9f7 | 802 | i2c_t *async_obj; |
<> | 144:ef7eb2e8f9f7 | 803 | uint32_t async_callback, event, shouldStop, address; |
<> | 144:ef7eb2e8f9f7 | 804 | }; |
<> | 144:ef7eb2e8f9f7 | 805 | |
<> | 144:ef7eb2e8f9f7 | 806 | static struct i2c_global_data_s i2c_data[RIIC_COUNT]; |
<> | 144:ef7eb2e8f9f7 | 807 | |
<> | 144:ef7eb2e8f9f7 | 808 | static void i2c_transfer_finished(i2c_t *obj) |
<> | 144:ef7eb2e8f9f7 | 809 | { |
<> | 144:ef7eb2e8f9f7 | 810 | i2c_irqs_set(obj, 0); |
<> | 144:ef7eb2e8f9f7 | 811 | uint32_t index = obj->i2c.i2c; |
<> | 144:ef7eb2e8f9f7 | 812 | i2c_data[index].event = I2C_EVENT_TRANSFER_COMPLETE; |
<> | 144:ef7eb2e8f9f7 | 813 | i2c_data[index].async_obj = NULL; |
<> | 144:ef7eb2e8f9f7 | 814 | ((void (*)())i2c_data[index].async_callback)(); |
<> | 144:ef7eb2e8f9f7 | 815 | } |
<> | 144:ef7eb2e8f9f7 | 816 | |
<> | 144:ef7eb2e8f9f7 | 817 | static void i2c_tx_irq(IRQn_Type irq_num, uint32_t index) |
<> | 144:ef7eb2e8f9f7 | 818 | { |
<> | 144:ef7eb2e8f9f7 | 819 | i2c_t *obj = i2c_data[index].async_obj; |
<> | 144:ef7eb2e8f9f7 | 820 | if ((REG(SR2.UINT32) & SR2_NACKF)) { |
<> | 144:ef7eb2e8f9f7 | 821 | /* Slave sends NACK */ |
<> | 144:ef7eb2e8f9f7 | 822 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 823 | i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; |
<> | 144:ef7eb2e8f9f7 | 824 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 825 | ((void (*)())i2c_data[index].async_callback)(); |
<> | 144:ef7eb2e8f9f7 | 826 | return; |
<> | 144:ef7eb2e8f9f7 | 827 | } |
<> | 144:ef7eb2e8f9f7 | 828 | if (obj->tx_buff.pos == obj->tx_buff.length) { |
<> | 144:ef7eb2e8f9f7 | 829 | /* All datas have tranferred */ |
<> | 144:ef7eb2e8f9f7 | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | /* Clear TEND */ |
<> | 144:ef7eb2e8f9f7 | 832 | REG(SR2.UINT32) &= ~(SR2_TEND); |
<> | 144:ef7eb2e8f9f7 | 833 | |
<> | 144:ef7eb2e8f9f7 | 834 | /* If not repeated start, send stop. */ |
<> | 144:ef7eb2e8f9f7 | 835 | if (i2c_data[index].shouldStop && obj->rx_buff.length == 0) { |
<> | 144:ef7eb2e8f9f7 | 836 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 837 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 838 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 839 | i2c_transfer_finished(obj); |
<> | 144:ef7eb2e8f9f7 | 840 | } else { |
<> | 144:ef7eb2e8f9f7 | 841 | (void)i2c_restart(obj); |
<> | 144:ef7eb2e8f9f7 | 842 | (void)i2c_wait_START(obj); |
<> | 144:ef7eb2e8f9f7 | 843 | /* SR2.START = 0 */ |
<> | 144:ef7eb2e8f9f7 | 844 | REG(SR2.UINT32) &= ~SR2_START; |
<> | 144:ef7eb2e8f9f7 | 845 | if (obj->rx_buff.length) { |
<> | 144:ef7eb2e8f9f7 | 846 | /* Ready to read */ |
<> | 144:ef7eb2e8f9f7 | 847 | i2c_set_MR3_ACK(obj); |
<> | 144:ef7eb2e8f9f7 | 848 | |
<> | 144:ef7eb2e8f9f7 | 849 | /* Disable INTRIICTEI */ |
<> | 144:ef7eb2e8f9f7 | 850 | REG(IER.UINT8[0]) &= ~(1 << 6); |
<> | 144:ef7eb2e8f9f7 | 851 | |
<> | 144:ef7eb2e8f9f7 | 852 | /* Send Slave address */ |
<> | 144:ef7eb2e8f9f7 | 853 | if (i2c_read_address_write(obj, (i2c_data[index].address | 0x01)) != 0) { |
<> | 144:ef7eb2e8f9f7 | 854 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 855 | i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 856 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 857 | ((void (*)())i2c_data[index].async_callback)(); |
<> | 144:ef7eb2e8f9f7 | 858 | return; |
<> | 144:ef7eb2e8f9f7 | 859 | } |
<> | 144:ef7eb2e8f9f7 | 860 | } else { |
<> | 144:ef7eb2e8f9f7 | 861 | i2c_transfer_finished(obj); |
<> | 144:ef7eb2e8f9f7 | 862 | } |
<> | 144:ef7eb2e8f9f7 | 863 | } |
<> | 144:ef7eb2e8f9f7 | 864 | } else { |
<> | 144:ef7eb2e8f9f7 | 865 | /* Send next 1 byte */ |
<> | 144:ef7eb2e8f9f7 | 866 | if (i2c_do_write(obj, *(uint8_t *)obj->tx_buff.buffer) != 0) { |
<> | 144:ef7eb2e8f9f7 | 867 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 868 | i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 869 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 870 | ((void (*)())i2c_data[index].async_callback)(); |
<> | 144:ef7eb2e8f9f7 | 871 | return; |
<> | 144:ef7eb2e8f9f7 | 872 | } |
<> | 144:ef7eb2e8f9f7 | 873 | obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1; |
<> | 144:ef7eb2e8f9f7 | 874 | ++obj->tx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 875 | } |
<> | 144:ef7eb2e8f9f7 | 876 | } |
<> | 144:ef7eb2e8f9f7 | 877 | |
<> | 144:ef7eb2e8f9f7 | 878 | static void i2c_rx_irq(IRQn_Type irq_num, uint32_t index) |
<> | 144:ef7eb2e8f9f7 | 879 | { |
<> | 144:ef7eb2e8f9f7 | 880 | i2c_t *obj = i2c_data[index].async_obj; |
<> | 144:ef7eb2e8f9f7 | 881 | if (obj->rx_buff.pos == SIZE_MAX) { |
<> | 144:ef7eb2e8f9f7 | 882 | if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { |
<> | 144:ef7eb2e8f9f7 | 883 | /* Slave sends NACK */ |
<> | 144:ef7eb2e8f9f7 | 884 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 885 | /* dummy read */ |
<> | 144:ef7eb2e8f9f7 | 886 | if (REG(DRR.UINT32)) {} |
<> | 144:ef7eb2e8f9f7 | 887 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 888 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 889 | obj->i2c.last_stop_flag = 1; |
<> | 144:ef7eb2e8f9f7 | 890 | |
<> | 144:ef7eb2e8f9f7 | 891 | i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; |
<> | 144:ef7eb2e8f9f7 | 892 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 893 | ((void (*)())i2c_data[index].async_callback)(); |
<> | 144:ef7eb2e8f9f7 | 894 | return; |
<> | 144:ef7eb2e8f9f7 | 895 | } |
<> | 144:ef7eb2e8f9f7 | 896 | if (obj->rx_buff.length == 1) { |
<> | 144:ef7eb2e8f9f7 | 897 | /* length == 1 */ |
<> | 144:ef7eb2e8f9f7 | 898 | /* Set MR3 WAIT bit is 1 */; |
<> | 144:ef7eb2e8f9f7 | 899 | REG(MR3.UINT32) |= MR3_WAIT; |
<> | 144:ef7eb2e8f9f7 | 900 | i2c_set_MR3_NACK(obj); |
<> | 144:ef7eb2e8f9f7 | 901 | } else if (obj->rx_buff.length == 2) { |
<> | 144:ef7eb2e8f9f7 | 902 | /* Set MR3 WAIT bit is 1 */ |
<> | 144:ef7eb2e8f9f7 | 903 | REG(MR3.UINT32) |= MR3_WAIT; |
<> | 144:ef7eb2e8f9f7 | 904 | } |
<> | 144:ef7eb2e8f9f7 | 905 | /* dummy read */ |
<> | 144:ef7eb2e8f9f7 | 906 | if (REG(DRR.UINT32)) {} |
<> | 144:ef7eb2e8f9f7 | 907 | obj->rx_buff.pos = 0; |
<> | 144:ef7eb2e8f9f7 | 908 | return; |
<> | 144:ef7eb2e8f9f7 | 909 | } |
<> | 144:ef7eb2e8f9f7 | 910 | if ((REG(SR2.UINT32) & SR2_NACKF) != 0) { |
<> | 144:ef7eb2e8f9f7 | 911 | /* Slave sends NACK */ |
<> | 144:ef7eb2e8f9f7 | 912 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 913 | i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; |
<> | 144:ef7eb2e8f9f7 | 914 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 915 | ((void (*)())i2c_data[index].async_callback)(); |
<> | 144:ef7eb2e8f9f7 | 916 | return; |
<> | 144:ef7eb2e8f9f7 | 917 | } else { |
<> | 144:ef7eb2e8f9f7 | 918 | switch (obj->rx_buff.length - obj->rx_buff.pos) { |
<> | 144:ef7eb2e8f9f7 | 919 | case 1: |
<> | 144:ef7eb2e8f9f7 | 920 | /* Finished */ |
<> | 144:ef7eb2e8f9f7 | 921 | /* If not repeated start, send stop. */ |
<> | 144:ef7eb2e8f9f7 | 922 | if (i2c_data[index].shouldStop) { |
<> | 144:ef7eb2e8f9f7 | 923 | (void)i2c_set_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 924 | /* RIICnDRR read */ |
<> | 144:ef7eb2e8f9f7 | 925 | *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF; |
<> | 144:ef7eb2e8f9f7 | 926 | /* RIICnMR3.WAIT = 0 */ |
<> | 144:ef7eb2e8f9f7 | 927 | REG(MR3.UINT32) &= ~MR3_WAIT; |
<> | 144:ef7eb2e8f9f7 | 928 | (void)i2c_wait_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 929 | i2c_set_SR2_NACKF_STOP(obj); |
<> | 144:ef7eb2e8f9f7 | 930 | } else { |
<> | 144:ef7eb2e8f9f7 | 931 | (void)i2c_restart(obj); |
<> | 144:ef7eb2e8f9f7 | 932 | /* RIICnDRR read */ |
<> | 144:ef7eb2e8f9f7 | 933 | *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF; |
<> | 144:ef7eb2e8f9f7 | 934 | /* RIICnMR3.WAIT = 0 */ |
<> | 144:ef7eb2e8f9f7 | 935 | REG(MR3.UINT32) &= ~MR3_WAIT; |
<> | 144:ef7eb2e8f9f7 | 936 | (void)i2c_wait_START(obj); |
<> | 144:ef7eb2e8f9f7 | 937 | /* SR2.START = 0 */ |
<> | 144:ef7eb2e8f9f7 | 938 | REG(SR2.UINT32) &= ~SR2_START; |
<> | 144:ef7eb2e8f9f7 | 939 | } |
<> | 144:ef7eb2e8f9f7 | 940 | |
<> | 144:ef7eb2e8f9f7 | 941 | i2c_transfer_finished(obj); |
<> | 144:ef7eb2e8f9f7 | 942 | return; |
<> | 144:ef7eb2e8f9f7 | 943 | |
<> | 144:ef7eb2e8f9f7 | 944 | case 2: |
<> | 144:ef7eb2e8f9f7 | 945 | i2c_set_MR3_NACK(obj); |
<> | 144:ef7eb2e8f9f7 | 946 | break; |
<> | 144:ef7eb2e8f9f7 | 947 | |
<> | 144:ef7eb2e8f9f7 | 948 | case 3: |
<> | 144:ef7eb2e8f9f7 | 949 | /* this time is befor last byte read */ |
<> | 144:ef7eb2e8f9f7 | 950 | /* Set MR3 WAIT bit is 1 */ |
<> | 144:ef7eb2e8f9f7 | 951 | REG(MR3.UINT32) |= MR3_WAIT; |
<> | 144:ef7eb2e8f9f7 | 952 | break; |
<> | 144:ef7eb2e8f9f7 | 953 | |
<> | 144:ef7eb2e8f9f7 | 954 | default: |
<> | 144:ef7eb2e8f9f7 | 955 | i2c_set_MR3_ACK(obj); |
<> | 144:ef7eb2e8f9f7 | 956 | break; |
<> | 144:ef7eb2e8f9f7 | 957 | } |
<> | 144:ef7eb2e8f9f7 | 958 | *(uint8_t *)obj->rx_buff.buffer = REG(DRR.UINT32) & 0xFF; |
<> | 144:ef7eb2e8f9f7 | 959 | obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + 1; |
<> | 144:ef7eb2e8f9f7 | 960 | ++obj->rx_buff.pos; |
<> | 144:ef7eb2e8f9f7 | 961 | } |
<> | 144:ef7eb2e8f9f7 | 962 | } |
<> | 144:ef7eb2e8f9f7 | 963 | |
<> | 144:ef7eb2e8f9f7 | 964 | static void i2c_err_irq(IRQn_Type irq_num, uint32_t index) |
<> | 144:ef7eb2e8f9f7 | 965 | { |
<> | 144:ef7eb2e8f9f7 | 966 | i2c_t *obj = i2c_data[index].async_obj; |
<> | 144:ef7eb2e8f9f7 | 967 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 968 | i2c_data[index].event = I2C_EVENT_ERROR; |
<> | 144:ef7eb2e8f9f7 | 969 | ((void (*)())i2c_data[index].async_callback)(); |
<> | 144:ef7eb2e8f9f7 | 970 | } |
<> | 144:ef7eb2e8f9f7 | 971 | |
<> | 144:ef7eb2e8f9f7 | 972 | /* TX handler */ |
<> | 144:ef7eb2e8f9f7 | 973 | static void i2c0_tx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 974 | { |
<> | 144:ef7eb2e8f9f7 | 975 | i2c_tx_irq(INTIICTEI0_IRQn, 0); |
<> | 144:ef7eb2e8f9f7 | 976 | } |
<> | 144:ef7eb2e8f9f7 | 977 | |
<> | 144:ef7eb2e8f9f7 | 978 | static void i2c1_tx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 979 | { |
<> | 144:ef7eb2e8f9f7 | 980 | i2c_tx_irq(INTIICTEI1_IRQn, 1); |
<> | 144:ef7eb2e8f9f7 | 981 | } |
<> | 144:ef7eb2e8f9f7 | 982 | |
<> | 144:ef7eb2e8f9f7 | 983 | static void i2c2_tx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 984 | { |
<> | 144:ef7eb2e8f9f7 | 985 | i2c_tx_irq(INTIICTEI2_IRQn, 2); |
<> | 144:ef7eb2e8f9f7 | 986 | } |
<> | 144:ef7eb2e8f9f7 | 987 | |
<> | 144:ef7eb2e8f9f7 | 988 | static void i2c3_tx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 989 | { |
<> | 144:ef7eb2e8f9f7 | 990 | i2c_tx_irq(INTIICTEI3_IRQn, 3); |
<> | 144:ef7eb2e8f9f7 | 991 | } |
<> | 144:ef7eb2e8f9f7 | 992 | |
<> | 144:ef7eb2e8f9f7 | 993 | /* RX handler */ |
<> | 144:ef7eb2e8f9f7 | 994 | static void i2c0_rx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 995 | { |
<> | 144:ef7eb2e8f9f7 | 996 | i2c_rx_irq(INTIICRI0_IRQn, 0); |
<> | 144:ef7eb2e8f9f7 | 997 | } |
<> | 144:ef7eb2e8f9f7 | 998 | |
<> | 144:ef7eb2e8f9f7 | 999 | static void i2c1_rx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1000 | { |
<> | 144:ef7eb2e8f9f7 | 1001 | i2c_rx_irq(INTIICRI1_IRQn, 1); |
<> | 144:ef7eb2e8f9f7 | 1002 | } |
<> | 144:ef7eb2e8f9f7 | 1003 | |
<> | 144:ef7eb2e8f9f7 | 1004 | static void i2c2_rx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1005 | { |
<> | 144:ef7eb2e8f9f7 | 1006 | i2c_rx_irq(INTIICRI2_IRQn, 2); |
<> | 144:ef7eb2e8f9f7 | 1007 | } |
<> | 144:ef7eb2e8f9f7 | 1008 | |
<> | 144:ef7eb2e8f9f7 | 1009 | static void i2c3_rx_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1010 | { |
<> | 144:ef7eb2e8f9f7 | 1011 | i2c_rx_irq(INTIICRI3_IRQn, 3); |
<> | 144:ef7eb2e8f9f7 | 1012 | } |
<> | 144:ef7eb2e8f9f7 | 1013 | |
<> | 144:ef7eb2e8f9f7 | 1014 | /* Arbitration Lost handler */ |
<> | 144:ef7eb2e8f9f7 | 1015 | static void i2c0_al_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1016 | { |
<> | 144:ef7eb2e8f9f7 | 1017 | i2c_err_irq(INTIICALI0_IRQn, 0); |
<> | 144:ef7eb2e8f9f7 | 1018 | } |
<> | 144:ef7eb2e8f9f7 | 1019 | |
<> | 144:ef7eb2e8f9f7 | 1020 | static void i2c1_al_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1021 | { |
<> | 144:ef7eb2e8f9f7 | 1022 | i2c_err_irq(INTIICALI1_IRQn, 1); |
<> | 144:ef7eb2e8f9f7 | 1023 | } |
<> | 144:ef7eb2e8f9f7 | 1024 | |
<> | 144:ef7eb2e8f9f7 | 1025 | static void i2c2_al_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1026 | { |
<> | 144:ef7eb2e8f9f7 | 1027 | i2c_err_irq(INTIICALI2_IRQn, 2); |
<> | 144:ef7eb2e8f9f7 | 1028 | } |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 144:ef7eb2e8f9f7 | 1030 | static void i2c3_al_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1031 | { |
<> | 144:ef7eb2e8f9f7 | 1032 | i2c_err_irq(INTIICALI3_IRQn, 3); |
<> | 144:ef7eb2e8f9f7 | 1033 | } |
<> | 144:ef7eb2e8f9f7 | 1034 | |
<> | 144:ef7eb2e8f9f7 | 1035 | /* Timeout handler */ |
<> | 144:ef7eb2e8f9f7 | 1036 | static void i2c0_to_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1037 | { |
<> | 144:ef7eb2e8f9f7 | 1038 | i2c_err_irq(INTIICTMOI0_IRQn, 0); |
<> | 144:ef7eb2e8f9f7 | 1039 | } |
<> | 144:ef7eb2e8f9f7 | 1040 | |
<> | 144:ef7eb2e8f9f7 | 1041 | static void i2c1_to_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1042 | { |
<> | 144:ef7eb2e8f9f7 | 1043 | i2c_err_irq(INTIICTMOI1_IRQn, 1); |
<> | 144:ef7eb2e8f9f7 | 1044 | } |
<> | 144:ef7eb2e8f9f7 | 1045 | |
<> | 144:ef7eb2e8f9f7 | 1046 | static void i2c2_to_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1047 | { |
<> | 144:ef7eb2e8f9f7 | 1048 | i2c_err_irq(INTIICTMOI2_IRQn, 2); |
<> | 144:ef7eb2e8f9f7 | 1049 | } |
<> | 144:ef7eb2e8f9f7 | 1050 | |
<> | 144:ef7eb2e8f9f7 | 1051 | static void i2c3_to_irq(void) |
<> | 144:ef7eb2e8f9f7 | 1052 | { |
<> | 144:ef7eb2e8f9f7 | 1053 | i2c_err_irq(INTIICTMOI3_IRQn, 3); |
<> | 144:ef7eb2e8f9f7 | 1054 | } |
<> | 144:ef7eb2e8f9f7 | 1055 | |
<> | 144:ef7eb2e8f9f7 | 1056 | static void i2c_irqs_set(i2c_t *obj, uint32_t enable) |
<> | 144:ef7eb2e8f9f7 | 1057 | { |
<> | 144:ef7eb2e8f9f7 | 1058 | int i; |
<> | 144:ef7eb2e8f9f7 | 1059 | const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.i2c]; |
<> | 144:ef7eb2e8f9f7 | 1060 | const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.i2c]; |
<> | 144:ef7eb2e8f9f7 | 1061 | for (i = 0; i < IRQ_NUM; ++i) { |
<> | 144:ef7eb2e8f9f7 | 1062 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 1063 | InterruptHandlerRegister(irqTable[i], handlerTable[i]); |
<> | 144:ef7eb2e8f9f7 | 1064 | GIC_SetPriority(irqTable[i], 5); |
<> | 144:ef7eb2e8f9f7 | 1065 | GIC_EnableIRQ(irqTable[i]); |
<> | 144:ef7eb2e8f9f7 | 1066 | } else { |
<> | 144:ef7eb2e8f9f7 | 1067 | GIC_DisableIRQ(irqTable[i]); |
<> | 144:ef7eb2e8f9f7 | 1068 | } |
<> | 144:ef7eb2e8f9f7 | 1069 | } |
<> | 144:ef7eb2e8f9f7 | 1070 | REG(IER.UINT8[0]) = enable ? 0x63 : 0x00; |
<> | 144:ef7eb2e8f9f7 | 1071 | } |
<> | 144:ef7eb2e8f9f7 | 1072 | |
<> | 144:ef7eb2e8f9f7 | 1073 | /****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 1074 | * ASYNCHRONOUS HAL |
<> | 144:ef7eb2e8f9f7 | 1075 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 1076 | |
<> | 144:ef7eb2e8f9f7 | 1077 | void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) |
<> | 144:ef7eb2e8f9f7 | 1078 | { |
<> | 144:ef7eb2e8f9f7 | 1079 | MBED_ASSERT(obj); |
<> | 144:ef7eb2e8f9f7 | 1080 | MBED_ASSERT(tx ? tx_length : 1); |
<> | 144:ef7eb2e8f9f7 | 1081 | MBED_ASSERT(rx ? rx_length : 1); |
<> | 144:ef7eb2e8f9f7 | 1082 | MBED_ASSERT((REG(SER.UINT32) & SER_SAR0E) == 0); /* Slave mode */ |
<> | 144:ef7eb2e8f9f7 | 1083 | |
<> | 144:ef7eb2e8f9f7 | 1084 | obj->tx_buff.buffer = (void *)tx; |
<> | 144:ef7eb2e8f9f7 | 1085 | obj->tx_buff.length = tx_length; |
<> | 144:ef7eb2e8f9f7 | 1086 | obj->tx_buff.pos = 0; |
<> | 144:ef7eb2e8f9f7 | 1087 | obj->tx_buff.width = 8; |
<> | 144:ef7eb2e8f9f7 | 1088 | obj->rx_buff.buffer = rx; |
<> | 144:ef7eb2e8f9f7 | 1089 | obj->rx_buff.length = rx_length; |
<> | 144:ef7eb2e8f9f7 | 1090 | obj->rx_buff.pos = SIZE_MAX; |
<> | 144:ef7eb2e8f9f7 | 1091 | obj->rx_buff.width = 8; |
<> | 144:ef7eb2e8f9f7 | 1092 | i2c_data[obj->i2c.i2c].async_obj = obj; |
<> | 144:ef7eb2e8f9f7 | 1093 | i2c_data[obj->i2c.i2c].async_callback = handler; |
<> | 144:ef7eb2e8f9f7 | 1094 | i2c_data[obj->i2c.i2c].event = 0; |
<> | 144:ef7eb2e8f9f7 | 1095 | i2c_data[obj->i2c.i2c].shouldStop = stop; |
<> | 144:ef7eb2e8f9f7 | 1096 | i2c_data[obj->i2c.i2c].address = address; |
<> | 144:ef7eb2e8f9f7 | 1097 | i2c_irqs_set(obj, 1); |
<> | 144:ef7eb2e8f9f7 | 1098 | |
<> | 144:ef7eb2e8f9f7 | 1099 | /* There is a STOP condition for last processing */ |
<> | 144:ef7eb2e8f9f7 | 1100 | if (obj->i2c.last_stop_flag != 0) { |
<> | 144:ef7eb2e8f9f7 | 1101 | if (i2c_start(obj) != 0) { |
<> | 144:ef7eb2e8f9f7 | 1102 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 1103 | i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 1104 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1105 | ((void (*)())handler)(); |
<> | 144:ef7eb2e8f9f7 | 1106 | return; |
<> | 144:ef7eb2e8f9f7 | 1107 | } |
<> | 144:ef7eb2e8f9f7 | 1108 | } |
<> | 144:ef7eb2e8f9f7 | 1109 | obj->i2c.last_stop_flag = stop; |
<> | 144:ef7eb2e8f9f7 | 1110 | |
<> | 144:ef7eb2e8f9f7 | 1111 | if (rx_length && tx_length == 0) { |
<> | 144:ef7eb2e8f9f7 | 1112 | /* Ready to read */ |
<> | 144:ef7eb2e8f9f7 | 1113 | i2c_set_MR3_ACK(obj); |
<> | 144:ef7eb2e8f9f7 | 1114 | |
<> | 144:ef7eb2e8f9f7 | 1115 | /* Disable INTRIICTEI */ |
<> | 144:ef7eb2e8f9f7 | 1116 | REG(IER.UINT8[0]) &= ~(1 << 6); |
<> | 144:ef7eb2e8f9f7 | 1117 | |
<> | 144:ef7eb2e8f9f7 | 1118 | address |= 0x01; |
<> | 144:ef7eb2e8f9f7 | 1119 | } |
<> | 144:ef7eb2e8f9f7 | 1120 | /* Send Slave address */ |
<> | 144:ef7eb2e8f9f7 | 1121 | if (i2c_do_write(obj, address) != 0) { |
<> | 144:ef7eb2e8f9f7 | 1122 | i2c_set_err_noslave(obj); |
<> | 144:ef7eb2e8f9f7 | 1123 | i2c_data[obj->i2c.i2c].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 1124 | i2c_abort_asynch(obj); |
<> | 144:ef7eb2e8f9f7 | 1125 | ((void (*)())handler)(); |
<> | 144:ef7eb2e8f9f7 | 1126 | return; |
<> | 144:ef7eb2e8f9f7 | 1127 | } |
<> | 144:ef7eb2e8f9f7 | 1128 | } |
<> | 144:ef7eb2e8f9f7 | 1129 | |
<> | 144:ef7eb2e8f9f7 | 1130 | uint32_t i2c_irq_handler_asynch(i2c_t *obj) |
<> | 144:ef7eb2e8f9f7 | 1131 | { |
<> | 144:ef7eb2e8f9f7 | 1132 | return i2c_data[obj->i2c.i2c].event; |
<> | 144:ef7eb2e8f9f7 | 1133 | } |
<> | 144:ef7eb2e8f9f7 | 1134 | |
<> | 144:ef7eb2e8f9f7 | 1135 | uint8_t i2c_active(i2c_t *obj) |
<> | 144:ef7eb2e8f9f7 | 1136 | { |
<> | 144:ef7eb2e8f9f7 | 1137 | return i2c_data[obj->i2c.i2c].async_obj != NULL; |
<> | 144:ef7eb2e8f9f7 | 1138 | } |
<> | 144:ef7eb2e8f9f7 | 1139 | |
<> | 144:ef7eb2e8f9f7 | 1140 | void i2c_abort_asynch(i2c_t *obj) |
<> | 144:ef7eb2e8f9f7 | 1141 | { |
<> | 144:ef7eb2e8f9f7 | 1142 | i2c_data[obj->i2c.i2c].async_obj = NULL; |
<> | 144:ef7eb2e8f9f7 | 1143 | i2c_irqs_set(obj, 0); |
<> | 144:ef7eb2e8f9f7 | 1144 | i2c_reg_reset(obj); |
<> | 144:ef7eb2e8f9f7 | 1145 | } |
<> | 144:ef7eb2e8f9f7 | 1146 | |
<> | 144:ef7eb2e8f9f7 | 1147 | #endif |