mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h@14:d797fbdad187, 2015-11-02 (annotated)

Committer:
mbed_official
Date:
Mon Nov 02 10:15:09 2015 +0000
Revision:
14:d797fbdad187
Parent:
0:9b334a45a8ff
Child:
135:eec55f8ee438
Synchronized with git revision 5eccd220ead2bdcde483fff5a2c4de66a0c0e08f



Full URL: https://github.com/mbedmicro/mbed/commit/5eccd220ead2bdcde483fff5a2c4de66a0c0e08f/



Added Keil compiler support for Atmel Targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f072xb.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V2.2.2
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file contains:
bogdanm 0:9b334a45a8ff 10 * - Data structures and the address mapping for all peripherals
bogdanm 0:9b334a45a8ff 11 * - Peripheral's registers declarations and bits definition
bogdanm 0:9b334a45a8ff 12 * - Macros to access peripheral’s registers hardware
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 ******************************************************************************
bogdanm 0:9b334a45a8ff 15 * @attention
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 20 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 21 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 22 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 24 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 25 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 27 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 28 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 29 *
bogdanm 0:9b334a45a8ff 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 40 *
bogdanm 0:9b334a45a8ff 41 ******************************************************************************
bogdanm 0:9b334a45a8ff 42 */
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 /** @addtogroup CMSIS_Device
bogdanm 0:9b334a45a8ff 45 * @{
bogdanm 0:9b334a45a8ff 46 */
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 /** @addtogroup stm32f072xb
bogdanm 0:9b334a45a8ff 49 * @{
bogdanm 0:9b334a45a8ff 50 */
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 #ifndef __STM32F072xB_H
bogdanm 0:9b334a45a8ff 53 #define __STM32F072xB_H
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 56 extern "C" {
bogdanm 0:9b334a45a8ff 57 #endif /* __cplusplus */
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /** @addtogroup Configuration_section_for_CMSIS
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62 /**
bogdanm 0:9b334a45a8ff 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
bogdanm 0:9b334a45a8ff 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
bogdanm 0:9b334a45a8ff 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
bogdanm 0:9b334a45a8ff 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /**
bogdanm 0:9b334a45a8ff 71 * @}
bogdanm 0:9b334a45a8ff 72 */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 /** @addtogroup Peripheral_interrupt_number_definition
bogdanm 0:9b334a45a8ff 75 * @{
bogdanm 0:9b334a45a8ff 76 */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /**
bogdanm 0:9b334a45a8ff 79 * @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
bogdanm 0:9b334a45a8ff 80 */
bogdanm 0:9b334a45a8ff 81 typedef enum
bogdanm 0:9b334a45a8ff 82 {
bogdanm 0:9b334a45a8ff 83 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
bogdanm 0:9b334a45a8ff 84 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 85 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 86 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 87 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 88 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /****** STM32F072x8/STM32F072xB specific Interrupt Numbers **************************************************/
bogdanm 0:9b334a45a8ff 91 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
bogdanm 0:9b334a45a8ff 92 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
bogdanm 0:9b334a45a8ff 93 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
bogdanm 0:9b334a45a8ff 94 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
bogdanm 0:9b334a45a8ff 95 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
bogdanm 0:9b334a45a8ff 96 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
bogdanm 0:9b334a45a8ff 97 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
bogdanm 0:9b334a45a8ff 98 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
bogdanm 0:9b334a45a8ff 99 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
bogdanm 0:9b334a45a8ff 100 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
bogdanm 0:9b334a45a8ff 101 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
bogdanm 0:9b334a45a8ff 102 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupts */
bogdanm 0:9b334a45a8ff 103 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
bogdanm 0:9b334a45a8ff 104 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
bogdanm 0:9b334a45a8ff 105 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
bogdanm 0:9b334a45a8ff 106 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
bogdanm 0:9b334a45a8ff 107 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
bogdanm 0:9b334a45a8ff 108 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
bogdanm 0:9b334a45a8ff 109 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
bogdanm 0:9b334a45a8ff 110 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
bogdanm 0:9b334a45a8ff 111 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
bogdanm 0:9b334a45a8ff 112 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
bogdanm 0:9b334a45a8ff 113 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
bogdanm 0:9b334a45a8ff 114 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
bogdanm 0:9b334a45a8ff 115 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
bogdanm 0:9b334a45a8ff 116 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
bogdanm 0:9b334a45a8ff 117 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
bogdanm 0:9b334a45a8ff 118 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
bogdanm 0:9b334a45a8ff 119 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
bogdanm 0:9b334a45a8ff 120 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
bogdanm 0:9b334a45a8ff 121 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
bogdanm 0:9b334a45a8ff 122 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
bogdanm 0:9b334a45a8ff 123 } IRQn_Type;
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 /**
bogdanm 0:9b334a45a8ff 126 * @}
bogdanm 0:9b334a45a8ff 127 */
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
bogdanm 0:9b334a45a8ff 130 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
bogdanm 0:9b334a45a8ff 131 #include <stdint.h>
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 /** @addtogroup Peripheral_registers_structures
bogdanm 0:9b334a45a8ff 134 * @{
bogdanm 0:9b334a45a8ff 135 */
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @brief Analog to Digital Converter
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 typedef struct
bogdanm 0:9b334a45a8ff 142 {
bogdanm 0:9b334a45a8ff 143 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
bogdanm 0:9b334a45a8ff 144 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
bogdanm 0:9b334a45a8ff 145 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
bogdanm 0:9b334a45a8ff 146 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
bogdanm 0:9b334a45a8ff 147 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
bogdanm 0:9b334a45a8ff 148 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
bogdanm 0:9b334a45a8ff 149 uint32_t RESERVED1; /*!< Reserved, 0x18 */
bogdanm 0:9b334a45a8ff 150 uint32_t RESERVED2; /*!< Reserved, 0x1C */
bogdanm 0:9b334a45a8ff 151 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
bogdanm 0:9b334a45a8ff 152 uint32_t RESERVED3; /*!< Reserved, 0x24 */
bogdanm 0:9b334a45a8ff 153 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
bogdanm 0:9b334a45a8ff 154 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
bogdanm 0:9b334a45a8ff 155 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
bogdanm 0:9b334a45a8ff 156 }ADC_TypeDef;
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 typedef struct
bogdanm 0:9b334a45a8ff 159 {
bogdanm 0:9b334a45a8ff 160 __IO uint32_t CCR;
bogdanm 0:9b334a45a8ff 161 }ADC_Common_TypeDef;
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 /**
bogdanm 0:9b334a45a8ff 164 * @brief Controller Area Network TxMailBox
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 typedef struct
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
bogdanm 0:9b334a45a8ff 169 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
bogdanm 0:9b334a45a8ff 170 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
bogdanm 0:9b334a45a8ff 171 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
bogdanm 0:9b334a45a8ff 172 }CAN_TxMailBox_TypeDef;
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /**
bogdanm 0:9b334a45a8ff 175 * @brief Controller Area Network FIFOMailBox
bogdanm 0:9b334a45a8ff 176 */
bogdanm 0:9b334a45a8ff 177 typedef struct
bogdanm 0:9b334a45a8ff 178 {
bogdanm 0:9b334a45a8ff 179 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
bogdanm 0:9b334a45a8ff 180 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
bogdanm 0:9b334a45a8ff 181 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
bogdanm 0:9b334a45a8ff 182 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
bogdanm 0:9b334a45a8ff 183 }CAN_FIFOMailBox_TypeDef;
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /**
bogdanm 0:9b334a45a8ff 186 * @brief Controller Area Network FilterRegister
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188 typedef struct
bogdanm 0:9b334a45a8ff 189 {
bogdanm 0:9b334a45a8ff 190 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
bogdanm 0:9b334a45a8ff 191 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
bogdanm 0:9b334a45a8ff 192 }CAN_FilterRegister_TypeDef;
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /**
bogdanm 0:9b334a45a8ff 195 * @brief Controller Area Network
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197 typedef struct
bogdanm 0:9b334a45a8ff 198 {
bogdanm 0:9b334a45a8ff 199 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 200 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 201 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 202 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 203 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 204 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 205 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 206 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 207 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
bogdanm 0:9b334a45a8ff 208 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
bogdanm 0:9b334a45a8ff 209 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
bogdanm 0:9b334a45a8ff 210 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
bogdanm 0:9b334a45a8ff 211 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
bogdanm 0:9b334a45a8ff 212 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
bogdanm 0:9b334a45a8ff 213 uint32_t RESERVED2; /*!< Reserved, 0x208 */
bogdanm 0:9b334a45a8ff 214 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
bogdanm 0:9b334a45a8ff 215 uint32_t RESERVED3; /*!< Reserved, 0x210 */
bogdanm 0:9b334a45a8ff 216 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
bogdanm 0:9b334a45a8ff 217 uint32_t RESERVED4; /*!< Reserved, 0x218 */
bogdanm 0:9b334a45a8ff 218 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
bogdanm 0:9b334a45a8ff 219 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
bogdanm 0:9b334a45a8ff 220 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
bogdanm 0:9b334a45a8ff 221 }CAN_TypeDef;
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /**
bogdanm 0:9b334a45a8ff 224 * @brief HDMI-CEC
bogdanm 0:9b334a45a8ff 225 */
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 typedef struct
bogdanm 0:9b334a45a8ff 228 {
bogdanm 0:9b334a45a8ff 229 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
bogdanm 0:9b334a45a8ff 230 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
bogdanm 0:9b334a45a8ff 231 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
bogdanm 0:9b334a45a8ff 232 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
bogdanm 0:9b334a45a8ff 233 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
bogdanm 0:9b334a45a8ff 234 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
bogdanm 0:9b334a45a8ff 235 }CEC_TypeDef;
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /**
bogdanm 0:9b334a45a8ff 238 * @brief Comparator
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240
bogdanm 0:9b334a45a8ff 241 typedef struct
bogdanm 0:9b334a45a8ff 242 {
bogdanm 0:9b334a45a8ff 243 __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 244 }COMP1_2_TypeDef;
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 typedef struct
bogdanm 0:9b334a45a8ff 247 {
bogdanm 0:9b334a45a8ff 248 __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 249 }COMP_TypeDef;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251 /**
bogdanm 0:9b334a45a8ff 252 * @brief CRC calculation unit
bogdanm 0:9b334a45a8ff 253 */
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 typedef struct
bogdanm 0:9b334a45a8ff 256 {
bogdanm 0:9b334a45a8ff 257 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 258 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 259 uint8_t RESERVED0; /*!< Reserved, 0x05 */
bogdanm 0:9b334a45a8ff 260 uint16_t RESERVED1; /*!< Reserved, 0x06 */
bogdanm 0:9b334a45a8ff 261 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 262 uint32_t RESERVED2; /*!< Reserved, 0x0C */
bogdanm 0:9b334a45a8ff 263 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 264 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 265 }CRC_TypeDef;
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 /**
bogdanm 0:9b334a45a8ff 268 * @brief Clock Recovery System
bogdanm 0:9b334a45a8ff 269 */
bogdanm 0:9b334a45a8ff 270 typedef struct
bogdanm 0:9b334a45a8ff 271 {
bogdanm 0:9b334a45a8ff 272 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 273 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 274 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 275 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 276 }CRS_TypeDef;
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /**
bogdanm 0:9b334a45a8ff 279 * @brief Digital to Analog Converter
bogdanm 0:9b334a45a8ff 280 */
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 typedef struct
bogdanm 0:9b334a45a8ff 283 {
bogdanm 0:9b334a45a8ff 284 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 285 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 286 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 287 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 288 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 289 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 290 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 291 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 292 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 293 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 294 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 295 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 296 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 297 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 298 }DAC_TypeDef;
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 /**
bogdanm 0:9b334a45a8ff 301 * @brief Debug MCU
bogdanm 0:9b334a45a8ff 302 */
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 typedef struct
bogdanm 0:9b334a45a8ff 305 {
bogdanm 0:9b334a45a8ff 306 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 307 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 308 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 309 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 310 }DBGMCU_TypeDef;
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /**
bogdanm 0:9b334a45a8ff 313 * @brief DMA Controller
bogdanm 0:9b334a45a8ff 314 */
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 typedef struct
bogdanm 0:9b334a45a8ff 317 {
bogdanm 0:9b334a45a8ff 318 __IO uint32_t CCR; /*!< DMA channel x configuration register */
bogdanm 0:9b334a45a8ff 319 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
bogdanm 0:9b334a45a8ff 320 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
bogdanm 0:9b334a45a8ff 321 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
bogdanm 0:9b334a45a8ff 322 }DMA_Channel_TypeDef;
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 typedef struct
bogdanm 0:9b334a45a8ff 325 {
bogdanm 0:9b334a45a8ff 326 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 327 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 328 }DMA_TypeDef;
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /**
bogdanm 0:9b334a45a8ff 331 * @brief External Interrupt/Event Controller
bogdanm 0:9b334a45a8ff 332 */
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 typedef struct
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 337 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 338 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 339 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 340 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 341 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 342 }EXTI_TypeDef;
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /**
bogdanm 0:9b334a45a8ff 345 * @brief FLASH Registers
bogdanm 0:9b334a45a8ff 346 */
bogdanm 0:9b334a45a8ff 347 typedef struct
bogdanm 0:9b334a45a8ff 348 {
bogdanm 0:9b334a45a8ff 349 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 350 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 351 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 352 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 353 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 354 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 355 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
bogdanm 0:9b334a45a8ff 356 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 357 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 358 }FLASH_TypeDef;
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /**
bogdanm 0:9b334a45a8ff 362 * @brief Option Bytes Registers
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364 typedef struct
bogdanm 0:9b334a45a8ff 365 {
bogdanm 0:9b334a45a8ff 366 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 367 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
bogdanm 0:9b334a45a8ff 368 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 369 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
bogdanm 0:9b334a45a8ff 370 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 371 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
bogdanm 0:9b334a45a8ff 372 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 373 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
bogdanm 0:9b334a45a8ff 374 }OB_TypeDef;
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /**
bogdanm 0:9b334a45a8ff 377 * @brief General Purpose I/O
bogdanm 0:9b334a45a8ff 378 */
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 typedef struct
bogdanm 0:9b334a45a8ff 381 {
bogdanm 0:9b334a45a8ff 382 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 383 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 384 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 385 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 386 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 387 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 388 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
bogdanm 0:9b334a45a8ff 389 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 390 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
bogdanm 0:9b334a45a8ff 391 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 392 }GPIO_TypeDef;
bogdanm 0:9b334a45a8ff 393
bogdanm 0:9b334a45a8ff 394 /**
bogdanm 0:9b334a45a8ff 395 * @brief SysTem Configuration
bogdanm 0:9b334a45a8ff 396 */
bogdanm 0:9b334a45a8ff 397
bogdanm 0:9b334a45a8ff 398 typedef struct
bogdanm 0:9b334a45a8ff 399 {
bogdanm 0:9b334a45a8ff 400 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 401 uint32_t RESERVED; /*!< Reserved, 0x04 */
bogdanm 0:9b334a45a8ff 402 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
bogdanm 0:9b334a45a8ff 403 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 404 }SYSCFG_TypeDef;
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /**
bogdanm 0:9b334a45a8ff 407 * @brief Inter-integrated Circuit Interface
bogdanm 0:9b334a45a8ff 408 */
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 typedef struct
bogdanm 0:9b334a45a8ff 411 {
bogdanm 0:9b334a45a8ff 412 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 413 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 414 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 415 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 416 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 417 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 418 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 419 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 420 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 421 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 422 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 423 }I2C_TypeDef;
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /**
bogdanm 0:9b334a45a8ff 426 * @brief Independent WATCHDOG
bogdanm 0:9b334a45a8ff 427 */
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 typedef struct
bogdanm 0:9b334a45a8ff 430 {
bogdanm 0:9b334a45a8ff 431 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 432 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 433 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 434 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 435 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 436 }IWDG_TypeDef;
bogdanm 0:9b334a45a8ff 437
bogdanm 0:9b334a45a8ff 438 /**
bogdanm 0:9b334a45a8ff 439 * @brief Power Control
bogdanm 0:9b334a45a8ff 440 */
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 typedef struct
bogdanm 0:9b334a45a8ff 443 {
bogdanm 0:9b334a45a8ff 444 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 445 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 446 }PWR_TypeDef;
bogdanm 0:9b334a45a8ff 447
bogdanm 0:9b334a45a8ff 448 /**
bogdanm 0:9b334a45a8ff 449 * @brief Reset and Clock Control
bogdanm 0:9b334a45a8ff 450 */
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 typedef struct
bogdanm 0:9b334a45a8ff 453 {
bogdanm 0:9b334a45a8ff 454 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 455 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 456 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 457 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 458 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 459 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 460 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 461 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 462 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 463 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 464 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 465 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 466 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 467 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 468 }RCC_TypeDef;
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /**
bogdanm 0:9b334a45a8ff 471 * @brief Real-Time Clock
bogdanm 0:9b334a45a8ff 472 */
bogdanm 0:9b334a45a8ff 473 typedef struct
bogdanm 0:9b334a45a8ff 474 {
bogdanm 0:9b334a45a8ff 475 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 476 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 477 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 478 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 479 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 480 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 481 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 482 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 483 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 484 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 485 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 486 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 487 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 488 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 489 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 490 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 491 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 492 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 493 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 494 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 495 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 496 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 497 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 498 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
bogdanm 0:9b334a45a8ff 499 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
bogdanm 0:9b334a45a8ff 500 }RTC_TypeDef;
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /**
bogdanm 0:9b334a45a8ff 503 * @brief Serial Peripheral Interface
bogdanm 0:9b334a45a8ff 504 */
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 typedef struct
bogdanm 0:9b334a45a8ff 507 {
bogdanm 0:9b334a45a8ff 508 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 509 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 510 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 511 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 512 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 513 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 514 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 515 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 516 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 517 }SPI_TypeDef;
bogdanm 0:9b334a45a8ff 518
bogdanm 0:9b334a45a8ff 519 /**
bogdanm 0:9b334a45a8ff 520 * @brief TIM
bogdanm 0:9b334a45a8ff 521 */
bogdanm 0:9b334a45a8ff 522 typedef struct
bogdanm 0:9b334a45a8ff 523 {
bogdanm 0:9b334a45a8ff 524 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 525 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 526 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 527 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 528 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 529 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 530 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 531 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 532 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 533 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 534 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 535 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 536 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 537 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
bogdanm 0:9b334a45a8ff 538 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
bogdanm 0:9b334a45a8ff 539 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
bogdanm 0:9b334a45a8ff 540 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 541 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 542 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 543 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 544 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 545 }TIM_TypeDef;
bogdanm 0:9b334a45a8ff 546
bogdanm 0:9b334a45a8ff 547 /**
bogdanm 0:9b334a45a8ff 548 * @brief Touch Sensing Controller (TSC)
bogdanm 0:9b334a45a8ff 549 */
bogdanm 0:9b334a45a8ff 550 typedef struct
bogdanm 0:9b334a45a8ff 551 {
bogdanm 0:9b334a45a8ff 552 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 553 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 554 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 555 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 556 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 557 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 558 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 559 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 560 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 561 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 562 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 563 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
bogdanm 0:9b334a45a8ff 564 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
bogdanm 0:9b334a45a8ff 565 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
bogdanm 0:9b334a45a8ff 566 }TSC_TypeDef;
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568 /**
bogdanm 0:9b334a45a8ff 569 * @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm 0:9b334a45a8ff 570 */
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 typedef struct
bogdanm 0:9b334a45a8ff 573 {
bogdanm 0:9b334a45a8ff 574 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 575 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 576 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 577 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 578 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 579 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 580 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 581 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 582 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
bogdanm 0:9b334a45a8ff 583 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
bogdanm 0:9b334a45a8ff 584 uint16_t RESERVED1; /*!< Reserved, 0x26 */
bogdanm 0:9b334a45a8ff 585 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
bogdanm 0:9b334a45a8ff 586 uint16_t RESERVED2; /*!< Reserved, 0x2A */
bogdanm 0:9b334a45a8ff 587 }USART_TypeDef;
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 /**
bogdanm 0:9b334a45a8ff 590 * @brief Universal Serial Bus Full Speed Device
bogdanm 0:9b334a45a8ff 591 */
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 typedef struct
bogdanm 0:9b334a45a8ff 594 {
bogdanm 0:9b334a45a8ff 595 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 596 __IO uint16_t RESERVED0; /*!< Reserved */
bogdanm 0:9b334a45a8ff 597 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 598 __IO uint16_t RESERVED1; /*!< Reserved */
bogdanm 0:9b334a45a8ff 599 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 600 __IO uint16_t RESERVED2; /*!< Reserved */
bogdanm 0:9b334a45a8ff 601 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
bogdanm 0:9b334a45a8ff 602 __IO uint16_t RESERVED3; /*!< Reserved */
bogdanm 0:9b334a45a8ff 603 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
bogdanm 0:9b334a45a8ff 604 __IO uint16_t RESERVED4; /*!< Reserved */
bogdanm 0:9b334a45a8ff 605 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
bogdanm 0:9b334a45a8ff 606 __IO uint16_t RESERVED5; /*!< Reserved */
bogdanm 0:9b334a45a8ff 607 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
bogdanm 0:9b334a45a8ff 608 __IO uint16_t RESERVED6; /*!< Reserved */
bogdanm 0:9b334a45a8ff 609 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
bogdanm 0:9b334a45a8ff 610 __IO uint16_t RESERVED7[17]; /*!< Reserved */
bogdanm 0:9b334a45a8ff 611 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
bogdanm 0:9b334a45a8ff 612 __IO uint16_t RESERVED8; /*!< Reserved */
bogdanm 0:9b334a45a8ff 613 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
bogdanm 0:9b334a45a8ff 614 __IO uint16_t RESERVED9; /*!< Reserved */
bogdanm 0:9b334a45a8ff 615 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
bogdanm 0:9b334a45a8ff 616 __IO uint16_t RESERVEDA; /*!< Reserved */
bogdanm 0:9b334a45a8ff 617 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
bogdanm 0:9b334a45a8ff 618 __IO uint16_t RESERVEDB; /*!< Reserved */
bogdanm 0:9b334a45a8ff 619 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
bogdanm 0:9b334a45a8ff 620 __IO uint16_t RESERVEDC; /*!< Reserved */
bogdanm 0:9b334a45a8ff 621 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
bogdanm 0:9b334a45a8ff 622 __IO uint16_t RESERVEDD; /*!< Reserved */
bogdanm 0:9b334a45a8ff 623 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
bogdanm 0:9b334a45a8ff 624 __IO uint16_t RESERVEDE; /*!< Reserved */
bogdanm 0:9b334a45a8ff 625 }USB_TypeDef;
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 /**
bogdanm 0:9b334a45a8ff 628 * @brief Window WATCHDOG
bogdanm 0:9b334a45a8ff 629 */
bogdanm 0:9b334a45a8ff 630 typedef struct
bogdanm 0:9b334a45a8ff 631 {
bogdanm 0:9b334a45a8ff 632 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
bogdanm 0:9b334a45a8ff 633 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
bogdanm 0:9b334a45a8ff 634 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
bogdanm 0:9b334a45a8ff 635 }WWDG_TypeDef;
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637 /**
bogdanm 0:9b334a45a8ff 638 * @}
bogdanm 0:9b334a45a8ff 639 */
bogdanm 0:9b334a45a8ff 640
bogdanm 0:9b334a45a8ff 641 /** @addtogroup Peripheral_memory_map
bogdanm 0:9b334a45a8ff 642 * @{
bogdanm 0:9b334a45a8ff 643 */
bogdanm 0:9b334a45a8ff 644
bogdanm 0:9b334a45a8ff 645 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
bogdanm 0:9b334a45a8ff 646 #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
bogdanm 0:9b334a45a8ff 647 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
bogdanm 0:9b334a45a8ff 648 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /*!< Peripheral memory map */
bogdanm 0:9b334a45a8ff 651 #define APBPERIPH_BASE PERIPH_BASE
bogdanm 0:9b334a45a8ff 652 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm 0:9b334a45a8ff 653 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
bogdanm 0:9b334a45a8ff 654
bogdanm 0:9b334a45a8ff 655 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 656 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
bogdanm 0:9b334a45a8ff 657 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 658 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
bogdanm 0:9b334a45a8ff 659 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
bogdanm 0:9b334a45a8ff 660 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
bogdanm 0:9b334a45a8ff 661 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
bogdanm 0:9b334a45a8ff 662 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
bogdanm 0:9b334a45a8ff 663 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
bogdanm 0:9b334a45a8ff 664 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
bogdanm 0:9b334a45a8ff 665 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
bogdanm 0:9b334a45a8ff 666 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
bogdanm 0:9b334a45a8ff 667 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
bogdanm 0:9b334a45a8ff 668 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
bogdanm 0:9b334a45a8ff 669 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
bogdanm 0:9b334a45a8ff 670 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
bogdanm 0:9b334a45a8ff 671 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
bogdanm 0:9b334a45a8ff 672 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
bogdanm 0:9b334a45a8ff 673 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
bogdanm 0:9b334a45a8ff 674 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
bogdanm 0:9b334a45a8ff 679 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
bogdanm 0:9b334a45a8ff 680 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
bogdanm 0:9b334a45a8ff 681 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
bogdanm 0:9b334a45a8ff 682 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
bogdanm 0:9b334a45a8ff 683 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
bogdanm 0:9b334a45a8ff 684 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
bogdanm 0:9b334a45a8ff 685 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
bogdanm 0:9b334a45a8ff 686 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
bogdanm 0:9b334a45a8ff 687 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
bogdanm 0:9b334a45a8ff 688 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
bogdanm 0:9b334a45a8ff 689 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 692 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
bogdanm 0:9b334a45a8ff 693 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
bogdanm 0:9b334a45a8ff 694 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
bogdanm 0:9b334a45a8ff 695 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
bogdanm 0:9b334a45a8ff 696 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
bogdanm 0:9b334a45a8ff 697 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
bogdanm 0:9b334a45a8ff 698 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 701 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
bogdanm 0:9b334a45a8ff 702 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
bogdanm 0:9b334a45a8ff 703 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
bogdanm 0:9b334a45a8ff 704 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
bogdanm 0:9b334a45a8ff 707 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
bogdanm 0:9b334a45a8ff 708 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
bogdanm 0:9b334a45a8ff 709 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
bogdanm 0:9b334a45a8ff 710 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
bogdanm 0:9b334a45a8ff 711 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 /**
bogdanm 0:9b334a45a8ff 714 * @}
bogdanm 0:9b334a45a8ff 715 */
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717 /** @addtogroup Peripheral_declaration
bogdanm 0:9b334a45a8ff 718 * @{
bogdanm 0:9b334a45a8ff 719 */
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm 0:9b334a45a8ff 722 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm 0:9b334a45a8ff 723 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm 0:9b334a45a8ff 724 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm 0:9b334a45a8ff 725 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm 0:9b334a45a8ff 726 #define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm 0:9b334a45a8ff 727 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm 0:9b334a45a8ff 728 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm 0:9b334a45a8ff 729 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm 0:9b334a45a8ff 730 #define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm 0:9b334a45a8ff 731 #define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm 0:9b334a45a8ff 732 #define USART4 ((USART_TypeDef *) USART4_BASE)
bogdanm 0:9b334a45a8ff 733 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm 0:9b334a45a8ff 734 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm 0:9b334a45a8ff 735 #define CAN ((CAN_TypeDef *) CAN_BASE)
bogdanm 0:9b334a45a8ff 736 #define CRS ((CRS_TypeDef *) CRS_BASE)
bogdanm 0:9b334a45a8ff 737 #define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm 0:9b334a45a8ff 738 #define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm 0:9b334a45a8ff 739 #define CEC ((CEC_TypeDef *) CEC_BASE)
bogdanm 0:9b334a45a8ff 740 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm 0:9b334a45a8ff 741 #define COMP ((COMP1_2_TypeDef *) COMP_BASE)
bogdanm 0:9b334a45a8ff 742 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
bogdanm 0:9b334a45a8ff 743 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
bogdanm 0:9b334a45a8ff 744 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm 0:9b334a45a8ff 745 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm 0:9b334a45a8ff 746 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm 0:9b334a45a8ff 747 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm 0:9b334a45a8ff 748 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm 0:9b334a45a8ff 749 #define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm 0:9b334a45a8ff 750 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm 0:9b334a45a8ff 751 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm 0:9b334a45a8ff 752 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm 0:9b334a45a8ff 753 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm 0:9b334a45a8ff 754 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm 0:9b334a45a8ff 755 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm 0:9b334a45a8ff 756 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm 0:9b334a45a8ff 757 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm 0:9b334a45a8ff 758 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm 0:9b334a45a8ff 759 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm 0:9b334a45a8ff 760 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm 0:9b334a45a8ff 761 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm 0:9b334a45a8ff 762 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm 0:9b334a45a8ff 763 #define OB ((OB_TypeDef *) OB_BASE)
bogdanm 0:9b334a45a8ff 764 #define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm 0:9b334a45a8ff 765 #define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm 0:9b334a45a8ff 766 #define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm 0:9b334a45a8ff 767 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm 0:9b334a45a8ff 768 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm 0:9b334a45a8ff 769 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm 0:9b334a45a8ff 770 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm 0:9b334a45a8ff 771 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm 0:9b334a45a8ff 772 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm 0:9b334a45a8ff 773 #define USB ((USB_TypeDef *) USB_BASE)
bogdanm 0:9b334a45a8ff 774 /**
bogdanm 0:9b334a45a8ff 775 * @}
bogdanm 0:9b334a45a8ff 776 */
bogdanm 0:9b334a45a8ff 777
bogdanm 0:9b334a45a8ff 778 /** @addtogroup Exported_constants
bogdanm 0:9b334a45a8ff 779 * @{
bogdanm 0:9b334a45a8ff 780 */
bogdanm 0:9b334a45a8ff 781
bogdanm 0:9b334a45a8ff 782 /** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm 0:9b334a45a8ff 783 * @{
bogdanm 0:9b334a45a8ff 784 */
bogdanm 0:9b334a45a8ff 785
bogdanm 0:9b334a45a8ff 786 /******************************************************************************/
bogdanm 0:9b334a45a8ff 787 /* Peripheral Registers Bits Definition */
bogdanm 0:9b334a45a8ff 788 /******************************************************************************/
bogdanm 0:9b334a45a8ff 789 /******************************************************************************/
bogdanm 0:9b334a45a8ff 790 /* */
bogdanm 0:9b334a45a8ff 791 /* Analog to Digital Converter (ADC) */
bogdanm 0:9b334a45a8ff 792 /* */
bogdanm 0:9b334a45a8ff 793 /******************************************************************************/
bogdanm 0:9b334a45a8ff 794 /******************** Bits definition for ADC_ISR register ******************/
bogdanm 0:9b334a45a8ff 795 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
bogdanm 0:9b334a45a8ff 796 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
bogdanm 0:9b334a45a8ff 797 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
bogdanm 0:9b334a45a8ff 798 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
bogdanm 0:9b334a45a8ff 799 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
bogdanm 0:9b334a45a8ff 800 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 /* Old EOSEQ bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 803 #define ADC_ISR_EOS ADC_ISR_EOSEQ
bogdanm 0:9b334a45a8ff 804
bogdanm 0:9b334a45a8ff 805 /******************** Bits definition for ADC_IER register ******************/
bogdanm 0:9b334a45a8ff 806 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
bogdanm 0:9b334a45a8ff 807 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
bogdanm 0:9b334a45a8ff 808 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
bogdanm 0:9b334a45a8ff 809 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
bogdanm 0:9b334a45a8ff 810 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
bogdanm 0:9b334a45a8ff 811 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /* Old EOSEQIE bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 814 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
bogdanm 0:9b334a45a8ff 815
bogdanm 0:9b334a45a8ff 816 /******************** Bits definition for ADC_CR register *******************/
bogdanm 0:9b334a45a8ff 817 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
bogdanm 0:9b334a45a8ff 818 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
bogdanm 0:9b334a45a8ff 819 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
bogdanm 0:9b334a45a8ff 820 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
bogdanm 0:9b334a45a8ff 821 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 /******************* Bits definition for ADC_CFGR1 register *****************/
bogdanm 0:9b334a45a8ff 824 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
bogdanm 0:9b334a45a8ff 825 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 826 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 827 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 828 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 829 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
bogdanm 0:9b334a45a8ff 830 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
bogdanm 0:9b334a45a8ff 831 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
bogdanm 0:9b334a45a8ff 832 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
bogdanm 0:9b334a45a8ff 833 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
bogdanm 0:9b334a45a8ff 834 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
bogdanm 0:9b334a45a8ff 835 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
bogdanm 0:9b334a45a8ff 836 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
bogdanm 0:9b334a45a8ff 837 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
bogdanm 0:9b334a45a8ff 838 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 839 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 840 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
bogdanm 0:9b334a45a8ff 841 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 842 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 843 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 844 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
bogdanm 0:9b334a45a8ff 845 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
bogdanm 0:9b334a45a8ff 846 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 847 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 848 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
bogdanm 0:9b334a45a8ff 849 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
bogdanm 0:9b334a45a8ff 850 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 /* Old WAIT bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 853 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
bogdanm 0:9b334a45a8ff 854
bogdanm 0:9b334a45a8ff 855 /******************* Bits definition for ADC_CFGR2 register *****************/
bogdanm 0:9b334a45a8ff 856 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
bogdanm 0:9b334a45a8ff 857 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
bogdanm 0:9b334a45a8ff 858 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
bogdanm 0:9b334a45a8ff 859
bogdanm 0:9b334a45a8ff 860 /* Old bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 861 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
bogdanm 0:9b334a45a8ff 862 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
bogdanm 0:9b334a45a8ff 863
bogdanm 0:9b334a45a8ff 864 /****************** Bit definition for ADC_SMPR register ********************/
bogdanm 0:9b334a45a8ff 865 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
bogdanm 0:9b334a45a8ff 866 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 867 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 868 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 869
bogdanm 0:9b334a45a8ff 870 /* Old bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 871 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
bogdanm 0:9b334a45a8ff 872 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 873 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 874 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 875
bogdanm 0:9b334a45a8ff 876 /******************* Bit definition for ADC_TR register ********************/
bogdanm 0:9b334a45a8ff 877 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
bogdanm 0:9b334a45a8ff 878 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
bogdanm 0:9b334a45a8ff 879
bogdanm 0:9b334a45a8ff 880 /* Old bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 881 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
bogdanm 0:9b334a45a8ff 882 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
bogdanm 0:9b334a45a8ff 883
bogdanm 0:9b334a45a8ff 884 /****************** Bit definition for ADC_CHSELR register ******************/
bogdanm 0:9b334a45a8ff 885 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
bogdanm 0:9b334a45a8ff 886 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
bogdanm 0:9b334a45a8ff 887 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
bogdanm 0:9b334a45a8ff 888 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
bogdanm 0:9b334a45a8ff 889 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
bogdanm 0:9b334a45a8ff 890 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
bogdanm 0:9b334a45a8ff 891 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
bogdanm 0:9b334a45a8ff 892 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
bogdanm 0:9b334a45a8ff 893 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
bogdanm 0:9b334a45a8ff 894 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
bogdanm 0:9b334a45a8ff 895 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
bogdanm 0:9b334a45a8ff 896 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
bogdanm 0:9b334a45a8ff 897 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
bogdanm 0:9b334a45a8ff 898 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
bogdanm 0:9b334a45a8ff 899 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
bogdanm 0:9b334a45a8ff 900 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
bogdanm 0:9b334a45a8ff 901 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
bogdanm 0:9b334a45a8ff 902 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
bogdanm 0:9b334a45a8ff 903 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
bogdanm 0:9b334a45a8ff 904
bogdanm 0:9b334a45a8ff 905 /******************** Bit definition for ADC_DR register ********************/
bogdanm 0:9b334a45a8ff 906 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
bogdanm 0:9b334a45a8ff 907
bogdanm 0:9b334a45a8ff 908 /******************* Bit definition for ADC_CCR register ********************/
bogdanm 0:9b334a45a8ff 909 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
bogdanm 0:9b334a45a8ff 910 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
bogdanm 0:9b334a45a8ff 911 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 /******************************************************************************/
bogdanm 0:9b334a45a8ff 914 /* */
bogdanm 0:9b334a45a8ff 915 /* Controller Area Network (CAN ) */
bogdanm 0:9b334a45a8ff 916 /* */
bogdanm 0:9b334a45a8ff 917 /******************************************************************************/
bogdanm 0:9b334a45a8ff 918 /*!<CAN control and status registers */
bogdanm 0:9b334a45a8ff 919 /******************* Bit definition for CAN_MCR register ********************/
bogdanm 0:9b334a45a8ff 920 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
bogdanm 0:9b334a45a8ff 921 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
bogdanm 0:9b334a45a8ff 922 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
bogdanm 0:9b334a45a8ff 923 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
bogdanm 0:9b334a45a8ff 924 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
bogdanm 0:9b334a45a8ff 925 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
bogdanm 0:9b334a45a8ff 926 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
bogdanm 0:9b334a45a8ff 927 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
bogdanm 0:9b334a45a8ff 928 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
bogdanm 0:9b334a45a8ff 929
bogdanm 0:9b334a45a8ff 930 /******************* Bit definition for CAN_MSR register ********************/
bogdanm 0:9b334a45a8ff 931 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
bogdanm 0:9b334a45a8ff 932 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
bogdanm 0:9b334a45a8ff 933 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
bogdanm 0:9b334a45a8ff 934 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
bogdanm 0:9b334a45a8ff 935 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
bogdanm 0:9b334a45a8ff 936 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
bogdanm 0:9b334a45a8ff 937 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
bogdanm 0:9b334a45a8ff 938 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
bogdanm 0:9b334a45a8ff 939 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
bogdanm 0:9b334a45a8ff 940
bogdanm 0:9b334a45a8ff 941 /******************* Bit definition for CAN_TSR register ********************/
bogdanm 0:9b334a45a8ff 942 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
bogdanm 0:9b334a45a8ff 943 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
bogdanm 0:9b334a45a8ff 944 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
bogdanm 0:9b334a45a8ff 945 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
bogdanm 0:9b334a45a8ff 946 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
bogdanm 0:9b334a45a8ff 947 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
bogdanm 0:9b334a45a8ff 948 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
bogdanm 0:9b334a45a8ff 949 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
bogdanm 0:9b334a45a8ff 950 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
bogdanm 0:9b334a45a8ff 951 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
bogdanm 0:9b334a45a8ff 952 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
bogdanm 0:9b334a45a8ff 953 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
bogdanm 0:9b334a45a8ff 954 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
bogdanm 0:9b334a45a8ff 955 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
bogdanm 0:9b334a45a8ff 956 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
bogdanm 0:9b334a45a8ff 957 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
bogdanm 0:9b334a45a8ff 958
bogdanm 0:9b334a45a8ff 959 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
bogdanm 0:9b334a45a8ff 960 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
bogdanm 0:9b334a45a8ff 961 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
bogdanm 0:9b334a45a8ff 962 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
bogdanm 0:9b334a45a8ff 963
bogdanm 0:9b334a45a8ff 964 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
bogdanm 0:9b334a45a8ff 965 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
bogdanm 0:9b334a45a8ff 966 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
bogdanm 0:9b334a45a8ff 967 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
bogdanm 0:9b334a45a8ff 968
bogdanm 0:9b334a45a8ff 969 /******************* Bit definition for CAN_RF0R register *******************/
bogdanm 0:9b334a45a8ff 970 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
bogdanm 0:9b334a45a8ff 971 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
bogdanm 0:9b334a45a8ff 972 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
bogdanm 0:9b334a45a8ff 973 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
bogdanm 0:9b334a45a8ff 974
bogdanm 0:9b334a45a8ff 975 /******************* Bit definition for CAN_RF1R register *******************/
bogdanm 0:9b334a45a8ff 976 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
bogdanm 0:9b334a45a8ff 977 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
bogdanm 0:9b334a45a8ff 978 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
bogdanm 0:9b334a45a8ff 979 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
bogdanm 0:9b334a45a8ff 980
bogdanm 0:9b334a45a8ff 981 /******************** Bit definition for CAN_IER register *******************/
bogdanm 0:9b334a45a8ff 982 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 983 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 0:9b334a45a8ff 984 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
bogdanm 0:9b334a45a8ff 985 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
bogdanm 0:9b334a45a8ff 986 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
bogdanm 0:9b334a45a8ff 987 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
bogdanm 0:9b334a45a8ff 988 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
bogdanm 0:9b334a45a8ff 989 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
bogdanm 0:9b334a45a8ff 990 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
bogdanm 0:9b334a45a8ff 991 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
bogdanm 0:9b334a45a8ff 992 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
bogdanm 0:9b334a45a8ff 993 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 994 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
bogdanm 0:9b334a45a8ff 995 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
bogdanm 0:9b334a45a8ff 996
bogdanm 0:9b334a45a8ff 997 /******************** Bit definition for CAN_ESR register *******************/
bogdanm 0:9b334a45a8ff 998 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
bogdanm 0:9b334a45a8ff 999 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
bogdanm 0:9b334a45a8ff 1000 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
bogdanm 0:9b334a45a8ff 1001
bogdanm 0:9b334a45a8ff 1002 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
bogdanm 0:9b334a45a8ff 1003 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 1004 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 1005 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 1006
bogdanm 0:9b334a45a8ff 1007 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
bogdanm 0:9b334a45a8ff 1008 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
bogdanm 0:9b334a45a8ff 1009
bogdanm 0:9b334a45a8ff 1010 /******************* Bit definition for CAN_BTR register ********************/
bogdanm 0:9b334a45a8ff 1011 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
bogdanm 0:9b334a45a8ff 1012 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
bogdanm 0:9b334a45a8ff 1013 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
bogdanm 0:9b334a45a8ff 1014 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
bogdanm 0:9b334a45a8ff 1015 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
bogdanm 0:9b334a45a8ff 1016 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
bogdanm 0:9b334a45a8ff 1017 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
bogdanm 0:9b334a45a8ff 1018 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
bogdanm 0:9b334a45a8ff 1019 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
bogdanm 0:9b334a45a8ff 1020 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
bogdanm 0:9b334a45a8ff 1021 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
bogdanm 0:9b334a45a8ff 1022 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
bogdanm 0:9b334a45a8ff 1023 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
bogdanm 0:9b334a45a8ff 1024 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
bogdanm 0:9b334a45a8ff 1025 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 /*!<Mailbox registers */
bogdanm 0:9b334a45a8ff 1028 /****************** Bit definition for CAN_TI0R register ********************/
bogdanm 0:9b334a45a8ff 1029 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 1030 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1031 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1032 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 1033 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1034
bogdanm 0:9b334a45a8ff 1035 /****************** Bit definition for CAN_TDT0R register *******************/
bogdanm 0:9b334a45a8ff 1036 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1037 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 1038 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1039
bogdanm 0:9b334a45a8ff 1040 /****************** Bit definition for CAN_TDL0R register *******************/
bogdanm 0:9b334a45a8ff 1041 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1042 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1043 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1044 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1045
bogdanm 0:9b334a45a8ff 1046 /****************** Bit definition for CAN_TDH0R register *******************/
bogdanm 0:9b334a45a8ff 1047 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1048 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1049 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1050 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 /******************* Bit definition for CAN_TI1R register *******************/
bogdanm 0:9b334a45a8ff 1053 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 1054 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1055 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1056 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 1057 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1058
bogdanm 0:9b334a45a8ff 1059 /******************* Bit definition for CAN_TDT1R register ******************/
bogdanm 0:9b334a45a8ff 1060 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1061 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 1062 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1063
bogdanm 0:9b334a45a8ff 1064 /******************* Bit definition for CAN_TDL1R register ******************/
bogdanm 0:9b334a45a8ff 1065 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1066 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1067 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1068 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1069
bogdanm 0:9b334a45a8ff 1070 /******************* Bit definition for CAN_TDH1R register ******************/
bogdanm 0:9b334a45a8ff 1071 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1072 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1073 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1074 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1075
bogdanm 0:9b334a45a8ff 1076 /******************* Bit definition for CAN_TI2R register *******************/
bogdanm 0:9b334a45a8ff 1077 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
bogdanm 0:9b334a45a8ff 1078 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1079 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1080 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 0:9b334a45a8ff 1081 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1082
bogdanm 0:9b334a45a8ff 1083 /******************* Bit definition for CAN_TDT2R register ******************/
bogdanm 0:9b334a45a8ff 1084 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1085 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
bogdanm 0:9b334a45a8ff 1086 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1087
bogdanm 0:9b334a45a8ff 1088 /******************* Bit definition for CAN_TDL2R register ******************/
bogdanm 0:9b334a45a8ff 1089 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1090 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1091 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1092 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1093
bogdanm 0:9b334a45a8ff 1094 /******************* Bit definition for CAN_TDH2R register ******************/
bogdanm 0:9b334a45a8ff 1095 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1096 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1097 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1098 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100 /******************* Bit definition for CAN_RI0R register *******************/
bogdanm 0:9b334a45a8ff 1101 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1102 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1103 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
bogdanm 0:9b334a45a8ff 1104 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1105
bogdanm 0:9b334a45a8ff 1106 /******************* Bit definition for CAN_RDT0R register ******************/
bogdanm 0:9b334a45a8ff 1107 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1108 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 0:9b334a45a8ff 1109 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1110
bogdanm 0:9b334a45a8ff 1111 /******************* Bit definition for CAN_RDL0R register ******************/
bogdanm 0:9b334a45a8ff 1112 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1113 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1114 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1115 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1116
bogdanm 0:9b334a45a8ff 1117 /******************* Bit definition for CAN_RDH0R register ******************/
bogdanm 0:9b334a45a8ff 1118 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1119 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1120 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1121 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123 /******************* Bit definition for CAN_RI1R register *******************/
bogdanm 0:9b334a45a8ff 1124 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
bogdanm 0:9b334a45a8ff 1125 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
bogdanm 0:9b334a45a8ff 1126 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
bogdanm 0:9b334a45a8ff 1127 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
bogdanm 0:9b334a45a8ff 1128
bogdanm 0:9b334a45a8ff 1129 /******************* Bit definition for CAN_RDT1R register ******************/
bogdanm 0:9b334a45a8ff 1130 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
bogdanm 0:9b334a45a8ff 1131 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
bogdanm 0:9b334a45a8ff 1132 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
bogdanm 0:9b334a45a8ff 1133
bogdanm 0:9b334a45a8ff 1134 /******************* Bit definition for CAN_RDL1R register ******************/
bogdanm 0:9b334a45a8ff 1135 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
bogdanm 0:9b334a45a8ff 1136 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
bogdanm 0:9b334a45a8ff 1137 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
bogdanm 0:9b334a45a8ff 1138 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
bogdanm 0:9b334a45a8ff 1139
bogdanm 0:9b334a45a8ff 1140 /******************* Bit definition for CAN_RDH1R register ******************/
bogdanm 0:9b334a45a8ff 1141 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
bogdanm 0:9b334a45a8ff 1142 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
bogdanm 0:9b334a45a8ff 1143 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
bogdanm 0:9b334a45a8ff 1144 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
bogdanm 0:9b334a45a8ff 1145
bogdanm 0:9b334a45a8ff 1146 /*!<CAN filter registers */
bogdanm 0:9b334a45a8ff 1147 /******************* Bit definition for CAN_FMR register ********************/
bogdanm 0:9b334a45a8ff 1148 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
bogdanm 0:9b334a45a8ff 1149 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
bogdanm 0:9b334a45a8ff 1150
bogdanm 0:9b334a45a8ff 1151 /******************* Bit definition for CAN_FM1R register *******************/
bogdanm 0:9b334a45a8ff 1152 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
bogdanm 0:9b334a45a8ff 1153 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
bogdanm 0:9b334a45a8ff 1154 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
bogdanm 0:9b334a45a8ff 1155 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
bogdanm 0:9b334a45a8ff 1156 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
bogdanm 0:9b334a45a8ff 1157 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
bogdanm 0:9b334a45a8ff 1158 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
bogdanm 0:9b334a45a8ff 1159 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
bogdanm 0:9b334a45a8ff 1160 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
bogdanm 0:9b334a45a8ff 1161 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
bogdanm 0:9b334a45a8ff 1162 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
bogdanm 0:9b334a45a8ff 1163 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
bogdanm 0:9b334a45a8ff 1164 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
bogdanm 0:9b334a45a8ff 1165 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
bogdanm 0:9b334a45a8ff 1166 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
bogdanm 0:9b334a45a8ff 1167 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
bogdanm 0:9b334a45a8ff 1168 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
bogdanm 0:9b334a45a8ff 1169 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
bogdanm 0:9b334a45a8ff 1170 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
bogdanm 0:9b334a45a8ff 1171 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
bogdanm 0:9b334a45a8ff 1172 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
bogdanm 0:9b334a45a8ff 1173 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
bogdanm 0:9b334a45a8ff 1174 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
bogdanm 0:9b334a45a8ff 1175 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
bogdanm 0:9b334a45a8ff 1176 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
bogdanm 0:9b334a45a8ff 1177 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
bogdanm 0:9b334a45a8ff 1178 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
bogdanm 0:9b334a45a8ff 1179 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
bogdanm 0:9b334a45a8ff 1180 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
bogdanm 0:9b334a45a8ff 1181
bogdanm 0:9b334a45a8ff 1182 /******************* Bit definition for CAN_FS1R register *******************/
bogdanm 0:9b334a45a8ff 1183 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
bogdanm 0:9b334a45a8ff 1184 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
bogdanm 0:9b334a45a8ff 1185 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
bogdanm 0:9b334a45a8ff 1186 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
bogdanm 0:9b334a45a8ff 1187 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
bogdanm 0:9b334a45a8ff 1188 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
bogdanm 0:9b334a45a8ff 1189 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
bogdanm 0:9b334a45a8ff 1190 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
bogdanm 0:9b334a45a8ff 1191 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
bogdanm 0:9b334a45a8ff 1192 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
bogdanm 0:9b334a45a8ff 1193 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
bogdanm 0:9b334a45a8ff 1194 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
bogdanm 0:9b334a45a8ff 1195 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
bogdanm 0:9b334a45a8ff 1196 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
bogdanm 0:9b334a45a8ff 1197 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
bogdanm 0:9b334a45a8ff 1198 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
bogdanm 0:9b334a45a8ff 1199 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
bogdanm 0:9b334a45a8ff 1200 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
bogdanm 0:9b334a45a8ff 1201 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
bogdanm 0:9b334a45a8ff 1202 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
bogdanm 0:9b334a45a8ff 1203 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
bogdanm 0:9b334a45a8ff 1204 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
bogdanm 0:9b334a45a8ff 1205 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
bogdanm 0:9b334a45a8ff 1206 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
bogdanm 0:9b334a45a8ff 1207 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
bogdanm 0:9b334a45a8ff 1208 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
bogdanm 0:9b334a45a8ff 1209 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
bogdanm 0:9b334a45a8ff 1210 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
bogdanm 0:9b334a45a8ff 1211 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
bogdanm 0:9b334a45a8ff 1212
bogdanm 0:9b334a45a8ff 1213 /****************** Bit definition for CAN_FFA1R register *******************/
bogdanm 0:9b334a45a8ff 1214 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
bogdanm 0:9b334a45a8ff 1215 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
bogdanm 0:9b334a45a8ff 1216 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
bogdanm 0:9b334a45a8ff 1217 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
bogdanm 0:9b334a45a8ff 1218 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
bogdanm 0:9b334a45a8ff 1219 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
bogdanm 0:9b334a45a8ff 1220 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
bogdanm 0:9b334a45a8ff 1221 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
bogdanm 0:9b334a45a8ff 1222 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
bogdanm 0:9b334a45a8ff 1223 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
bogdanm 0:9b334a45a8ff 1224 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
bogdanm 0:9b334a45a8ff 1225 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
bogdanm 0:9b334a45a8ff 1226 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
bogdanm 0:9b334a45a8ff 1227 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
bogdanm 0:9b334a45a8ff 1228 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
bogdanm 0:9b334a45a8ff 1229 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
bogdanm 0:9b334a45a8ff 1230 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
bogdanm 0:9b334a45a8ff 1231 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
bogdanm 0:9b334a45a8ff 1232 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
bogdanm 0:9b334a45a8ff 1233 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
bogdanm 0:9b334a45a8ff 1234 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
bogdanm 0:9b334a45a8ff 1235 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
bogdanm 0:9b334a45a8ff 1236 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
bogdanm 0:9b334a45a8ff 1237 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
bogdanm 0:9b334a45a8ff 1238 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
bogdanm 0:9b334a45a8ff 1239 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
bogdanm 0:9b334a45a8ff 1240 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
bogdanm 0:9b334a45a8ff 1241 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
bogdanm 0:9b334a45a8ff 1242 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
bogdanm 0:9b334a45a8ff 1243
bogdanm 0:9b334a45a8ff 1244 /******************* Bit definition for CAN_FA1R register *******************/
bogdanm 0:9b334a45a8ff 1245 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
bogdanm 0:9b334a45a8ff 1246 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
bogdanm 0:9b334a45a8ff 1247 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
bogdanm 0:9b334a45a8ff 1248 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
bogdanm 0:9b334a45a8ff 1249 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
bogdanm 0:9b334a45a8ff 1250 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
bogdanm 0:9b334a45a8ff 1251 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
bogdanm 0:9b334a45a8ff 1252 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
bogdanm 0:9b334a45a8ff 1253 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
bogdanm 0:9b334a45a8ff 1254 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
bogdanm 0:9b334a45a8ff 1255 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
bogdanm 0:9b334a45a8ff 1256 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
bogdanm 0:9b334a45a8ff 1257 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
bogdanm 0:9b334a45a8ff 1258 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
bogdanm 0:9b334a45a8ff 1259 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
bogdanm 0:9b334a45a8ff 1260 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
bogdanm 0:9b334a45a8ff 1261 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
bogdanm 0:9b334a45a8ff 1262 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
bogdanm 0:9b334a45a8ff 1263 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
bogdanm 0:9b334a45a8ff 1264 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
bogdanm 0:9b334a45a8ff 1265 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
bogdanm 0:9b334a45a8ff 1266 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
bogdanm 0:9b334a45a8ff 1267 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
bogdanm 0:9b334a45a8ff 1268 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
bogdanm 0:9b334a45a8ff 1269 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
bogdanm 0:9b334a45a8ff 1270 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
bogdanm 0:9b334a45a8ff 1271 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
bogdanm 0:9b334a45a8ff 1272 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
bogdanm 0:9b334a45a8ff 1273 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
bogdanm 0:9b334a45a8ff 1274
bogdanm 0:9b334a45a8ff 1275 /******************* Bit definition for CAN_F0R1 register *******************/
bogdanm 0:9b334a45a8ff 1276 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1277 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1278 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1279 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1280 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1281 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1282 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1283 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1284 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1285 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1286 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1287 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1288 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1289 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1290 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1291 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1292 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1293 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1294 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1295 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1296 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1297 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1298 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1299 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1300 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1301 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1302 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1303 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1304 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1305 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1306 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1307 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1308
bogdanm 0:9b334a45a8ff 1309 /******************* Bit definition for CAN_F1R1 register *******************/
bogdanm 0:9b334a45a8ff 1310 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1311 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1312 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1313 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1314 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1315 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1316 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1317 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1318 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1319 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1320 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1321 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1322 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1323 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1324 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1325 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1326 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1327 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1328 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1329 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1330 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1331 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1332 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1333 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1334 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1335 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1336 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1337 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1338 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1339 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1340 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1341 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1342
bogdanm 0:9b334a45a8ff 1343 /******************* Bit definition for CAN_F2R1 register *******************/
bogdanm 0:9b334a45a8ff 1344 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1345 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1346 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1347 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1348 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1349 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1350 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1351 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1352 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1353 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1354 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1355 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1356 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1357 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1358 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1359 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1360 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1361 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1362 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1363 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1364 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1365 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1366 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1367 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1368 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1369 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1370 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1371 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1372 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1373 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1374 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1375 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1376
bogdanm 0:9b334a45a8ff 1377 /******************* Bit definition for CAN_F3R1 register *******************/
bogdanm 0:9b334a45a8ff 1378 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1379 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1380 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1381 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1382 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1383 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1384 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1385 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1386 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1387 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1388 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1389 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1390 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1391 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1392 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1393 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1394 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1395 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1396 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1397 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1398 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1399 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1400 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1401 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1402 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1403 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1404 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1405 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1406 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1407 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1408 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1409 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1410
bogdanm 0:9b334a45a8ff 1411 /******************* Bit definition for CAN_F4R1 register *******************/
bogdanm 0:9b334a45a8ff 1412 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1413 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1414 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1415 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1416 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1417 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1418 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1419 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1420 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1421 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1422 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1423 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1424 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1425 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1426 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1427 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1428 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1429 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1430 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1431 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1432 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1433 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1434 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1435 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1436 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1437 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1438 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1439 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1440 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1441 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1442 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1443 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1444
bogdanm 0:9b334a45a8ff 1445 /******************* Bit definition for CAN_F5R1 register *******************/
bogdanm 0:9b334a45a8ff 1446 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1447 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1448 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1449 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1450 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1451 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1452 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1453 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1454 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1455 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1456 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1457 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1458 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1459 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1460 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1461 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1462 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1463 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1464 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1465 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1466 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1467 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1468 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1469 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1470 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1471 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1472 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1473 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1474 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1475 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1476 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1477 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1478
bogdanm 0:9b334a45a8ff 1479 /******************* Bit definition for CAN_F6R1 register *******************/
bogdanm 0:9b334a45a8ff 1480 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1481 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1482 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1483 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1484 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1485 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1486 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1487 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1488 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1489 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1490 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1491 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1492 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1493 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1494 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1495 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1496 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1497 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1498 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1499 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1500 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1501 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1502 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1503 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1504 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1505 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1506 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1507 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1508 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1509 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1510 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1511 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1512
bogdanm 0:9b334a45a8ff 1513 /******************* Bit definition for CAN_F7R1 register *******************/
bogdanm 0:9b334a45a8ff 1514 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1515 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1516 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1517 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1518 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1519 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1520 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1521 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1522 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1523 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1524 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1525 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1526 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1527 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1528 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1529 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1530 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1531 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1532 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1533 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1534 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1535 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1536 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1537 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1538 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1539 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1540 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1541 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1542 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1543 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1544 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1545 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1546
bogdanm 0:9b334a45a8ff 1547 /******************* Bit definition for CAN_F8R1 register *******************/
bogdanm 0:9b334a45a8ff 1548 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1549 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1550 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1551 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1552 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1553 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1554 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1555 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1556 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1557 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1558 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1559 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1560 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1561 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1562 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1563 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1564 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1565 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1566 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1567 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1568 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1569 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1570 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1571 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1572 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1573 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1574 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1575 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1576 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1577 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1578 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1579 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1580
bogdanm 0:9b334a45a8ff 1581 /******************* Bit definition for CAN_F9R1 register *******************/
bogdanm 0:9b334a45a8ff 1582 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1583 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1584 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1585 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1586 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1587 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1588 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1589 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1590 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1591 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1592 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1593 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1594 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1595 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1596 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1597 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1598 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1599 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1600 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1601 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1602 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1603 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1604 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1605 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1606 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1607 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1608 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1609 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1610 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1611 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1612 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1613 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1614
bogdanm 0:9b334a45a8ff 1615 /******************* Bit definition for CAN_F10R1 register ******************/
bogdanm 0:9b334a45a8ff 1616 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1617 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1618 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1619 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1620 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1621 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1622 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1623 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1624 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1625 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1626 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1627 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1628 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1629 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1630 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1631 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1632 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1633 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1634 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1635 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1636 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1637 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1638 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1639 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1640 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1641 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1642 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1643 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1644 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1645 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1646 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1647 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1648
bogdanm 0:9b334a45a8ff 1649 /******************* Bit definition for CAN_F11R1 register ******************/
bogdanm 0:9b334a45a8ff 1650 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1651 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1652 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1653 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1654 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1655 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1656 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1657 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1658 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1659 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1660 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1661 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1662 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1663 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1664 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1665 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1666 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1667 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1668 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1669 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1670 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1671 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1672 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1673 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1674 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1675 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1676 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1677 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1678 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1679 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1680 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1681 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1682
bogdanm 0:9b334a45a8ff 1683 /******************* Bit definition for CAN_F12R1 register ******************/
bogdanm 0:9b334a45a8ff 1684 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1685 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1686 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1687 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1688 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1689 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1690 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1691 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1692 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1693 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1694 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1695 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1696 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1697 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1698 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1699 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1700 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1701 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1702 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1703 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1704 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1705 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1706 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1707 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1708 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1709 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1710 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1711 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1712 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1713 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1714 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1715 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1716
bogdanm 0:9b334a45a8ff 1717 /******************* Bit definition for CAN_F13R1 register ******************/
bogdanm 0:9b334a45a8ff 1718 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1719 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1720 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1721 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1722 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1723 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1724 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1725 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1726 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1727 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1728 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1729 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1730 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1731 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1732 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1733 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1734 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1735 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1736 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1737 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1738 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1739 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1740 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1741 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1742 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1743 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1744 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1745 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1746 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1747 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1748 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1749 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1750
bogdanm 0:9b334a45a8ff 1751 /******************* Bit definition for CAN_F0R2 register *******************/
bogdanm 0:9b334a45a8ff 1752 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1753 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1754 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1755 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1756 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1757 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1758 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1759 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1760 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1761 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1762 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1763 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1764 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1765 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1766 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1767 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1768 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1769 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1770 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1771 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1772 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1773 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1774 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1775 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1776 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1777 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1778 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1779 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1780 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1781 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1782 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1783 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1784
bogdanm 0:9b334a45a8ff 1785 /******************* Bit definition for CAN_F1R2 register *******************/
bogdanm 0:9b334a45a8ff 1786 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1787 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1788 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1789 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1790 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1791 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1792 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1793 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1794 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1795 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1796 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1797 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1798 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1799 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1800 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1801 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1802 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1803 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1804 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1805 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1806 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1807 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1808 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1809 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1810 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1811 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1812 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1813 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1814 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1815 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1816 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1817 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1818
bogdanm 0:9b334a45a8ff 1819 /******************* Bit definition for CAN_F2R2 register *******************/
bogdanm 0:9b334a45a8ff 1820 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1821 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1822 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1823 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1824 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1825 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1826 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1827 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1828 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1829 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1830 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1831 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1832 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1833 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1834 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1835 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1836 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1837 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1838 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1839 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1840 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1841 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1842 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1843 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1844 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1845 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1846 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1847 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1848 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1849 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1850 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1851 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1852
bogdanm 0:9b334a45a8ff 1853 /******************* Bit definition for CAN_F3R2 register *******************/
bogdanm 0:9b334a45a8ff 1854 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1855 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1856 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1857 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1858 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1859 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1860 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1861 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1862 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1863 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1864 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1865 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1866 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1867 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1868 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1869 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1870 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1871 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1872 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1873 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1874 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1875 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1876 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1877 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1878 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1879 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1880 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1881 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1882 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1883 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1884 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1885 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1886
bogdanm 0:9b334a45a8ff 1887 /******************* Bit definition for CAN_F4R2 register *******************/
bogdanm 0:9b334a45a8ff 1888 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1889 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1890 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1891 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1892 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1893 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1894 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1895 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1896 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1897 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1898 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1899 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1900 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1901 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1902 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1903 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1904 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1905 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1906 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1907 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1908 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1909 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1910 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1911 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1912 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1913 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1914 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1915 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1916 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1917 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1918 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1919 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1920
bogdanm 0:9b334a45a8ff 1921 /******************* Bit definition for CAN_F5R2 register *******************/
bogdanm 0:9b334a45a8ff 1922 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1923 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1924 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1925 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1926 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1927 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1928 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1929 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1930 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1931 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1932 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1933 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1934 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1935 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1936 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1937 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1938 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1939 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1940 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1941 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1942 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1943 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1944 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1945 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1946 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1947 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1948 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1949 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1950 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1951 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1952 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1953 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1954
bogdanm 0:9b334a45a8ff 1955 /******************* Bit definition for CAN_F6R2 register *******************/
bogdanm 0:9b334a45a8ff 1956 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1957 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1958 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1959 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1960 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1961 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1962 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1963 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1964 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1965 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 1966 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 1967 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 1968 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 1969 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 1970 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 1971 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 1972 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 1973 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 1974 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 1975 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 1976 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 1977 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 1978 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 1979 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 1980 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 1981 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 1982 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 1983 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 1984 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 1985 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 1986 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 1987 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 1988
bogdanm 0:9b334a45a8ff 1989 /******************* Bit definition for CAN_F7R2 register *******************/
bogdanm 0:9b334a45a8ff 1990 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 1991 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 1992 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 1993 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 1994 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 1995 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 1996 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 1997 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 1998 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 1999 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2000 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2001 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2002 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2003 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2004 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2005 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2006 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2007 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2008 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2009 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2010 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2011 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2012 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2013 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2014 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2015 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2016 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2017 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2018 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2019 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2020 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2021 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2022
bogdanm 0:9b334a45a8ff 2023 /******************* Bit definition for CAN_F8R2 register *******************/
bogdanm 0:9b334a45a8ff 2024 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2025 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2026 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2027 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2028 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2029 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2030 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2031 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2032 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2033 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2034 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2035 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2036 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2037 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2038 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2039 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2040 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2041 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2042 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2043 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2044 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2045 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2046 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2047 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2048 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2049 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2050 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2051 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2052 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2053 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2054 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2055 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2056
bogdanm 0:9b334a45a8ff 2057 /******************* Bit definition for CAN_F9R2 register *******************/
bogdanm 0:9b334a45a8ff 2058 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2059 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2060 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2061 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2062 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2063 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2064 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2065 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2066 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2067 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2068 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2069 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2070 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2071 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2072 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2073 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2074 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2075 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2076 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2077 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2078 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2079 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2080 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2081 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2082 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2083 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2084 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2085 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2086 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2087 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2088 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2089 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2090
bogdanm 0:9b334a45a8ff 2091 /******************* Bit definition for CAN_F10R2 register ******************/
bogdanm 0:9b334a45a8ff 2092 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2093 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2094 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2095 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2096 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2097 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2098 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2099 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2100 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2101 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2102 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2103 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2104 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2105 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2106 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2107 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2108 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2109 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2110 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2111 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2112 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2113 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2114 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2115 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2116 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2117 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2118 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2119 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2120 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2121 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2122 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2123 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2124
bogdanm 0:9b334a45a8ff 2125 /******************* Bit definition for CAN_F11R2 register ******************/
bogdanm 0:9b334a45a8ff 2126 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2127 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2128 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2129 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2130 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2131 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2132 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2133 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2134 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2135 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2136 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2137 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2138 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2139 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2140 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2141 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2142 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2143 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2144 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2145 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2146 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2147 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2148 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2149 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2150 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2151 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2152 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2153 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2154 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2155 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2156 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2157 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2158
bogdanm 0:9b334a45a8ff 2159 /******************* Bit definition for CAN_F12R2 register ******************/
bogdanm 0:9b334a45a8ff 2160 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2161 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2162 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2163 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2164 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2165 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2166 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2167 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2168 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2169 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2170 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2171 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2172 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2173 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2174 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2175 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2176 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2177 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2178 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2179 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2180 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2181 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2182 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2183 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2184 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2185 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2186 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2187 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2188 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2189 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2190 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2191 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2192
bogdanm 0:9b334a45a8ff 2193 /******************* Bit definition for CAN_F13R2 register ******************/
bogdanm 0:9b334a45a8ff 2194 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
bogdanm 0:9b334a45a8ff 2195 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
bogdanm 0:9b334a45a8ff 2196 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
bogdanm 0:9b334a45a8ff 2197 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
bogdanm 0:9b334a45a8ff 2198 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
bogdanm 0:9b334a45a8ff 2199 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
bogdanm 0:9b334a45a8ff 2200 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
bogdanm 0:9b334a45a8ff 2201 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
bogdanm 0:9b334a45a8ff 2202 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
bogdanm 0:9b334a45a8ff 2203 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
bogdanm 0:9b334a45a8ff 2204 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
bogdanm 0:9b334a45a8ff 2205 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
bogdanm 0:9b334a45a8ff 2206 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
bogdanm 0:9b334a45a8ff 2207 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
bogdanm 0:9b334a45a8ff 2208 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
bogdanm 0:9b334a45a8ff 2209 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
bogdanm 0:9b334a45a8ff 2210 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
bogdanm 0:9b334a45a8ff 2211 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
bogdanm 0:9b334a45a8ff 2212 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
bogdanm 0:9b334a45a8ff 2213 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
bogdanm 0:9b334a45a8ff 2214 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
bogdanm 0:9b334a45a8ff 2215 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
bogdanm 0:9b334a45a8ff 2216 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
bogdanm 0:9b334a45a8ff 2217 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
bogdanm 0:9b334a45a8ff 2218 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
bogdanm 0:9b334a45a8ff 2219 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
bogdanm 0:9b334a45a8ff 2220 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
bogdanm 0:9b334a45a8ff 2221 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
bogdanm 0:9b334a45a8ff 2222 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
bogdanm 0:9b334a45a8ff 2223 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
bogdanm 0:9b334a45a8ff 2224 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
bogdanm 0:9b334a45a8ff 2225 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
bogdanm 0:9b334a45a8ff 2226
bogdanm 0:9b334a45a8ff 2227 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2228 /* */
bogdanm 0:9b334a45a8ff 2229 /* HDMI-CEC (CEC) */
bogdanm 0:9b334a45a8ff 2230 /* */
bogdanm 0:9b334a45a8ff 2231 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2232
bogdanm 0:9b334a45a8ff 2233 /******************* Bit definition for CEC_CR register *********************/
bogdanm 0:9b334a45a8ff 2234 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
bogdanm 0:9b334a45a8ff 2235 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
bogdanm 0:9b334a45a8ff 2236 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
bogdanm 0:9b334a45a8ff 2237
bogdanm 0:9b334a45a8ff 2238 /******************* Bit definition for CEC_CFGR register *******************/
bogdanm 0:9b334a45a8ff 2239 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
bogdanm 0:9b334a45a8ff 2240 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
bogdanm 0:9b334a45a8ff 2241 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
bogdanm 0:9b334a45a8ff 2242 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
bogdanm 0:9b334a45a8ff 2243 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
bogdanm 0:9b334a45a8ff 2244 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
bogdanm 0:9b334a45a8ff 2245 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
bogdanm 0:9b334a45a8ff 2246 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
bogdanm 0:9b334a45a8ff 2247 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
bogdanm 0:9b334a45a8ff 2248
bogdanm 0:9b334a45a8ff 2249 /******************* Bit definition for CEC_TXDR register *******************/
bogdanm 0:9b334a45a8ff 2250 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
bogdanm 0:9b334a45a8ff 2251
bogdanm 0:9b334a45a8ff 2252 /******************* Bit definition for CEC_RXDR register *******************/
bogdanm 0:9b334a45a8ff 2253 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
bogdanm 0:9b334a45a8ff 2254
bogdanm 0:9b334a45a8ff 2255 /******************* Bit definition for CEC_ISR register ********************/
bogdanm 0:9b334a45a8ff 2256 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
bogdanm 0:9b334a45a8ff 2257 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
bogdanm 0:9b334a45a8ff 2258 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
bogdanm 0:9b334a45a8ff 2259 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
bogdanm 0:9b334a45a8ff 2260 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
bogdanm 0:9b334a45a8ff 2261 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
bogdanm 0:9b334a45a8ff 2262 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
bogdanm 0:9b334a45a8ff 2263 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
bogdanm 0:9b334a45a8ff 2264 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
bogdanm 0:9b334a45a8ff 2265 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
bogdanm 0:9b334a45a8ff 2266 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
bogdanm 0:9b334a45a8ff 2267 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
bogdanm 0:9b334a45a8ff 2268 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
bogdanm 0:9b334a45a8ff 2269
bogdanm 0:9b334a45a8ff 2270 /******************* Bit definition for CEC_IER register ********************/
bogdanm 0:9b334a45a8ff 2271 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
bogdanm 0:9b334a45a8ff 2272 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
bogdanm 0:9b334a45a8ff 2273 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
bogdanm 0:9b334a45a8ff 2274 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
bogdanm 0:9b334a45a8ff 2275 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
bogdanm 0:9b334a45a8ff 2276 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
bogdanm 0:9b334a45a8ff 2277 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
bogdanm 0:9b334a45a8ff 2278 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
bogdanm 0:9b334a45a8ff 2279 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
bogdanm 0:9b334a45a8ff 2280 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
bogdanm 0:9b334a45a8ff 2281 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
bogdanm 0:9b334a45a8ff 2282 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
bogdanm 0:9b334a45a8ff 2283 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
bogdanm 0:9b334a45a8ff 2284
bogdanm 0:9b334a45a8ff 2285 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2286 /* */
bogdanm 0:9b334a45a8ff 2287 /* Analog Comparators (COMP) */
bogdanm 0:9b334a45a8ff 2288 /* */
bogdanm 0:9b334a45a8ff 2289 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2290 /*********************** Bit definition for COMP_CSR register ***************/
bogdanm 0:9b334a45a8ff 2291 /* COMP1 bits definition */
bogdanm 0:9b334a45a8ff 2292 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
bogdanm 0:9b334a45a8ff 2293 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
bogdanm 0:9b334a45a8ff 2294 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
bogdanm 0:9b334a45a8ff 2295 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
bogdanm 0:9b334a45a8ff 2296 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
bogdanm 0:9b334a45a8ff 2297 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
bogdanm 0:9b334a45a8ff 2298 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
bogdanm 0:9b334a45a8ff 2299 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
bogdanm 0:9b334a45a8ff 2300 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
bogdanm 0:9b334a45a8ff 2301 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
bogdanm 0:9b334a45a8ff 2302 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
bogdanm 0:9b334a45a8ff 2303 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
bogdanm 0:9b334a45a8ff 2304 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
bogdanm 0:9b334a45a8ff 2305 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
bogdanm 0:9b334a45a8ff 2306 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
bogdanm 0:9b334a45a8ff 2307 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
bogdanm 0:9b334a45a8ff 2308 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
bogdanm 0:9b334a45a8ff 2309 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
bogdanm 0:9b334a45a8ff 2310 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
bogdanm 0:9b334a45a8ff 2311 /* COMP2 bits definition */
bogdanm 0:9b334a45a8ff 2312 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
bogdanm 0:9b334a45a8ff 2313 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
bogdanm 0:9b334a45a8ff 2314 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
bogdanm 0:9b334a45a8ff 2315 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
bogdanm 0:9b334a45a8ff 2316 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
bogdanm 0:9b334a45a8ff 2317 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
bogdanm 0:9b334a45a8ff 2318 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
bogdanm 0:9b334a45a8ff 2319 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
bogdanm 0:9b334a45a8ff 2320 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
bogdanm 0:9b334a45a8ff 2321 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
bogdanm 0:9b334a45a8ff 2322 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
bogdanm 0:9b334a45a8ff 2323 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
bogdanm 0:9b334a45a8ff 2324 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
bogdanm 0:9b334a45a8ff 2325 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
bogdanm 0:9b334a45a8ff 2326 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
bogdanm 0:9b334a45a8ff 2327 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
bogdanm 0:9b334a45a8ff 2328 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
bogdanm 0:9b334a45a8ff 2329 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
bogdanm 0:9b334a45a8ff 2330 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
bogdanm 0:9b334a45a8ff 2331 /* COMPx bits definition */
bogdanm 0:9b334a45a8ff 2332 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
bogdanm 0:9b334a45a8ff 2333 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
bogdanm 0:9b334a45a8ff 2334 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
bogdanm 0:9b334a45a8ff 2335 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
bogdanm 0:9b334a45a8ff 2336 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
bogdanm 0:9b334a45a8ff 2337 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
bogdanm 0:9b334a45a8ff 2338 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
bogdanm 0:9b334a45a8ff 2339 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
bogdanm 0:9b334a45a8ff 2340 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
bogdanm 0:9b334a45a8ff 2341 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
bogdanm 0:9b334a45a8ff 2342 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
bogdanm 0:9b334a45a8ff 2343 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
bogdanm 0:9b334a45a8ff 2344 #define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
bogdanm 0:9b334a45a8ff 2345 #define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
bogdanm 0:9b334a45a8ff 2346 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
bogdanm 0:9b334a45a8ff 2347 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
bogdanm 0:9b334a45a8ff 2348 #define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
bogdanm 0:9b334a45a8ff 2349 #define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
bogdanm 0:9b334a45a8ff 2350
bogdanm 0:9b334a45a8ff 2351 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2352 /* */
bogdanm 0:9b334a45a8ff 2353 /* CRC calculation unit (CRC) */
bogdanm 0:9b334a45a8ff 2354 /* */
bogdanm 0:9b334a45a8ff 2355 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2356 /******************* Bit definition for CRC_DR register *********************/
bogdanm 0:9b334a45a8ff 2357 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
bogdanm 0:9b334a45a8ff 2358
bogdanm 0:9b334a45a8ff 2359 /******************* Bit definition for CRC_IDR register ********************/
bogdanm 0:9b334a45a8ff 2360 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
bogdanm 0:9b334a45a8ff 2361
bogdanm 0:9b334a45a8ff 2362 /******************** Bit definition for CRC_CR register ********************/
bogdanm 0:9b334a45a8ff 2363 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
bogdanm 0:9b334a45a8ff 2364 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
bogdanm 0:9b334a45a8ff 2365 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
bogdanm 0:9b334a45a8ff 2366 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
bogdanm 0:9b334a45a8ff 2367 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
bogdanm 0:9b334a45a8ff 2368 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
bogdanm 0:9b334a45a8ff 2369 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
bogdanm 0:9b334a45a8ff 2370 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
bogdanm 0:9b334a45a8ff 2371
bogdanm 0:9b334a45a8ff 2372 /******************* Bit definition for CRC_INIT register *******************/
bogdanm 0:9b334a45a8ff 2373 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
bogdanm 0:9b334a45a8ff 2374
bogdanm 0:9b334a45a8ff 2375 /******************* Bit definition for CRC_POL register ********************/
bogdanm 0:9b334a45a8ff 2376 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
bogdanm 0:9b334a45a8ff 2377
bogdanm 0:9b334a45a8ff 2378 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2379 /* */
bogdanm 0:9b334a45a8ff 2380 /* CRS Clock Recovery System */
bogdanm 0:9b334a45a8ff 2381 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2382
bogdanm 0:9b334a45a8ff 2383 /******************* Bit definition for CRS_CR register *********************/
bogdanm 0:9b334a45a8ff 2384 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
bogdanm 0:9b334a45a8ff 2385 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
bogdanm 0:9b334a45a8ff 2386 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
bogdanm 0:9b334a45a8ff 2387 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
bogdanm 0:9b334a45a8ff 2388 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
bogdanm 0:9b334a45a8ff 2389 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
bogdanm 0:9b334a45a8ff 2390 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
bogdanm 0:9b334a45a8ff 2391 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
bogdanm 0:9b334a45a8ff 2392
bogdanm 0:9b334a45a8ff 2393 /******************* Bit definition for CRS_CFGR register *********************/
bogdanm 0:9b334a45a8ff 2394 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
bogdanm 0:9b334a45a8ff 2395 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
bogdanm 0:9b334a45a8ff 2396
bogdanm 0:9b334a45a8ff 2397 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
bogdanm 0:9b334a45a8ff 2398 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
bogdanm 0:9b334a45a8ff 2399 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
bogdanm 0:9b334a45a8ff 2400 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
bogdanm 0:9b334a45a8ff 2401
bogdanm 0:9b334a45a8ff 2402 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
bogdanm 0:9b334a45a8ff 2403 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
bogdanm 0:9b334a45a8ff 2404 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
bogdanm 0:9b334a45a8ff 2405
bogdanm 0:9b334a45a8ff 2406 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
bogdanm 0:9b334a45a8ff 2407
bogdanm 0:9b334a45a8ff 2408 /******************* Bit definition for CRS_ISR register *********************/
bogdanm 0:9b334a45a8ff 2409 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
bogdanm 0:9b334a45a8ff 2410 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
bogdanm 0:9b334a45a8ff 2411 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
bogdanm 0:9b334a45a8ff 2412 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
bogdanm 0:9b334a45a8ff 2413 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
bogdanm 0:9b334a45a8ff 2414 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
bogdanm 0:9b334a45a8ff 2415 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
bogdanm 0:9b334a45a8ff 2416 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
bogdanm 0:9b334a45a8ff 2417 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
bogdanm 0:9b334a45a8ff 2418
bogdanm 0:9b334a45a8ff 2419 /******************* Bit definition for CRS_ICR register *********************/
bogdanm 0:9b334a45a8ff 2420 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
bogdanm 0:9b334a45a8ff 2421 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
bogdanm 0:9b334a45a8ff 2422 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
bogdanm 0:9b334a45a8ff 2423 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
bogdanm 0:9b334a45a8ff 2424
bogdanm 0:9b334a45a8ff 2425 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2426 /* */
bogdanm 0:9b334a45a8ff 2427 /* Digital to Analog Converter (DAC) */
bogdanm 0:9b334a45a8ff 2428 /* */
bogdanm 0:9b334a45a8ff 2429 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2430 /******************** Bit definition for DAC_CR register ********************/
bogdanm 0:9b334a45a8ff 2431 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
bogdanm 0:9b334a45a8ff 2432 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
bogdanm 0:9b334a45a8ff 2433 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
bogdanm 0:9b334a45a8ff 2434
bogdanm 0:9b334a45a8ff 2435 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
bogdanm 0:9b334a45a8ff 2436 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2437 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2438 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 2439
bogdanm 0:9b334a45a8ff 2440 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
bogdanm 0:9b334a45a8ff 2441 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2442 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2443
bogdanm 0:9b334a45a8ff 2444 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
bogdanm 0:9b334a45a8ff 2445 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2446 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2447 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 2448 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 2449
bogdanm 0:9b334a45a8ff 2450 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
bogdanm 0:9b334a45a8ff 2451 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
bogdanm 0:9b334a45a8ff 2452
bogdanm 0:9b334a45a8ff 2453 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
bogdanm 0:9b334a45a8ff 2454 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
bogdanm 0:9b334a45a8ff 2455 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
bogdanm 0:9b334a45a8ff 2456
bogdanm 0:9b334a45a8ff 2457 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
bogdanm 0:9b334a45a8ff 2458 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2459 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2460 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 2461
bogdanm 0:9b334a45a8ff 2462 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
bogdanm 0:9b334a45a8ff 2463 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2464 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2465
bogdanm 0:9b334a45a8ff 2466 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
bogdanm 0:9b334a45a8ff 2467 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2468 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2469 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 2470 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 2471
bogdanm 0:9b334a45a8ff 2472 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
bogdanm 0:9b334a45a8ff 2473 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
bogdanm 0:9b334a45a8ff 2474
bogdanm 0:9b334a45a8ff 2475 /***************** Bit definition for DAC_SWTRIGR register ******************/
bogdanm 0:9b334a45a8ff 2476 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
bogdanm 0:9b334a45a8ff 2477 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
bogdanm 0:9b334a45a8ff 2478
bogdanm 0:9b334a45a8ff 2479 /***************** Bit definition for DAC_DHR12R1 register ******************/
bogdanm 0:9b334a45a8ff 2480 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2481
bogdanm 0:9b334a45a8ff 2482 /***************** Bit definition for DAC_DHR12L1 register ******************/
bogdanm 0:9b334a45a8ff 2483 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 2484
bogdanm 0:9b334a45a8ff 2485 /****************** Bit definition for DAC_DHR8R1 register ******************/
bogdanm 0:9b334a45a8ff 2486 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2487
bogdanm 0:9b334a45a8ff 2488 /***************** Bit definition for DAC_DHR12R2 register ******************/
bogdanm 0:9b334a45a8ff 2489 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2490
bogdanm 0:9b334a45a8ff 2491 /***************** Bit definition for DAC_DHR12L2 register ******************/
bogdanm 0:9b334a45a8ff 2492 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 2493
bogdanm 0:9b334a45a8ff 2494 /****************** Bit definition for DAC_DHR8R2 register ******************/
bogdanm 0:9b334a45a8ff 2495 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2496
bogdanm 0:9b334a45a8ff 2497 /***************** Bit definition for DAC_DHR12RD register ******************/
bogdanm 0:9b334a45a8ff 2498 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2499 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2500
bogdanm 0:9b334a45a8ff 2501 /***************** Bit definition for DAC_DHR12LD register ******************/
bogdanm 0:9b334a45a8ff 2502 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 2503 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
bogdanm 0:9b334a45a8ff 2504
bogdanm 0:9b334a45a8ff 2505 /****************** Bit definition for DAC_DHR8RD register ******************/
bogdanm 0:9b334a45a8ff 2506 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2507 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
bogdanm 0:9b334a45a8ff 2508
bogdanm 0:9b334a45a8ff 2509 /******************* Bit definition for DAC_DOR1 register *******************/
bogdanm 0:9b334a45a8ff 2510 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
bogdanm 0:9b334a45a8ff 2511
bogdanm 0:9b334a45a8ff 2512 /******************* Bit definition for DAC_DOR2 register *******************/
bogdanm 0:9b334a45a8ff 2513 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
bogdanm 0:9b334a45a8ff 2514
bogdanm 0:9b334a45a8ff 2515 /******************** Bit definition for DAC_SR register ********************/
bogdanm 0:9b334a45a8ff 2516 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
bogdanm 0:9b334a45a8ff 2517 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
bogdanm 0:9b334a45a8ff 2518
bogdanm 0:9b334a45a8ff 2519 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2520 /* */
bogdanm 0:9b334a45a8ff 2521 /* Debug MCU (DBGMCU) */
bogdanm 0:9b334a45a8ff 2522 /* */
bogdanm 0:9b334a45a8ff 2523 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2524
bogdanm 0:9b334a45a8ff 2525 /**************** Bit definition for DBGMCU_IDCODE register *****************/
bogdanm 0:9b334a45a8ff 2526 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
bogdanm 0:9b334a45a8ff 2527
bogdanm 0:9b334a45a8ff 2528 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
bogdanm 0:9b334a45a8ff 2529 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2530 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2531 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 2532 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 2533 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 0:9b334a45a8ff 2534 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
bogdanm 0:9b334a45a8ff 2535 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
bogdanm 0:9b334a45a8ff 2536 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
bogdanm 0:9b334a45a8ff 2537 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
bogdanm 0:9b334a45a8ff 2538 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
bogdanm 0:9b334a45a8ff 2539 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
bogdanm 0:9b334a45a8ff 2540 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
bogdanm 0:9b334a45a8ff 2541 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
bogdanm 0:9b334a45a8ff 2542 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
bogdanm 0:9b334a45a8ff 2543 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
bogdanm 0:9b334a45a8ff 2544 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
bogdanm 0:9b334a45a8ff 2545
bogdanm 0:9b334a45a8ff 2546 /****************** Bit definition for DBGMCU_CR register *******************/
bogdanm 0:9b334a45a8ff 2547 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
bogdanm 0:9b334a45a8ff 2548 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
bogdanm 0:9b334a45a8ff 2549
bogdanm 0:9b334a45a8ff 2550 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
bogdanm 0:9b334a45a8ff 2551 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2552 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2553 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2554 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2555 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2556 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
bogdanm 0:9b334a45a8ff 2557 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
bogdanm 0:9b334a45a8ff 2558 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
bogdanm 0:9b334a45a8ff 2559 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
bogdanm 0:9b334a45a8ff 2560 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
bogdanm 0:9b334a45a8ff 2561
bogdanm 0:9b334a45a8ff 2562 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
bogdanm 0:9b334a45a8ff 2563 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2564 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2565 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2566 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
bogdanm 0:9b334a45a8ff 2567
bogdanm 0:9b334a45a8ff 2568 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2569 /* */
bogdanm 0:9b334a45a8ff 2570 /* DMA Controller (DMA) */
bogdanm 0:9b334a45a8ff 2571 /* */
bogdanm 0:9b334a45a8ff 2572 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2573 /******************* Bit definition for DMA_ISR register ********************/
bogdanm 0:9b334a45a8ff 2574 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
bogdanm 0:9b334a45a8ff 2575 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 2576 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
bogdanm 0:9b334a45a8ff 2577 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
bogdanm 0:9b334a45a8ff 2578 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
bogdanm 0:9b334a45a8ff 2579 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 2580 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
bogdanm 0:9b334a45a8ff 2581 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
bogdanm 0:9b334a45a8ff 2582 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
bogdanm 0:9b334a45a8ff 2583 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 2584 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
bogdanm 0:9b334a45a8ff 2585 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
bogdanm 0:9b334a45a8ff 2586 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
bogdanm 0:9b334a45a8ff 2587 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 2588 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
bogdanm 0:9b334a45a8ff 2589 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
bogdanm 0:9b334a45a8ff 2590 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
bogdanm 0:9b334a45a8ff 2591 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 2592 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
bogdanm 0:9b334a45a8ff 2593 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
bogdanm 0:9b334a45a8ff 2594 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
bogdanm 0:9b334a45a8ff 2595 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 2596 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
bogdanm 0:9b334a45a8ff 2597 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
bogdanm 0:9b334a45a8ff 2598 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
bogdanm 0:9b334a45a8ff 2599 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
bogdanm 0:9b334a45a8ff 2600 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
bogdanm 0:9b334a45a8ff 2601 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
bogdanm 0:9b334a45a8ff 2602
bogdanm 0:9b334a45a8ff 2603 /******************* Bit definition for DMA_IFCR register *******************/
bogdanm 0:9b334a45a8ff 2604 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
bogdanm 0:9b334a45a8ff 2605 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 2606 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
bogdanm 0:9b334a45a8ff 2607 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
bogdanm 0:9b334a45a8ff 2608 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
bogdanm 0:9b334a45a8ff 2609 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 2610 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
bogdanm 0:9b334a45a8ff 2611 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
bogdanm 0:9b334a45a8ff 2612 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
bogdanm 0:9b334a45a8ff 2613 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 2614 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
bogdanm 0:9b334a45a8ff 2615 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
bogdanm 0:9b334a45a8ff 2616 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
bogdanm 0:9b334a45a8ff 2617 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 2618 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
bogdanm 0:9b334a45a8ff 2619 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
bogdanm 0:9b334a45a8ff 2620 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
bogdanm 0:9b334a45a8ff 2621 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 2622 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
bogdanm 0:9b334a45a8ff 2623 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
bogdanm 0:9b334a45a8ff 2624 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
bogdanm 0:9b334a45a8ff 2625 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 2626 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
bogdanm 0:9b334a45a8ff 2627 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
bogdanm 0:9b334a45a8ff 2628 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
bogdanm 0:9b334a45a8ff 2629 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
bogdanm 0:9b334a45a8ff 2630 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
bogdanm 0:9b334a45a8ff 2631 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
bogdanm 0:9b334a45a8ff 2632
bogdanm 0:9b334a45a8ff 2633 /******************* Bit definition for DMA_CCR register ********************/
bogdanm 0:9b334a45a8ff 2634 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
bogdanm 0:9b334a45a8ff 2635 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
bogdanm 0:9b334a45a8ff 2636 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
bogdanm 0:9b334a45a8ff 2637 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
bogdanm 0:9b334a45a8ff 2638 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
bogdanm 0:9b334a45a8ff 2639 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
bogdanm 0:9b334a45a8ff 2640 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
bogdanm 0:9b334a45a8ff 2641 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
bogdanm 0:9b334a45a8ff 2642
bogdanm 0:9b334a45a8ff 2643 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
bogdanm 0:9b334a45a8ff 2644 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2645 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2646
bogdanm 0:9b334a45a8ff 2647 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
bogdanm 0:9b334a45a8ff 2648 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2649 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2650
bogdanm 0:9b334a45a8ff 2651 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
bogdanm 0:9b334a45a8ff 2652 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 2653 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 2654
bogdanm 0:9b334a45a8ff 2655 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
bogdanm 0:9b334a45a8ff 2656
bogdanm 0:9b334a45a8ff 2657 /****************** Bit definition for DMA_CNDTR register *******************/
bogdanm 0:9b334a45a8ff 2658 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
bogdanm 0:9b334a45a8ff 2659
bogdanm 0:9b334a45a8ff 2660 /****************** Bit definition for DMA_CPAR register ********************/
bogdanm 0:9b334a45a8ff 2661 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
bogdanm 0:9b334a45a8ff 2662
bogdanm 0:9b334a45a8ff 2663 /****************** Bit definition for DMA_CMAR register ********************/
bogdanm 0:9b334a45a8ff 2664 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
bogdanm 0:9b334a45a8ff 2665
bogdanm 0:9b334a45a8ff 2666 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2667 /* */
bogdanm 0:9b334a45a8ff 2668 /* External Interrupt/Event Controller (EXTI) */
bogdanm 0:9b334a45a8ff 2669 /* */
bogdanm 0:9b334a45a8ff 2670 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2671 /******************* Bit definition for EXTI_IMR register *******************/
bogdanm 0:9b334a45a8ff 2672 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
bogdanm 0:9b334a45a8ff 2673 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
bogdanm 0:9b334a45a8ff 2674 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
bogdanm 0:9b334a45a8ff 2675 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
bogdanm 0:9b334a45a8ff 2676 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
bogdanm 0:9b334a45a8ff 2677 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
bogdanm 0:9b334a45a8ff 2678 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
bogdanm 0:9b334a45a8ff 2679 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
bogdanm 0:9b334a45a8ff 2680 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
bogdanm 0:9b334a45a8ff 2681 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
bogdanm 0:9b334a45a8ff 2682 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
bogdanm 0:9b334a45a8ff 2683 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
bogdanm 0:9b334a45a8ff 2684 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
bogdanm 0:9b334a45a8ff 2685 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
bogdanm 0:9b334a45a8ff 2686 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
bogdanm 0:9b334a45a8ff 2687 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
bogdanm 0:9b334a45a8ff 2688 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
bogdanm 0:9b334a45a8ff 2689 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
bogdanm 0:9b334a45a8ff 2690 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
bogdanm 0:9b334a45a8ff 2691 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
bogdanm 0:9b334a45a8ff 2692 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
bogdanm 0:9b334a45a8ff 2693 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
bogdanm 0:9b334a45a8ff 2694 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
bogdanm 0:9b334a45a8ff 2695 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
bogdanm 0:9b334a45a8ff 2696 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 - reserved */
bogdanm 0:9b334a45a8ff 2697 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
bogdanm 0:9b334a45a8ff 2698 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
bogdanm 0:9b334a45a8ff 2699 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
bogdanm 0:9b334a45a8ff 2700 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 - reserved */
bogdanm 0:9b334a45a8ff 2701 #define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 - reserved */
bogdanm 0:9b334a45a8ff 2702 #define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 - reserved */
bogdanm 0:9b334a45a8ff 2703 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
bogdanm 0:9b334a45a8ff 2704
bogdanm 0:9b334a45a8ff 2705 /****************** Bit definition for EXTI_EMR register ********************/
bogdanm 0:9b334a45a8ff 2706 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
bogdanm 0:9b334a45a8ff 2707 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
bogdanm 0:9b334a45a8ff 2708 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
bogdanm 0:9b334a45a8ff 2709 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
bogdanm 0:9b334a45a8ff 2710 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
bogdanm 0:9b334a45a8ff 2711 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
bogdanm 0:9b334a45a8ff 2712 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
bogdanm 0:9b334a45a8ff 2713 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
bogdanm 0:9b334a45a8ff 2714 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
bogdanm 0:9b334a45a8ff 2715 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
bogdanm 0:9b334a45a8ff 2716 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
bogdanm 0:9b334a45a8ff 2717 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
bogdanm 0:9b334a45a8ff 2718 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
bogdanm 0:9b334a45a8ff 2719 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
bogdanm 0:9b334a45a8ff 2720 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
bogdanm 0:9b334a45a8ff 2721 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
bogdanm 0:9b334a45a8ff 2722 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
bogdanm 0:9b334a45a8ff 2723 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
bogdanm 0:9b334a45a8ff 2724 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
bogdanm 0:9b334a45a8ff 2725 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
bogdanm 0:9b334a45a8ff 2726 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
bogdanm 0:9b334a45a8ff 2727 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
bogdanm 0:9b334a45a8ff 2728 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
bogdanm 0:9b334a45a8ff 2729 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
bogdanm 0:9b334a45a8ff 2730 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 - reserved */
bogdanm 0:9b334a45a8ff 2731 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
bogdanm 0:9b334a45a8ff 2732 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
bogdanm 0:9b334a45a8ff 2733 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
bogdanm 0:9b334a45a8ff 2734 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 - reserved */
bogdanm 0:9b334a45a8ff 2735 #define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 - reserved */
bogdanm 0:9b334a45a8ff 2736 #define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 - reserved */
bogdanm 0:9b334a45a8ff 2737 #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
bogdanm 0:9b334a45a8ff 2738
bogdanm 0:9b334a45a8ff 2739 /******************* Bit definition for EXTI_RTSR register ******************/
bogdanm 0:9b334a45a8ff 2740 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
bogdanm 0:9b334a45a8ff 2741 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
bogdanm 0:9b334a45a8ff 2742 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
bogdanm 0:9b334a45a8ff 2743 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
bogdanm 0:9b334a45a8ff 2744 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
bogdanm 0:9b334a45a8ff 2745 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
bogdanm 0:9b334a45a8ff 2746 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
bogdanm 0:9b334a45a8ff 2747 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
bogdanm 0:9b334a45a8ff 2748 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
bogdanm 0:9b334a45a8ff 2749 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
bogdanm 0:9b334a45a8ff 2750 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
bogdanm 0:9b334a45a8ff 2751 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
bogdanm 0:9b334a45a8ff 2752 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
bogdanm 0:9b334a45a8ff 2753 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
bogdanm 0:9b334a45a8ff 2754 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
bogdanm 0:9b334a45a8ff 2755 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
bogdanm 0:9b334a45a8ff 2756 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
bogdanm 0:9b334a45a8ff 2757 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
bogdanm 0:9b334a45a8ff 2758 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
bogdanm 0:9b334a45a8ff 2759 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
bogdanm 0:9b334a45a8ff 2760 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
bogdanm 0:9b334a45a8ff 2761 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
bogdanm 0:9b334a45a8ff 2762
bogdanm 0:9b334a45a8ff 2763 /******************* Bit definition for EXTI_FTSR register *******************/
bogdanm 0:9b334a45a8ff 2764 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
bogdanm 0:9b334a45a8ff 2765 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
bogdanm 0:9b334a45a8ff 2766 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
bogdanm 0:9b334a45a8ff 2767 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
bogdanm 0:9b334a45a8ff 2768 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
bogdanm 0:9b334a45a8ff 2769 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
bogdanm 0:9b334a45a8ff 2770 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
bogdanm 0:9b334a45a8ff 2771 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
bogdanm 0:9b334a45a8ff 2772 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
bogdanm 0:9b334a45a8ff 2773 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
bogdanm 0:9b334a45a8ff 2774 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
bogdanm 0:9b334a45a8ff 2775 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
bogdanm 0:9b334a45a8ff 2776 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
bogdanm 0:9b334a45a8ff 2777 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
bogdanm 0:9b334a45a8ff 2778 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
bogdanm 0:9b334a45a8ff 2779 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
bogdanm 0:9b334a45a8ff 2780 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
bogdanm 0:9b334a45a8ff 2781 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
bogdanm 0:9b334a45a8ff 2782 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
bogdanm 0:9b334a45a8ff 2783 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
bogdanm 0:9b334a45a8ff 2784 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
bogdanm 0:9b334a45a8ff 2785 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
bogdanm 0:9b334a45a8ff 2786
bogdanm 0:9b334a45a8ff 2787 /******************* Bit definition for EXTI_SWIER register *******************/
bogdanm 0:9b334a45a8ff 2788 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
bogdanm 0:9b334a45a8ff 2789 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
bogdanm 0:9b334a45a8ff 2790 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
bogdanm 0:9b334a45a8ff 2791 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
bogdanm 0:9b334a45a8ff 2792 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
bogdanm 0:9b334a45a8ff 2793 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
bogdanm 0:9b334a45a8ff 2794 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
bogdanm 0:9b334a45a8ff 2795 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
bogdanm 0:9b334a45a8ff 2796 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
bogdanm 0:9b334a45a8ff 2797 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
bogdanm 0:9b334a45a8ff 2798 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
bogdanm 0:9b334a45a8ff 2799 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
bogdanm 0:9b334a45a8ff 2800 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
bogdanm 0:9b334a45a8ff 2801 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
bogdanm 0:9b334a45a8ff 2802 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
bogdanm 0:9b334a45a8ff 2803 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
bogdanm 0:9b334a45a8ff 2804 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
bogdanm 0:9b334a45a8ff 2805 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
bogdanm 0:9b334a45a8ff 2806 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
bogdanm 0:9b334a45a8ff 2807 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
bogdanm 0:9b334a45a8ff 2808 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
bogdanm 0:9b334a45a8ff 2809 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
bogdanm 0:9b334a45a8ff 2810
bogdanm 0:9b334a45a8ff 2811 /****************** Bit definition for EXTI_PR register *********************/
bogdanm 0:9b334a45a8ff 2812 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
bogdanm 0:9b334a45a8ff 2813 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
bogdanm 0:9b334a45a8ff 2814 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
bogdanm 0:9b334a45a8ff 2815 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
bogdanm 0:9b334a45a8ff 2816 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
bogdanm 0:9b334a45a8ff 2817 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
bogdanm 0:9b334a45a8ff 2818 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
bogdanm 0:9b334a45a8ff 2819 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
bogdanm 0:9b334a45a8ff 2820 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
bogdanm 0:9b334a45a8ff 2821 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
bogdanm 0:9b334a45a8ff 2822 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
bogdanm 0:9b334a45a8ff 2823 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
bogdanm 0:9b334a45a8ff 2824 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
bogdanm 0:9b334a45a8ff 2825 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
bogdanm 0:9b334a45a8ff 2826 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
bogdanm 0:9b334a45a8ff 2827 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
bogdanm 0:9b334a45a8ff 2828 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
bogdanm 0:9b334a45a8ff 2829 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
bogdanm 0:9b334a45a8ff 2830 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
bogdanm 0:9b334a45a8ff 2831 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
bogdanm 0:9b334a45a8ff 2832 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
bogdanm 0:9b334a45a8ff 2833 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
bogdanm 0:9b334a45a8ff 2834
bogdanm 0:9b334a45a8ff 2835 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2836 /* */
bogdanm 0:9b334a45a8ff 2837 /* FLASH and Option Bytes Registers */
bogdanm 0:9b334a45a8ff 2838 /* */
bogdanm 0:9b334a45a8ff 2839 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2840
bogdanm 0:9b334a45a8ff 2841 /******************* Bit definition for FLASH_ACR register ******************/
bogdanm 0:9b334a45a8ff 2842 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
bogdanm 0:9b334a45a8ff 2843
bogdanm 0:9b334a45a8ff 2844 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
bogdanm 0:9b334a45a8ff 2845 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
bogdanm 0:9b334a45a8ff 2846
bogdanm 0:9b334a45a8ff 2847 /****************** Bit definition for FLASH_KEYR register ******************/
bogdanm 0:9b334a45a8ff 2848 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
bogdanm 0:9b334a45a8ff 2849
bogdanm 0:9b334a45a8ff 2850 /***************** Bit definition for FLASH_OPTKEYR register ****************/
bogdanm 0:9b334a45a8ff 2851 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
bogdanm 0:9b334a45a8ff 2852
bogdanm 0:9b334a45a8ff 2853 /****************** FLASH Keys **********************************************/
bogdanm 0:9b334a45a8ff 2854 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
bogdanm 0:9b334a45a8ff 2855 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
bogdanm 0:9b334a45a8ff 2856 to unlock the write access to the FPEC. */
bogdanm 0:9b334a45a8ff 2857
bogdanm 0:9b334a45a8ff 2858 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
bogdanm 0:9b334a45a8ff 2859 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
bogdanm 0:9b334a45a8ff 2860 unlock the write access to the option byte block */
bogdanm 0:9b334a45a8ff 2861
bogdanm 0:9b334a45a8ff 2862 /****************** Bit definition for FLASH_SR register *******************/
bogdanm 0:9b334a45a8ff 2863 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
bogdanm 0:9b334a45a8ff 2864 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
bogdanm 0:9b334a45a8ff 2865 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
bogdanm 0:9b334a45a8ff 2866 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
bogdanm 0:9b334a45a8ff 2867 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
bogdanm 0:9b334a45a8ff 2868
bogdanm 0:9b334a45a8ff 2869 /******************* Bit definition for FLASH_CR register *******************/
bogdanm 0:9b334a45a8ff 2870 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
bogdanm 0:9b334a45a8ff 2871 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
bogdanm 0:9b334a45a8ff 2872 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
bogdanm 0:9b334a45a8ff 2873 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
bogdanm 0:9b334a45a8ff 2874 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
bogdanm 0:9b334a45a8ff 2875 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
bogdanm 0:9b334a45a8ff 2876 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
bogdanm 0:9b334a45a8ff 2877 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
bogdanm 0:9b334a45a8ff 2878 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 2879 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
bogdanm 0:9b334a45a8ff 2880 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
bogdanm 0:9b334a45a8ff 2881
bogdanm 0:9b334a45a8ff 2882 /******************* Bit definition for FLASH_AR register *******************/
bogdanm 0:9b334a45a8ff 2883 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
bogdanm 0:9b334a45a8ff 2884
bogdanm 0:9b334a45a8ff 2885 /****************** Bit definition for FLASH_OBR register *******************/
bogdanm 0:9b334a45a8ff 2886 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
bogdanm 0:9b334a45a8ff 2887 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
bogdanm 0:9b334a45a8ff 2888 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
bogdanm 0:9b334a45a8ff 2889
bogdanm 0:9b334a45a8ff 2890 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
bogdanm 0:9b334a45a8ff 2891 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
bogdanm 0:9b334a45a8ff 2892 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
bogdanm 0:9b334a45a8ff 2893 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
bogdanm 0:9b334a45a8ff 2894 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
bogdanm 0:9b334a45a8ff 2895 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
bogdanm 0:9b334a45a8ff 2896 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
bogdanm 0:9b334a45a8ff 2897
bogdanm 0:9b334a45a8ff 2898 /* Old BOOT1 bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 2899 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
bogdanm 0:9b334a45a8ff 2900
bogdanm 0:9b334a45a8ff 2901 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 2902 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
bogdanm 0:9b334a45a8ff 2903
bogdanm 0:9b334a45a8ff 2904 /****************** Bit definition for FLASH_WRPR register ******************/
bogdanm 0:9b334a45a8ff 2905 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
bogdanm 0:9b334a45a8ff 2906
bogdanm 0:9b334a45a8ff 2907 /*----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 2908
bogdanm 0:9b334a45a8ff 2909 /****************** Bit definition for OB_RDP register **********************/
bogdanm 0:9b334a45a8ff 2910 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
bogdanm 0:9b334a45a8ff 2911 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
bogdanm 0:9b334a45a8ff 2912
bogdanm 0:9b334a45a8ff 2913 /****************** Bit definition for OB_USER register *********************/
bogdanm 0:9b334a45a8ff 2914 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
bogdanm 0:9b334a45a8ff 2915 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
bogdanm 0:9b334a45a8ff 2916
bogdanm 0:9b334a45a8ff 2917 /****************** Bit definition for OB_WRP0 register *********************/
bogdanm 0:9b334a45a8ff 2918 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 2919 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 2920
bogdanm 0:9b334a45a8ff 2921 /****************** Bit definition for OB_WRP1 register *********************/
bogdanm 0:9b334a45a8ff 2922 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 2923 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 2924
bogdanm 0:9b334a45a8ff 2925 /****************** Bit definition for OB_WRP2 register *********************/
bogdanm 0:9b334a45a8ff 2926 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 2927 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 2928
bogdanm 0:9b334a45a8ff 2929 /****************** Bit definition for OB_WRP3 register *********************/
bogdanm 0:9b334a45a8ff 2930 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
bogdanm 0:9b334a45a8ff 2931 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
bogdanm 0:9b334a45a8ff 2932
bogdanm 0:9b334a45a8ff 2933 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2934 /* */
bogdanm 0:9b334a45a8ff 2935 /* General Purpose IOs (GPIO) */
bogdanm 0:9b334a45a8ff 2936 /* */
bogdanm 0:9b334a45a8ff 2937 /******************************************************************************/
bogdanm 0:9b334a45a8ff 2938 /******************* Bit definition for GPIO_MODER register *****************/
bogdanm 0:9b334a45a8ff 2939 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 2940 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 2941 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 2942 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 2943 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 2944 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 2945 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 2946 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 2947 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 2948 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 2949 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 2950 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 2951 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 2952 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 2953 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 2954 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 2955 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 2956 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 2957 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 2958 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 2959 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 2960 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 2961 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 2962 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 2963 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 2964 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 2965 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 2966 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 2967 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 2968 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 2969 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 2970 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 2971 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 2972 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 2973 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 2974 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 2975 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 2976 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 2977 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 2978 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 2979 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 2980 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 2981 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 2982 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 2983 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 2984 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 2985 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 2986 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 2987
bogdanm 0:9b334a45a8ff 2988 /****************** Bit definition for GPIO_OTYPER register *****************/
bogdanm 0:9b334a45a8ff 2989 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 2990 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 2991 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 2992 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 2993 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 2994 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 2995 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 2996 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 2997 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 2998 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 2999 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3000 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3001 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3002 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3003 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3004 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3005
bogdanm 0:9b334a45a8ff 3006 /**************** Bit definition for GPIO_OSPEEDR register ******************/
bogdanm 0:9b334a45a8ff 3007 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 3008 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3009 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3010 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 3011 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3012 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3013 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 3014 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3015 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3016 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 3017 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3018 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3019 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 3020 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3021 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3022 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 3023 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3024 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3025 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 3026 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3027 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3028 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 3029 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3030 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3031 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 3032 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3033 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3034 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 3035 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3036 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3037 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 3038 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3039 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3040 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 3041 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3042 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3043 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 3044 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3045 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3046 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 3047 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3048 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3049 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 3050 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3051 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3052 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 3053 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3054 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3055
bogdanm 0:9b334a45a8ff 3056 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 3057 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
bogdanm 0:9b334a45a8ff 3058 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
bogdanm 0:9b334a45a8ff 3059 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
bogdanm 0:9b334a45a8ff 3060 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
bogdanm 0:9b334a45a8ff 3061 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
bogdanm 0:9b334a45a8ff 3062 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
bogdanm 0:9b334a45a8ff 3063 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
bogdanm 0:9b334a45a8ff 3064 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
bogdanm 0:9b334a45a8ff 3065 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
bogdanm 0:9b334a45a8ff 3066 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
bogdanm 0:9b334a45a8ff 3067 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
bogdanm 0:9b334a45a8ff 3068 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
bogdanm 0:9b334a45a8ff 3069 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
bogdanm 0:9b334a45a8ff 3070 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
bogdanm 0:9b334a45a8ff 3071 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
bogdanm 0:9b334a45a8ff 3072 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
bogdanm 0:9b334a45a8ff 3073 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
bogdanm 0:9b334a45a8ff 3074 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
bogdanm 0:9b334a45a8ff 3075 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
bogdanm 0:9b334a45a8ff 3076 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
bogdanm 0:9b334a45a8ff 3077 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
bogdanm 0:9b334a45a8ff 3078 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
bogdanm 0:9b334a45a8ff 3079 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
bogdanm 0:9b334a45a8ff 3080 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
bogdanm 0:9b334a45a8ff 3081 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
bogdanm 0:9b334a45a8ff 3082 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
bogdanm 0:9b334a45a8ff 3083 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
bogdanm 0:9b334a45a8ff 3084 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
bogdanm 0:9b334a45a8ff 3085 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
bogdanm 0:9b334a45a8ff 3086 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
bogdanm 0:9b334a45a8ff 3087 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
bogdanm 0:9b334a45a8ff 3088 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
bogdanm 0:9b334a45a8ff 3089 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
bogdanm 0:9b334a45a8ff 3090 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
bogdanm 0:9b334a45a8ff 3091 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
bogdanm 0:9b334a45a8ff 3092 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
bogdanm 0:9b334a45a8ff 3093 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
bogdanm 0:9b334a45a8ff 3094 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
bogdanm 0:9b334a45a8ff 3095 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
bogdanm 0:9b334a45a8ff 3096 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
bogdanm 0:9b334a45a8ff 3097 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
bogdanm 0:9b334a45a8ff 3098 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
bogdanm 0:9b334a45a8ff 3099 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
bogdanm 0:9b334a45a8ff 3100 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
bogdanm 0:9b334a45a8ff 3101 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
bogdanm 0:9b334a45a8ff 3102 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
bogdanm 0:9b334a45a8ff 3103 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
bogdanm 0:9b334a45a8ff 3104 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
bogdanm 0:9b334a45a8ff 3105
bogdanm 0:9b334a45a8ff 3106 /******************* Bit definition for GPIO_PUPDR register ******************/
bogdanm 0:9b334a45a8ff 3107 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm 0:9b334a45a8ff 3108 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3109 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3110 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm 0:9b334a45a8ff 3111 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3112 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3113 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 3114 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3115 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3116 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm 0:9b334a45a8ff 3117 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3118 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3119 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm 0:9b334a45a8ff 3120 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3121 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3122 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm 0:9b334a45a8ff 3123 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3124 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3125 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm 0:9b334a45a8ff 3126 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3127 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3128 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm 0:9b334a45a8ff 3129 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3130 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3131 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm 0:9b334a45a8ff 3132 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3133 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3134 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm 0:9b334a45a8ff 3135 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3136 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3137 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 3138 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3139 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3140 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm 0:9b334a45a8ff 3141 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3142 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3143 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm 0:9b334a45a8ff 3144 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3145 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3146 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm 0:9b334a45a8ff 3147 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3148 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3149 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 3150 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3151 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3152 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm 0:9b334a45a8ff 3153 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3154 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3155
bogdanm 0:9b334a45a8ff 3156 /******************* Bit definition for GPIO_IDR register *******************/
bogdanm 0:9b334a45a8ff 3157 #define GPIO_IDR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3158 #define GPIO_IDR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3159 #define GPIO_IDR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3160 #define GPIO_IDR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3161 #define GPIO_IDR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3162 #define GPIO_IDR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3163 #define GPIO_IDR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3164 #define GPIO_IDR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3165 #define GPIO_IDR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3166 #define GPIO_IDR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3167 #define GPIO_IDR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3168 #define GPIO_IDR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3169 #define GPIO_IDR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3170 #define GPIO_IDR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3171 #define GPIO_IDR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3172 #define GPIO_IDR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3173
bogdanm 0:9b334a45a8ff 3174 /****************** Bit definition for GPIO_ODR register ********************/
bogdanm 0:9b334a45a8ff 3175 #define GPIO_ODR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3176 #define GPIO_ODR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3177 #define GPIO_ODR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3178 #define GPIO_ODR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3179 #define GPIO_ODR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3180 #define GPIO_ODR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3181 #define GPIO_ODR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3182 #define GPIO_ODR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3183 #define GPIO_ODR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3184 #define GPIO_ODR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3185 #define GPIO_ODR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3186 #define GPIO_ODR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3187 #define GPIO_ODR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3188 #define GPIO_ODR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3189 #define GPIO_ODR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3190 #define GPIO_ODR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3191
bogdanm 0:9b334a45a8ff 3192 /****************** Bit definition for GPIO_BSRR register ********************/
bogdanm 0:9b334a45a8ff 3193 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3194 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3195 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3196 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3197 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3198 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3199 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3200 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3201 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3202 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3203 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3204 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3205 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3206 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3207 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3208 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3209 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3210 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3211 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3212 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3213 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3214 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3215 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3216 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3217 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3218 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3219 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3220 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3221 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3222 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3223 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3224 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3225
bogdanm 0:9b334a45a8ff 3226 /****************** Bit definition for GPIO_LCKR register ********************/
bogdanm 0:9b334a45a8ff 3227 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3228 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3229 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3230 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3231 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3232 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3233 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3234 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3235 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3236 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3237 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3238 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3239 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3240 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3241 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3242 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3243 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3244
bogdanm 0:9b334a45a8ff 3245 /****************** Bit definition for GPIO_AFRL register ********************/
bogdanm 0:9b334a45a8ff 3246 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3247 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
bogdanm 0:9b334a45a8ff 3248 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 3249 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
bogdanm 0:9b334a45a8ff 3250 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 3251 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
bogdanm 0:9b334a45a8ff 3252 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 3253 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
bogdanm 0:9b334a45a8ff 3254
bogdanm 0:9b334a45a8ff 3255 /****************** Bit definition for GPIO_AFRH register ********************/
bogdanm 0:9b334a45a8ff 3256 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3257 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
bogdanm 0:9b334a45a8ff 3258 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 3259 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
bogdanm 0:9b334a45a8ff 3260 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 3261 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
bogdanm 0:9b334a45a8ff 3262 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 3263 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
bogdanm 0:9b334a45a8ff 3264
bogdanm 0:9b334a45a8ff 3265 /****************** Bit definition for GPIO_BRR register *********************/
bogdanm 0:9b334a45a8ff 3266 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3267 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3268 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3269 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3270 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3271 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3272 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3273 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3274 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3275 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3276 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3277 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3278 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3279 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3280 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3281 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3282
bogdanm 0:9b334a45a8ff 3283 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3284 /* */
bogdanm 0:9b334a45a8ff 3285 /* Inter-integrated Circuit Interface (I2C) */
bogdanm 0:9b334a45a8ff 3286 /* */
bogdanm 0:9b334a45a8ff 3287 /******************************************************************************/
bogdanm 0:9b334a45a8ff 3288
bogdanm 0:9b334a45a8ff 3289 /******************* Bit definition for I2C_CR1 register *******************/
bogdanm 0:9b334a45a8ff 3290 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
bogdanm 0:9b334a45a8ff 3291 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
bogdanm 0:9b334a45a8ff 3292 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
bogdanm 0:9b334a45a8ff 3293 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
bogdanm 0:9b334a45a8ff 3294 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
bogdanm 0:9b334a45a8ff 3295 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
bogdanm 0:9b334a45a8ff 3296 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
bogdanm 0:9b334a45a8ff 3297 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
bogdanm 0:9b334a45a8ff 3298 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
bogdanm 0:9b334a45a8ff 3299 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
bogdanm 0:9b334a45a8ff 3300 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
bogdanm 0:9b334a45a8ff 3301 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
bogdanm 0:9b334a45a8ff 3302 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
bogdanm 0:9b334a45a8ff 3303 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
bogdanm 0:9b334a45a8ff 3304 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
bogdanm 0:9b334a45a8ff 3305 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
bogdanm 0:9b334a45a8ff 3306 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
bogdanm 0:9b334a45a8ff 3307 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
bogdanm 0:9b334a45a8ff 3308 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
bogdanm 0:9b334a45a8ff 3309 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
bogdanm 0:9b334a45a8ff 3310 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
bogdanm 0:9b334a45a8ff 3311
bogdanm 0:9b334a45a8ff 3312 /****************** Bit definition for I2C_CR2 register ********************/
bogdanm 0:9b334a45a8ff 3313 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
bogdanm 0:9b334a45a8ff 3314 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
bogdanm 0:9b334a45a8ff 3315 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
bogdanm 0:9b334a45a8ff 3316 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
bogdanm 0:9b334a45a8ff 3317 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
bogdanm 0:9b334a45a8ff 3318 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
bogdanm 0:9b334a45a8ff 3319 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
bogdanm 0:9b334a45a8ff 3320 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
bogdanm 0:9b334a45a8ff 3321 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
bogdanm 0:9b334a45a8ff 3322 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
bogdanm 0:9b334a45a8ff 3323 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
bogdanm 0:9b334a45a8ff 3324
bogdanm 0:9b334a45a8ff 3325 /******************* Bit definition for I2C_OAR1 register ******************/
bogdanm 0:9b334a45a8ff 3326 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
bogdanm 0:9b334a45a8ff 3327 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
bogdanm 0:9b334a45a8ff 3328 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
bogdanm 0:9b334a45a8ff 3329
bogdanm 0:9b334a45a8ff 3330 /******************* Bit definition for I2C_OAR2 register ******************/
bogdanm 0:9b334a45a8ff 3331 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
bogdanm 0:9b334a45a8ff 3332 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
bogdanm 0:9b334a45a8ff 3333 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
bogdanm 0:9b334a45a8ff 3334
bogdanm 0:9b334a45a8ff 3335 /******************* Bit definition for I2C_TIMINGR register ****************/
bogdanm 0:9b334a45a8ff 3336 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
bogdanm 0:9b334a45a8ff 3337 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
bogdanm 0:9b334a45a8ff 3338 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
bogdanm 0:9b334a45a8ff 3339 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
bogdanm 0:9b334a45a8ff 3340 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
bogdanm 0:9b334a45a8ff 3341
bogdanm 0:9b334a45a8ff 3342 /******************* Bit definition for I2C_TIMEOUTR register ****************/
bogdanm 0:9b334a45a8ff 3343 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
bogdanm 0:9b334a45a8ff 3344 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
bogdanm 0:9b334a45a8ff 3345 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
bogdanm 0:9b334a45a8ff 3346 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
bogdanm 0:9b334a45a8ff 3347 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
bogdanm 0:9b334a45a8ff 3348
bogdanm 0:9b334a45a8ff 3349 /****************** Bit definition for I2C_ISR register ********************/
bogdanm 0:9b334a45a8ff 3350 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
bogdanm 0:9b334a45a8ff 3351 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
bogdanm 0:9b334a45a8ff 3352 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
bogdanm 0:9b334a45a8ff 3353 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
bogdanm 0:9b334a45a8ff 3354 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
bogdanm 0:9b334a45a8ff 3355 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
bogdanm 0:9b334a45a8ff 3356 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
bogdanm 0:9b334a45a8ff 3357 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
bogdanm 0:9b334a45a8ff 3358 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
bogdanm 0:9b334a45a8ff 3359 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
bogdanm 0:9b334a45a8ff 3360 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
bogdanm 0:9b334a45a8ff 3361 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
bogdanm 0:9b334a45a8ff 3362 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
bogdanm 0:9b334a45a8ff 3363 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
bogdanm 0:9b334a45a8ff 3364 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
bogdanm 0:9b334a45a8ff 3365 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
bogdanm 0:9b334a45a8ff 3366 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
bogdanm 0:9b334a45a8ff 3367
bogdanm 0:9b334a45a8ff 3368 /****************** Bit definition for I2C_ICR register ********************/
bogdanm 0:9b334a45a8ff 3369 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
bogdanm 0:9b334a45a8ff 3370 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
bogdanm 0:9b334a45a8ff 3371 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
bogdanm 0:9b334a45a8ff 3372 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
bogdanm 0:9b334a45a8ff 3373 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
bogdanm 0:9b334a45a8ff 3374 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
bogdanm 0:9b334a45a8ff 3375 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
bogdanm 0:9b334a45a8ff 3376 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
bogdanm 0:9b334a45a8ff 3377 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
bogdanm 0:9b334a45a8ff 3378
bogdanm 0:9b334a45a8ff 3379 /****************** Bit definition for I2C_PECR register *******************/
bogdanm 0:9b334a45a8ff 3380 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
bogdanm 0:9b334a45a8ff 3381
bogdanm 0:9b334a45a8ff 3382 /****************** Bit definition for I2C_RXDR register *********************/
bogdanm 0:9b334a45a8ff 3383 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
bogdanm 0:9b334a45a8ff 3384
bogdanm 0:9b334a45a8ff 3385 /****************** Bit definition for I2C_TXDR register *******************/
bogdanm 0:9b334a45a8ff 3386 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
bogdanm 0:9b334a45a8ff 3387
bogdanm 0:9b334a45a8ff 3388 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3389 /* */
bogdanm 0:9b334a45a8ff 3390 /* Independent WATCHDOG (IWDG) */
bogdanm 0:9b334a45a8ff 3391 /* */
bogdanm 0:9b334a45a8ff 3392 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3393 /******************* Bit definition for IWDG_KR register *******************/
bogdanm 0:9b334a45a8ff 3394 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
bogdanm 0:9b334a45a8ff 3395
bogdanm 0:9b334a45a8ff 3396 /******************* Bit definition for IWDG_PR register *******************/
bogdanm 0:9b334a45a8ff 3397 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
bogdanm 0:9b334a45a8ff 3398 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3399 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3400 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3401
bogdanm 0:9b334a45a8ff 3402 /******************* Bit definition for IWDG_RLR register ******************/
bogdanm 0:9b334a45a8ff 3403 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
bogdanm 0:9b334a45a8ff 3404
bogdanm 0:9b334a45a8ff 3405 /******************* Bit definition for IWDG_SR register *******************/
bogdanm 0:9b334a45a8ff 3406 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
bogdanm 0:9b334a45a8ff 3407 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
bogdanm 0:9b334a45a8ff 3408 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
bogdanm 0:9b334a45a8ff 3409
bogdanm 0:9b334a45a8ff 3410 /******************* Bit definition for IWDG_KR register *******************/
bogdanm 0:9b334a45a8ff 3411 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
bogdanm 0:9b334a45a8ff 3412
bogdanm 0:9b334a45a8ff 3413 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3414 /* */
bogdanm 0:9b334a45a8ff 3415 /* Power Control (PWR) */
bogdanm 0:9b334a45a8ff 3416 /* */
bogdanm 0:9b334a45a8ff 3417 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3418
bogdanm 0:9b334a45a8ff 3419 /******************** Bit definition for PWR_CR register *******************/
bogdanm 0:9b334a45a8ff 3420 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
bogdanm 0:9b334a45a8ff 3421 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
bogdanm 0:9b334a45a8ff 3422 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
bogdanm 0:9b334a45a8ff 3423 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
bogdanm 0:9b334a45a8ff 3424 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
bogdanm 0:9b334a45a8ff 3425
bogdanm 0:9b334a45a8ff 3426 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
bogdanm 0:9b334a45a8ff 3427 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3428 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3429 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3430
bogdanm 0:9b334a45a8ff 3431 /*!< PVD level configuration */
bogdanm 0:9b334a45a8ff 3432 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
bogdanm 0:9b334a45a8ff 3433 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
bogdanm 0:9b334a45a8ff 3434 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
bogdanm 0:9b334a45a8ff 3435 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
bogdanm 0:9b334a45a8ff 3436 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
bogdanm 0:9b334a45a8ff 3437 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
bogdanm 0:9b334a45a8ff 3438 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
bogdanm 0:9b334a45a8ff 3439 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
bogdanm 0:9b334a45a8ff 3440
bogdanm 0:9b334a45a8ff 3441 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
bogdanm 0:9b334a45a8ff 3442
bogdanm 0:9b334a45a8ff 3443 /******************* Bit definition for PWR_CSR register *******************/
bogdanm 0:9b334a45a8ff 3444 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
bogdanm 0:9b334a45a8ff 3445 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
bogdanm 0:9b334a45a8ff 3446 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
bogdanm 0:9b334a45a8ff 3447 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
bogdanm 0:9b334a45a8ff 3448
bogdanm 0:9b334a45a8ff 3449 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
bogdanm 0:9b334a45a8ff 3450 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
bogdanm 0:9b334a45a8ff 3451 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
bogdanm 0:9b334a45a8ff 3452 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
bogdanm 0:9b334a45a8ff 3453 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
bogdanm 0:9b334a45a8ff 3454 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
bogdanm 0:9b334a45a8ff 3455 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
bogdanm 0:9b334a45a8ff 3456 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
bogdanm 0:9b334a45a8ff 3457
bogdanm 0:9b334a45a8ff 3458 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3459 /* */
bogdanm 0:9b334a45a8ff 3460 /* Reset and Clock Control */
bogdanm 0:9b334a45a8ff 3461 /* */
bogdanm 0:9b334a45a8ff 3462 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3463
bogdanm 0:9b334a45a8ff 3464 /******************** Bit definition for RCC_CR register *******************/
bogdanm 0:9b334a45a8ff 3465 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
bogdanm 0:9b334a45a8ff 3466 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
bogdanm 0:9b334a45a8ff 3467
bogdanm 0:9b334a45a8ff 3468 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
bogdanm 0:9b334a45a8ff 3469 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3470 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3471 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3472 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3473 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 3474
bogdanm 0:9b334a45a8ff 3475 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
bogdanm 0:9b334a45a8ff 3476 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 3477 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 3478 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 3479 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 3480 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 3481 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 3482 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 3483 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 3484
bogdanm 0:9b334a45a8ff 3485 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
bogdanm 0:9b334a45a8ff 3486 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
bogdanm 0:9b334a45a8ff 3487 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
bogdanm 0:9b334a45a8ff 3488 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
bogdanm 0:9b334a45a8ff 3489 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
bogdanm 0:9b334a45a8ff 3490 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
bogdanm 0:9b334a45a8ff 3491
bogdanm 0:9b334a45a8ff 3492 /******************** Bit definition for RCC_CFGR register *****************/
bogdanm 0:9b334a45a8ff 3493 /*!< SW configuration */
bogdanm 0:9b334a45a8ff 3494 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
bogdanm 0:9b334a45a8ff 3495 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3496 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3497
bogdanm 0:9b334a45a8ff 3498 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
bogdanm 0:9b334a45a8ff 3499 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
bogdanm 0:9b334a45a8ff 3500 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
bogdanm 0:9b334a45a8ff 3501 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
bogdanm 0:9b334a45a8ff 3502
bogdanm 0:9b334a45a8ff 3503 /*!< SWS configuration */
bogdanm 0:9b334a45a8ff 3504 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
bogdanm 0:9b334a45a8ff 3505 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3506 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3507
bogdanm 0:9b334a45a8ff 3508 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
bogdanm 0:9b334a45a8ff 3509 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
bogdanm 0:9b334a45a8ff 3510 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
bogdanm 0:9b334a45a8ff 3511 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
bogdanm 0:9b334a45a8ff 3512
bogdanm 0:9b334a45a8ff 3513 /*!< HPRE configuration */
bogdanm 0:9b334a45a8ff 3514 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
bogdanm 0:9b334a45a8ff 3515 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3516 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3517 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3518 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 3519
bogdanm 0:9b334a45a8ff 3520 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
bogdanm 0:9b334a45a8ff 3521 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
bogdanm 0:9b334a45a8ff 3522 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
bogdanm 0:9b334a45a8ff 3523 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
bogdanm 0:9b334a45a8ff 3524 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
bogdanm 0:9b334a45a8ff 3525 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
bogdanm 0:9b334a45a8ff 3526 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
bogdanm 0:9b334a45a8ff 3527 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
bogdanm 0:9b334a45a8ff 3528 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
bogdanm 0:9b334a45a8ff 3529
bogdanm 0:9b334a45a8ff 3530 /*!< PPRE configuration */
bogdanm 0:9b334a45a8ff 3531 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
bogdanm 0:9b334a45a8ff 3532 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3533 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3534 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3535
bogdanm 0:9b334a45a8ff 3536 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
bogdanm 0:9b334a45a8ff 3537 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
bogdanm 0:9b334a45a8ff 3538 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
bogdanm 0:9b334a45a8ff 3539 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
bogdanm 0:9b334a45a8ff 3540 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
bogdanm 0:9b334a45a8ff 3541
bogdanm 0:9b334a45a8ff 3542 /*!< ADCPPRE configuration */
bogdanm 0:9b334a45a8ff 3543 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
bogdanm 0:9b334a45a8ff 3544
bogdanm 0:9b334a45a8ff 3545 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
bogdanm 0:9b334a45a8ff 3546 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
bogdanm 0:9b334a45a8ff 3547
bogdanm 0:9b334a45a8ff 3548 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
bogdanm 0:9b334a45a8ff 3549 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
bogdanm 0:9b334a45a8ff 3550 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
bogdanm 0:9b334a45a8ff 3551 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
bogdanm 0:9b334a45a8ff 3552 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
bogdanm 0:9b334a45a8ff 3553
bogdanm 0:9b334a45a8ff 3554 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
bogdanm 0:9b334a45a8ff 3555 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
bogdanm 0:9b334a45a8ff 3556 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
bogdanm 0:9b334a45a8ff 3557
bogdanm 0:9b334a45a8ff 3558 /*!< PLLMUL configuration */
bogdanm 0:9b334a45a8ff 3559 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
bogdanm 0:9b334a45a8ff 3560 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3561 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3562 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3563 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 3564
bogdanm 0:9b334a45a8ff 3565 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
bogdanm 0:9b334a45a8ff 3566 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
bogdanm 0:9b334a45a8ff 3567 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
bogdanm 0:9b334a45a8ff 3568 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
bogdanm 0:9b334a45a8ff 3569 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
bogdanm 0:9b334a45a8ff 3570 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
bogdanm 0:9b334a45a8ff 3571 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
bogdanm 0:9b334a45a8ff 3572 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
bogdanm 0:9b334a45a8ff 3573 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
bogdanm 0:9b334a45a8ff 3574 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
bogdanm 0:9b334a45a8ff 3575 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
bogdanm 0:9b334a45a8ff 3576 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
bogdanm 0:9b334a45a8ff 3577 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
bogdanm 0:9b334a45a8ff 3578 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
bogdanm 0:9b334a45a8ff 3579 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
bogdanm 0:9b334a45a8ff 3580
bogdanm 0:9b334a45a8ff 3581 /*!< USB configuration */
bogdanm 0:9b334a45a8ff 3582 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
bogdanm 0:9b334a45a8ff 3583
bogdanm 0:9b334a45a8ff 3584 /*!< MCO configuration */
bogdanm 0:9b334a45a8ff 3585 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
bogdanm 0:9b334a45a8ff 3586 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3587 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3588 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3589 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 3590
bogdanm 0:9b334a45a8ff 3591 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 0:9b334a45a8ff 3592 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
bogdanm 0:9b334a45a8ff 3593 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
bogdanm 0:9b334a45a8ff 3594 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
bogdanm 0:9b334a45a8ff 3595 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
bogdanm 0:9b334a45a8ff 3596 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
bogdanm 0:9b334a45a8ff 3597 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
bogdanm 0:9b334a45a8ff 3598 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
bogdanm 0:9b334a45a8ff 3599 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
bogdanm 0:9b334a45a8ff 3600
bogdanm 0:9b334a45a8ff 3601 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
bogdanm 0:9b334a45a8ff 3602 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
bogdanm 0:9b334a45a8ff 3603 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
bogdanm 0:9b334a45a8ff 3604 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
bogdanm 0:9b334a45a8ff 3605 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
bogdanm 0:9b334a45a8ff 3606 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
bogdanm 0:9b334a45a8ff 3607 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
bogdanm 0:9b334a45a8ff 3608 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
bogdanm 0:9b334a45a8ff 3609 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
bogdanm 0:9b334a45a8ff 3610
bogdanm 0:9b334a45a8ff 3611 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
bogdanm 0:9b334a45a8ff 3612
bogdanm 0:9b334a45a8ff 3613 /*!<****************** Bit definition for RCC_CIR register *****************/
bogdanm 0:9b334a45a8ff 3614 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 3615 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 3616 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 3617 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 3618 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 3619 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 3620 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
bogdanm 0:9b334a45a8ff 3621 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
bogdanm 0:9b334a45a8ff 3622 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 3623 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 3624 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 3625 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 3626 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 3627 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 3628 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
bogdanm 0:9b334a45a8ff 3629 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 3630 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 3631 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 3632 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 3633 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 3634 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 3635 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
bogdanm 0:9b334a45a8ff 3636 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
bogdanm 0:9b334a45a8ff 3637
bogdanm 0:9b334a45a8ff 3638 /***************** Bit definition for RCC_APB2RSTR register ****************/
bogdanm 0:9b334a45a8ff 3639 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
bogdanm 0:9b334a45a8ff 3640 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
bogdanm 0:9b334a45a8ff 3641 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
bogdanm 0:9b334a45a8ff 3642 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
bogdanm 0:9b334a45a8ff 3643 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
bogdanm 0:9b334a45a8ff 3644 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
bogdanm 0:9b334a45a8ff 3645 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
bogdanm 0:9b334a45a8ff 3646 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
bogdanm 0:9b334a45a8ff 3647 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
bogdanm 0:9b334a45a8ff 3648
bogdanm 0:9b334a45a8ff 3649 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 3650 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
bogdanm 0:9b334a45a8ff 3651
bogdanm 0:9b334a45a8ff 3652 /***************** Bit definition for RCC_APB1RSTR register ****************/
bogdanm 0:9b334a45a8ff 3653 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
bogdanm 0:9b334a45a8ff 3654 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
bogdanm 0:9b334a45a8ff 3655 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
bogdanm 0:9b334a45a8ff 3656 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
bogdanm 0:9b334a45a8ff 3657 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
bogdanm 0:9b334a45a8ff 3658 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
bogdanm 0:9b334a45a8ff 3659 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
bogdanm 0:9b334a45a8ff 3660 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
bogdanm 0:9b334a45a8ff 3661 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
bogdanm 0:9b334a45a8ff 3662 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
bogdanm 0:9b334a45a8ff 3663 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
bogdanm 0:9b334a45a8ff 3664 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
bogdanm 0:9b334a45a8ff 3665 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
bogdanm 0:9b334a45a8ff 3666 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
bogdanm 0:9b334a45a8ff 3667 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
bogdanm 0:9b334a45a8ff 3668 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
bogdanm 0:9b334a45a8ff 3669 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
bogdanm 0:9b334a45a8ff 3670 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
bogdanm 0:9b334a45a8ff 3671
bogdanm 0:9b334a45a8ff 3672 /****************** Bit definition for RCC_AHBENR register *****************/
bogdanm 0:9b334a45a8ff 3673 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
bogdanm 0:9b334a45a8ff 3674 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
bogdanm 0:9b334a45a8ff 3675 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
bogdanm 0:9b334a45a8ff 3676 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
bogdanm 0:9b334a45a8ff 3677 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
bogdanm 0:9b334a45a8ff 3678 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
bogdanm 0:9b334a45a8ff 3679 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
bogdanm 0:9b334a45a8ff 3680 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
bogdanm 0:9b334a45a8ff 3681 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
bogdanm 0:9b334a45a8ff 3682 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
bogdanm 0:9b334a45a8ff 3683 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
bogdanm 0:9b334a45a8ff 3684
bogdanm 0:9b334a45a8ff 3685 /* Old Bit definition maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 3686 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
bogdanm 0:9b334a45a8ff 3687 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
bogdanm 0:9b334a45a8ff 3688
bogdanm 0:9b334a45a8ff 3689 /***************** Bit definition for RCC_APB2ENR register *****************/
bogdanm 0:9b334a45a8ff 3690 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
bogdanm 0:9b334a45a8ff 3691 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
bogdanm 0:9b334a45a8ff 3692 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
bogdanm 0:9b334a45a8ff 3693 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
bogdanm 0:9b334a45a8ff 3694 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
bogdanm 0:9b334a45a8ff 3695 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
bogdanm 0:9b334a45a8ff 3696 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
bogdanm 0:9b334a45a8ff 3697 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
bogdanm 0:9b334a45a8ff 3698 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
bogdanm 0:9b334a45a8ff 3699
bogdanm 0:9b334a45a8ff 3700 /* Old Bit definition maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 3701 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
bogdanm 0:9b334a45a8ff 3702 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
bogdanm 0:9b334a45a8ff 3703
bogdanm 0:9b334a45a8ff 3704 /***************** Bit definition for RCC_APB1ENR register *****************/
bogdanm 0:9b334a45a8ff 3705 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
bogdanm 0:9b334a45a8ff 3706 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
bogdanm 0:9b334a45a8ff 3707 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
bogdanm 0:9b334a45a8ff 3708 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
bogdanm 0:9b334a45a8ff 3709 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
bogdanm 0:9b334a45a8ff 3710 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
bogdanm 0:9b334a45a8ff 3711 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
bogdanm 0:9b334a45a8ff 3712 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
bogdanm 0:9b334a45a8ff 3713 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
bogdanm 0:9b334a45a8ff 3714 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
bogdanm 0:9b334a45a8ff 3715 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
bogdanm 0:9b334a45a8ff 3716 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
bogdanm 0:9b334a45a8ff 3717 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
bogdanm 0:9b334a45a8ff 3718 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
bogdanm 0:9b334a45a8ff 3719 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
bogdanm 0:9b334a45a8ff 3720 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
bogdanm 0:9b334a45a8ff 3721 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
bogdanm 0:9b334a45a8ff 3722 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
bogdanm 0:9b334a45a8ff 3723
bogdanm 0:9b334a45a8ff 3724 /******************* Bit definition for RCC_BDCR register ******************/
bogdanm 0:9b334a45a8ff 3725 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
bogdanm 0:9b334a45a8ff 3726 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
bogdanm 0:9b334a45a8ff 3727 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
bogdanm 0:9b334a45a8ff 3728
bogdanm 0:9b334a45a8ff 3729 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
bogdanm 0:9b334a45a8ff 3730 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3731 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3732
bogdanm 0:9b334a45a8ff 3733 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
bogdanm 0:9b334a45a8ff 3734 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3735 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3736
bogdanm 0:9b334a45a8ff 3737 /*!< RTC configuration */
bogdanm 0:9b334a45a8ff 3738 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
bogdanm 0:9b334a45a8ff 3739 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
bogdanm 0:9b334a45a8ff 3740 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
bogdanm 0:9b334a45a8ff 3741 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
bogdanm 0:9b334a45a8ff 3742
bogdanm 0:9b334a45a8ff 3743 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
bogdanm 0:9b334a45a8ff 3744 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
bogdanm 0:9b334a45a8ff 3745
bogdanm 0:9b334a45a8ff 3746 /******************* Bit definition for RCC_CSR register *******************/
bogdanm 0:9b334a45a8ff 3747 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
bogdanm 0:9b334a45a8ff 3748 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
bogdanm 0:9b334a45a8ff 3749 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
bogdanm 0:9b334a45a8ff 3750 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
bogdanm 0:9b334a45a8ff 3751 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
bogdanm 0:9b334a45a8ff 3752 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
bogdanm 0:9b334a45a8ff 3753 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
bogdanm 0:9b334a45a8ff 3754 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
bogdanm 0:9b334a45a8ff 3755 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
bogdanm 0:9b334a45a8ff 3756 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
bogdanm 0:9b334a45a8ff 3757 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
bogdanm 0:9b334a45a8ff 3758
bogdanm 0:9b334a45a8ff 3759 /* Old Bit definition maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 3760 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
bogdanm 0:9b334a45a8ff 3761
bogdanm 0:9b334a45a8ff 3762 /******************* Bit definition for RCC_AHBRSTR register ***************/
bogdanm 0:9b334a45a8ff 3763 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
bogdanm 0:9b334a45a8ff 3764 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
bogdanm 0:9b334a45a8ff 3765 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
bogdanm 0:9b334a45a8ff 3766 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
bogdanm 0:9b334a45a8ff 3767 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
bogdanm 0:9b334a45a8ff 3768 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
bogdanm 0:9b334a45a8ff 3769 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
bogdanm 0:9b334a45a8ff 3770
bogdanm 0:9b334a45a8ff 3771 /* Old Bit definition maintained for legacy purpose */
bogdanm 0:9b334a45a8ff 3772 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
bogdanm 0:9b334a45a8ff 3773
bogdanm 0:9b334a45a8ff 3774 /******************* Bit definition for RCC_CFGR2 register *****************/
bogdanm 0:9b334a45a8ff 3775 /*!< PREDIV configuration */
bogdanm 0:9b334a45a8ff 3776 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
bogdanm 0:9b334a45a8ff 3777 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3778 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3779 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 3780 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 3781
bogdanm 0:9b334a45a8ff 3782 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
bogdanm 0:9b334a45a8ff 3783 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
bogdanm 0:9b334a45a8ff 3784 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
bogdanm 0:9b334a45a8ff 3785 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
bogdanm 0:9b334a45a8ff 3786 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
bogdanm 0:9b334a45a8ff 3787 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
bogdanm 0:9b334a45a8ff 3788 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
bogdanm 0:9b334a45a8ff 3789 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
bogdanm 0:9b334a45a8ff 3790 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
bogdanm 0:9b334a45a8ff 3791 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
bogdanm 0:9b334a45a8ff 3792 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
bogdanm 0:9b334a45a8ff 3793 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
bogdanm 0:9b334a45a8ff 3794 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
bogdanm 0:9b334a45a8ff 3795 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
bogdanm 0:9b334a45a8ff 3796 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
bogdanm 0:9b334a45a8ff 3797 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
bogdanm 0:9b334a45a8ff 3798
bogdanm 0:9b334a45a8ff 3799 /******************* Bit definition for RCC_CFGR3 register *****************/
bogdanm 0:9b334a45a8ff 3800 /*!< USART1 Clock source selection */
bogdanm 0:9b334a45a8ff 3801 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
bogdanm 0:9b334a45a8ff 3802 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3803 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3804
bogdanm 0:9b334a45a8ff 3805 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
bogdanm 0:9b334a45a8ff 3806 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
bogdanm 0:9b334a45a8ff 3807 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
bogdanm 0:9b334a45a8ff 3808 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
bogdanm 0:9b334a45a8ff 3809
bogdanm 0:9b334a45a8ff 3810 /*!< I2C1 Clock source selection */
bogdanm 0:9b334a45a8ff 3811 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
bogdanm 0:9b334a45a8ff 3812
bogdanm 0:9b334a45a8ff 3813 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
bogdanm 0:9b334a45a8ff 3814 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
bogdanm 0:9b334a45a8ff 3815
bogdanm 0:9b334a45a8ff 3816 /*!< CEC Clock source selection */
bogdanm 0:9b334a45a8ff 3817 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
bogdanm 0:9b334a45a8ff 3818
bogdanm 0:9b334a45a8ff 3819 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
bogdanm 0:9b334a45a8ff 3820 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
bogdanm 0:9b334a45a8ff 3821
bogdanm 0:9b334a45a8ff 3822 /*!< USB Clock source selection */
bogdanm 0:9b334a45a8ff 3823 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
bogdanm 0:9b334a45a8ff 3824
bogdanm 0:9b334a45a8ff 3825 #define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
bogdanm 0:9b334a45a8ff 3826 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
bogdanm 0:9b334a45a8ff 3827
bogdanm 0:9b334a45a8ff 3828 /*!< USART2 Clock source selection */
bogdanm 0:9b334a45a8ff 3829 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
bogdanm 0:9b334a45a8ff 3830 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 3831 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 3832
bogdanm 0:9b334a45a8ff 3833 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
bogdanm 0:9b334a45a8ff 3834 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
bogdanm 0:9b334a45a8ff 3835 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
bogdanm 0:9b334a45a8ff 3836 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
bogdanm 0:9b334a45a8ff 3837
bogdanm 0:9b334a45a8ff 3838 /******************* Bit definition for RCC_CR2 register *******************/
bogdanm 0:9b334a45a8ff 3839 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
bogdanm 0:9b334a45a8ff 3840 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
bogdanm 0:9b334a45a8ff 3841 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
bogdanm 0:9b334a45a8ff 3842 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
bogdanm 0:9b334a45a8ff 3843 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
bogdanm 0:9b334a45a8ff 3844 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
bogdanm 0:9b334a45a8ff 3845 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
bogdanm 0:9b334a45a8ff 3846 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
bogdanm 0:9b334a45a8ff 3847
bogdanm 0:9b334a45a8ff 3848 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3849 /* */
bogdanm 0:9b334a45a8ff 3850 /* Real-Time Clock (RTC) */
bogdanm 0:9b334a45a8ff 3851 /* */
bogdanm 0:9b334a45a8ff 3852 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 3853 /******************** Bits definition for RTC_TR register ******************/
bogdanm 0:9b334a45a8ff 3854 #define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3855 #define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 3856 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3857 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3858 #define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 3859 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3860 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3861 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3862 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3863 #define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 3864 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3865 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3866 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3867 #define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 3868 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3869 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3870 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3871 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3872 #define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 3873 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3874 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3875 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3876 #define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3877 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3878 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3879 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3880 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3881
bogdanm 0:9b334a45a8ff 3882 /******************** Bits definition for RTC_DR register ******************/
bogdanm 0:9b334a45a8ff 3883 #define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm 0:9b334a45a8ff 3884 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3885 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3886 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3887 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3888 #define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 3889 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3890 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3891 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3892 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3893 #define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm 0:9b334a45a8ff 3894 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3895 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3896 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3897 #define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3898 #define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 3899 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3900 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3901 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3902 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3903 #define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 3904 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3905 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3906 #define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3907 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3908 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3909 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3910 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3911
bogdanm 0:9b334a45a8ff 3912 /******************** Bits definition for RTC_CR register ******************/
bogdanm 0:9b334a45a8ff 3913 #define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3914 #define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm 0:9b334a45a8ff 3915 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3916 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3917 #define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3918 #define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3919 #define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3920 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3921 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3922 #define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3923 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3924 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3925 #define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3926 #define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3927 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3928 #define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3929 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3930 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3931 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3932 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm 0:9b334a45a8ff 3933 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3934 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 3935 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3936
bogdanm 0:9b334a45a8ff 3937 /******************** Bits definition for RTC_ISR register *****************/
bogdanm 0:9b334a45a8ff 3938 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3939 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3940 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3941 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3942 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3943 #define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3944 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3945 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3946 #define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3947 #define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3948 #define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3949 #define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3950 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 3951 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 3952 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3953
bogdanm 0:9b334a45a8ff 3954 /******************** Bits definition for RTC_PRER register ****************/
bogdanm 0:9b334a45a8ff 3955 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm 0:9b334a45a8ff 3956 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 3957
bogdanm 0:9b334a45a8ff 3958 /******************** Bits definition for RTC_WUTR register ****************/
bogdanm 0:9b334a45a8ff 3959 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 3960
bogdanm 0:9b334a45a8ff 3961 /******************** Bits definition for RTC_ALRMAR register **************/
bogdanm 0:9b334a45a8ff 3962 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 3963 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm 0:9b334a45a8ff 3964 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm 0:9b334a45a8ff 3965 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm 0:9b334a45a8ff 3966 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm 0:9b334a45a8ff 3967 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 3968 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 3969 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 3970 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 3971 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 3972 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm 0:9b334a45a8ff 3973 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 3974 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 3975 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 3976 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 3977 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 3978 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 3979 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 3980 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 3981 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 3982 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 3983 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 3984 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 3985 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 3986 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 3987 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 3988 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 3989 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 3990 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 3991 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 3992 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 3993 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 3994 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 3995 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 3996 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 3997 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 3998 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 3999 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4000 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4001 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4002
bogdanm 0:9b334a45a8ff 4003 /******************** Bits definition for RTC_WPR register *****************/
bogdanm 0:9b334a45a8ff 4004 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm 0:9b334a45a8ff 4005
bogdanm 0:9b334a45a8ff 4006 /******************** Bits definition for RTC_SSR register *****************/
bogdanm 0:9b334a45a8ff 4007 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 4008
bogdanm 0:9b334a45a8ff 4009 /******************** Bits definition for RTC_SHIFTR register **************/
bogdanm 0:9b334a45a8ff 4010 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 4011 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm 0:9b334a45a8ff 4012
bogdanm 0:9b334a45a8ff 4013 /******************** Bits definition for RTC_TSTR register ****************/
bogdanm 0:9b334a45a8ff 4014 #define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm 0:9b334a45a8ff 4015 #define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm 0:9b334a45a8ff 4016 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm 0:9b334a45a8ff 4017 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm 0:9b334a45a8ff 4018 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm 0:9b334a45a8ff 4019 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm 0:9b334a45a8ff 4020 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm 0:9b334a45a8ff 4021 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4022 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm 0:9b334a45a8ff 4023 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm 0:9b334a45a8ff 4024 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4025 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4026 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4027 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 4028 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4029 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4030 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4031 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4032 #define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm 0:9b334a45a8ff 4033 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4034 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4035 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4036 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 4037 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4038 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4039 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4040 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4041
bogdanm 0:9b334a45a8ff 4042 /******************** Bits definition for RTC_TSDR register ****************/
bogdanm 0:9b334a45a8ff 4043 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm 0:9b334a45a8ff 4044 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4045 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4046 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4047 #define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4048 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm 0:9b334a45a8ff 4049 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4050 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4051 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4052 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4053 #define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm 0:9b334a45a8ff 4054 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4055 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4056 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm 0:9b334a45a8ff 4057 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4058 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4059 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4060 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4061
bogdanm 0:9b334a45a8ff 4062 /******************** Bits definition for RTC_TSSSR register ***************/
bogdanm 0:9b334a45a8ff 4063 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm 0:9b334a45a8ff 4064
bogdanm 0:9b334a45a8ff 4065 /******************** Bits definition for RTC_CALR register ****************/
bogdanm 0:9b334a45a8ff 4066 #define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4067 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4068 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4069 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm 0:9b334a45a8ff 4070 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4071 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4072 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4073 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4074 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4075 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4076 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4077 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4078 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4079
bogdanm 0:9b334a45a8ff 4080 /******************** Bits definition for RTC_TAFCR register ***************/
bogdanm 0:9b334a45a8ff 4081 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm 0:9b334a45a8ff 4082 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm 0:9b334a45a8ff 4083 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm 0:9b334a45a8ff 4084 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm 0:9b334a45a8ff 4085 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm 0:9b334a45a8ff 4086 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm 0:9b334a45a8ff 4087 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm 0:9b334a45a8ff 4088 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm 0:9b334a45a8ff 4089 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm 0:9b334a45a8ff 4090 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 4091 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 4092 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm 0:9b334a45a8ff 4093 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm 0:9b334a45a8ff 4094 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
bogdanm 0:9b334a45a8ff 4095 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
bogdanm 0:9b334a45a8ff 4096 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm 0:9b334a45a8ff 4097 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 4098 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 4099 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 4100 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 4101
bogdanm 0:9b334a45a8ff 4102 /******************** Bits definition for RTC_ALRMASSR register ************/
bogdanm 0:9b334a45a8ff 4103 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm 0:9b334a45a8ff 4104 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm 0:9b334a45a8ff 4105 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm 0:9b334a45a8ff 4106 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm 0:9b334a45a8ff 4107 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm 0:9b334a45a8ff 4108 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm 0:9b334a45a8ff 4109
bogdanm 0:9b334a45a8ff 4110 /******************** Bits definition for RTC_BKP0R register ***************/
bogdanm 0:9b334a45a8ff 4111 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 4112
bogdanm 0:9b334a45a8ff 4113 /******************** Bits definition for RTC_BKP1R register ***************/
bogdanm 0:9b334a45a8ff 4114 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 4115
bogdanm 0:9b334a45a8ff 4116 /******************** Bits definition for RTC_BKP2R register ***************/
bogdanm 0:9b334a45a8ff 4117 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 4118
bogdanm 0:9b334a45a8ff 4119 /******************** Bits definition for RTC_BKP3R register ***************/
bogdanm 0:9b334a45a8ff 4120 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 4121
bogdanm 0:9b334a45a8ff 4122 /******************** Bits definition for RTC_BKP4R register ***************/
bogdanm 0:9b334a45a8ff 4123 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 4124
bogdanm 0:9b334a45a8ff 4125 /******************** Number of backup registers ******************************/
bogdanm 0:9b334a45a8ff 4126 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
bogdanm 0:9b334a45a8ff 4127
bogdanm 0:9b334a45a8ff 4128 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 4129 /* */
bogdanm 0:9b334a45a8ff 4130 /* Serial Peripheral Interface (SPI) */
bogdanm 0:9b334a45a8ff 4131 /* */
bogdanm 0:9b334a45a8ff 4132 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 4133 /******************* Bit definition for SPI_CR1 register *******************/
bogdanm 0:9b334a45a8ff 4134 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
bogdanm 0:9b334a45a8ff 4135 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
bogdanm 0:9b334a45a8ff 4136 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
bogdanm 0:9b334a45a8ff 4137 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
bogdanm 0:9b334a45a8ff 4138 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4139 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4140 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4141 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
bogdanm 0:9b334a45a8ff 4142 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
bogdanm 0:9b334a45a8ff 4143 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
bogdanm 0:9b334a45a8ff 4144 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
bogdanm 0:9b334a45a8ff 4145 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
bogdanm 0:9b334a45a8ff 4146 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
bogdanm 0:9b334a45a8ff 4147 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
bogdanm 0:9b334a45a8ff 4148 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
bogdanm 0:9b334a45a8ff 4149 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
bogdanm 0:9b334a45a8ff 4150 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
bogdanm 0:9b334a45a8ff 4151
bogdanm 0:9b334a45a8ff 4152 /******************* Bit definition for SPI_CR2 register *******************/
bogdanm 0:9b334a45a8ff 4153 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
bogdanm 0:9b334a45a8ff 4154 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
bogdanm 0:9b334a45a8ff 4155 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
bogdanm 0:9b334a45a8ff 4156 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
bogdanm 0:9b334a45a8ff 4157 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
bogdanm 0:9b334a45a8ff 4158 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 4159 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 4160 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
bogdanm 0:9b334a45a8ff 4161 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
bogdanm 0:9b334a45a8ff 4162 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4163 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4164 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4165 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 4166 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
bogdanm 0:9b334a45a8ff 4167 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
bogdanm 0:9b334a45a8ff 4168 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
bogdanm 0:9b334a45a8ff 4169
bogdanm 0:9b334a45a8ff 4170 /******************** Bit definition for SPI_SR register *******************/
bogdanm 0:9b334a45a8ff 4171 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
bogdanm 0:9b334a45a8ff 4172 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
bogdanm 0:9b334a45a8ff 4173 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
bogdanm 0:9b334a45a8ff 4174 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
bogdanm 0:9b334a45a8ff 4175 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
bogdanm 0:9b334a45a8ff 4176 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
bogdanm 0:9b334a45a8ff 4177 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
bogdanm 0:9b334a45a8ff 4178 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
bogdanm 0:9b334a45a8ff 4179 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
bogdanm 0:9b334a45a8ff 4180 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
bogdanm 0:9b334a45a8ff 4181 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4182 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4183 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
bogdanm 0:9b334a45a8ff 4184 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4185 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4186
bogdanm 0:9b334a45a8ff 4187 /******************** Bit definition for SPI_DR register *******************/
bogdanm 0:9b334a45a8ff 4188 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
bogdanm 0:9b334a45a8ff 4189
bogdanm 0:9b334a45a8ff 4190 /******************* Bit definition for SPI_CRCPR register *****************/
bogdanm 0:9b334a45a8ff 4191 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
bogdanm 0:9b334a45a8ff 4192
bogdanm 0:9b334a45a8ff 4193 /****************** Bit definition for SPI_RXCRCR register *****************/
bogdanm 0:9b334a45a8ff 4194 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
bogdanm 0:9b334a45a8ff 4195
bogdanm 0:9b334a45a8ff 4196 /****************** Bit definition for SPI_TXCRCR register *****************/
bogdanm 0:9b334a45a8ff 4197 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
bogdanm 0:9b334a45a8ff 4198
bogdanm 0:9b334a45a8ff 4199 /****************** Bit definition for SPI_I2SCFGR register ****************/
bogdanm 0:9b334a45a8ff 4200 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
bogdanm 0:9b334a45a8ff 4201 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
bogdanm 0:9b334a45a8ff 4202 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4203 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4204 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
bogdanm 0:9b334a45a8ff 4205 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
bogdanm 0:9b334a45a8ff 4206 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4207 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4208 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
bogdanm 0:9b334a45a8ff 4209 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
bogdanm 0:9b334a45a8ff 4210 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4211 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4212 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
bogdanm 0:9b334a45a8ff 4213 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
bogdanm 0:9b334a45a8ff 4214
bogdanm 0:9b334a45a8ff 4215 /****************** Bit definition for SPI_I2SPR register ******************/
bogdanm 0:9b334a45a8ff 4216 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
bogdanm 0:9b334a45a8ff 4217 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
bogdanm 0:9b334a45a8ff 4218 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
bogdanm 0:9b334a45a8ff 4219
bogdanm 0:9b334a45a8ff 4220 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 4221 /* */
bogdanm 0:9b334a45a8ff 4222 /* System Configuration (SYSCFG) */
bogdanm 0:9b334a45a8ff 4223 /* */
bogdanm 0:9b334a45a8ff 4224 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 4225 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
bogdanm 0:9b334a45a8ff 4226 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
bogdanm 0:9b334a45a8ff 4227 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
bogdanm 0:9b334a45a8ff 4228 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
bogdanm 0:9b334a45a8ff 4229
bogdanm 0:9b334a45a8ff 4230
bogdanm 0:9b334a45a8ff 4231 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /*!< DMA remap mask */
bogdanm 0:9b334a45a8ff 4232 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
bogdanm 0:9b334a45a8ff 4233 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
bogdanm 0:9b334a45a8ff 4234 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
bogdanm 0:9b334a45a8ff 4235 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
bogdanm 0:9b334a45a8ff 4236 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
bogdanm 0:9b334a45a8ff 4237 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 */
bogdanm 0:9b334a45a8ff 4238 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 */
bogdanm 0:9b334a45a8ff 4239 #define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap */
bogdanm 0:9b334a45a8ff 4240 #define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap */
bogdanm 0:9b334a45a8ff 4241 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
bogdanm 0:9b334a45a8ff 4242 #define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap */
bogdanm 0:9b334a45a8ff 4243 #define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap */
bogdanm 0:9b334a45a8ff 4244 #define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap */
bogdanm 0:9b334a45a8ff 4245 #define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap */
bogdanm 0:9b334a45a8ff 4246
bogdanm 0:9b334a45a8ff 4247 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
bogdanm 0:9b334a45a8ff 4248 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
bogdanm 0:9b334a45a8ff 4249 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
bogdanm 0:9b334a45a8ff 4250 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
bogdanm 0:9b334a45a8ff 4251 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
bogdanm 0:9b334a45a8ff 4252
bogdanm 0:9b334a45a8ff 4253 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
bogdanm 0:9b334a45a8ff 4254
bogdanm 0:9b334a45a8ff 4255 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
bogdanm 0:9b334a45a8ff 4256 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
bogdanm 0:9b334a45a8ff 4257 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
bogdanm 0:9b334a45a8ff 4258 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
bogdanm 0:9b334a45a8ff 4259 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
bogdanm 0:9b334a45a8ff 4260
bogdanm 0:9b334a45a8ff 4261 /**
bogdanm 0:9b334a45a8ff 4262 * @brief EXTI0 configuration
bogdanm 0:9b334a45a8ff 4263 */
bogdanm 0:9b334a45a8ff 4264 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
bogdanm 0:9b334a45a8ff 4265 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
bogdanm 0:9b334a45a8ff 4266 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
bogdanm 0:9b334a45a8ff 4267 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
bogdanm 0:9b334a45a8ff 4268 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
bogdanm 0:9b334a45a8ff 4269 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
bogdanm 0:9b334a45a8ff 4270
bogdanm 0:9b334a45a8ff 4271 /**
bogdanm 0:9b334a45a8ff 4272 * @brief EXTI1 configuration
bogdanm 0:9b334a45a8ff 4273 */
bogdanm 0:9b334a45a8ff 4274 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
bogdanm 0:9b334a45a8ff 4275 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
bogdanm 0:9b334a45a8ff 4276 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
bogdanm 0:9b334a45a8ff 4277 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
bogdanm 0:9b334a45a8ff 4278 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
bogdanm 0:9b334a45a8ff 4279 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
bogdanm 0:9b334a45a8ff 4280
bogdanm 0:9b334a45a8ff 4281 /**
bogdanm 0:9b334a45a8ff 4282 * @brief EXTI2 configuration
bogdanm 0:9b334a45a8ff 4283 */
bogdanm 0:9b334a45a8ff 4284 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
bogdanm 0:9b334a45a8ff 4285 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
bogdanm 0:9b334a45a8ff 4286 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
bogdanm 0:9b334a45a8ff 4287 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
bogdanm 0:9b334a45a8ff 4288 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
bogdanm 0:9b334a45a8ff 4289 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
bogdanm 0:9b334a45a8ff 4290
bogdanm 0:9b334a45a8ff 4291 /**
bogdanm 0:9b334a45a8ff 4292 * @brief EXTI3 configuration
bogdanm 0:9b334a45a8ff 4293 */
bogdanm 0:9b334a45a8ff 4294 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
bogdanm 0:9b334a45a8ff 4295 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
bogdanm 0:9b334a45a8ff 4296 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
bogdanm 0:9b334a45a8ff 4297 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
bogdanm 0:9b334a45a8ff 4298 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
bogdanm 0:9b334a45a8ff 4299 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
bogdanm 0:9b334a45a8ff 4300
bogdanm 0:9b334a45a8ff 4301 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
bogdanm 0:9b334a45a8ff 4302 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
bogdanm 0:9b334a45a8ff 4303 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
bogdanm 0:9b334a45a8ff 4304 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
bogdanm 0:9b334a45a8ff 4305 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
bogdanm 0:9b334a45a8ff 4306
bogdanm 0:9b334a45a8ff 4307 /**
bogdanm 0:9b334a45a8ff 4308 * @brief EXTI4 configuration
bogdanm 0:9b334a45a8ff 4309 */
bogdanm 0:9b334a45a8ff 4310 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
bogdanm 0:9b334a45a8ff 4311 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
bogdanm 0:9b334a45a8ff 4312 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
bogdanm 0:9b334a45a8ff 4313 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
bogdanm 0:9b334a45a8ff 4314 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
bogdanm 0:9b334a45a8ff 4315 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
bogdanm 0:9b334a45a8ff 4316
bogdanm 0:9b334a45a8ff 4317 /**
bogdanm 0:9b334a45a8ff 4318 * @brief EXTI5 configuration
bogdanm 0:9b334a45a8ff 4319 */
bogdanm 0:9b334a45a8ff 4320 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
bogdanm 0:9b334a45a8ff 4321 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
bogdanm 0:9b334a45a8ff 4322 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
bogdanm 0:9b334a45a8ff 4323 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
bogdanm 0:9b334a45a8ff 4324 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
bogdanm 0:9b334a45a8ff 4325 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
bogdanm 0:9b334a45a8ff 4326
bogdanm 0:9b334a45a8ff 4327 /**
bogdanm 0:9b334a45a8ff 4328 * @brief EXTI6 configuration
bogdanm 0:9b334a45a8ff 4329 */
bogdanm 0:9b334a45a8ff 4330 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
bogdanm 0:9b334a45a8ff 4331 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
bogdanm 0:9b334a45a8ff 4332 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
bogdanm 0:9b334a45a8ff 4333 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
bogdanm 0:9b334a45a8ff 4334 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
bogdanm 0:9b334a45a8ff 4335 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
bogdanm 0:9b334a45a8ff 4336
bogdanm 0:9b334a45a8ff 4337 /**
bogdanm 0:9b334a45a8ff 4338 * @brief EXTI7 configuration
bogdanm 0:9b334a45a8ff 4339 */
bogdanm 0:9b334a45a8ff 4340 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
bogdanm 0:9b334a45a8ff 4341 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
bogdanm 0:9b334a45a8ff 4342 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
bogdanm 0:9b334a45a8ff 4343 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
bogdanm 0:9b334a45a8ff 4344 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
bogdanm 0:9b334a45a8ff 4345 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
bogdanm 0:9b334a45a8ff 4346
bogdanm 0:9b334a45a8ff 4347 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
bogdanm 0:9b334a45a8ff 4348 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
bogdanm 0:9b334a45a8ff 4349 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
bogdanm 0:9b334a45a8ff 4350 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
bogdanm 0:9b334a45a8ff 4351 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
bogdanm 0:9b334a45a8ff 4352
bogdanm 0:9b334a45a8ff 4353 /**
bogdanm 0:9b334a45a8ff 4354 * @brief EXTI8 configuration
bogdanm 0:9b334a45a8ff 4355 */
bogdanm 0:9b334a45a8ff 4356 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
bogdanm 0:9b334a45a8ff 4357 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
bogdanm 0:9b334a45a8ff 4358 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
bogdanm 0:9b334a45a8ff 4359 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
bogdanm 0:9b334a45a8ff 4360 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
bogdanm 0:9b334a45a8ff 4361
bogdanm 0:9b334a45a8ff 4362 /**
bogdanm 0:9b334a45a8ff 4363 * @brief EXTI9 configuration
bogdanm 0:9b334a45a8ff 4364 */
bogdanm 0:9b334a45a8ff 4365 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
bogdanm 0:9b334a45a8ff 4366 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
bogdanm 0:9b334a45a8ff 4367 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
bogdanm 0:9b334a45a8ff 4368 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
bogdanm 0:9b334a45a8ff 4369 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
bogdanm 0:9b334a45a8ff 4370 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
bogdanm 0:9b334a45a8ff 4371
bogdanm 0:9b334a45a8ff 4372 /**
bogdanm 0:9b334a45a8ff 4373 * @brief EXTI10 configuration
bogdanm 0:9b334a45a8ff 4374 */
bogdanm 0:9b334a45a8ff 4375 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
bogdanm 0:9b334a45a8ff 4376 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
bogdanm 0:9b334a45a8ff 4377 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
bogdanm 0:9b334a45a8ff 4378 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
bogdanm 0:9b334a45a8ff 4379 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
bogdanm 0:9b334a45a8ff 4380 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
bogdanm 0:9b334a45a8ff 4381
bogdanm 0:9b334a45a8ff 4382 /**
bogdanm 0:9b334a45a8ff 4383 * @brief EXTI11 configuration
bogdanm 0:9b334a45a8ff 4384 */
bogdanm 0:9b334a45a8ff 4385 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
bogdanm 0:9b334a45a8ff 4386 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
bogdanm 0:9b334a45a8ff 4387 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
bogdanm 0:9b334a45a8ff 4388 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
bogdanm 0:9b334a45a8ff 4389 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
bogdanm 0:9b334a45a8ff 4390
bogdanm 0:9b334a45a8ff 4391 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
bogdanm 0:9b334a45a8ff 4392 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
bogdanm 0:9b334a45a8ff 4393 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
bogdanm 0:9b334a45a8ff 4394 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
bogdanm 0:9b334a45a8ff 4395 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
bogdanm 0:9b334a45a8ff 4396
bogdanm 0:9b334a45a8ff 4397 /**
bogdanm 0:9b334a45a8ff 4398 * @brief EXTI12 configuration
bogdanm 0:9b334a45a8ff 4399 */
bogdanm 0:9b334a45a8ff 4400 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
bogdanm 0:9b334a45a8ff 4401 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
bogdanm 0:9b334a45a8ff 4402 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
bogdanm 0:9b334a45a8ff 4403 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
bogdanm 0:9b334a45a8ff 4404 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
bogdanm 0:9b334a45a8ff 4405
bogdanm 0:9b334a45a8ff 4406 /**
bogdanm 0:9b334a45a8ff 4407 * @brief EXTI13 configuration
bogdanm 0:9b334a45a8ff 4408 */
bogdanm 0:9b334a45a8ff 4409 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
bogdanm 0:9b334a45a8ff 4410 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
bogdanm 0:9b334a45a8ff 4411 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
bogdanm 0:9b334a45a8ff 4412 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
bogdanm 0:9b334a45a8ff 4413 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
bogdanm 0:9b334a45a8ff 4414
bogdanm 0:9b334a45a8ff 4415 /**
bogdanm 0:9b334a45a8ff 4416 * @brief EXTI14 configuration
bogdanm 0:9b334a45a8ff 4417 */
bogdanm 0:9b334a45a8ff 4418 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
bogdanm 0:9b334a45a8ff 4419 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
bogdanm 0:9b334a45a8ff 4420 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
bogdanm 0:9b334a45a8ff 4421 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
bogdanm 0:9b334a45a8ff 4422 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
bogdanm 0:9b334a45a8ff 4423
bogdanm 0:9b334a45a8ff 4424 /**
bogdanm 0:9b334a45a8ff 4425 * @brief EXTI15 configuration
bogdanm 0:9b334a45a8ff 4426 */
bogdanm 0:9b334a45a8ff 4427 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
bogdanm 0:9b334a45a8ff 4428 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
bogdanm 0:9b334a45a8ff 4429 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
bogdanm 0:9b334a45a8ff 4430 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
bogdanm 0:9b334a45a8ff 4431 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
bogdanm 0:9b334a45a8ff 4432
bogdanm 0:9b334a45a8ff 4433 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
bogdanm 0:9b334a45a8ff 4434 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
bogdanm 0:9b334a45a8ff 4435 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
bogdanm 0:9b334a45a8ff 4436 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
bogdanm 0:9b334a45a8ff 4437 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
bogdanm 0:9b334a45a8ff 4438 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
bogdanm 0:9b334a45a8ff 4439
bogdanm 0:9b334a45a8ff 4440 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 4441 /* */
bogdanm 0:9b334a45a8ff 4442 /* Timers (TIM) */
bogdanm 0:9b334a45a8ff 4443 /* */
bogdanm 0:9b334a45a8ff 4444 /*****************************************************************************/
bogdanm 0:9b334a45a8ff 4445 /******************* Bit definition for TIM_CR1 register *******************/
bogdanm 0:9b334a45a8ff 4446 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
bogdanm 0:9b334a45a8ff 4447 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
bogdanm 0:9b334a45a8ff 4448 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
bogdanm 0:9b334a45a8ff 4449 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
bogdanm 0:9b334a45a8ff 4450 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
bogdanm 0:9b334a45a8ff 4451
bogdanm 0:9b334a45a8ff 4452 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
bogdanm 0:9b334a45a8ff 4453 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4454 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4455
bogdanm 0:9b334a45a8ff 4456 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
bogdanm 0:9b334a45a8ff 4457
bogdanm 0:9b334a45a8ff 4458 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
bogdanm 0:9b334a45a8ff 4459 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4460 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4461
bogdanm 0:9b334a45a8ff 4462 /******************* Bit definition for TIM_CR2 register *******************/
bogdanm 0:9b334a45a8ff 4463 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
bogdanm 0:9b334a45a8ff 4464 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
bogdanm 0:9b334a45a8ff 4465 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
bogdanm 0:9b334a45a8ff 4466
bogdanm 0:9b334a45a8ff 4467 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
bogdanm 0:9b334a45a8ff 4468 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4469 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4470 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4471
bogdanm 0:9b334a45a8ff 4472 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
bogdanm 0:9b334a45a8ff 4473 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
bogdanm 0:9b334a45a8ff 4474 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
bogdanm 0:9b334a45a8ff 4475 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
bogdanm 0:9b334a45a8ff 4476 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
bogdanm 0:9b334a45a8ff 4477 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
bogdanm 0:9b334a45a8ff 4478 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
bogdanm 0:9b334a45a8ff 4479 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
bogdanm 0:9b334a45a8ff 4480
bogdanm 0:9b334a45a8ff 4481 /******************* Bit definition for TIM_SMCR register ******************/
bogdanm 0:9b334a45a8ff 4482 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
bogdanm 0:9b334a45a8ff 4483 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4484 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4485 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4486
bogdanm 0:9b334a45a8ff 4487 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
bogdanm 0:9b334a45a8ff 4488
bogdanm 0:9b334a45a8ff 4489 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
bogdanm 0:9b334a45a8ff 4490 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4491 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4492 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4493
bogdanm 0:9b334a45a8ff 4494 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
bogdanm 0:9b334a45a8ff 4495
bogdanm 0:9b334a45a8ff 4496 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
bogdanm 0:9b334a45a8ff 4497 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4498 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4499 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4500 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4501
bogdanm 0:9b334a45a8ff 4502 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
bogdanm 0:9b334a45a8ff 4503 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4504 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4505
bogdanm 0:9b334a45a8ff 4506 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
bogdanm 0:9b334a45a8ff 4507 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
bogdanm 0:9b334a45a8ff 4508
bogdanm 0:9b334a45a8ff 4509 /******************* Bit definition for TIM_DIER register ******************/
bogdanm 0:9b334a45a8ff 4510 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
bogdanm 0:9b334a45a8ff 4511 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
bogdanm 0:9b334a45a8ff 4512 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
bogdanm 0:9b334a45a8ff 4513 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
bogdanm 0:9b334a45a8ff 4514 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
bogdanm 0:9b334a45a8ff 4515 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
bogdanm 0:9b334a45a8ff 4516 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
bogdanm 0:9b334a45a8ff 4517 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
bogdanm 0:9b334a45a8ff 4518 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
bogdanm 0:9b334a45a8ff 4519 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
bogdanm 0:9b334a45a8ff 4520 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
bogdanm 0:9b334a45a8ff 4521 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
bogdanm 0:9b334a45a8ff 4522 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
bogdanm 0:9b334a45a8ff 4523 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
bogdanm 0:9b334a45a8ff 4524 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
bogdanm 0:9b334a45a8ff 4525
bogdanm 0:9b334a45a8ff 4526 /******************** Bit definition for TIM_SR register *******************/
bogdanm 0:9b334a45a8ff 4527 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
bogdanm 0:9b334a45a8ff 4528 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
bogdanm 0:9b334a45a8ff 4529 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
bogdanm 0:9b334a45a8ff 4530 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
bogdanm 0:9b334a45a8ff 4531 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
bogdanm 0:9b334a45a8ff 4532 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
bogdanm 0:9b334a45a8ff 4533 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
bogdanm 0:9b334a45a8ff 4534 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
bogdanm 0:9b334a45a8ff 4535 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
bogdanm 0:9b334a45a8ff 4536 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
bogdanm 0:9b334a45a8ff 4537 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
bogdanm 0:9b334a45a8ff 4538 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
bogdanm 0:9b334a45a8ff 4539
bogdanm 0:9b334a45a8ff 4540 /******************* Bit definition for TIM_EGR register *******************/
bogdanm 0:9b334a45a8ff 4541 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
bogdanm 0:9b334a45a8ff 4542 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
bogdanm 0:9b334a45a8ff 4543 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
bogdanm 0:9b334a45a8ff 4544 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
bogdanm 0:9b334a45a8ff 4545 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
bogdanm 0:9b334a45a8ff 4546 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
bogdanm 0:9b334a45a8ff 4547 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
bogdanm 0:9b334a45a8ff 4548 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
bogdanm 0:9b334a45a8ff 4549
bogdanm 0:9b334a45a8ff 4550 /****************** Bit definition for TIM_CCMR1 register ******************/
bogdanm 0:9b334a45a8ff 4551 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
bogdanm 0:9b334a45a8ff 4552 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4553 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4554
bogdanm 0:9b334a45a8ff 4555 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
bogdanm 0:9b334a45a8ff 4556 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
bogdanm 0:9b334a45a8ff 4557
bogdanm 0:9b334a45a8ff 4558 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
bogdanm 0:9b334a45a8ff 4559 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4560 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4561 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4562
bogdanm 0:9b334a45a8ff 4563 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
bogdanm 0:9b334a45a8ff 4564
bogdanm 0:9b334a45a8ff 4565 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
bogdanm 0:9b334a45a8ff 4566 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4567 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4568
bogdanm 0:9b334a45a8ff 4569 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
bogdanm 0:9b334a45a8ff 4570 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
bogdanm 0:9b334a45a8ff 4571
bogdanm 0:9b334a45a8ff 4572 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
bogdanm 0:9b334a45a8ff 4573 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4574 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4575 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4576
bogdanm 0:9b334a45a8ff 4577 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
bogdanm 0:9b334a45a8ff 4578
bogdanm 0:9b334a45a8ff 4579 /*---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 4580
bogdanm 0:9b334a45a8ff 4581 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
bogdanm 0:9b334a45a8ff 4582 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4583 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4584
bogdanm 0:9b334a45a8ff 4585 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
bogdanm 0:9b334a45a8ff 4586 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4587 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4588 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4589 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4590
bogdanm 0:9b334a45a8ff 4591 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
bogdanm 0:9b334a45a8ff 4592 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4593 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4594
bogdanm 0:9b334a45a8ff 4595 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
bogdanm 0:9b334a45a8ff 4596 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4597 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4598 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4599 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4600
bogdanm 0:9b334a45a8ff 4601 /****************** Bit definition for TIM_CCMR2 register ******************/
bogdanm 0:9b334a45a8ff 4602 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
bogdanm 0:9b334a45a8ff 4603 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4604 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4605
bogdanm 0:9b334a45a8ff 4606 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
bogdanm 0:9b334a45a8ff 4607 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
bogdanm 0:9b334a45a8ff 4608
bogdanm 0:9b334a45a8ff 4609 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
bogdanm 0:9b334a45a8ff 4610 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4611 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4612 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4613
bogdanm 0:9b334a45a8ff 4614 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
bogdanm 0:9b334a45a8ff 4615
bogdanm 0:9b334a45a8ff 4616 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
bogdanm 0:9b334a45a8ff 4617 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4618 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4619
bogdanm 0:9b334a45a8ff 4620 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
bogdanm 0:9b334a45a8ff 4621 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
bogdanm 0:9b334a45a8ff 4622
bogdanm 0:9b334a45a8ff 4623 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
bogdanm 0:9b334a45a8ff 4624 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4625 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4626 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4627
bogdanm 0:9b334a45a8ff 4628 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
bogdanm 0:9b334a45a8ff 4629
bogdanm 0:9b334a45a8ff 4630 /*---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 4631
bogdanm 0:9b334a45a8ff 4632 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
bogdanm 0:9b334a45a8ff 4633 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4634 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4635
bogdanm 0:9b334a45a8ff 4636 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
bogdanm 0:9b334a45a8ff 4637 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4638 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4639 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4640 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4641
bogdanm 0:9b334a45a8ff 4642 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
bogdanm 0:9b334a45a8ff 4643 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4644 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4645
bogdanm 0:9b334a45a8ff 4646 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
bogdanm 0:9b334a45a8ff 4647 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4648 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4649 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4650 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4651
bogdanm 0:9b334a45a8ff 4652 /******************* Bit definition for TIM_CCER register ******************/
bogdanm 0:9b334a45a8ff 4653 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
bogdanm 0:9b334a45a8ff 4654 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
bogdanm 0:9b334a45a8ff 4655 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
bogdanm 0:9b334a45a8ff 4656 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 4657 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
bogdanm 0:9b334a45a8ff 4658 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
bogdanm 0:9b334a45a8ff 4659 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
bogdanm 0:9b334a45a8ff 4660 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 4661 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
bogdanm 0:9b334a45a8ff 4662 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
bogdanm 0:9b334a45a8ff 4663 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
bogdanm 0:9b334a45a8ff 4664 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 4665 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
bogdanm 0:9b334a45a8ff 4666 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
bogdanm 0:9b334a45a8ff 4667 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
bogdanm 0:9b334a45a8ff 4668
bogdanm 0:9b334a45a8ff 4669 /******************* Bit definition for TIM_CNT register *******************/
bogdanm 0:9b334a45a8ff 4670 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
bogdanm 0:9b334a45a8ff 4671
bogdanm 0:9b334a45a8ff 4672 /******************* Bit definition for TIM_PSC register *******************/
bogdanm 0:9b334a45a8ff 4673 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
bogdanm 0:9b334a45a8ff 4674
bogdanm 0:9b334a45a8ff 4675 /******************* Bit definition for TIM_ARR register *******************/
bogdanm 0:9b334a45a8ff 4676 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
bogdanm 0:9b334a45a8ff 4677
bogdanm 0:9b334a45a8ff 4678 /******************* Bit definition for TIM_RCR register *******************/
bogdanm 0:9b334a45a8ff 4679 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
bogdanm 0:9b334a45a8ff 4680
bogdanm 0:9b334a45a8ff 4681 /******************* Bit definition for TIM_CCR1 register ******************/
bogdanm 0:9b334a45a8ff 4682 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
bogdanm 0:9b334a45a8ff 4683
bogdanm 0:9b334a45a8ff 4684 /******************* Bit definition for TIM_CCR2 register ******************/
bogdanm 0:9b334a45a8ff 4685 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
bogdanm 0:9b334a45a8ff 4686
bogdanm 0:9b334a45a8ff 4687 /******************* Bit definition for TIM_CCR3 register ******************/
bogdanm 0:9b334a45a8ff 4688 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
bogdanm 0:9b334a45a8ff 4689
bogdanm 0:9b334a45a8ff 4690 /******************* Bit definition for TIM_CCR4 register ******************/
bogdanm 0:9b334a45a8ff 4691 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
bogdanm 0:9b334a45a8ff 4692
bogdanm 0:9b334a45a8ff 4693 /******************* Bit definition for TIM_BDTR register ******************/
bogdanm 0:9b334a45a8ff 4694 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
bogdanm 0:9b334a45a8ff 4695 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4696 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4697 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4698 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4699 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4700 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4701 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4702 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
bogdanm 0:9b334a45a8ff 4703
bogdanm 0:9b334a45a8ff 4704 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
bogdanm 0:9b334a45a8ff 4705 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4706 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4707
bogdanm 0:9b334a45a8ff 4708 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
bogdanm 0:9b334a45a8ff 4709 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
bogdanm 0:9b334a45a8ff 4710 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
bogdanm 0:9b334a45a8ff 4711 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
bogdanm 0:9b334a45a8ff 4712 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
bogdanm 0:9b334a45a8ff 4713 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
bogdanm 0:9b334a45a8ff 4714
bogdanm 0:9b334a45a8ff 4715 /******************* Bit definition for TIM_DCR register *******************/
bogdanm 0:9b334a45a8ff 4716 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
bogdanm 0:9b334a45a8ff 4717 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4718 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4719 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4720 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4721 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4722
bogdanm 0:9b334a45a8ff 4723 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
bogdanm 0:9b334a45a8ff 4724 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4725 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4726 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4727 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4728 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4729
bogdanm 0:9b334a45a8ff 4730 /******************* Bit definition for TIM_DMAR register ******************/
bogdanm 0:9b334a45a8ff 4731 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
bogdanm 0:9b334a45a8ff 4732
bogdanm 0:9b334a45a8ff 4733 /******************* Bit definition for TIM14_OR register ********************/
bogdanm 0:9b334a45a8ff 4734 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
bogdanm 0:9b334a45a8ff 4735 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4736 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4737
bogdanm 0:9b334a45a8ff 4738 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4739 /* */
bogdanm 0:9b334a45a8ff 4740 /* Touch Sensing Controller (TSC) */
bogdanm 0:9b334a45a8ff 4741 /* */
bogdanm 0:9b334a45a8ff 4742 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4743 /******************* Bit definition for TSC_CR register *********************/
bogdanm 0:9b334a45a8ff 4744 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
bogdanm 0:9b334a45a8ff 4745 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
bogdanm 0:9b334a45a8ff 4746 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
bogdanm 0:9b334a45a8ff 4747 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
bogdanm 0:9b334a45a8ff 4748 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
bogdanm 0:9b334a45a8ff 4749
bogdanm 0:9b334a45a8ff 4750 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
bogdanm 0:9b334a45a8ff 4751 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4752 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4753 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4754
bogdanm 0:9b334a45a8ff 4755 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
bogdanm 0:9b334a45a8ff 4756 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4757 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4758 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4759
bogdanm 0:9b334a45a8ff 4760 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
bogdanm 0:9b334a45a8ff 4761 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
bogdanm 0:9b334a45a8ff 4762
bogdanm 0:9b334a45a8ff 4763 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
bogdanm 0:9b334a45a8ff 4764 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4765 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4766 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4767 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4768 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 4769 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 4770 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 4771
bogdanm 0:9b334a45a8ff 4772 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
bogdanm 0:9b334a45a8ff 4773 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4774 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4775 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4776 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4777
bogdanm 0:9b334a45a8ff 4778 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
bogdanm 0:9b334a45a8ff 4779 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 4780 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 4781 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 4782 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 4783
bogdanm 0:9b334a45a8ff 4784 /******************* Bit definition for TSC_IER register ********************/
bogdanm 0:9b334a45a8ff 4785 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
bogdanm 0:9b334a45a8ff 4786 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
bogdanm 0:9b334a45a8ff 4787
bogdanm 0:9b334a45a8ff 4788 /******************* Bit definition for TSC_ICR register ********************/
bogdanm 0:9b334a45a8ff 4789 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
bogdanm 0:9b334a45a8ff 4790 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
bogdanm 0:9b334a45a8ff 4791
bogdanm 0:9b334a45a8ff 4792 /******************* Bit definition for TSC_ISR register ********************/
bogdanm 0:9b334a45a8ff 4793 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
bogdanm 0:9b334a45a8ff 4794 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
bogdanm 0:9b334a45a8ff 4795
bogdanm 0:9b334a45a8ff 4796 /******************* Bit definition for TSC_IOHCR register ******************/
bogdanm 0:9b334a45a8ff 4797 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4798 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4799 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4800 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4801 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4802 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4803 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4804 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4805 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4806 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4807 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4808 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4809 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4810 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4811 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4812 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4813 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4814 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4815 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4816 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4817 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4818 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4819 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4820 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4821 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4822 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4823 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4824 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4825 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4826 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4827 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4828 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
bogdanm 0:9b334a45a8ff 4829
bogdanm 0:9b334a45a8ff 4830 /******************* Bit definition for TSC_IOASCR register *****************/
bogdanm 0:9b334a45a8ff 4831 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4832 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4833 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4834 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4835 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4836 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4837 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4838 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4839 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4840 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4841 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4842 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4843 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4844 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4845 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4846 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4847 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4848 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4849 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4850 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4851 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4852 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4853 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4854 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4855 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4856 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4857 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4858 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4859 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
bogdanm 0:9b334a45a8ff 4860 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
bogdanm 0:9b334a45a8ff 4861 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
bogdanm 0:9b334a45a8ff 4862 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
bogdanm 0:9b334a45a8ff 4863
bogdanm 0:9b334a45a8ff 4864 /******************* Bit definition for TSC_IOSCR register ******************/
bogdanm 0:9b334a45a8ff 4865 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4866 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4867 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4868 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4869 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4870 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4871 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4872 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4873 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4874 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4875 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4876 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4877 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4878 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4879 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4880 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4881 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4882 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4883 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4884 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4885 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4886 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4887 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4888 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4889 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4890 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4891 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4892 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4893 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
bogdanm 0:9b334a45a8ff 4894 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
bogdanm 0:9b334a45a8ff 4895 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
bogdanm 0:9b334a45a8ff 4896 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
bogdanm 0:9b334a45a8ff 4897
bogdanm 0:9b334a45a8ff 4898 /******************* Bit definition for TSC_IOCCR register ******************/
bogdanm 0:9b334a45a8ff 4899 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4900 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4901 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4902 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4903 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4904 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4905 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4906 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4907 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4908 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4909 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4910 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4911 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4912 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4913 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4914 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4915 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4916 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4917 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4918 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4919 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4920 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4921 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4922 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4923 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4924 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4925 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4926 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4927 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
bogdanm 0:9b334a45a8ff 4928 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
bogdanm 0:9b334a45a8ff 4929 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
bogdanm 0:9b334a45a8ff 4930 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
bogdanm 0:9b334a45a8ff 4931
bogdanm 0:9b334a45a8ff 4932 /******************* Bit definition for TSC_IOGCSR register *****************/
bogdanm 0:9b334a45a8ff 4933 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
bogdanm 0:9b334a45a8ff 4934 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
bogdanm 0:9b334a45a8ff 4935 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
bogdanm 0:9b334a45a8ff 4936 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
bogdanm 0:9b334a45a8ff 4937 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
bogdanm 0:9b334a45a8ff 4938 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
bogdanm 0:9b334a45a8ff 4939 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
bogdanm 0:9b334a45a8ff 4940 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
bogdanm 0:9b334a45a8ff 4941 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
bogdanm 0:9b334a45a8ff 4942 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
bogdanm 0:9b334a45a8ff 4943 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
bogdanm 0:9b334a45a8ff 4944 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
bogdanm 0:9b334a45a8ff 4945 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
bogdanm 0:9b334a45a8ff 4946 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
bogdanm 0:9b334a45a8ff 4947 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
bogdanm 0:9b334a45a8ff 4948 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
bogdanm 0:9b334a45a8ff 4949
bogdanm 0:9b334a45a8ff 4950 /******************* Bit definition for TSC_IOGXCR register *****************/
bogdanm 0:9b334a45a8ff 4951 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
bogdanm 0:9b334a45a8ff 4952
bogdanm 0:9b334a45a8ff 4953 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4954 /* */
bogdanm 0:9b334a45a8ff 4955 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm 0:9b334a45a8ff 4956 /* */
bogdanm 0:9b334a45a8ff 4957 /******************************************************************************/
bogdanm 0:9b334a45a8ff 4958 /****************** Bit definition for USART_CR1 register *******************/
bogdanm 0:9b334a45a8ff 4959 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
bogdanm 0:9b334a45a8ff 4960 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
bogdanm 0:9b334a45a8ff 4961 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
bogdanm 0:9b334a45a8ff 4962 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
bogdanm 0:9b334a45a8ff 4963 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
bogdanm 0:9b334a45a8ff 4964 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
bogdanm 0:9b334a45a8ff 4965 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
bogdanm 0:9b334a45a8ff 4966 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
bogdanm 0:9b334a45a8ff 4967 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
bogdanm 0:9b334a45a8ff 4968 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
bogdanm 0:9b334a45a8ff 4969 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
bogdanm 0:9b334a45a8ff 4970 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
bogdanm 0:9b334a45a8ff 4971 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
bogdanm 0:9b334a45a8ff 4972 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
bogdanm 0:9b334a45a8ff 4973 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
bogdanm 0:9b334a45a8ff 4974 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
bogdanm 0:9b334a45a8ff 4975 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
bogdanm 0:9b334a45a8ff 4976 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4977 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4978 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4979 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 4980 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
bogdanm 0:9b334a45a8ff 4981 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
bogdanm 0:9b334a45a8ff 4982 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 4983 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 4984 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 4985 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
bogdanm 0:9b334a45a8ff 4986 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
bogdanm 0:9b334a45a8ff 4987 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
bogdanm 0:9b334a45a8ff 4988 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
bogdanm 0:9b334a45a8ff 4989 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
bogdanm 0:9b334a45a8ff 4990 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
bogdanm 0:9b334a45a8ff 4991
bogdanm 0:9b334a45a8ff 4992 /****************** Bit definition for USART_CR2 register *******************/
bogdanm 0:9b334a45a8ff 4993 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
bogdanm 0:9b334a45a8ff 4994 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
bogdanm 0:9b334a45a8ff 4995 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
bogdanm 0:9b334a45a8ff 4996 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
bogdanm 0:9b334a45a8ff 4997 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
bogdanm 0:9b334a45a8ff 4998 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
bogdanm 0:9b334a45a8ff 4999 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
bogdanm 0:9b334a45a8ff 5000 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
bogdanm 0:9b334a45a8ff 5001 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5002 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5003 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
bogdanm 0:9b334a45a8ff 5004 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
bogdanm 0:9b334a45a8ff 5005 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
bogdanm 0:9b334a45a8ff 5006 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
bogdanm 0:9b334a45a8ff 5007 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
bogdanm 0:9b334a45a8ff 5008 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
bogdanm 0:9b334a45a8ff 5009 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
bogdanm 0:9b334a45a8ff 5010 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
bogdanm 0:9b334a45a8ff 5011 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5012 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5013 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
bogdanm 0:9b334a45a8ff 5014 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
bogdanm 0:9b334a45a8ff 5015
bogdanm 0:9b334a45a8ff 5016 /****************** Bit definition for USART_CR3 register *******************/
bogdanm 0:9b334a45a8ff 5017 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
bogdanm 0:9b334a45a8ff 5018 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
bogdanm 0:9b334a45a8ff 5019 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
bogdanm 0:9b334a45a8ff 5020 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
bogdanm 0:9b334a45a8ff 5021 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
bogdanm 0:9b334a45a8ff 5022 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
bogdanm 0:9b334a45a8ff 5023 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
bogdanm 0:9b334a45a8ff 5024 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
bogdanm 0:9b334a45a8ff 5025 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
bogdanm 0:9b334a45a8ff 5026 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
bogdanm 0:9b334a45a8ff 5027 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
bogdanm 0:9b334a45a8ff 5028 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
bogdanm 0:9b334a45a8ff 5029 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
bogdanm 0:9b334a45a8ff 5030 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
bogdanm 0:9b334a45a8ff 5031 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
bogdanm 0:9b334a45a8ff 5032 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
bogdanm 0:9b334a45a8ff 5033 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
bogdanm 0:9b334a45a8ff 5034 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5035 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5036 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
bogdanm 0:9b334a45a8ff 5037 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
bogdanm 0:9b334a45a8ff 5038 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
bogdanm 0:9b334a45a8ff 5039 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
bogdanm 0:9b334a45a8ff 5040 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
bogdanm 0:9b334a45a8ff 5041
bogdanm 0:9b334a45a8ff 5042 /****************** Bit definition for USART_BRR register *******************/
bogdanm 0:9b334a45a8ff 5043 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
bogdanm 0:9b334a45a8ff 5044 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
bogdanm 0:9b334a45a8ff 5045
bogdanm 0:9b334a45a8ff 5046 /****************** Bit definition for USART_GTPR register ******************/
bogdanm 0:9b334a45a8ff 5047 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
bogdanm 0:9b334a45a8ff 5048 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
bogdanm 0:9b334a45a8ff 5049
bogdanm 0:9b334a45a8ff 5050
bogdanm 0:9b334a45a8ff 5051 /******************* Bit definition for USART_RTOR register *****************/
bogdanm 0:9b334a45a8ff 5052 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
bogdanm 0:9b334a45a8ff 5053 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
bogdanm 0:9b334a45a8ff 5054
bogdanm 0:9b334a45a8ff 5055 /******************* Bit definition for USART_RQR register ******************/
bogdanm 0:9b334a45a8ff 5056 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
bogdanm 0:9b334a45a8ff 5057 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
bogdanm 0:9b334a45a8ff 5058 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
bogdanm 0:9b334a45a8ff 5059 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
bogdanm 0:9b334a45a8ff 5060 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
bogdanm 0:9b334a45a8ff 5061
bogdanm 0:9b334a45a8ff 5062 /******************* Bit definition for USART_ISR register ******************/
bogdanm 0:9b334a45a8ff 5063 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
bogdanm 0:9b334a45a8ff 5064 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
bogdanm 0:9b334a45a8ff 5065 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
bogdanm 0:9b334a45a8ff 5066 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
bogdanm 0:9b334a45a8ff 5067 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
bogdanm 0:9b334a45a8ff 5068 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
bogdanm 0:9b334a45a8ff 5069 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
bogdanm 0:9b334a45a8ff 5070 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
bogdanm 0:9b334a45a8ff 5071 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
bogdanm 0:9b334a45a8ff 5072 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
bogdanm 0:9b334a45a8ff 5073 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
bogdanm 0:9b334a45a8ff 5074 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
bogdanm 0:9b334a45a8ff 5075 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
bogdanm 0:9b334a45a8ff 5076 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
bogdanm 0:9b334a45a8ff 5077 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
bogdanm 0:9b334a45a8ff 5078 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
bogdanm 0:9b334a45a8ff 5079 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
bogdanm 0:9b334a45a8ff 5080 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
bogdanm 0:9b334a45a8ff 5081 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
bogdanm 0:9b334a45a8ff 5082 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
bogdanm 0:9b334a45a8ff 5083 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
bogdanm 0:9b334a45a8ff 5084 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
bogdanm 0:9b334a45a8ff 5085
bogdanm 0:9b334a45a8ff 5086 /******************* Bit definition for USART_ICR register ******************/
bogdanm 0:9b334a45a8ff 5087 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
bogdanm 0:9b334a45a8ff 5088 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
bogdanm 0:9b334a45a8ff 5089 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
bogdanm 0:9b334a45a8ff 5090 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
bogdanm 0:9b334a45a8ff 5091 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
bogdanm 0:9b334a45a8ff 5092 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
bogdanm 0:9b334a45a8ff 5093 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
bogdanm 0:9b334a45a8ff 5094 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
bogdanm 0:9b334a45a8ff 5095 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
bogdanm 0:9b334a45a8ff 5096 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
bogdanm 0:9b334a45a8ff 5097 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
bogdanm 0:9b334a45a8ff 5098 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
bogdanm 0:9b334a45a8ff 5099
bogdanm 0:9b334a45a8ff 5100 /******************* Bit definition for USART_RDR register ******************/
bogdanm 0:9b334a45a8ff 5101 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
bogdanm 0:9b334a45a8ff 5102
bogdanm 0:9b334a45a8ff 5103 /******************* Bit definition for USART_TDR register ******************/
bogdanm 0:9b334a45a8ff 5104 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
bogdanm 0:9b334a45a8ff 5105
bogdanm 0:9b334a45a8ff 5106 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5107 /* */
bogdanm 0:9b334a45a8ff 5108 /* USB Device General registers */
bogdanm 0:9b334a45a8ff 5109 /* */
bogdanm 0:9b334a45a8ff 5110 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5111 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
bogdanm 0:9b334a45a8ff 5112 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
bogdanm 0:9b334a45a8ff 5113 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
bogdanm 0:9b334a45a8ff 5114 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
bogdanm 0:9b334a45a8ff 5115 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
bogdanm 0:9b334a45a8ff 5116 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
bogdanm 0:9b334a45a8ff 5117 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
bogdanm 0:9b334a45a8ff 5118
bogdanm 0:9b334a45a8ff 5119 /**************************** ISTR interrupt events *************************/
bogdanm 0:9b334a45a8ff 5120 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
bogdanm 0:9b334a45a8ff 5121 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
bogdanm 0:9b334a45a8ff 5122 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
bogdanm 0:9b334a45a8ff 5123 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
bogdanm 0:9b334a45a8ff 5124 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
bogdanm 0:9b334a45a8ff 5125 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
bogdanm 0:9b334a45a8ff 5126 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
bogdanm 0:9b334a45a8ff 5127 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
bogdanm 0:9b334a45a8ff 5128 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
bogdanm 0:9b334a45a8ff 5129 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
bogdanm 0:9b334a45a8ff 5130 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
bogdanm 0:9b334a45a8ff 5131
bogdanm 0:9b334a45a8ff 5132 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
bogdanm 0:9b334a45a8ff 5133 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
bogdanm 0:9b334a45a8ff 5134 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
bogdanm 0:9b334a45a8ff 5135 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
bogdanm 0:9b334a45a8ff 5136 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
bogdanm 0:9b334a45a8ff 5137 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
bogdanm 0:9b334a45a8ff 5138 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
bogdanm 0:9b334a45a8ff 5139 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
bogdanm 0:9b334a45a8ff 5140 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
bogdanm 0:9b334a45a8ff 5141
bogdanm 0:9b334a45a8ff 5142 /************************* CNTR control register bits definitions ***********/
bogdanm 0:9b334a45a8ff 5143 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
bogdanm 0:9b334a45a8ff 5144 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
bogdanm 0:9b334a45a8ff 5145 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
bogdanm 0:9b334a45a8ff 5146 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
bogdanm 0:9b334a45a8ff 5147 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
bogdanm 0:9b334a45a8ff 5148 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
bogdanm 0:9b334a45a8ff 5149 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
bogdanm 0:9b334a45a8ff 5150 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
bogdanm 0:9b334a45a8ff 5151 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
bogdanm 0:9b334a45a8ff 5152 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
bogdanm 0:9b334a45a8ff 5153 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
bogdanm 0:9b334a45a8ff 5154 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
bogdanm 0:9b334a45a8ff 5155 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
bogdanm 0:9b334a45a8ff 5156 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
bogdanm 0:9b334a45a8ff 5157 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
bogdanm 0:9b334a45a8ff 5158
bogdanm 0:9b334a45a8ff 5159 /************************* BCDR control register bits definitions ***********/
bogdanm 0:9b334a45a8ff 5160 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
bogdanm 0:9b334a45a8ff 5161 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
bogdanm 0:9b334a45a8ff 5162 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
bogdanm 0:9b334a45a8ff 5163 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
bogdanm 0:9b334a45a8ff 5164 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
bogdanm 0:9b334a45a8ff 5165 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
bogdanm 0:9b334a45a8ff 5166 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
bogdanm 0:9b334a45a8ff 5167 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
bogdanm 0:9b334a45a8ff 5168 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
bogdanm 0:9b334a45a8ff 5169
bogdanm 0:9b334a45a8ff 5170 /*************************** LPM register bits definitions ******************/
bogdanm 0:9b334a45a8ff 5171 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
bogdanm 0:9b334a45a8ff 5172 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
bogdanm 0:9b334a45a8ff 5173 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
bogdanm 0:9b334a45a8ff 5174 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
bogdanm 0:9b334a45a8ff 5175
bogdanm 0:9b334a45a8ff 5176 /******************** FNR Frame Number Register bit definitions ************/
bogdanm 0:9b334a45a8ff 5177 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
bogdanm 0:9b334a45a8ff 5178 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
bogdanm 0:9b334a45a8ff 5179 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
bogdanm 0:9b334a45a8ff 5180 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
bogdanm 0:9b334a45a8ff 5181 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
bogdanm 0:9b334a45a8ff 5182
bogdanm 0:9b334a45a8ff 5183 /******************** DADDR Device ADDRess bit definitions ****************/
bogdanm 0:9b334a45a8ff 5184 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
bogdanm 0:9b334a45a8ff 5185 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
bogdanm 0:9b334a45a8ff 5186
bogdanm 0:9b334a45a8ff 5187 /****************************** Endpoint register *************************/
bogdanm 0:9b334a45a8ff 5188 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
bogdanm 0:9b334a45a8ff 5189 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
bogdanm 0:9b334a45a8ff 5190 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
bogdanm 0:9b334a45a8ff 5191 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
bogdanm 0:9b334a45a8ff 5192 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
bogdanm 0:9b334a45a8ff 5193 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
bogdanm 0:9b334a45a8ff 5194 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
bogdanm 0:9b334a45a8ff 5195 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
bogdanm 0:9b334a45a8ff 5196 /* bit positions */
bogdanm 0:9b334a45a8ff 5197 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
bogdanm 0:9b334a45a8ff 5198 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
bogdanm 0:9b334a45a8ff 5199 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
bogdanm 0:9b334a45a8ff 5200 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
bogdanm 0:9b334a45a8ff 5201 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
bogdanm 0:9b334a45a8ff 5202 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
bogdanm 0:9b334a45a8ff 5203 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
bogdanm 0:9b334a45a8ff 5204 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
bogdanm 0:9b334a45a8ff 5205 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
bogdanm 0:9b334a45a8ff 5206 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
bogdanm 0:9b334a45a8ff 5207
bogdanm 0:9b334a45a8ff 5208 /* EndPoint REGister MASK (no toggle fields) */
bogdanm 0:9b334a45a8ff 5209 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
bogdanm 0:9b334a45a8ff 5210 /*!< EP_TYPE[1:0] EndPoint TYPE */
bogdanm 0:9b334a45a8ff 5211 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
bogdanm 0:9b334a45a8ff 5212 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
bogdanm 0:9b334a45a8ff 5213 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
bogdanm 0:9b334a45a8ff 5214 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
bogdanm 0:9b334a45a8ff 5215 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
bogdanm 0:9b334a45a8ff 5216 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
bogdanm 0:9b334a45a8ff 5217
bogdanm 0:9b334a45a8ff 5218 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
bogdanm 0:9b334a45a8ff 5219 /*!< STAT_TX[1:0] STATus for TX transfer */
bogdanm 0:9b334a45a8ff 5220 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
bogdanm 0:9b334a45a8ff 5221 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
bogdanm 0:9b334a45a8ff 5222 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
bogdanm 0:9b334a45a8ff 5223 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
bogdanm 0:9b334a45a8ff 5224 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
bogdanm 0:9b334a45a8ff 5225 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
bogdanm 0:9b334a45a8ff 5226 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
bogdanm 0:9b334a45a8ff 5227 /*!< STAT_RX[1:0] STATus for RX transfer */
bogdanm 0:9b334a45a8ff 5228 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
bogdanm 0:9b334a45a8ff 5229 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
bogdanm 0:9b334a45a8ff 5230 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
bogdanm 0:9b334a45a8ff 5231 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
bogdanm 0:9b334a45a8ff 5232 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
bogdanm 0:9b334a45a8ff 5233 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
bogdanm 0:9b334a45a8ff 5234 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
bogdanm 0:9b334a45a8ff 5235
bogdanm 0:9b334a45a8ff 5236 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5237 /* */
bogdanm 0:9b334a45a8ff 5238 /* Window WATCHDOG (WWDG) */
bogdanm 0:9b334a45a8ff 5239 /* */
bogdanm 0:9b334a45a8ff 5240 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5241 /******************* Bit definition for WWDG_CR register ********************/
bogdanm 0:9b334a45a8ff 5242 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
bogdanm 0:9b334a45a8ff 5243 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5244 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5245 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 5246 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 5247 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 5248 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 5249 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 5250
bogdanm 0:9b334a45a8ff 5251 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
bogdanm 0:9b334a45a8ff 5252
bogdanm 0:9b334a45a8ff 5253 /******************* Bit definition for WWDG_CFR register *******************/
bogdanm 0:9b334a45a8ff 5254 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
bogdanm 0:9b334a45a8ff 5255 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5256 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5257 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
bogdanm 0:9b334a45a8ff 5258 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
bogdanm 0:9b334a45a8ff 5259 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
bogdanm 0:9b334a45a8ff 5260 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
bogdanm 0:9b334a45a8ff 5261 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
bogdanm 0:9b334a45a8ff 5262
bogdanm 0:9b334a45a8ff 5263 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
bogdanm 0:9b334a45a8ff 5264 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
bogdanm 0:9b334a45a8ff 5265 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
bogdanm 0:9b334a45a8ff 5266
bogdanm 0:9b334a45a8ff 5267 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
bogdanm 0:9b334a45a8ff 5268
bogdanm 0:9b334a45a8ff 5269 /******************* Bit definition for WWDG_SR register ********************/
bogdanm 0:9b334a45a8ff 5270 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
bogdanm 0:9b334a45a8ff 5271
bogdanm 0:9b334a45a8ff 5272 /**
bogdanm 0:9b334a45a8ff 5273 * @}
bogdanm 0:9b334a45a8ff 5274 */
bogdanm 0:9b334a45a8ff 5275
bogdanm 0:9b334a45a8ff 5276 /**
bogdanm 0:9b334a45a8ff 5277 * @}
bogdanm 0:9b334a45a8ff 5278 */
bogdanm 0:9b334a45a8ff 5279
bogdanm 0:9b334a45a8ff 5280
bogdanm 0:9b334a45a8ff 5281 /** @addtogroup Exported_macro
bogdanm 0:9b334a45a8ff 5282 * @{
bogdanm 0:9b334a45a8ff 5283 */
bogdanm 0:9b334a45a8ff 5284
bogdanm 0:9b334a45a8ff 5285 /****************************** ADC Instances *********************************/
bogdanm 0:9b334a45a8ff 5286 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm 0:9b334a45a8ff 5287
bogdanm 0:9b334a45a8ff 5288 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
bogdanm 0:9b334a45a8ff 5289
bogdanm 0:9b334a45a8ff 5290 /******************************* CAN Instances ********************************/
bogdanm 0:9b334a45a8ff 5291 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
bogdanm 0:9b334a45a8ff 5292
bogdanm 0:9b334a45a8ff 5293 /****************************** COMP Instances *********************************/
bogdanm 0:9b334a45a8ff 5294 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
bogdanm 0:9b334a45a8ff 5295 ((INSTANCE) == COMP2))
bogdanm 0:9b334a45a8ff 5296
bogdanm 0:9b334a45a8ff 5297 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
bogdanm 0:9b334a45a8ff 5298
bogdanm 0:9b334a45a8ff 5299 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
bogdanm 0:9b334a45a8ff 5300
bogdanm 0:9b334a45a8ff 5301 /****************************** CEC Instances *********************************/
bogdanm 0:9b334a45a8ff 5302 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
bogdanm 0:9b334a45a8ff 5303
bogdanm 0:9b334a45a8ff 5304 /****************************** CRC Instances *********************************/
bogdanm 0:9b334a45a8ff 5305 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm 0:9b334a45a8ff 5306
bogdanm 0:9b334a45a8ff 5307 /******************************* DAC Instances ********************************/
bogdanm 0:9b334a45a8ff 5308 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm 0:9b334a45a8ff 5309
bogdanm 0:9b334a45a8ff 5310 /******************************* DMA Instances ******************************/
bogdanm 0:9b334a45a8ff 5311 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
bogdanm 0:9b334a45a8ff 5312 ((INSTANCE) == DMA1_Channel2) || \
bogdanm 0:9b334a45a8ff 5313 ((INSTANCE) == DMA1_Channel3) || \
bogdanm 0:9b334a45a8ff 5314 ((INSTANCE) == DMA1_Channel4) || \
bogdanm 0:9b334a45a8ff 5315 ((INSTANCE) == DMA1_Channel5) || \
bogdanm 0:9b334a45a8ff 5316 ((INSTANCE) == DMA1_Channel6) || \
bogdanm 0:9b334a45a8ff 5317 ((INSTANCE) == DMA1_Channel7))
bogdanm 0:9b334a45a8ff 5318
bogdanm 0:9b334a45a8ff 5319 /****************************** GPIO Instances ********************************/
bogdanm 0:9b334a45a8ff 5320 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 0:9b334a45a8ff 5321 ((INSTANCE) == GPIOB) || \
bogdanm 0:9b334a45a8ff 5322 ((INSTANCE) == GPIOC) || \
bogdanm 0:9b334a45a8ff 5323 ((INSTANCE) == GPIOD) || \
bogdanm 0:9b334a45a8ff 5324 ((INSTANCE) == GPIOE) || \
bogdanm 0:9b334a45a8ff 5325 ((INSTANCE) == GPIOF))
bogdanm 0:9b334a45a8ff 5326
bogdanm 0:9b334a45a8ff 5327 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 0:9b334a45a8ff 5328 ((INSTANCE) == GPIOB) || \
bogdanm 0:9b334a45a8ff 5329 ((INSTANCE) == GPIOC) || \
bogdanm 0:9b334a45a8ff 5330 ((INSTANCE) == GPIOD) || \
bogdanm 0:9b334a45a8ff 5331 ((INSTANCE) == GPIOE))
bogdanm 0:9b334a45a8ff 5332
bogdanm 0:9b334a45a8ff 5333 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
bogdanm 0:9b334a45a8ff 5334 ((INSTANCE) == GPIOB))
bogdanm 0:9b334a45a8ff 5335
bogdanm 0:9b334a45a8ff 5336 /****************************** I2C Instances *********************************/
bogdanm 0:9b334a45a8ff 5337 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
bogdanm 0:9b334a45a8ff 5338 ((INSTANCE) == I2C2))
bogdanm 0:9b334a45a8ff 5339
bogdanm 0:9b334a45a8ff 5340 /****************************** I2S Instances *********************************/
bogdanm 0:9b334a45a8ff 5341 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 0:9b334a45a8ff 5342 ((INSTANCE) == SPI2))
bogdanm 0:9b334a45a8ff 5343
bogdanm 0:9b334a45a8ff 5344 /****************************** IWDG Instances ********************************/
bogdanm 0:9b334a45a8ff 5345 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm 0:9b334a45a8ff 5346
bogdanm 0:9b334a45a8ff 5347 /****************************** RTC Instances *********************************/
bogdanm 0:9b334a45a8ff 5348 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm 0:9b334a45a8ff 5349
bogdanm 0:9b334a45a8ff 5350 /****************************** SMBUS Instances *********************************/
bogdanm 0:9b334a45a8ff 5351 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
bogdanm 0:9b334a45a8ff 5352
bogdanm 0:9b334a45a8ff 5353 /****************************** SPI Instances *********************************/
bogdanm 0:9b334a45a8ff 5354 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
bogdanm 0:9b334a45a8ff 5355 ((INSTANCE) == SPI2))
bogdanm 0:9b334a45a8ff 5356
bogdanm 0:9b334a45a8ff 5357 /****************************** TIM Instances *********************************/
bogdanm 0:9b334a45a8ff 5358 #define IS_TIM_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5359 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5360 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5361 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5362 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 5363 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 5364 ((INSTANCE) == TIM14) || \
bogdanm 0:9b334a45a8ff 5365 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5366 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5367 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5368
bogdanm 0:9b334a45a8ff 5369 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5370 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5371 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5372 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5373 ((INSTANCE) == TIM14) || \
bogdanm 0:9b334a45a8ff 5374 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5375 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5376 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5377
bogdanm 0:9b334a45a8ff 5378 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5379 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5380 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5381 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5382 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 5383
bogdanm 0:9b334a45a8ff 5384 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5385 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5386 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5387 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5388
bogdanm 0:9b334a45a8ff 5389 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5390 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5391 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5392 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5393
bogdanm 0:9b334a45a8ff 5394 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5395 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5396 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5397 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5398
bogdanm 0:9b334a45a8ff 5399 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5400 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5401 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5402 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5403
bogdanm 0:9b334a45a8ff 5404 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5405 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5406 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5407 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5408 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 5409
bogdanm 0:9b334a45a8ff 5410 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5411 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5412 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5413 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5414 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 5415
bogdanm 0:9b334a45a8ff 5416 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5417 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5418 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5419 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5420
bogdanm 0:9b334a45a8ff 5421 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5422 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5423 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5424 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5425
bogdanm 0:9b334a45a8ff 5426 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5427 (((INSTANCE) == TIM1))
bogdanm 0:9b334a45a8ff 5428
bogdanm 0:9b334a45a8ff 5429 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5430 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5431 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5432 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5433
bogdanm 0:9b334a45a8ff 5434 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5435 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5436 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5437 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5438 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 5439 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 5440 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 5441
bogdanm 0:9b334a45a8ff 5442 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5443 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5444 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5445 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5446 ((INSTANCE) == TIM15))
bogdanm 0:9b334a45a8ff 5447
bogdanm 0:9b334a45a8ff 5448 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5449 ((INSTANCE) == TIM2)
bogdanm 0:9b334a45a8ff 5450
bogdanm 0:9b334a45a8ff 5451 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5452 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5453 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5454 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5455 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5456 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5457 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5458
bogdanm 0:9b334a45a8ff 5459 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5460 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5461 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5462 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5463 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5464
bogdanm 0:9b334a45a8ff 5465 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 0:9b334a45a8ff 5466 ((((INSTANCE) == TIM1) && \
bogdanm 0:9b334a45a8ff 5467 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 5468 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 5469 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 5470 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 0:9b334a45a8ff 5471 || \
bogdanm 0:9b334a45a8ff 5472 (((INSTANCE) == TIM2) && \
bogdanm 0:9b334a45a8ff 5473 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 5474 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 5475 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 5476 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 0:9b334a45a8ff 5477 || \
bogdanm 0:9b334a45a8ff 5478 (((INSTANCE) == TIM3) && \
bogdanm 0:9b334a45a8ff 5479 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 5480 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 5481 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 0:9b334a45a8ff 5482 ((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm 0:9b334a45a8ff 5483 || \
bogdanm 0:9b334a45a8ff 5484 (((INSTANCE) == TIM14) && \
bogdanm 0:9b334a45a8ff 5485 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 0:9b334a45a8ff 5486 || \
bogdanm 0:9b334a45a8ff 5487 (((INSTANCE) == TIM15) && \
bogdanm 0:9b334a45a8ff 5488 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 5489 ((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm 0:9b334a45a8ff 5490 || \
bogdanm 0:9b334a45a8ff 5491 (((INSTANCE) == TIM16) && \
bogdanm 0:9b334a45a8ff 5492 (((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm 0:9b334a45a8ff 5493 || \
bogdanm 0:9b334a45a8ff 5494 (((INSTANCE) == TIM17) && \
bogdanm 0:9b334a45a8ff 5495 (((CHANNEL) == TIM_CHANNEL_1))))
bogdanm 0:9b334a45a8ff 5496
bogdanm 0:9b334a45a8ff 5497 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm 0:9b334a45a8ff 5498 ((((INSTANCE) == TIM1) && \
bogdanm 0:9b334a45a8ff 5499 (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 0:9b334a45a8ff 5500 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 0:9b334a45a8ff 5501 ((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm 0:9b334a45a8ff 5502 || \
bogdanm 0:9b334a45a8ff 5503 (((INSTANCE) == TIM15) && \
bogdanm 0:9b334a45a8ff 5504 ((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm 0:9b334a45a8ff 5505 || \
bogdanm 0:9b334a45a8ff 5506 (((INSTANCE) == TIM16) && \
bogdanm 0:9b334a45a8ff 5507 ((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm 0:9b334a45a8ff 5508 || \
bogdanm 0:9b334a45a8ff 5509 (((INSTANCE) == TIM17) && \
bogdanm 0:9b334a45a8ff 5510 ((CHANNEL) == TIM_CHANNEL_1)))
bogdanm 0:9b334a45a8ff 5511
bogdanm 0:9b334a45a8ff 5512 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5513 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5514 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5515 ((INSTANCE) == TIM3))
bogdanm 0:9b334a45a8ff 5516
bogdanm 0:9b334a45a8ff 5517 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5518 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5519 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5520 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5521 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5522
bogdanm 0:9b334a45a8ff 5523 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5524 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5525 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5526 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5527 ((INSTANCE) == TIM14) || \
bogdanm 0:9b334a45a8ff 5528 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5529 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5530 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5531
bogdanm 0:9b334a45a8ff 5532 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5533 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5534 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5535 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5536 ((INSTANCE) == TIM6) || \
bogdanm 0:9b334a45a8ff 5537 ((INSTANCE) == TIM7) || \
bogdanm 0:9b334a45a8ff 5538 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5539 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5540 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5541
bogdanm 0:9b334a45a8ff 5542 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5543 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5544 ((INSTANCE) == TIM2) || \
bogdanm 0:9b334a45a8ff 5545 ((INSTANCE) == TIM3) || \
bogdanm 0:9b334a45a8ff 5546 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5547 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5548 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5549
bogdanm 0:9b334a45a8ff 5550 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5551 (((INSTANCE) == TIM1) || \
bogdanm 0:9b334a45a8ff 5552 ((INSTANCE) == TIM15) || \
bogdanm 0:9b334a45a8ff 5553 ((INSTANCE) == TIM16) || \
bogdanm 0:9b334a45a8ff 5554 ((INSTANCE) == TIM17))
bogdanm 0:9b334a45a8ff 5555
bogdanm 0:9b334a45a8ff 5556 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
bogdanm 0:9b334a45a8ff 5557 ((INSTANCE) == TIM14)
bogdanm 0:9b334a45a8ff 5558
bogdanm 0:9b334a45a8ff 5559 /****************************** TSC Instances *********************************/
bogdanm 0:9b334a45a8ff 5560 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
bogdanm 0:9b334a45a8ff 5561
bogdanm 0:9b334a45a8ff 5562 /*********************** UART Instances : IRDA mode ***************************/
bogdanm 0:9b334a45a8ff 5563 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5564 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 5565
bogdanm 0:9b334a45a8ff 5566 /********************* UART Instances : Smard card mode ***********************/
bogdanm 0:9b334a45a8ff 5567 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5568 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 5569
bogdanm 0:9b334a45a8ff 5570 /******************** USART Instances : Synchronous mode **********************/
bogdanm 0:9b334a45a8ff 5571 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5572 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 5573 ((INSTANCE) == USART3) || \
bogdanm 0:9b334a45a8ff 5574 ((INSTANCE) == USART4))
bogdanm 0:9b334a45a8ff 5575
bogdanm 0:9b334a45a8ff 5576 /******************** USART Instances : auto Baud rate detection **************/
bogdanm 0:9b334a45a8ff 5577 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5578 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 5579
bogdanm 0:9b334a45a8ff 5580 /******************** UART Instances : Asynchronous mode **********************/
bogdanm 0:9b334a45a8ff 5581 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5582 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 5583 ((INSTANCE) == USART3) || \
bogdanm 0:9b334a45a8ff 5584 ((INSTANCE) == USART4))
bogdanm 0:9b334a45a8ff 5585
bogdanm 0:9b334a45a8ff 5586 /******************** UART Instances : Half-Duplex mode **********************/
bogdanm 0:9b334a45a8ff 5587 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5588 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 5589 ((INSTANCE) == USART3) || \
bogdanm 0:9b334a45a8ff 5590 ((INSTANCE) == USART4))
bogdanm 0:9b334a45a8ff 5591
bogdanm 0:9b334a45a8ff 5592 /****************** UART Instances : Hardware Flow control ********************/
bogdanm 0:9b334a45a8ff 5593 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5594 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 5595 ((INSTANCE) == USART3) || \
bogdanm 0:9b334a45a8ff 5596 ((INSTANCE) == USART4))
bogdanm 0:9b334a45a8ff 5597
bogdanm 0:9b334a45a8ff 5598 /****************** UART Instances : LIN mode ********************/
bogdanm 0:9b334a45a8ff 5599 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5600 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 5601
bogdanm 0:9b334a45a8ff 5602 /****************** UART Instances : wakeup from stop mode ********************/
bogdanm 0:9b334a45a8ff 5603 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5604 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 5605
bogdanm 0:9b334a45a8ff 5606 /****************** UART Instances : Auto Baud Rate detection ********************/
bogdanm 0:9b334a45a8ff 5607 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5608 ((INSTANCE) == USART2))
bogdanm 0:9b334a45a8ff 5609
bogdanm 0:9b334a45a8ff 5610 /****************** UART Instances : Driver enable detection ********************/
bogdanm 0:9b334a45a8ff 5611 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
bogdanm 0:9b334a45a8ff 5612 ((INSTANCE) == USART2) || \
bogdanm 0:9b334a45a8ff 5613 ((INSTANCE) == USART3) || \
bogdanm 0:9b334a45a8ff 5614 ((INSTANCE) == USART4))
bogdanm 0:9b334a45a8ff 5615
bogdanm 0:9b334a45a8ff 5616 /****************************** USB Instances ********************************/
bogdanm 0:9b334a45a8ff 5617 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
bogdanm 0:9b334a45a8ff 5618
bogdanm 0:9b334a45a8ff 5619 /****************************** WWDG Instances ********************************/
bogdanm 0:9b334a45a8ff 5620 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm 0:9b334a45a8ff 5621
bogdanm 0:9b334a45a8ff 5622 /**
bogdanm 0:9b334a45a8ff 5623 * @}
bogdanm 0:9b334a45a8ff 5624 */
bogdanm 0:9b334a45a8ff 5625
bogdanm 0:9b334a45a8ff 5626
bogdanm 0:9b334a45a8ff 5627 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5628 /* For a painless codes migration between the STM32F0xx device product */
bogdanm 0:9b334a45a8ff 5629 /* lines, the aliases defined below are put in place to overcome the */
bogdanm 0:9b334a45a8ff 5630 /* differences in the interrupt handlers and IRQn definitions. */
bogdanm 0:9b334a45a8ff 5631 /* No need to update developed interrupt code when moving across */
bogdanm 0:9b334a45a8ff 5632 /* product lines within the same STM32F0 Family */
bogdanm 0:9b334a45a8ff 5633 /******************************************************************************/
bogdanm 0:9b334a45a8ff 5634
bogdanm 0:9b334a45a8ff 5635 /* Aliases for __IRQn */
bogdanm 0:9b334a45a8ff 5636 #define PVD_IRQn PVD_VDDIO2_IRQn
bogdanm 0:9b334a45a8ff 5637 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
bogdanm 0:9b334a45a8ff 5638 #define RCC_IRQn RCC_CRS_IRQn
bogdanm 0:9b334a45a8ff 5639 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
bogdanm 0:9b334a45a8ff 5640 #define ADC1_IRQn ADC1_COMP_IRQn
bogdanm 0:9b334a45a8ff 5641 #define TIM6_IRQn TIM6_DAC_IRQn
bogdanm 0:9b334a45a8ff 5642
bogdanm 0:9b334a45a8ff 5643 /* Aliases for __IRQHandler */
bogdanm 0:9b334a45a8ff 5644 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
bogdanm 0:9b334a45a8ff 5645 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
bogdanm 0:9b334a45a8ff 5646 #define RCC_IRQHandler RCC_CRS_IRQHandler
bogdanm 0:9b334a45a8ff 5647 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
bogdanm 0:9b334a45a8ff 5648 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
bogdanm 0:9b334a45a8ff 5649 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
bogdanm 0:9b334a45a8ff 5650
bogdanm 0:9b334a45a8ff 5651 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 5652 }
bogdanm 0:9b334a45a8ff 5653 #endif /* __cplusplus */
bogdanm 0:9b334a45a8ff 5654
bogdanm 0:9b334a45a8ff 5655 #endif /* __STM32F072xB_H */
bogdanm 0:9b334a45a8ff 5656
bogdanm 0:9b334a45a8ff 5657 /**
bogdanm 0:9b334a45a8ff 5658 * @}
bogdanm 0:9b334a45a8ff 5659 */
bogdanm 0:9b334a45a8ff 5660
bogdanm 0:9b334a45a8ff 5661 /**
bogdanm 0:9b334a45a8ff 5662 * @}
bogdanm 0:9b334a45a8ff 5663 */
bogdanm 0:9b334a45a8ff 5664
bogdanm 0:9b334a45a8ff 5665 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/