mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h@160:d5399cc887bb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:40:56 2017 +0000
Revision:
160:d5399cc887bb
Parent:
151:5eaa88a5bcc7 
This updates the lib to the mbed lib v138

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file memory_map.h
<> 149:156823d33999 4 * @brief Defines the silicon memory map. All peripheral devices shall be mapped in structures.
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3525 $
<> 149:156823d33999 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup bsp
<> 149:156823d33999 28 @verbatim
<> 149:156823d33999 29 +-----------------+
<> 149:156823d33999 30 | | ,_________________________
<> 149:156823d33999 31 | Private Per. | |PMUREG 0x4001D000|
<> 149:156823d33999 32 0xE0000000 +-----------------+ |PADREG 0x4001C000|
<> 149:156823d33999 33 | |_____________|CLOCKREG 0x4001B000|
<> 149:156823d33999 34 | PERIPHERALS | |RFANAREG 0x40019000|
<> 149:156823d33999 35 +-----------------+ |RESETREG 0x40018000|
<> 149:156823d33999 36 | | |FLASHREG 0x40017000|
<> 149:156823d33999 37 0x3FFF8000 |SRAM A 32K | |AESREG 0x40016000|
<> 149:156823d33999 38 +-----------------+ |ADCREG 0x40015000|
<> 149:156823d33999 39 | | |MACHWREG 0x40014000|
<> 149:156823d33999 40 |SRAM B 16K | |RANDREG 0x40011000|
<> 149:156823d33999 41 0x3FFF4000 +-----------------+ |CROSSBREG 0x40010000|
<> 149:156823d33999 42 | | |RTCREG 0x4000F000|
<> 149:156823d33999 43 0x24000100 |SRAM DMA 7B | |GPIOREG 0x4000C000|
<> 149:156823d33999 44 +-----------------+ |PWMREG 0x4000B000|
<> 149:156823d33999 45 0x24000000 |SRAM MAC 256B | |WDTREG 0x4000A000|
<> 149:156823d33999 46 +-----------------+ |UARTREG 0x40008000|
<> 149:156823d33999 47 | 320K | |I2CREG 0x40007000|
<> 149:156823d33999 48 0x00102000 |FLASHB | |SPIREG 0x40006000|
<> 149:156823d33999 49 0x00100000 |FLASHB Inf Block | |UARTREG 0x40005000|
<> 149:156823d33999 50 +-----------------+ |TIM2REG 0x40002000|
<> 149:156823d33999 51 | 320K | |TIM1REG 0x40001000|
<> 149:156823d33999 52 0x00002000 |FLASHA | |TIM0REG 0x40000000|
<> 149:156823d33999 53 0x00000000 |FLASHA Inf Block | '`''''''''''''''''''''''''
<> 149:156823d33999 54 '`'''''''''''''''''
<> 149:156823d33999 55
<> 149:156823d33999 56 @endverbatim
<> 149:156823d33999 57 */
<> 149:156823d33999 58
<> 149:156823d33999 59 #ifndef _MEMORY_MAP_H_
<> 149:156823d33999 60 #define _MEMORY_MAP_H_
<> 149:156823d33999 61
<> 149:156823d33999 62 /*************************************************************************************************
<> 149:156823d33999 63 * *
<> 149:156823d33999 64 * Header files *
<> 149:156823d33999 65 * *
<> 149:156823d33999 66 *************************************************************************************************/
<> 149:156823d33999 67
<> 149:156823d33999 68 #include <stdint.h>
<> 149:156823d33999 69
<> 149:156823d33999 70 #include "architecture.h"
<> 149:156823d33999 71
<> 149:156823d33999 72 // Register maps of HW modules controlled with device drivers
<> 149:156823d33999 73 #include "adc_sar_map.h"
<> 149:156823d33999 74 #include "aes_map.h"
<> 149:156823d33999 75 #include "flash_map.h"
<> 149:156823d33999 76 #include "gpio_map.h"
<> 149:156823d33999 77 #include "i2c_ipc7208_map.h"
<> 149:156823d33999 78 #include "pwm_map.h"
<> 149:156823d33999 79 #include "rtc_map.h"
<> 149:156823d33999 80 #include "spi_ipc7207_map.h"
<> 149:156823d33999 81 #include "timer_map.h"
<> 149:156823d33999 82 #include "uart_16c550_map.h"
<> 149:156823d33999 83 #include "wdt_map.h"
<> 149:156823d33999 84
<> 149:156823d33999 85 // Register maps of HW modules controlled with specific functions
<> 149:156823d33999 86 #include "clock_map.h"
<> 149:156823d33999 87 #include "crossbar_map.h"
<> 149:156823d33999 88 #include "dma_map.h"
<> 149:156823d33999 89 #include "macHw_map.h"
<> 149:156823d33999 90 #include "pad_map.h"
<> 149:156823d33999 91 #include "pmu_map.h"
<> 149:156823d33999 92 #include "random_map.h"
<> 149:156823d33999 93 #include "reset_map.h"
<> 149:156823d33999 94 #include "rfAna_map.h"
<> 149:156823d33999 95 #include "test_map.h"
<> 149:156823d33999 96
<> 149:156823d33999 97 // Trim structure map
<> 149:156823d33999 98 #include "trim_map.h"
<> 149:156823d33999 99
<> 149:156823d33999 100 /*************************************************************************************************
<> 149:156823d33999 101 * *
<> 149:156823d33999 102 * Symbolic Constants *
<> 149:156823d33999 103 * *
<> 149:156823d33999 104 *************************************************************************************************/
<> 149:156823d33999 105
<> 149:156823d33999 106 /** Trim structure mapping
<> 149:156823d33999 107 *
<> 149:156823d33999 108 */
<> 149:156823d33999 109 #define TRIMREG_BASE ((uint32_t)0x1FA0)
<> 149:156823d33999 110 #define TRIMREG ((TrimReg_t *)TRIMREG_BASE)
<> 149:156823d33999 111
<> 151:5eaa88a5bcc7 112 /** User trim structure mapping
<> 151:5eaa88a5bcc7 113 *
<> 151:5eaa88a5bcc7 114 */
<> 151:5eaa88a5bcc7 115 #define USRETRIMREG_BASE ((uint32_t)0x2800)
<> 151:5eaa88a5bcc7 116 #define USERTRIMREG ((UserTrimReg_t *)USRETRIMREG_BASE)
<> 151:5eaa88a5bcc7 117
<> 149:156823d33999 118 /** DMA HW Registers Offset */
<> 149:156823d33999 119 #define DMAREG_BASE ((uint32_t)0x24000400)
<> 149:156823d33999 120 /** DMA HW Structure Overlay */
<> 149:156823d33999 121 #define DMAREG ((DmaReg_pt)DMAREG_BASE)
<> 149:156823d33999 122
<> 149:156823d33999 123 /** MAC MATCH HW Registers Offset */
<> 149:156823d33999 124 #define MACMATCHREG_BASE ((uint32_t)0x24000100)
<> 149:156823d33999 125 /** MAC MATCH HW Structure Overlay */
<> 149:156823d33999 126 #define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
<> 149:156823d33999 127
<> 149:156823d33999 128 /** MAC RX HW Registers Offset */
<> 149:156823d33999 129 #define MACRXREG_BASE ((uint32_t)0x24000080)
<> 149:156823d33999 130 /** MAC RX HW Structure Overlay */
<> 149:156823d33999 131 #define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
<> 149:156823d33999 132
<> 149:156823d33999 133 /** MAC TX HW Registers Offset */
<> 149:156823d33999 134 #define MACTXREG_BASE ((uint32_t)0x24000000)
<> 149:156823d33999 135 /** MAC TX HW Structure Overlay */
<> 149:156823d33999 136 #define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
<> 149:156823d33999 137
<> 149:156823d33999 138 /** TEST Interface for flash HW Registers Offset */
<> 149:156823d33999 139 #define TESTNVMREG_BASE ((uint32_t)0x4001F140)
<> 149:156823d33999 140 /** TEST Interface for flash HW Structure Overlay */
<> 149:156823d33999 141 #define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
<> 149:156823d33999 142
<> 149:156823d33999 143 /** Test Interface for digital HW Registers Offset */
<> 149:156823d33999 144 #define TESTDIGREG_BASE ((uint32_t)0x4001F100)
<> 149:156823d33999 145 /** Test Interface for digital HW Structure Overlay */
<> 149:156823d33999 146 #define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
<> 149:156823d33999 147
<> 149:156823d33999 148 /** Test Interface HW Registers Offset */
<> 149:156823d33999 149 #define TESTREG_BASE ((uint32_t)0x4001F000)
<> 149:156823d33999 150 /** Test Interface HW Structure Overlay */
<> 149:156823d33999 151 #define TESTREG ((TestReg_pt)TESTREG_BASE)
<> 149:156823d33999 152
<> 149:156823d33999 153 /** Device option HW Registers Offset */
<> 149:156823d33999 154 #define DEVOPTREG_BASE ((uint32_t)0x4001E000)
<> 149:156823d33999 155 /** MAC TX HW Structure Overlay */
<> 149:156823d33999 156 #define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
<> 149:156823d33999 157
<> 149:156823d33999 158 /** PMU HW Registers Offset */
<> 149:156823d33999 159 #define PMUREG_BASE ((uint32_t)0x4001D000)
<> 149:156823d33999 160 /** PMU HW Structure Overlay */
<> 149:156823d33999 161 #define PMUREG ((PmuReg_pt)PMUREG_BASE)
<> 149:156823d33999 162
<> 149:156823d33999 163 /** PAD Control HW Registers Offset */
<> 149:156823d33999 164 #define PADREG_BASE ((uint32_t)0x4001C000)
<> 149:156823d33999 165 /** PAD Control HW Structure Overlay */
<> 149:156823d33999 166 #define PADREG ((PadReg_pt)PADREG_BASE)
<> 149:156823d33999 167
<> 149:156823d33999 168 /** Clock Control HW Registers Offset */
<> 149:156823d33999 169 #define CLOCKREG_BASE ((uint32_t)0x4001B000)
<> 149:156823d33999 170 /** Clock Control HW Structure Overlay */
<> 149:156823d33999 171 #define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
<> 149:156823d33999 172
<> 149:156823d33999 173 /** Analogue Trim HW Registers Offset */
<> 149:156823d33999 174 #define RFANATRIMREG_BASE ((uint32_t)0x40019080)
<> 149:156823d33999 175 /** Analogue Trim HW Structure Overlay */
<> 149:156823d33999 176 #define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
<> 149:156823d33999 177
<> 149:156823d33999 178 /** Analogue RF HW Registers Offset */
<> 149:156823d33999 179 #define RFANAREG_BASE ((uint32_t)0x40019000)
<> 149:156823d33999 180 /** Analogue RF HW Structure Overlay */
<> 149:156823d33999 181 #define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
<> 149:156823d33999 182
<> 149:156823d33999 183 /** Reset Cause HW Registers Offset */
<> 149:156823d33999 184 #define RESETREG_BASE ((uint32_t)0x40018000)
<> 149:156823d33999 185 /** Reset Cause HW Structure Overlay */
<> 149:156823d33999 186 #define RESETREG ((ResetReg_pt)RESETREG_BASE)
<> 149:156823d33999 187
<> 149:156823d33999 188 /** FLASH Control HW Registers Offset */
<> 149:156823d33999 189 #define FLASHREG_BASE ((uint32_t)0x40017000)
<> 149:156823d33999 190 /** FLASH Control HW Structure Overlay */
<> 149:156823d33999 191 #define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
<> 149:156823d33999 192
<> 149:156823d33999 193 /** AES Encryption HW Registers Offset */
<> 149:156823d33999 194 #define AESREG_BASE ((uint32_t)0x40016000)
<> 149:156823d33999 195 /** AES Encryption HW Structure Overlay */
<> 149:156823d33999 196 #define AESREG ((AesReg_pt)AESREG_BASE)
<> 149:156823d33999 197
<> 149:156823d33999 198 /** SAR ADC HW Registers Offset */
<> 149:156823d33999 199 #define ADCREG_BASE ((uint32_t)0x40015000)
<> 149:156823d33999 200 /** SAR ADC HW Structure Overlay */
<> 149:156823d33999 201 #define ADCREG ((AdcReg_pt)ADCREG_BASE)
<> 149:156823d33999 202
<> 149:156823d33999 203 /** Demodulator HW Registers Offset */
<> 149:156823d33999 204 #define DMDREG_BASE ((uint32_t)0x40014100)
<> 149:156823d33999 205 /** Demodulator HW Structure Overlay */
<> 149:156823d33999 206 #define DMDREG ((DmdReg_pt)DMDREG_BASE)
<> 149:156823d33999 207
<> 149:156823d33999 208 /** MAC Control HW Registers Offset */
<> 149:156823d33999 209 #define MACHWREG_BASE ((uint32_t)0x40014000)
<> 149:156823d33999 210 /** MAC Control HW Structure Overlay */
<> 149:156823d33999 211 #define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
<> 149:156823d33999 212
<> 149:156823d33999 213 /** Random Generator HW Registers Offset */
<> 149:156823d33999 214 #define RANDREG_BASE ((uint32_t)0x40011000)
<> 149:156823d33999 215 /** Random Generator HW Structure Overlay */
<> 149:156823d33999 216 #define RANDREG ((RandReg_pt)RANDREG_BASE)
<> 149:156823d33999 217
<> 149:156823d33999 218 /** Cross Bar HW Registers Offset */
<> 149:156823d33999 219 #define CROSSBREG_BASE ((uint32_t)0x40010000)
<> 149:156823d33999 220 /** Cross Bar HW Structure Overlay */
<> 149:156823d33999 221 #define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
<> 149:156823d33999 222
<> 149:156823d33999 223 /** Real Time Clock HW Registers Offset */
<> 149:156823d33999 224 #define RTCREG_BASE ((uint32_t)0x4000F000)
<> 149:156823d33999 225 /** Real Time Clock HW Structure Overlay */
<> 149:156823d33999 226 #define RTCREG ((RtcReg_pt)RTCREG_BASE)
<> 149:156823d33999 227
<> 149:156823d33999 228 /** GPIO HW Registers Offset */
<> 149:156823d33999 229 #define GPIOREG_BASE ((uint32_t)0x4000C000)
<> 149:156823d33999 230 /** GPIO HW Structure Overlay */
<> 149:156823d33999 231 #define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
<> 149:156823d33999 232
<> 149:156823d33999 233 /** PWM HW Registers Offset */
<> 149:156823d33999 234 #define PWMREG_BASE ((uint32_t)0x4000B000)
<> 149:156823d33999 235 /** PWM HW Structure Overlay */
<> 149:156823d33999 236 #define PWMREG ((PwmReg_pt)PWMREG_BASE)
<> 149:156823d33999 237
<> 149:156823d33999 238 /** Watchdog Timer HW Registers Offset */
<> 149:156823d33999 239 #define WDTREG_BASE ((uint32_t)0x4000A000)
<> 149:156823d33999 240 /** Watchdog Timer HW Structure Overlay */
<> 149:156823d33999 241 #define WDTREG ((WdtReg_pt)WDTREG_BASE)
<> 149:156823d33999 242
<> 149:156823d33999 243 /** UART 2 HW Registers Offset */
<> 149:156823d33999 244 #define UART2REG_BASE ((uint32_t)0x40008000)
<> 149:156823d33999 245 /** UART 2 HW Structure Overlay */
<> 149:156823d33999 246 #define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
<> 149:156823d33999 247
<> 149:156823d33999 248 /** I2C HW Registers Offset */
<> 149:156823d33999 249 #define I2C1REG_BASE ((uint32_t)0x40007000)
<> 149:156823d33999 250 /** I2C HW Structure Overlay */
<> 149:156823d33999 251 #define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
<> 149:156823d33999 252
<> 149:156823d33999 253 /** SPI HW Registers Offset */
<> 149:156823d33999 254 #define SPI1REG_BASE ((uint32_t)0x40006000)
<> 149:156823d33999 255 /** SPI HW Structure Overlay */
<> 149:156823d33999 256 #define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
<> 149:156823d33999 257
<> 149:156823d33999 258 /** UART1 HW Registers Offset */
<> 149:156823d33999 259 #define UART1REG_BASE ((uint32_t)0x40005000)
<> 149:156823d33999 260 /** UART1 HW Structure Overlay */
<> 149:156823d33999 261 #define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
<> 149:156823d33999 262
<> 149:156823d33999 263 #define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
<> 149:156823d33999 264
<> 149:156823d33999 265 /** Timer 2 HW Registers Offset */
<> 149:156823d33999 266 #define TIM2REG_BASE ((uint32_t)0x40002000)
<> 149:156823d33999 267 /** Timer 2 HW Structure Overlay */
<> 149:156823d33999 268 #define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
<> 149:156823d33999 269
<> 149:156823d33999 270 /** Timer 1 HW Registers Offset */
<> 149:156823d33999 271 #define TIM1REG_BASE ((uint32_t)0x40001000)
<> 149:156823d33999 272 /** Timer 1 HW Structure Overlay */
<> 149:156823d33999 273 #define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
<> 149:156823d33999 274
<> 149:156823d33999 275 /** Timer 0 HW Registers Offset */
<> 149:156823d33999 276 #define TIM0REG_BASE ((uint32_t)0x40000000)
<> 149:156823d33999 277 /** Timer 0 HW Structure Overlay */
<> 149:156823d33999 278 #define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
<> 149:156823d33999 279
<> 149:156823d33999 280 /** I2C2 HW Registers Offset */
<> 149:156823d33999 281 #define I2C2REG_BASE ((uint32_t)0x4000D000)
<> 149:156823d33999 282 /** I2C2 HW Structure Overlay */
<> 149:156823d33999 283 #define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
<> 149:156823d33999 284
<> 149:156823d33999 285 /** SPI2 HW Registers Offset */
<> 149:156823d33999 286 #define SPI2REG_BASE ((uint32_t)0x40009000)
<> 149:156823d33999 287 /** SPI2 HW Structure Overlay */
<> 149:156823d33999 288 #define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
<> 149:156823d33999 289
<> 149:156823d33999 290 #endif /*_MEMORY_MAP_H_*/