mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h@160:d5399cc887bb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:40:56 2017 +0000
Revision:
160:d5399cc887bb
Parent:
151:5eaa88a5bcc7 
This updates the lib to the mbed lib v138

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file clock_map.h
<> 149:156823d33999 4 * @brief CLOCK hw module register map
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 2848 $
<> 149:156823d33999 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup clock
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 */
<> 149:156823d33999 31
<> 149:156823d33999 32 #ifndef CLOCK_MAP_H_
<> 149:156823d33999 33 #define CLOCK_MAP_H_
<> 149:156823d33999 34
<> 149:156823d33999 35 /*************************************************************************************************
<> 149:156823d33999 36 * *
<> 149:156823d33999 37 * Header files *
<> 149:156823d33999 38 * *
<> 149:156823d33999 39 *************************************************************************************************/
<> 149:156823d33999 40
<> 149:156823d33999 41 #include "architecture.h"
<> 149:156823d33999 42
<> 149:156823d33999 43 /**************************************************************************************************
<> 149:156823d33999 44 * *
<> 149:156823d33999 45 * Type definitions *
<> 149:156823d33999 46 * *
<> 149:156823d33999 47 **************************************************************************************************/
<> 149:156823d33999 48
<> 149:156823d33999 49 /** Clock control HW structure overlay */
<> 149:156823d33999 50 typedef struct {
<> 149:156823d33999 51 union {
<> 149:156823d33999 52 struct {
<> 149:156823d33999 53 __IO uint32_t OSC_SEL:1;
<> 149:156823d33999 54 __IO uint32_t PAD0:1;
<> 149:156823d33999 55 __IO uint32_t CAL32K:1;
<> 149:156823d33999 56 __IO uint32_t CAL32M:1;
<> 149:156823d33999 57 __IO uint32_t RTCEN:1;
<> 149:156823d33999 58 } BITS;
<> 149:156823d33999 59 __IO uint32_t WORD;
<> 149:156823d33999 60 } CCR; /**< 0x4001B000 Clock control register */
<> 149:156823d33999 61 union {
<> 149:156823d33999 62 struct {
<> 149:156823d33999 63 __I uint32_t XTAL32M:1;
<> 149:156823d33999 64 __I uint32_t XTAL32K:1;
<> 149:156823d33999 65 __I uint32_t CAL32K:1;
<> 149:156823d33999 66 __I uint32_t DONE32K:1;
<> 149:156823d33999 67 __I uint32_t CAL32MFAIL:1;
<> 149:156823d33999 68 __I uint32_t CAL32MDONE:1;
<> 149:156823d33999 69 } BITS;
<> 149:156823d33999 70 __I uint32_t WORD;
<> 149:156823d33999 71 } CSR; /**< 0x4001B004 Clock status register */
<> 149:156823d33999 72 union {
<> 149:156823d33999 73 struct {
<> 149:156823d33999 74 __IO uint32_t IE32K:1;
<> 149:156823d33999 75 __IO uint32_t IE32M:1;
<> 149:156823d33999 76 } BITS;
<> 149:156823d33999 77 __IO uint32_t WORD;
<> 149:156823d33999 78 } IER; /**< 0x4001B008 Interrup enable register */
<> 149:156823d33999 79 __IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
<> 149:156823d33999 80 union {
<> 149:156823d33999 81 struct {
<> 149:156823d33999 82 __IO uint32_t TIMER0:1;
<> 149:156823d33999 83 __IO uint32_t TIMER1:1;
<> 149:156823d33999 84 __IO uint32_t TIMER2:1;
<> 149:156823d33999 85 __IO uint32_t PAD0:2;
<> 149:156823d33999 86 __IO uint32_t UART1:1;
<> 149:156823d33999 87 __IO uint32_t SPI:1;
<> 149:156823d33999 88 __IO uint32_t I2C:1;
<> 149:156823d33999 89 __IO uint32_t UART2:1;
<> 149:156823d33999 90 __IO uint32_t PAD1:1;
<> 149:156823d33999 91 __IO uint32_t WDOG:1;
<> 149:156823d33999 92 __IO uint32_t PWM:1;
<> 149:156823d33999 93 __IO uint32_t GPIO:1;
<> 149:156823d33999 94 __IO uint32_t PAD2:2;
<> 149:156823d33999 95 __IO uint32_t RTC:1;
<> 149:156823d33999 96 __IO uint32_t XBAR:1;
<> 149:156823d33999 97 __IO uint32_t RAND:1;
<> 149:156823d33999 98 __IO uint32_t PAD3:2;
<> 149:156823d33999 99 __IO uint32_t MACHW:1;
<> 149:156823d33999 100 __IO uint32_t ADC:1;
<> 149:156823d33999 101 __IO uint32_t AES:1;
<> 149:156823d33999 102 __IO uint32_t FLASH:1;
<> 149:156823d33999 103 __IO uint32_t PAD4:1;
<> 149:156823d33999 104 __IO uint32_t RFANA:1;
<> 149:156823d33999 105 __IO uint32_t IO:1;
<> 149:156823d33999 106 __IO uint32_t PAD5:1;
<> 149:156823d33999 107 __IO uint32_t PAD:1;
<> 149:156823d33999 108 __IO uint32_t PMU:1;
<> 149:156823d33999 109 __IO uint32_t PAD6:1;
<> 149:156823d33999 110 __IO uint32_t TEST:1;
<> 149:156823d33999 111 } BITS;
<> 149:156823d33999 112 __IO uint32_t WORD;
<> 149:156823d33999 113 } PDIS; /**< 0x4001B010 Periphery disable */
<> 149:156823d33999 114 __IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
<> 149:156823d33999 115 __IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
<> 149:156823d33999 116 __IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
<> 149:156823d33999 117 __IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
<> 149:156823d33999 118 __IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
<> 151:5eaa88a5bcc7 119 union {
<> 151:5eaa88a5bcc7 120 struct {
<> 151:5eaa88a5bcc7 121 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
<> 151:5eaa88a5bcc7 122 __IO uint32_t BOOST :2; /* Boost done signal tap control */
<> 151:5eaa88a5bcc7 123 __IO uint32_t READY :2; /* Ready signal tap control */
<> 151:5eaa88a5bcc7 124 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
<> 151:5eaa88a5bcc7 125 __IO uint32_t PAD :20; /* Unused bits */
<> 151:5eaa88a5bcc7 126 } BITS;
<> 151:5eaa88a5bcc7 127 __IO uint32_t WORD;
<> 151:5eaa88a5bcc7 128 } TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
<> 151:5eaa88a5bcc7 129
<> 151:5eaa88a5bcc7 130 union {
<> 151:5eaa88a5bcc7 131 struct {
<> 151:5eaa88a5bcc7 132 __IO uint32_t TRIM_VALUE :6; /* External 32MHz Trim Value */
<> 151:5eaa88a5bcc7 133 __IO uint32_t BOOST :2; /* Boost done signal tap control */
<> 151:5eaa88a5bcc7 134 __IO uint32_t READY :2; /* Ready signal tap control */
<> 151:5eaa88a5bcc7 135 __IO uint32_t GAIN_MODE :2; /* Gain Mode */
<> 151:5eaa88a5bcc7 136 __IO uint32_t PAD :20; /* Unused bits */
<> 151:5eaa88a5bcc7 137 } BITS;
<> 151:5eaa88a5bcc7 138 __IO uint32_t WORD;
<> 151:5eaa88a5bcc7 139 } TRIM_32K_EXT;
<> 149:156823d33999 140 union {
<> 149:156823d33999 141 struct {
<> 149:156823d33999 142 __IO uint32_t OV32M;
<> 149:156823d33999 143 __IO uint32_t EN32M;
<> 149:156823d33999 144 __IO uint32_t OV32K;
<> 149:156823d33999 145 __IO uint32_t EN32K;
<> 149:156823d33999 146 } BITS;
<> 149:156823d33999 147 __IO uint32_t WORD;
<> 149:156823d33999 148 } CER; /**< 0x4001B038 clock enable register*/
<> 149:156823d33999 149 } ClockReg_t, *ClockReg_pt;
<> 149:156823d33999 150
<> 149:156823d33999 151 #endif /* CLOCK_MAP_H_ */