mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_system.h@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 16:56:18 2018 +0000
Revision:
182:a56a73fd2a6f
Parent:
161:2cc1468da177 
mbed-dev library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**
<> 161:2cc1468da177 2 ******************************************************************************
<> 161:2cc1468da177 3 * @file stm32f7xx_ll_system.h
<> 161:2cc1468da177 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @brief Header file of SYSTEM LL module.
<> 161:2cc1468da177 6 @verbatim
<> 161:2cc1468da177 7 ==============================================================================
<> 161:2cc1468da177 8 ##### How to use this driver #####
<> 161:2cc1468da177 9 ==============================================================================
<> 161:2cc1468da177 10 [..]
<> 161:2cc1468da177 11 The LL SYSTEM driver contains a set of generic APIs that can be
<> 161:2cc1468da177 12 used by user:
<> 161:2cc1468da177 13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
<> 161:2cc1468da177 14 (+) Access to DBGCMU registers
<> 161:2cc1468da177 15 (+) Access to SYSCFG registers
<> 161:2cc1468da177 16
<> 161:2cc1468da177 17 @endverbatim
<> 161:2cc1468da177 18 ******************************************************************************
<> 161:2cc1468da177 19 * @attention
<> 161:2cc1468da177 20 *
<> 161:2cc1468da177 21 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 161:2cc1468da177 22 *
<> 161:2cc1468da177 23 * Redistribution and use in source and binary forms, with or without modification,
<> 161:2cc1468da177 24 * are permitted provided that the following conditions are met:
<> 161:2cc1468da177 25 * 1. Redistributions of source code must retain the above copyright notice,
<> 161:2cc1468da177 26 * this list of conditions and the following disclaimer.
<> 161:2cc1468da177 27 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 161:2cc1468da177 28 * this list of conditions and the following disclaimer in the documentation
<> 161:2cc1468da177 29 * and/or other materials provided with the distribution.
<> 161:2cc1468da177 30 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 161:2cc1468da177 31 * may be used to endorse or promote products derived from this software
<> 161:2cc1468da177 32 * without specific prior written permission.
<> 161:2cc1468da177 33 *
<> 161:2cc1468da177 34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 161:2cc1468da177 37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 161:2cc1468da177 38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 161:2cc1468da177 39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 161:2cc1468da177 40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 161:2cc1468da177 41 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 161:2cc1468da177 42 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 161:2cc1468da177 43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 44 *
<> 161:2cc1468da177 45 ******************************************************************************
<> 161:2cc1468da177 46 */
<> 161:2cc1468da177 47
<> 161:2cc1468da177 48 /* Define to prevent recursive inclusion -------------------------------------*/
<> 161:2cc1468da177 49 #ifndef __STM32F7xx_LL_SYSTEM_H
<> 161:2cc1468da177 50 #define __STM32F7xx_LL_SYSTEM_H
<> 161:2cc1468da177 51
<> 161:2cc1468da177 52 #ifdef __cplusplus
<> 161:2cc1468da177 53 extern "C" {
<> 161:2cc1468da177 54 #endif
<> 161:2cc1468da177 55
<> 161:2cc1468da177 56 /* Includes ------------------------------------------------------------------*/
<> 161:2cc1468da177 57 #include "stm32f7xx.h"
<> 161:2cc1468da177 58
<> 161:2cc1468da177 59 /** @addtogroup STM32F7xx_LL_Driver
<> 161:2cc1468da177 60 * @{
<> 161:2cc1468da177 61 */
<> 161:2cc1468da177 62
<> 161:2cc1468da177 63 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
<> 161:2cc1468da177 64
<> 161:2cc1468da177 65 /** @defgroup SYSTEM_LL SYSTEM
<> 161:2cc1468da177 66 * @{
<> 161:2cc1468da177 67 */
<> 161:2cc1468da177 68
<> 161:2cc1468da177 69 /* Private types -------------------------------------------------------------*/
<> 161:2cc1468da177 70 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 71
<> 161:2cc1468da177 72 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 73 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
<> 161:2cc1468da177 74 * @{
<> 161:2cc1468da177 75 */
<> 161:2cc1468da177 76
<> 161:2cc1468da177 77 /**
<> 161:2cc1468da177 78 * @}
<> 161:2cc1468da177 79 */
<> 161:2cc1468da177 80
<> 161:2cc1468da177 81 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 82
<> 161:2cc1468da177 83 /* Exported types ------------------------------------------------------------*/
<> 161:2cc1468da177 84 /* Exported constants --------------------------------------------------------*/
<> 161:2cc1468da177 85 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
<> 161:2cc1468da177 86 * @{
<> 161:2cc1468da177 87 */
<> 161:2cc1468da177 88
<> 161:2cc1468da177 89 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
<> 161:2cc1468da177 90 * @{
<> 161:2cc1468da177 91 */
<> 161:2cc1468da177 92 #define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*!< Boot information after Reset */
<> 161:2cc1468da177 93 #define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*!< Boot information after Reset */
<> 161:2cc1468da177 94 /**
<> 161:2cc1468da177 95 * @}
<> 161:2cc1468da177 96 */
<> 161:2cc1468da177 97
<> 161:2cc1468da177 98
<> 161:2cc1468da177 99 #if defined(SYSCFG_MEMRMP_SWP_FB)
<> 161:2cc1468da177 100 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
<> 161:2cc1468da177 101 * @{
<> 161:2cc1468da177 102 */
<> 161:2cc1468da177 103 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
<> 161:2cc1468da177 104 and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
<> 161:2cc1468da177 105
<> 161:2cc1468da177 106 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
<> 161:2cc1468da177 107 and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
<> 161:2cc1468da177 108 /**
<> 161:2cc1468da177 109 * @}
<> 161:2cc1468da177 110 */
<> 161:2cc1468da177 111 #endif /* SYSCFG_MEMRMP_SWP_FB */
<> 161:2cc1468da177 112
<> 161:2cc1468da177 113 #if defined(SYSCFG_PMC_MII_RMII_SEL)
<> 161:2cc1468da177 114 /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
<> 161:2cc1468da177 115 * @{
<> 161:2cc1468da177 116 */
<> 161:2cc1468da177 117 #define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< ETH Media MII interface */
<> 161:2cc1468da177 118 #define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
<> 161:2cc1468da177 119
<> 161:2cc1468da177 120 /**
<> 161:2cc1468da177 121 * @}
<> 161:2cc1468da177 122 */
<> 161:2cc1468da177 123 #endif /* SYSCFG_PMC_MII_RMII_SEL */
<> 161:2cc1468da177 124
<> 161:2cc1468da177 125 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
<> 161:2cc1468da177 126 * @{
<> 161:2cc1468da177 127 */
<> 161:2cc1468da177 128 #if defined(SYSCFG_PMC_I2C1_FMP)
<> 161:2cc1468da177 129 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
<> 161:2cc1468da177 130 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
<> 161:2cc1468da177 131 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
<> 161:2cc1468da177 132 #endif /* SYSCFG_PMC_I2C1_FMP */
<> 161:2cc1468da177 133 #if defined(SYSCFG_PMC_I2C4_FMP)
<> 161:2cc1468da177 134 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
<> 161:2cc1468da177 135 #endif /* SYSCFG_PMC_I2C4_FMP */
<> 161:2cc1468da177 136 #if defined(SYSCFG_PMC_I2C_PB6_FMP)
<> 161:2cc1468da177 137 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
<> 161:2cc1468da177 138 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
<> 161:2cc1468da177 139 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
<> 161:2cc1468da177 140 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
<> 161:2cc1468da177 141 #endif /* SYSCFG_PMC_I2C_PB6_FMP */
<> 161:2cc1468da177 142 /**
<> 161:2cc1468da177 143 * @}
<> 161:2cc1468da177 144 */
<> 161:2cc1468da177 145
<> 161:2cc1468da177 146 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
<> 161:2cc1468da177 147 * @{
<> 161:2cc1468da177 148 */
<> 161:2cc1468da177 149 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
<> 161:2cc1468da177 150 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
<> 161:2cc1468da177 151 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
<> 161:2cc1468da177 152 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
<> 161:2cc1468da177 153 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
<> 161:2cc1468da177 154 #if defined(GPIOF)
<> 161:2cc1468da177 155 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
<> 161:2cc1468da177 156 #endif /* GPIOF */
<> 161:2cc1468da177 157 #if defined(GPIOG)
<> 161:2cc1468da177 158 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
<> 161:2cc1468da177 159 #endif /* GPIOG */
<> 161:2cc1468da177 160 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
<> 161:2cc1468da177 161 #if defined(GPIOI)
<> 161:2cc1468da177 162 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
<> 161:2cc1468da177 163 #endif /* GPIOI */
<> 161:2cc1468da177 164 #if defined(GPIOJ)
<> 161:2cc1468da177 165 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
<> 161:2cc1468da177 166 #endif /* GPIOJ */
<> 161:2cc1468da177 167 #if defined(GPIOK)
<> 161:2cc1468da177 168 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
<> 161:2cc1468da177 169 #endif /* GPIOK */
<> 161:2cc1468da177 170 /**
<> 161:2cc1468da177 171 * @}
<> 161:2cc1468da177 172 */
<> 161:2cc1468da177 173
<> 161:2cc1468da177 174 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
<> 161:2cc1468da177 175 * @{
<> 161:2cc1468da177 176 */
<> 161:2cc1468da177 177 #define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
<> 161:2cc1468da177 178 #define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
<> 161:2cc1468da177 179 #define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
<> 161:2cc1468da177 180 #define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
<> 161:2cc1468da177 181 #define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
<> 161:2cc1468da177 182 #define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
<> 161:2cc1468da177 183 #define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
<> 161:2cc1468da177 184 #define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
<> 161:2cc1468da177 185 #define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
<> 161:2cc1468da177 186 #define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
<> 161:2cc1468da177 187 #define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
<> 161:2cc1468da177 188 #define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
<> 161:2cc1468da177 189 #define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
<> 161:2cc1468da177 190 #define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
<> 161:2cc1468da177 191 #define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
<> 161:2cc1468da177 192 #define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
<> 161:2cc1468da177 193 /**
<> 161:2cc1468da177 194 * @}
<> 161:2cc1468da177 195 */
<> 161:2cc1468da177 196
<> 161:2cc1468da177 197 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
<> 161:2cc1468da177 198 * @{
<> 161:2cc1468da177 199 */
<> 161:2cc1468da177 200 #if defined(SYSCFG_CBR_CLL)
<> 161:2cc1468da177 201 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup output (raised during core
<> 161:2cc1468da177 202 lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */
<> 161:2cc1468da177 203 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input.
<> 161:2cc1468da177 204 It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits
<> 161:2cc1468da177 205 of the power controller */
<> 161:2cc1468da177 206 #endif /* SYSCFG_CBR_CLL */
<> 161:2cc1468da177 207 /**
<> 161:2cc1468da177 208 * @}
<> 161:2cc1468da177 209 */
<> 161:2cc1468da177 210 /** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD
<> 161:2cc1468da177 211 * @{
<> 161:2cc1468da177 212 */
<> 161:2cc1468da177 213 #define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power-down mode */
<> 161:2cc1468da177 214 #define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enabled */
<> 161:2cc1468da177 215 /**
<> 161:2cc1468da177 216 * @}
<> 161:2cc1468da177 217 */
<> 161:2cc1468da177 218 /**
<> 161:2cc1468da177 219 * @}
<> 161:2cc1468da177 220 */
<> 161:2cc1468da177 221
<> 161:2cc1468da177 222 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
<> 161:2cc1468da177 223 * @{
<> 161:2cc1468da177 224 */
<> 161:2cc1468da177 225 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
<> 161:2cc1468da177 226 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
<> 161:2cc1468da177 227 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
<> 161:2cc1468da177 228 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
<> 161:2cc1468da177 229 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
<> 161:2cc1468da177 230 /**
<> 161:2cc1468da177 231 * @}
<> 161:2cc1468da177 232 */
<> 161:2cc1468da177 233
<> 161:2cc1468da177 234 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
<> 161:2cc1468da177 235 * @{
<> 161:2cc1468da177 236 */
<> 161:2cc1468da177 237 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
<> 161:2cc1468da177 238 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
<> 161:2cc1468da177 239 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
<> 161:2cc1468da177 240 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
<> 161:2cc1468da177 241 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
<> 161:2cc1468da177 242 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
<> 161:2cc1468da177 243 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
<> 161:2cc1468da177 244 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
<> 161:2cc1468da177 245 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
<> 161:2cc1468da177 246 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 counter stopped when core is halted */
<> 161:2cc1468da177 247 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
<> 161:2cc1468da177 248 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
<> 161:2cc1468da177 249 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
<> 161:2cc1468da177 250 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
<> 161:2cc1468da177 251 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
<> 161:2cc1468da177 252 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
<> 161:2cc1468da177 253 #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
<> 161:2cc1468da177 254 #define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */
<> 161:2cc1468da177 255 #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
<> 161:2cc1468da177 256 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
<> 161:2cc1468da177 257 #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
<> 161:2cc1468da177 258 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
<> 161:2cc1468da177 259 #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
<> 161:2cc1468da177 260 #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
<> 161:2cc1468da177 261 #define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */
<> 161:2cc1468da177 262 #endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/
<> 161:2cc1468da177 263 /**
<> 161:2cc1468da177 264 * @}
<> 161:2cc1468da177 265 */
<> 161:2cc1468da177 266
<> 161:2cc1468da177 267 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
<> 161:2cc1468da177 268 * @{
<> 161:2cc1468da177 269 */
<> 161:2cc1468da177 270 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
<> 161:2cc1468da177 271 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
<> 161:2cc1468da177 272 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
<> 161:2cc1468da177 273 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
<> 161:2cc1468da177 274 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
<> 161:2cc1468da177 275 /**
<> 161:2cc1468da177 276 * @}
<> 161:2cc1468da177 277 */
<> 161:2cc1468da177 278
<> 161:2cc1468da177 279 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
<> 161:2cc1468da177 280 * @{
<> 161:2cc1468da177 281 */
<> 161:2cc1468da177 282 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
<> 161:2cc1468da177 283 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
<> 161:2cc1468da177 284 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
<> 161:2cc1468da177 285 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
<> 161:2cc1468da177 286 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
<> 161:2cc1468da177 287 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
<> 161:2cc1468da177 288 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
<> 161:2cc1468da177 289 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
<> 161:2cc1468da177 290 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
<> 161:2cc1468da177 291 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
<> 161:2cc1468da177 292 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
<> 161:2cc1468da177 293 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
<> 161:2cc1468da177 294 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
<> 161:2cc1468da177 295 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
<> 161:2cc1468da177 296 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
<> 161:2cc1468da177 297 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
<> 161:2cc1468da177 298 /**
<> 161:2cc1468da177 299 * @}
<> 161:2cc1468da177 300 */
<> 161:2cc1468da177 301
<> 161:2cc1468da177 302 /**
<> 161:2cc1468da177 303 * @}
<> 161:2cc1468da177 304 */
<> 161:2cc1468da177 305
<> 161:2cc1468da177 306 /* Exported macro ------------------------------------------------------------*/
<> 161:2cc1468da177 307
<> 161:2cc1468da177 308 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 309 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
<> 161:2cc1468da177 310 * @{
<> 161:2cc1468da177 311 */
<> 161:2cc1468da177 312
<> 161:2cc1468da177 313 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
<> 161:2cc1468da177 314 * @{
<> 161:2cc1468da177 315 */
<> 161:2cc1468da177 316
<> 161:2cc1468da177 317 /**
<> 161:2cc1468da177 318 * @brief Enables the FMC Memory Mapping Swapping
<> 161:2cc1468da177 319 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
<> 161:2cc1468da177 320 * @note SDRAM is accessible at 0x60000000 and NOR/RAM
<> 161:2cc1468da177 321 * is accessible at 0xC0000000
<> 161:2cc1468da177 322 * @retval None
<> 161:2cc1468da177 323 */
<> 161:2cc1468da177 324 __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
<> 161:2cc1468da177 325 {
<> 161:2cc1468da177 326 SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
<> 161:2cc1468da177 327 }
<> 161:2cc1468da177 328
<> 161:2cc1468da177 329 /**
<> 161:2cc1468da177 330 * @brief Disables the FMC Memory Mapping Swapping
<> 161:2cc1468da177 331 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
<> 161:2cc1468da177 332 * @note SDRAM is accessible at 0xC0000000 (default mapping)
<> 161:2cc1468da177 333 * and NOR/RAM is accessible at 0x60000000 (default mapping)
<> 161:2cc1468da177 334 * @retval None
<> 161:2cc1468da177 335 */
<> 161:2cc1468da177 336 __STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
<> 161:2cc1468da177 337 {
<> 161:2cc1468da177 338 CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
<> 161:2cc1468da177 339 }
<> 161:2cc1468da177 340
<> 161:2cc1468da177 341 /**
<> 161:2cc1468da177 342 * @brief Enables the Compensation Cell
<> 161:2cc1468da177 343 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
<> 161:2cc1468da177 344 * @note The I/O compensation cell can be used only when the device supply
<> 161:2cc1468da177 345 * voltage ranges from 2.4 to 3.6 V
<> 161:2cc1468da177 346 * @retval None
<> 161:2cc1468da177 347 */
<> 161:2cc1468da177 348 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
<> 161:2cc1468da177 349 {
<> 161:2cc1468da177 350 SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
<> 161:2cc1468da177 351 }
<> 161:2cc1468da177 352
<> 161:2cc1468da177 353 /**
<> 161:2cc1468da177 354 * @brief Disables the Compensation Cell
<> 161:2cc1468da177 355 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
<> 161:2cc1468da177 356 * @note The I/O compensation cell can be used only when the device supply
<> 161:2cc1468da177 357 * voltage ranges from 2.4 to 3.6 V
<> 161:2cc1468da177 358 * @retval None
<> 161:2cc1468da177 359 */
<> 161:2cc1468da177 360 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
<> 161:2cc1468da177 361 {
<> 161:2cc1468da177 362 CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
<> 161:2cc1468da177 363 }
<> 161:2cc1468da177 364
<> 161:2cc1468da177 365 /**
<> 161:2cc1468da177 366 * @brief Get Compensation Cell ready Flag
<> 161:2cc1468da177 367 * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
<> 161:2cc1468da177 368 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 369 */
<> 161:2cc1468da177 370 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
<> 161:2cc1468da177 371 {
<> 161:2cc1468da177 372 return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
<> 161:2cc1468da177 373 }
<> 161:2cc1468da177 374
<> 161:2cc1468da177 375
<> 161:2cc1468da177 376 /**
<> 161:2cc1468da177 377 * @brief Get the memory boot mapping as configured by user
<> 161:2cc1468da177 378 * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot
<> 161:2cc1468da177 379 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 380 * @arg @ref LL_SYSCFG_REMAP_BOOT0
<> 161:2cc1468da177 381 * @arg @ref LL_SYSCFG_REMAP_BOOT1
<> 161:2cc1468da177 382 *
<> 161:2cc1468da177 383 * (*) value not defined in all devices
<> 161:2cc1468da177 384 */
<> 161:2cc1468da177 385 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void)
<> 161:2cc1468da177 386 {
<> 161:2cc1468da177 387 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT));
<> 161:2cc1468da177 388 }
<> 161:2cc1468da177 389
<> 161:2cc1468da177 390 #if defined(SYSCFG_PMC_MII_RMII_SEL)
<> 161:2cc1468da177 391 /**
<> 161:2cc1468da177 392 * @brief Select Ethernet PHY interface
<> 161:2cc1468da177 393 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
<> 161:2cc1468da177 394 * @param Interface This parameter can be one of the following values:
<> 161:2cc1468da177 395 * @arg @ref LL_SYSCFG_PMC_ETHMII
<> 161:2cc1468da177 396 * @arg @ref LL_SYSCFG_PMC_ETHRMII
<> 161:2cc1468da177 397 * @retval None
<> 161:2cc1468da177 398 */
<> 161:2cc1468da177 399 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
<> 161:2cc1468da177 400 {
<> 161:2cc1468da177 401 MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
<> 161:2cc1468da177 402 }
<> 161:2cc1468da177 403
<> 161:2cc1468da177 404 /**
<> 161:2cc1468da177 405 * @brief Get Ethernet PHY interface
<> 161:2cc1468da177 406 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
<> 161:2cc1468da177 407 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 408 * @arg @ref LL_SYSCFG_PMC_ETHMII
<> 161:2cc1468da177 409 * @arg @ref LL_SYSCFG_PMC_ETHRMII
<> 161:2cc1468da177 410 * @retval None
<> 161:2cc1468da177 411 */
<> 161:2cc1468da177 412 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
<> 161:2cc1468da177 413 {
<> 161:2cc1468da177 414 return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
<> 161:2cc1468da177 415 }
<> 161:2cc1468da177 416 #endif /* SYSCFG_PMC_MII_RMII_SEL */
<> 161:2cc1468da177 417
<> 161:2cc1468da177 418
<> 161:2cc1468da177 419 #if defined(SYSCFG_MEMRMP_SWP_FB)
<> 161:2cc1468da177 420 /**
<> 161:2cc1468da177 421 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
<> 161:2cc1468da177 422 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
<> 161:2cc1468da177 423 * @param Bank This parameter can be one of the following values:
<> 161:2cc1468da177 424 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
<> 161:2cc1468da177 425 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
<> 161:2cc1468da177 426 * @retval None
<> 161:2cc1468da177 427 */
<> 161:2cc1468da177 428 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
<> 161:2cc1468da177 429 {
<> 161:2cc1468da177 430 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank);
<> 161:2cc1468da177 431 }
<> 161:2cc1468da177 432
<> 161:2cc1468da177 433 /**
<> 161:2cc1468da177 434 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
<> 161:2cc1468da177 435 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
<> 161:2cc1468da177 436 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 437 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
<> 161:2cc1468da177 438 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
<> 161:2cc1468da177 439 */
<> 161:2cc1468da177 440 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
<> 161:2cc1468da177 441 {
<> 161:2cc1468da177 442 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB));
<> 161:2cc1468da177 443 }
<> 161:2cc1468da177 444
<> 161:2cc1468da177 445 #endif /* SYSCFG_MEMRMP_SWP_FB */
<> 161:2cc1468da177 446
<> 161:2cc1468da177 447 #if defined(SYSCFG_PMC_I2C1_FMP)
<> 161:2cc1468da177 448 /**
<> 161:2cc1468da177 449 * @brief Enable the I2C fast mode plus driving capability.
<> 161:2cc1468da177 450 * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
<> 161:2cc1468da177 451 * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus
<> 161:2cc1468da177 452 * @param ConfigFastModePlus This parameter can be a combination of the following values:
<> 161:2cc1468da177 453 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<> 161:2cc1468da177 454 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<> 161:2cc1468da177 455 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
<> 161:2cc1468da177 456 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
<> 161:2cc1468da177 457 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
<> 161:2cc1468da177 458 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<> 161:2cc1468da177 459 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
<> 161:2cc1468da177 460 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
<> 161:2cc1468da177 461 *
<> 161:2cc1468da177 462 * (*) value not defined in all devices
<> 161:2cc1468da177 463 * @retval None
<> 161:2cc1468da177 464 */
<> 161:2cc1468da177 465 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
<> 161:2cc1468da177 466 {
<> 161:2cc1468da177 467 SET_BIT(SYSCFG->PMC, ConfigFastModePlus);
<> 161:2cc1468da177 468 }
<> 161:2cc1468da177 469
<> 161:2cc1468da177 470 /**
<> 161:2cc1468da177 471 * @brief Disable the I2C fast mode plus driving capability.
<> 161:2cc1468da177 472 * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
<> 161:2cc1468da177 473 * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus
<> 161:2cc1468da177 474 * @param ConfigFastModePlus This parameter can be a combination of the following values:
<> 161:2cc1468da177 475 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
<> 161:2cc1468da177 476 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
<> 161:2cc1468da177 477 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
<> 161:2cc1468da177 478 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
<> 161:2cc1468da177 479 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
<> 161:2cc1468da177 480 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
<> 161:2cc1468da177 481 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
<> 161:2cc1468da177 482 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
<> 161:2cc1468da177 483 * (*) value not defined in all devices
<> 161:2cc1468da177 484 * @retval None
<> 161:2cc1468da177 485 */
<> 161:2cc1468da177 486 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
<> 161:2cc1468da177 487 {
<> 161:2cc1468da177 488 CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus);
<> 161:2cc1468da177 489 }
<> 161:2cc1468da177 490 #endif /* SYSCFG_PMC_I2C1_FMP */
<> 161:2cc1468da177 491
<> 161:2cc1468da177 492
<> 161:2cc1468da177 493 /**
<> 161:2cc1468da177 494 * @brief Configure source input for the EXTI external interrupt.
<> 161:2cc1468da177 495 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
<> 161:2cc1468da177 496 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
<> 161:2cc1468da177 497 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
<> 161:2cc1468da177 498 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
<> 161:2cc1468da177 499 * @param Port This parameter can be one of the following values:
<> 161:2cc1468da177 500 * @arg @ref LL_SYSCFG_EXTI_PORTA
<> 161:2cc1468da177 501 * @arg @ref LL_SYSCFG_EXTI_PORTB
<> 161:2cc1468da177 502 * @arg @ref LL_SYSCFG_EXTI_PORTC
<> 161:2cc1468da177 503 * @arg @ref LL_SYSCFG_EXTI_PORTD
<> 161:2cc1468da177 504 * @arg @ref LL_SYSCFG_EXTI_PORTE
<> 161:2cc1468da177 505 * @arg @ref LL_SYSCFG_EXTI_PORTF
<> 161:2cc1468da177 506 * @arg @ref LL_SYSCFG_EXTI_PORTG
<> 161:2cc1468da177 507 * @arg @ref LL_SYSCFG_EXTI_PORTH
<> 161:2cc1468da177 508 * @arg @ref LL_SYSCFG_EXTI_PORTI
<> 161:2cc1468da177 509 * @arg @ref LL_SYSCFG_EXTI_PORTJ
<> 161:2cc1468da177 510 * @arg @ref LL_SYSCFG_EXTI_PORTK
<> 161:2cc1468da177 511 *
<> 161:2cc1468da177 512 * (*) value not defined in all devices
<> 161:2cc1468da177 513 * @param Line This parameter can be one of the following values:
<> 161:2cc1468da177 514 * @arg @ref LL_SYSCFG_EXTI_LINE0
<> 161:2cc1468da177 515 * @arg @ref LL_SYSCFG_EXTI_LINE1
<> 161:2cc1468da177 516 * @arg @ref LL_SYSCFG_EXTI_LINE2
<> 161:2cc1468da177 517 * @arg @ref LL_SYSCFG_EXTI_LINE3
<> 161:2cc1468da177 518 * @arg @ref LL_SYSCFG_EXTI_LINE4
<> 161:2cc1468da177 519 * @arg @ref LL_SYSCFG_EXTI_LINE5
<> 161:2cc1468da177 520 * @arg @ref LL_SYSCFG_EXTI_LINE6
<> 161:2cc1468da177 521 * @arg @ref LL_SYSCFG_EXTI_LINE7
<> 161:2cc1468da177 522 * @arg @ref LL_SYSCFG_EXTI_LINE8
<> 161:2cc1468da177 523 * @arg @ref LL_SYSCFG_EXTI_LINE9
<> 161:2cc1468da177 524 * @arg @ref LL_SYSCFG_EXTI_LINE10
<> 161:2cc1468da177 525 * @arg @ref LL_SYSCFG_EXTI_LINE11
<> 161:2cc1468da177 526 * @arg @ref LL_SYSCFG_EXTI_LINE12
<> 161:2cc1468da177 527 * @arg @ref LL_SYSCFG_EXTI_LINE13
<> 161:2cc1468da177 528 * @arg @ref LL_SYSCFG_EXTI_LINE14
<> 161:2cc1468da177 529 * @arg @ref LL_SYSCFG_EXTI_LINE15
<> 161:2cc1468da177 530 * @retval None
<> 161:2cc1468da177 531 */
<> 161:2cc1468da177 532 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
<> 161:2cc1468da177 533 {
<> 161:2cc1468da177 534 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
<> 161:2cc1468da177 535 }
<> 161:2cc1468da177 536
<> 161:2cc1468da177 537 /**
<> 161:2cc1468da177 538 * @brief Get the configured defined for specific EXTI Line
<> 161:2cc1468da177 539 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
<> 161:2cc1468da177 540 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
<> 161:2cc1468da177 541 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
<> 161:2cc1468da177 542 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
<> 161:2cc1468da177 543 * @param Line This parameter can be one of the following values:
<> 161:2cc1468da177 544 * @arg @ref LL_SYSCFG_EXTI_LINE0
<> 161:2cc1468da177 545 * @arg @ref LL_SYSCFG_EXTI_LINE1
<> 161:2cc1468da177 546 * @arg @ref LL_SYSCFG_EXTI_LINE2
<> 161:2cc1468da177 547 * @arg @ref LL_SYSCFG_EXTI_LINE3
<> 161:2cc1468da177 548 * @arg @ref LL_SYSCFG_EXTI_LINE4
<> 161:2cc1468da177 549 * @arg @ref LL_SYSCFG_EXTI_LINE5
<> 161:2cc1468da177 550 * @arg @ref LL_SYSCFG_EXTI_LINE6
<> 161:2cc1468da177 551 * @arg @ref LL_SYSCFG_EXTI_LINE7
<> 161:2cc1468da177 552 * @arg @ref LL_SYSCFG_EXTI_LINE8
<> 161:2cc1468da177 553 * @arg @ref LL_SYSCFG_EXTI_LINE9
<> 161:2cc1468da177 554 * @arg @ref LL_SYSCFG_EXTI_LINE10
<> 161:2cc1468da177 555 * @arg @ref LL_SYSCFG_EXTI_LINE11
<> 161:2cc1468da177 556 * @arg @ref LL_SYSCFG_EXTI_LINE12
<> 161:2cc1468da177 557 * @arg @ref LL_SYSCFG_EXTI_LINE13
<> 161:2cc1468da177 558 * @arg @ref LL_SYSCFG_EXTI_LINE14
<> 161:2cc1468da177 559 * @arg @ref LL_SYSCFG_EXTI_LINE15
<> 161:2cc1468da177 560 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 561 * @arg @ref LL_SYSCFG_EXTI_PORTA
<> 161:2cc1468da177 562 * @arg @ref LL_SYSCFG_EXTI_PORTB
<> 161:2cc1468da177 563 * @arg @ref LL_SYSCFG_EXTI_PORTC
<> 161:2cc1468da177 564 * @arg @ref LL_SYSCFG_EXTI_PORTD
<> 161:2cc1468da177 565 * @arg @ref LL_SYSCFG_EXTI_PORTE
<> 161:2cc1468da177 566 * @arg @ref LL_SYSCFG_EXTI_PORTF
<> 161:2cc1468da177 567 * @arg @ref LL_SYSCFG_EXTI_PORTG
<> 161:2cc1468da177 568 * @arg @ref LL_SYSCFG_EXTI_PORTH
<> 161:2cc1468da177 569 * @arg @ref LL_SYSCFG_EXTI_PORTI
<> 161:2cc1468da177 570 * @arg @ref LL_SYSCFG_EXTI_PORTJ
<> 161:2cc1468da177 571 * @arg @ref LL_SYSCFG_EXTI_PORTK
<> 161:2cc1468da177 572 * (*) value not defined in all devices
<> 161:2cc1468da177 573 */
<> 161:2cc1468da177 574 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
<> 161:2cc1468da177 575 {
<> 161:2cc1468da177 576 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
<> 161:2cc1468da177 577 }
<> 161:2cc1468da177 578
<> 161:2cc1468da177 579 #if defined(SYSCFG_CBR_CLL)
<> 161:2cc1468da177 580 /**
<> 161:2cc1468da177 581 * @brief Set connections to TIM1/8/15/16/17 Break inputs
<> 161:2cc1468da177 582 * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n
<> 161:2cc1468da177 583 * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs
<> 161:2cc1468da177 584 * @param Break This parameter can be a combination of the following values:
<> 161:2cc1468da177 585 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<> 161:2cc1468da177 586 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
<> 161:2cc1468da177 587 * @retval None
<> 161:2cc1468da177 588 */
<> 161:2cc1468da177 589 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
<> 161:2cc1468da177 590 {
<> 161:2cc1468da177 591 MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break);
<> 161:2cc1468da177 592 }
<> 161:2cc1468da177 593
<> 161:2cc1468da177 594 /**
<> 161:2cc1468da177 595 * @brief Get connections to TIM1/8/15/16/17 Break inputs
<> 161:2cc1468da177 596 * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n
<> 161:2cc1468da177 597 * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs
<> 161:2cc1468da177 598 * @retval Returned value can be can be a combination of the following values:
<> 161:2cc1468da177 599 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
<> 161:2cc1468da177 600 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
<> 161:2cc1468da177 601 */
<> 161:2cc1468da177 602 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
<> 161:2cc1468da177 603 {
<> 161:2cc1468da177 604 return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL));
<> 161:2cc1468da177 605 }
<> 161:2cc1468da177 606 #endif /* SYSCFG_CBR_CLL */
<> 161:2cc1468da177 607
<> 161:2cc1468da177 608 /**
<> 161:2cc1468da177 609 * @}
<> 161:2cc1468da177 610 */
<> 161:2cc1468da177 611
<> 161:2cc1468da177 612 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
<> 161:2cc1468da177 613 * @{
<> 161:2cc1468da177 614 */
<> 161:2cc1468da177 615
<> 161:2cc1468da177 616 /**
<> 161:2cc1468da177 617 * @brief Return the device identifier
<> 161:2cc1468da177 618 * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449
<> 161:2cc1468da177 619 * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451
<> 161:2cc1468da177 620 * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452
<> 161:2cc1468da177 621 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
<> 161:2cc1468da177 622 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
<> 161:2cc1468da177 623 */
<> 161:2cc1468da177 624 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
<> 161:2cc1468da177 625 {
<> 161:2cc1468da177 626 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
<> 161:2cc1468da177 627 }
<> 161:2cc1468da177 628
<> 161:2cc1468da177 629 /**
<> 161:2cc1468da177 630 * @brief Return the device revision identifier
<> 161:2cc1468da177 631 * @note This field indicates the revision of the device.
<> 161:2cc1468da177 632 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
<> 161:2cc1468da177 633 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
<> 161:2cc1468da177 634 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
<> 161:2cc1468da177 635 */
<> 161:2cc1468da177 636 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
<> 161:2cc1468da177 637 {
<> 161:2cc1468da177 638 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
<> 161:2cc1468da177 639 }
<> 161:2cc1468da177 640
<> 161:2cc1468da177 641 /**
<> 161:2cc1468da177 642 * @brief Enable the Debug Module during SLEEP mode
<> 161:2cc1468da177 643 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
<> 161:2cc1468da177 644 * @retval None
<> 161:2cc1468da177 645 */
<> 161:2cc1468da177 646 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
<> 161:2cc1468da177 647 {
<> 161:2cc1468da177 648 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<> 161:2cc1468da177 649 }
<> 161:2cc1468da177 650
<> 161:2cc1468da177 651 /**
<> 161:2cc1468da177 652 * @brief Disable the Debug Module during SLEEP mode
<> 161:2cc1468da177 653 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
<> 161:2cc1468da177 654 * @retval None
<> 161:2cc1468da177 655 */
<> 161:2cc1468da177 656 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
<> 161:2cc1468da177 657 {
<> 161:2cc1468da177 658 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
<> 161:2cc1468da177 659 }
<> 161:2cc1468da177 660
<> 161:2cc1468da177 661 /**
<> 161:2cc1468da177 662 * @brief Enable the Debug Module during STOP mode
<> 161:2cc1468da177 663 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
<> 161:2cc1468da177 664 * @retval None
<> 161:2cc1468da177 665 */
<> 161:2cc1468da177 666 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
<> 161:2cc1468da177 667 {
<> 161:2cc1468da177 668 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<> 161:2cc1468da177 669 }
<> 161:2cc1468da177 670
<> 161:2cc1468da177 671 /**
<> 161:2cc1468da177 672 * @brief Disable the Debug Module during STOP mode
<> 161:2cc1468da177 673 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
<> 161:2cc1468da177 674 * @retval None
<> 161:2cc1468da177 675 */
<> 161:2cc1468da177 676 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
<> 161:2cc1468da177 677 {
<> 161:2cc1468da177 678 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
<> 161:2cc1468da177 679 }
<> 161:2cc1468da177 680
<> 161:2cc1468da177 681 /**
<> 161:2cc1468da177 682 * @brief Enable the Debug Module during STANDBY mode
<> 161:2cc1468da177 683 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
<> 161:2cc1468da177 684 * @retval None
<> 161:2cc1468da177 685 */
<> 161:2cc1468da177 686 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
<> 161:2cc1468da177 687 {
<> 161:2cc1468da177 688 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<> 161:2cc1468da177 689 }
<> 161:2cc1468da177 690
<> 161:2cc1468da177 691 /**
<> 161:2cc1468da177 692 * @brief Disable the Debug Module during STANDBY mode
<> 161:2cc1468da177 693 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
<> 161:2cc1468da177 694 * @retval None
<> 161:2cc1468da177 695 */
<> 161:2cc1468da177 696 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
<> 161:2cc1468da177 697 {
<> 161:2cc1468da177 698 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
<> 161:2cc1468da177 699 }
<> 161:2cc1468da177 700
<> 161:2cc1468da177 701 /**
<> 161:2cc1468da177 702 * @brief Set Trace pin assignment control
<> 161:2cc1468da177 703 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
<> 161:2cc1468da177 704 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
<> 161:2cc1468da177 705 * @param PinAssignment This parameter can be one of the following values:
<> 161:2cc1468da177 706 * @arg @ref LL_DBGMCU_TRACE_NONE
<> 161:2cc1468da177 707 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
<> 161:2cc1468da177 708 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<> 161:2cc1468da177 709 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<> 161:2cc1468da177 710 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<> 161:2cc1468da177 711 * @retval None
<> 161:2cc1468da177 712 */
<> 161:2cc1468da177 713 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
<> 161:2cc1468da177 714 {
<> 161:2cc1468da177 715 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
<> 161:2cc1468da177 716 }
<> 161:2cc1468da177 717
<> 161:2cc1468da177 718 /**
<> 161:2cc1468da177 719 * @brief Get Trace pin assignment control
<> 161:2cc1468da177 720 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
<> 161:2cc1468da177 721 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
<> 161:2cc1468da177 722 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 723 * @arg @ref LL_DBGMCU_TRACE_NONE
<> 161:2cc1468da177 724 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
<> 161:2cc1468da177 725 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
<> 161:2cc1468da177 726 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
<> 161:2cc1468da177 727 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
<> 161:2cc1468da177 728 */
<> 161:2cc1468da177 729 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
<> 161:2cc1468da177 730 {
<> 161:2cc1468da177 731 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
<> 161:2cc1468da177 732 }
<> 161:2cc1468da177 733
<> 161:2cc1468da177 734 /**
<> 161:2cc1468da177 735 * @brief Freeze APB1 peripherals (group1 peripherals)
<> 161:2cc1468da177 736 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 737 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 738 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 739 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 740 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 741 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 742 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 743 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 744 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 745 * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 746 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 747 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 748 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 749 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 750 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 751 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 752 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 753 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 754 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
<> 161:2cc1468da177 755 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
<> 161:2cc1468da177 756 * @param Periphs This parameter can be a combination of the following values:
<> 161:2cc1468da177 757 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<> 161:2cc1468da177 758 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<> 161:2cc1468da177 759 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
<> 161:2cc1468da177 760 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
<> 161:2cc1468da177 761 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<> 161:2cc1468da177 762 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
<> 161:2cc1468da177 763 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
<> 161:2cc1468da177 764 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
<> 161:2cc1468da177 765 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<> 161:2cc1468da177 766 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
<> 161:2cc1468da177 767 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<> 161:2cc1468da177 768 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<> 161:2cc1468da177 769 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<> 161:2cc1468da177 770 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<> 161:2cc1468da177 771 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
<> 161:2cc1468da177 772 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
<> 161:2cc1468da177 773 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
<> 161:2cc1468da177 774 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
<> 161:2cc1468da177 775 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
<> 161:2cc1468da177 776 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
<> 161:2cc1468da177 777 *
<> 161:2cc1468da177 778 * (*) value not defined in all devices.
<> 161:2cc1468da177 779 * @retval None
<> 161:2cc1468da177 780 */
<> 161:2cc1468da177 781 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
<> 161:2cc1468da177 782 {
<> 161:2cc1468da177 783 SET_BIT(DBGMCU->APB1FZ, Periphs);
<> 161:2cc1468da177 784 }
<> 161:2cc1468da177 785
<> 161:2cc1468da177 786 /**
<> 161:2cc1468da177 787 * @brief Unfreeze APB1 peripherals (group1 peripherals)
<> 161:2cc1468da177 788 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 789 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 790 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 791 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 792 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 793 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 794 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 795 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 796 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 797 * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 798 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 799 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 800 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 801 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 802 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 803 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 804 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 805 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 806 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 807 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
<> 161:2cc1468da177 808 * @param Periphs This parameter can be a combination of the following values:
<> 161:2cc1468da177 809 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
<> 161:2cc1468da177 810 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
<> 161:2cc1468da177 811 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
<> 161:2cc1468da177 812 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
<> 161:2cc1468da177 813 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
<> 161:2cc1468da177 814 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
<> 161:2cc1468da177 815 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
<> 161:2cc1468da177 816 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
<> 161:2cc1468da177 817 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
<> 161:2cc1468da177 818 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
<> 161:2cc1468da177 819 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
<> 161:2cc1468da177 820 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
<> 161:2cc1468da177 821 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
<> 161:2cc1468da177 822 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
<> 161:2cc1468da177 823 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
<> 161:2cc1468da177 824 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
<> 161:2cc1468da177 825 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
<> 161:2cc1468da177 826 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
<> 161:2cc1468da177 827 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
<> 161:2cc1468da177 828 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
<> 161:2cc1468da177 829 * (*) value not defined in all devices.
<> 161:2cc1468da177 830 * @retval None
<> 161:2cc1468da177 831 */
<> 161:2cc1468da177 832 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
<> 161:2cc1468da177 833 {
<> 161:2cc1468da177 834 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
<> 161:2cc1468da177 835 }
<> 161:2cc1468da177 836
<> 161:2cc1468da177 837 /**
<> 161:2cc1468da177 838 * @brief Freeze APB2 peripherals
<> 161:2cc1468da177 839 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 161:2cc1468da177 840 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 161:2cc1468da177 841 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 161:2cc1468da177 842 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
<> 161:2cc1468da177 843 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
<> 161:2cc1468da177 844 * @param Periphs This parameter can be a combination of the following values:
<> 161:2cc1468da177 845 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
<> 161:2cc1468da177 846 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
<> 161:2cc1468da177 847 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
<> 161:2cc1468da177 848 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
<> 161:2cc1468da177 849 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
<> 161:2cc1468da177 850 *
<> 161:2cc1468da177 851 * (*) value not defined in all devices.
<> 161:2cc1468da177 852 * @retval None
<> 161:2cc1468da177 853 */
<> 161:2cc1468da177 854 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
<> 161:2cc1468da177 855 {
<> 161:2cc1468da177 856 SET_BIT(DBGMCU->APB2FZ, Periphs);
<> 161:2cc1468da177 857 }
<> 161:2cc1468da177 858
<> 161:2cc1468da177 859 /**
<> 161:2cc1468da177 860 * @brief Unfreeze APB2 peripherals
<> 161:2cc1468da177 861 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 862 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 863 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 864 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
<> 161:2cc1468da177 865 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
<> 161:2cc1468da177 866 * @param Periphs This parameter can be a combination of the following values:
<> 161:2cc1468da177 867 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
<> 161:2cc1468da177 868 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
<> 161:2cc1468da177 869 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
<> 161:2cc1468da177 870 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
<> 161:2cc1468da177 871 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
<> 161:2cc1468da177 872 *
<> 161:2cc1468da177 873 * (*) value not defined in all devices.
<> 161:2cc1468da177 874 * @retval None
<> 161:2cc1468da177 875 */
<> 161:2cc1468da177 876 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
<> 161:2cc1468da177 877 {
<> 161:2cc1468da177 878 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
<> 161:2cc1468da177 879 }
<> 161:2cc1468da177 880 /**
<> 161:2cc1468da177 881 * @}
<> 161:2cc1468da177 882 */
<> 161:2cc1468da177 883
<> 161:2cc1468da177 884 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
<> 161:2cc1468da177 885 * @{
<> 161:2cc1468da177 886 */
<> 161:2cc1468da177 887
<> 161:2cc1468da177 888 /**
<> 161:2cc1468da177 889 * @brief Set FLASH Latency
<> 161:2cc1468da177 890 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
<> 161:2cc1468da177 891 * @param Latency This parameter can be one of the following values:
<> 161:2cc1468da177 892 * @arg @ref LL_FLASH_LATENCY_0
<> 161:2cc1468da177 893 * @arg @ref LL_FLASH_LATENCY_1
<> 161:2cc1468da177 894 * @arg @ref LL_FLASH_LATENCY_2
<> 161:2cc1468da177 895 * @arg @ref LL_FLASH_LATENCY_3
<> 161:2cc1468da177 896 * @arg @ref LL_FLASH_LATENCY_4
<> 161:2cc1468da177 897 * @arg @ref LL_FLASH_LATENCY_5
<> 161:2cc1468da177 898 * @arg @ref LL_FLASH_LATENCY_6
<> 161:2cc1468da177 899 * @arg @ref LL_FLASH_LATENCY_7
<> 161:2cc1468da177 900 * @arg @ref LL_FLASH_LATENCY_8
<> 161:2cc1468da177 901 * @arg @ref LL_FLASH_LATENCY_9
<> 161:2cc1468da177 902 * @arg @ref LL_FLASH_LATENCY_10
<> 161:2cc1468da177 903 * @arg @ref LL_FLASH_LATENCY_11
<> 161:2cc1468da177 904 * @arg @ref LL_FLASH_LATENCY_12
<> 161:2cc1468da177 905 * @arg @ref LL_FLASH_LATENCY_13
<> 161:2cc1468da177 906 * @arg @ref LL_FLASH_LATENCY_14
<> 161:2cc1468da177 907 * @arg @ref LL_FLASH_LATENCY_15
<> 161:2cc1468da177 908 * @retval None
<> 161:2cc1468da177 909 */
<> 161:2cc1468da177 910 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
<> 161:2cc1468da177 911 {
<> 161:2cc1468da177 912 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
<> 161:2cc1468da177 913 }
<> 161:2cc1468da177 914
<> 161:2cc1468da177 915 /**
<> 161:2cc1468da177 916 * @brief Get FLASH Latency
<> 161:2cc1468da177 917 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
<> 161:2cc1468da177 918 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 919 * @arg @ref LL_FLASH_LATENCY_0
<> 161:2cc1468da177 920 * @arg @ref LL_FLASH_LATENCY_1
<> 161:2cc1468da177 921 * @arg @ref LL_FLASH_LATENCY_2
<> 161:2cc1468da177 922 * @arg @ref LL_FLASH_LATENCY_3
<> 161:2cc1468da177 923 * @arg @ref LL_FLASH_LATENCY_4
<> 161:2cc1468da177 924 * @arg @ref LL_FLASH_LATENCY_5
<> 161:2cc1468da177 925 * @arg @ref LL_FLASH_LATENCY_6
<> 161:2cc1468da177 926 * @arg @ref LL_FLASH_LATENCY_7
<> 161:2cc1468da177 927 * @arg @ref LL_FLASH_LATENCY_8
<> 161:2cc1468da177 928 * @arg @ref LL_FLASH_LATENCY_9
<> 161:2cc1468da177 929 * @arg @ref LL_FLASH_LATENCY_10
<> 161:2cc1468da177 930 * @arg @ref LL_FLASH_LATENCY_11
<> 161:2cc1468da177 931 * @arg @ref LL_FLASH_LATENCY_12
<> 161:2cc1468da177 932 * @arg @ref LL_FLASH_LATENCY_13
<> 161:2cc1468da177 933 * @arg @ref LL_FLASH_LATENCY_14
<> 161:2cc1468da177 934 * @arg @ref LL_FLASH_LATENCY_15
<> 161:2cc1468da177 935 */
<> 161:2cc1468da177 936 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
<> 161:2cc1468da177 937 {
<> 161:2cc1468da177 938 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
<> 161:2cc1468da177 939 }
<> 161:2cc1468da177 940
<> 161:2cc1468da177 941 /**
<> 161:2cc1468da177 942 * @brief Enable Prefetch
<> 161:2cc1468da177 943 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
<> 161:2cc1468da177 944 * @retval None
<> 161:2cc1468da177 945 */
<> 161:2cc1468da177 946 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
<> 161:2cc1468da177 947 {
<> 161:2cc1468da177 948 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
<> 161:2cc1468da177 949 }
<> 161:2cc1468da177 950
<> 161:2cc1468da177 951 /**
<> 161:2cc1468da177 952 * @brief Disable Prefetch
<> 161:2cc1468da177 953 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
<> 161:2cc1468da177 954 * @retval None
<> 161:2cc1468da177 955 */
<> 161:2cc1468da177 956 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
<> 161:2cc1468da177 957 {
<> 161:2cc1468da177 958 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
<> 161:2cc1468da177 959 }
<> 161:2cc1468da177 960
<> 161:2cc1468da177 961 /**
<> 161:2cc1468da177 962 * @brief Check if Prefetch buffer is enabled
<> 161:2cc1468da177 963 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
<> 161:2cc1468da177 964 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 965 */
<> 161:2cc1468da177 966 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
<> 161:2cc1468da177 967 {
<> 161:2cc1468da177 968 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
<> 161:2cc1468da177 969 }
<> 161:2cc1468da177 970
<> 161:2cc1468da177 971
<> 161:2cc1468da177 972
<> 161:2cc1468da177 973 /**
<> 161:2cc1468da177 974 * @brief Enable ART Accelerator
<> 161:2cc1468da177 975 * @rmtoll FLASH_ACR ARTEN LL_FLASH_EnableART
<> 161:2cc1468da177 976 * @retval None
<> 161:2cc1468da177 977 */
<> 161:2cc1468da177 978 __STATIC_INLINE void LL_FLASH_EnableART(void)
<> 161:2cc1468da177 979 {
<> 161:2cc1468da177 980 SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN);
<> 161:2cc1468da177 981 }
<> 161:2cc1468da177 982
<> 161:2cc1468da177 983 /**
<> 161:2cc1468da177 984 * @brief Disable ART Accelerator
<> 161:2cc1468da177 985 * @rmtoll FLASH_ACR ARTEN LL_FLASH_DisableART
<> 161:2cc1468da177 986 * @retval None
<> 161:2cc1468da177 987 */
<> 161:2cc1468da177 988 __STATIC_INLINE void LL_FLASH_DisableART(void)
<> 161:2cc1468da177 989 {
<> 161:2cc1468da177 990 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN);
<> 161:2cc1468da177 991 }
<> 161:2cc1468da177 992
<> 161:2cc1468da177 993 /**
<> 161:2cc1468da177 994 * @brief Enable ART Reset
<> 161:2cc1468da177 995 * @rmtoll FLASH_ACR ARTRST LL_FLASH_EnableARTReset
<> 161:2cc1468da177 996 * @retval None
<> 161:2cc1468da177 997 */
<> 161:2cc1468da177 998 __STATIC_INLINE void LL_FLASH_EnableARTReset(void)
<> 161:2cc1468da177 999 {
<> 161:2cc1468da177 1000 SET_BIT(FLASH->ACR, FLASH_ACR_ARTRST);
<> 161:2cc1468da177 1001 }
<> 161:2cc1468da177 1002
<> 161:2cc1468da177 1003 /**
<> 161:2cc1468da177 1004 * @brief Disable ART Reset
<> 161:2cc1468da177 1005 * @rmtoll FLASH_ACR ARTRST LL_FLASH_DisableARTReset
<> 161:2cc1468da177 1006 * @retval None
<> 161:2cc1468da177 1007 */
<> 161:2cc1468da177 1008 __STATIC_INLINE void LL_FLASH_DisableARTReset(void)
<> 161:2cc1468da177 1009 {
<> 161:2cc1468da177 1010 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTRST);
<> 161:2cc1468da177 1011 }
<> 161:2cc1468da177 1012
<> 161:2cc1468da177 1013 /**
<> 161:2cc1468da177 1014 * @}
<> 161:2cc1468da177 1015 */
<> 161:2cc1468da177 1016
<> 161:2cc1468da177 1017 /**
<> 161:2cc1468da177 1018 * @}
<> 161:2cc1468da177 1019 */
<> 161:2cc1468da177 1020
<> 161:2cc1468da177 1021 /**
<> 161:2cc1468da177 1022 * @}
<> 161:2cc1468da177 1023 */
<> 161:2cc1468da177 1024
<> 161:2cc1468da177 1025 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
<> 161:2cc1468da177 1026
<> 161:2cc1468da177 1027 /**
<> 161:2cc1468da177 1028 * @}
<> 161:2cc1468da177 1029 */
<> 161:2cc1468da177 1030
<> 161:2cc1468da177 1031 #ifdef __cplusplus
<> 161:2cc1468da177 1032 }
<> 161:2cc1468da177 1033 #endif
<> 161:2cc1468da177 1034
<> 161:2cc1468da177 1035 #endif /* __STM32F7xx_LL_SYSTEM_H */
<> 161:2cc1468da177 1036
<> 161:2cc1468da177 1037 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/