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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.h@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:: AnnaBridge
Date:: Tue Mar 20 16:56:18 2018 +0000
Revision:: 182:a56a73fd2a6f
Parent:: 161:2cc1468da177

mbed-dev library. Release version 160

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_i2c.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @brief Header file of I2C LL module.
<>	161:2cc1468da177	6	******************************************************************************
<>	161:2cc1468da177	7	* @attention
<>	161:2cc1468da177	8	*
<>	161:2cc1468da177	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	10	*
<>	161:2cc1468da177	11	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	12	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	14	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	16	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	17	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	19	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	20	* without specific prior written permission.
<>	161:2cc1468da177	21	*
<>	161:2cc1468da177	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	32	*
<>	161:2cc1468da177	33	******************************************************************************
<>	161:2cc1468da177	34	*/
<>	161:2cc1468da177	35
<>	161:2cc1468da177	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	37	#ifndef __STM32F7xx_LL_I2C_H
<>	161:2cc1468da177	38	#define __STM32F7xx_LL_I2C_H
<>	161:2cc1468da177	39
<>	161:2cc1468da177	40	#ifdef __cplusplus
<>	161:2cc1468da177	41	extern "C" {
<>	161:2cc1468da177	42	#endif
<>	161:2cc1468da177	43
<>	161:2cc1468da177	44	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	45	#include "stm32f7xx.h"
<>	161:2cc1468da177	46
<>	161:2cc1468da177	47	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	48	* @{
<>	161:2cc1468da177	49	*/
<>	161:2cc1468da177	50
<>	161:2cc1468da177	51	#if defined (I2C1) \|\| defined (I2C2) \|\| defined (I2C3) \|\| defined (I2C4)
<>	161:2cc1468da177	52
<>	161:2cc1468da177	53	/** @defgroup I2C_LL I2C
<>	161:2cc1468da177	54	* @{
<>	161:2cc1468da177	55	*/
<>	161:2cc1468da177	56
<>	161:2cc1468da177	57	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	58	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	59
<>	161:2cc1468da177	60	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	61	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
<>	161:2cc1468da177	62	* @{
<>	161:2cc1468da177	63	*/
<>	161:2cc1468da177	64	/**
<>	161:2cc1468da177	65	* @}
<>	161:2cc1468da177	66	*/
<>	161:2cc1468da177	67
<>	161:2cc1468da177	68	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	69	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	70	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
<>	161:2cc1468da177	71	* @{
<>	161:2cc1468da177	72	*/
<>	161:2cc1468da177	73	/**
<>	161:2cc1468da177	74	* @}
<>	161:2cc1468da177	75	*/
<>	161:2cc1468da177	76	#endif /USE_FULL_LL_DRIVER/
<>	161:2cc1468da177	77
<>	161:2cc1468da177	78	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	79	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	80	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
<>	161:2cc1468da177	81	* @{
<>	161:2cc1468da177	82	*/
<>	161:2cc1468da177	83	typedef struct
<>	161:2cc1468da177	84	{
<>	161:2cc1468da177	85	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
<>	161:2cc1468da177	86	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
<>	161:2cc1468da177	87
<>	161:2cc1468da177	88	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
<>	161:2cc1468da177	89
<>	161:2cc1468da177	90	uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
<>	161:2cc1468da177	91	This parameter must be set by referring to the STM32CubeMX Tool and
<>	161:2cc1468da177	92	the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
<>	161:2cc1468da177	93
<>	161:2cc1468da177	94	This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
<>	161:2cc1468da177	95
<>	161:2cc1468da177	96	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
<>	161:2cc1468da177	97	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
<>	161:2cc1468da177	98
<>	161:2cc1468da177	99	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
<>	161:2cc1468da177	100
<>	161:2cc1468da177	101	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
<>	161:2cc1468da177	102	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
<>	161:2cc1468da177	103
<>	161:2cc1468da177	104	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
<>	161:2cc1468da177	105
<>	161:2cc1468da177	106	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
<>	161:2cc1468da177	107	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
<>	161:2cc1468da177	108
<>	161:2cc1468da177	109	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	161:2cc1468da177	110
<>	161:2cc1468da177	111	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	161:2cc1468da177	112	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
<>	161:2cc1468da177	113
<>	161:2cc1468da177	114	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
<>	161:2cc1468da177	115
<>	161:2cc1468da177	116	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
<>	161:2cc1468da177	117	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
<>	161:2cc1468da177	118
<>	161:2cc1468da177	119	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	161:2cc1468da177	120	} LL_I2C_InitTypeDef;
<>	161:2cc1468da177	121	/**
<>	161:2cc1468da177	122	* @}
<>	161:2cc1468da177	123	*/
<>	161:2cc1468da177	124	#endif /USE_FULL_LL_DRIVER/
<>	161:2cc1468da177	125
<>	161:2cc1468da177	126	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	127	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
<>	161:2cc1468da177	128	* @{
<>	161:2cc1468da177	129	*/
<>	161:2cc1468da177	130
<>	161:2cc1468da177	131	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	161:2cc1468da177	132	* @brief Flags defines which can be used with LL_I2C_WriteReg function
<>	161:2cc1468da177	133	* @{
<>	161:2cc1468da177	134	*/
<>	161:2cc1468da177	135	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /!< Address Matched flag /
<>	161:2cc1468da177	136	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /!< Not Acknowledge flag /
<>	161:2cc1468da177	137	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /!< Stop detection flag /
<>	161:2cc1468da177	138	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /!< Bus error flag /
<>	161:2cc1468da177	139	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /!< Arbitration Lost flag /
<>	161:2cc1468da177	140	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /!< Overrun/Underrun flag /
<>	161:2cc1468da177	141	#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /!< PEC error flag /
<>	161:2cc1468da177	142	#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /!< Timeout detection flag /
<>	161:2cc1468da177	143	#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /!< Alert flag /
<>	161:2cc1468da177	144	/**
<>	161:2cc1468da177	145	* @}
<>	161:2cc1468da177	146	*/
<>	161:2cc1468da177	147
<>	161:2cc1468da177	148	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
<>	161:2cc1468da177	149	* @brief Flags defines which can be used with LL_I2C_ReadReg function
<>	161:2cc1468da177	150	* @{
<>	161:2cc1468da177	151	*/
<>	161:2cc1468da177	152	#define LL_I2C_ISR_TXE I2C_ISR_TXE /!< Transmit data register empty /
<>	161:2cc1468da177	153	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /!< Transmit interrupt status /
<>	161:2cc1468da177	154	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /!< Receive data register not empty /
<>	161:2cc1468da177	155	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /!< Address matched (slave mode) /
<>	161:2cc1468da177	156	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /!< Not Acknowledge received flag /
<>	161:2cc1468da177	157	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /!< Stop detection flag /
<>	161:2cc1468da177	158	#define LL_I2C_ISR_TC I2C_ISR_TC /!< Transfer Complete (master mode) /
<>	161:2cc1468da177	159	#define LL_I2C_ISR_TCR I2C_ISR_TCR /!< Transfer Complete Reload /
<>	161:2cc1468da177	160	#define LL_I2C_ISR_BERR I2C_ISR_BERR /!< Bus error /
<>	161:2cc1468da177	161	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /!< Arbitration lost /
<>	161:2cc1468da177	162	#define LL_I2C_ISR_OVR I2C_ISR_OVR /!< Overrun/Underrun (slave mode) /
<>	161:2cc1468da177	163	#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
<>	161:2cc1468da177	164	#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
<>	161:2cc1468da177	165	#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /!< SMBus alert (SMBus mode) /
<>	161:2cc1468da177	166	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /!< Bus busy /
<>	161:2cc1468da177	167	/**
<>	161:2cc1468da177	168	* @}
<>	161:2cc1468da177	169	*/
<>	161:2cc1468da177	170
<>	161:2cc1468da177	171	/** @defgroup I2C_LL_EC_IT IT Defines
<>	161:2cc1468da177	172	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
<>	161:2cc1468da177	173	* @{
<>	161:2cc1468da177	174	*/
<>	161:2cc1468da177	175	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /!< TX Interrupt enable /
<>	161:2cc1468da177	176	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /!< RX Interrupt enable /
<>	161:2cc1468da177	177	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /!< Address match Interrupt enable (slave only) /
<>	161:2cc1468da177	178	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /!< Not acknowledge received Interrupt enable /
<>	161:2cc1468da177	179	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /!< STOP detection Interrupt enable /
<>	161:2cc1468da177	180	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /!< Transfer Complete interrupt enable /
<>	161:2cc1468da177	181	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /!< Error interrupts enable /
<>	161:2cc1468da177	182	/**
<>	161:2cc1468da177	183	* @}
<>	161:2cc1468da177	184	*/
<>	161:2cc1468da177	185
<>	161:2cc1468da177	186	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
<>	161:2cc1468da177	187	* @{
<>	161:2cc1468da177	188	*/
<>	161:2cc1468da177	189	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
<>	161:2cc1468da177	190	#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /!< SMBus Host address acknowledge /
<>	161:2cc1468da177	191	#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /!< SMBus Device default mode (Default address not acknowledge) /
<>	161:2cc1468da177	192	#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /!< SMBus Device Default address acknowledge /
<>	161:2cc1468da177	193	/**
<>	161:2cc1468da177	194	* @}
<>	161:2cc1468da177	195	*/
<>	161:2cc1468da177	196
<>	161:2cc1468da177	197	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
<>	161:2cc1468da177	198	* @{
<>	161:2cc1468da177	199	*/
<>	161:2cc1468da177	200	#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /!< Analog filter is enabled. /
<>	161:2cc1468da177	201	#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /!< Analog filter is disabled. /
<>	161:2cc1468da177	202	/**
<>	161:2cc1468da177	203	* @}
<>	161:2cc1468da177	204	*/
<>	161:2cc1468da177	205
<>	161:2cc1468da177	206	/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
<>	161:2cc1468da177	207	* @{
<>	161:2cc1468da177	208	*/
<>	161:2cc1468da177	209	#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /!< Master operates in 7-bit addressing mode. /
<>	161:2cc1468da177	210	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!< Master operates in 10-bit addressing mode./
<>	161:2cc1468da177	211	/**
<>	161:2cc1468da177	212	* @}
<>	161:2cc1468da177	213	*/
<>	161:2cc1468da177	214
<>	161:2cc1468da177	215	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
<>	161:2cc1468da177	216	* @{
<>	161:2cc1468da177	217	*/
<>	161:2cc1468da177	218	#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /!< Own address 1 is a 7-bit address. /
<>	161:2cc1468da177	219	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!< Own address 1 is a 10-bit address./
<>	161:2cc1468da177	220	/**
<>	161:2cc1468da177	221	* @}
<>	161:2cc1468da177	222	*/
<>	161:2cc1468da177	223
<>	161:2cc1468da177	224	/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
<>	161:2cc1468da177	225	* @{
<>	161:2cc1468da177	226	*/
<>	161:2cc1468da177	227	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!< Own Address2 No mask. /
<>	161:2cc1468da177	228	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!< Only Address2 bits[7:2] are compared. /
<>	161:2cc1468da177	229	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!< Only Address2 bits[7:3] are compared. /
<>	161:2cc1468da177	230	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!< Only Address2 bits[7:4] are compared. /
<>	161:2cc1468da177	231	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!< Only Address2 bits[7:5] are compared. /
<>	161:2cc1468da177	232	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!< Only Address2 bits[7:6] are compared. /
<>	161:2cc1468da177	233	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!< Only Address2 bits[7] are compared. /
<>	161:2cc1468da177	234	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!< No comparison is done. All Address2 are acknowledged./
<>	161:2cc1468da177	235	/**
<>	161:2cc1468da177	236	* @}
<>	161:2cc1468da177	237	*/
<>	161:2cc1468da177	238
<>	161:2cc1468da177	239	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
<>	161:2cc1468da177	240	* @{
<>	161:2cc1468da177	241	*/
<>	161:2cc1468da177	242	#define LL_I2C_ACK 0x00000000U /!< ACK is sent after current received byte. /
<>	161:2cc1468da177	243	#define LL_I2C_NACK I2C_CR2_NACK /!< NACK is sent after current received byte./
<>	161:2cc1468da177	244	/**
<>	161:2cc1468da177	245	* @}
<>	161:2cc1468da177	246	*/
<>	161:2cc1468da177	247
<>	161:2cc1468da177	248	/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
<>	161:2cc1468da177	249	* @{
<>	161:2cc1468da177	250	*/
<>	161:2cc1468da177	251	#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /!< Slave Address in 7-bit. /
<>	161:2cc1468da177	252	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!< Slave Address in 10-bit./
<>	161:2cc1468da177	253	/**
<>	161:2cc1468da177	254	* @}
<>	161:2cc1468da177	255	*/
<>	161:2cc1468da177	256
<>	161:2cc1468da177	257	/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
<>	161:2cc1468da177	258	* @{
<>	161:2cc1468da177	259	*/
<>	161:2cc1468da177	260	#define LL_I2C_REQUEST_WRITE 0x00000000U /!< Master request a write transfer. /
<>	161:2cc1468da177	261	#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /!< Master request a read transfer. /
<>	161:2cc1468da177	262	/**
<>	161:2cc1468da177	263	* @}
<>	161:2cc1468da177	264	*/
<>	161:2cc1468da177	265
<>	161:2cc1468da177	266	/** @defgroup I2C_LL_EC_MODE Transfer End Mode
<>	161:2cc1468da177	267	* @{
<>	161:2cc1468da177	268	*/
<>	161:2cc1468da177	269	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!< Enable I2C Reload mode. /
<>	161:2cc1468da177	270	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!< Enable I2C Automatic end mode with no HW PEC comparison. /
<>	161:2cc1468da177	271	#define LL_I2C_MODE_SOFTEND 0x00000000U /!< Enable I2C Software end mode with no HW PEC comparison. /
<>	161:2cc1468da177	272	#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	161:2cc1468da177	273	#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	161:2cc1468da177	274	#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	161:2cc1468da177	275	#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	161:2cc1468da177	276	#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	161:2cc1468da177	277	/**
<>	161:2cc1468da177	278	* @}
<>	161:2cc1468da177	279	*/
<>	161:2cc1468da177	280
<>	161:2cc1468da177	281	/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
<>	161:2cc1468da177	282	* @{
<>	161:2cc1468da177	283	*/
AnnaBridge	182:a56a73fd2a6f	284	#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /!< Don't Generate Stop and Start condition. /
AnnaBridge	182:a56a73fd2a6f	285	#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U \| I2C_CR2_STOP) /!< Generate Stop condition (Size should be set to 0). /
AnnaBridge	182:a56a73fd2a6f	286	#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U \| I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Start for read request. /
AnnaBridge	182:a56a73fd2a6f	287	#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U \| I2C_CR2_START) /!< Generate Start for write request. /
AnnaBridge	182:a56a73fd2a6f	288	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U \| I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Restart for read request, slave 7Bit address. /
AnnaBridge	182:a56a73fd2a6f	289	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U \| I2C_CR2_START) /!< Generate Restart for write request, slave 7Bit address. /
AnnaBridge	182:a56a73fd2a6f	290	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U \| I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!< Generate Restart for read request, slave 10Bit address. /
AnnaBridge	182:a56a73fd2a6f	291	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U \| I2C_CR2_START) /!< Generate Restart for write request, slave 10Bit address./
<>	161:2cc1468da177	292	/**
<>	161:2cc1468da177	293	* @}
<>	161:2cc1468da177	294	*/
<>	161:2cc1468da177	295
<>	161:2cc1468da177	296	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
<>	161:2cc1468da177	297	* @{
<>	161:2cc1468da177	298	*/
<>	161:2cc1468da177	299	#define LL_I2C_DIRECTION_WRITE 0x00000000U /!< Write transfer request by master, slave enters receiver mode. /
<>	161:2cc1468da177	300	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!< Read transfer request by master, slave enters transmitter mode./
<>	161:2cc1468da177	301	/**
<>	161:2cc1468da177	302	* @}
<>	161:2cc1468da177	303	*/
<>	161:2cc1468da177	304
<>	161:2cc1468da177	305	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
<>	161:2cc1468da177	306	* @{
<>	161:2cc1468da177	307	*/
<>	161:2cc1468da177	308	#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /!< Get address of data register used for transmission /
<>	161:2cc1468da177	309	#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /!< Get address of data register used for reception /
<>	161:2cc1468da177	310	/**
<>	161:2cc1468da177	311	* @}
<>	161:2cc1468da177	312	*/
<>	161:2cc1468da177	313
<>	161:2cc1468da177	314	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
<>	161:2cc1468da177	315	* @{
<>	161:2cc1468da177	316	*/
<>	161:2cc1468da177	317	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /!< TimeoutA is used to detect SCL low level timeout. /
<>	161:2cc1468da177	318	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /!< TimeoutA is used to detect both SCL and SDA high level timeout./
<>	161:2cc1468da177	319	/**
<>	161:2cc1468da177	320	* @}
<>	161:2cc1468da177	321	*/
<>	161:2cc1468da177	322
<>	161:2cc1468da177	323	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
<>	161:2cc1468da177	324	* @{
<>	161:2cc1468da177	325	*/
<>	161:2cc1468da177	326	#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /!< TimeoutA enable bit /
<>	161:2cc1468da177	327	#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /!< TimeoutB (extended clock) enable bit /
<>	161:2cc1468da177	328	#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN) /!< TimeoutA and TimeoutB (extended clock) enable bits /
<>	161:2cc1468da177	329	/**
<>	161:2cc1468da177	330	* @}
<>	161:2cc1468da177	331	*/
<>	161:2cc1468da177	332
<>	161:2cc1468da177	333	/**
<>	161:2cc1468da177	334	* @}
<>	161:2cc1468da177	335	*/
<>	161:2cc1468da177	336
<>	161:2cc1468da177	337	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	338	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
<>	161:2cc1468da177	339	* @{
<>	161:2cc1468da177	340	*/
<>	161:2cc1468da177	341
<>	161:2cc1468da177	342	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
<>	161:2cc1468da177	343	* @{
<>	161:2cc1468da177	344	*/
<>	161:2cc1468da177	345
<>	161:2cc1468da177	346	/**
<>	161:2cc1468da177	347	* @brief Write a value in I2C register
<>	161:2cc1468da177	348	* @param __INSTANCE__ I2C Instance
<>	161:2cc1468da177	349	* @param __REG__ Register to be written
<>	161:2cc1468da177	350	* @param __VALUE__ Value to be written in the register
<>	161:2cc1468da177	351	* @retval None
<>	161:2cc1468da177	352	*/
<>	161:2cc1468da177	353	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	161:2cc1468da177	354
<>	161:2cc1468da177	355	/**
<>	161:2cc1468da177	356	* @brief Read a value in I2C register
<>	161:2cc1468da177	357	* @param __INSTANCE__ I2C Instance
<>	161:2cc1468da177	358	* @param __REG__ Register to be read
<>	161:2cc1468da177	359	* @retval Register value
<>	161:2cc1468da177	360	*/
<>	161:2cc1468da177	361	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	161:2cc1468da177	362	/**
<>	161:2cc1468da177	363	* @}
<>	161:2cc1468da177	364	*/
<>	161:2cc1468da177	365
<>	161:2cc1468da177	366	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
<>	161:2cc1468da177	367	* @{
<>	161:2cc1468da177	368	*/
<>	161:2cc1468da177	369	/**
<>	161:2cc1468da177	370	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	161:2cc1468da177	371	* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
<>	161:2cc1468da177	372	* @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
<>	161:2cc1468da177	373	* @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
<>	161:2cc1468da177	374	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
<>	161:2cc1468da177	375	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
<>	161:2cc1468da177	376	* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	161:2cc1468da177	377	*/
<>	161:2cc1468da177	378	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
<>	161:2cc1468da177	379	((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) \| \
<>	161:2cc1468da177	380	(((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) \| \
<>	161:2cc1468da177	381	(((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) \| \
<>	161:2cc1468da177	382	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) \| \
<>	161:2cc1468da177	383	(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
<>	161:2cc1468da177	384	/**
<>	161:2cc1468da177	385	* @}
<>	161:2cc1468da177	386	*/
<>	161:2cc1468da177	387
<>	161:2cc1468da177	388	/**
<>	161:2cc1468da177	389	* @}
<>	161:2cc1468da177	390	*/
<>	161:2cc1468da177	391
<>	161:2cc1468da177	392	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	393	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
<>	161:2cc1468da177	394	* @{
<>	161:2cc1468da177	395	*/
<>	161:2cc1468da177	396
<>	161:2cc1468da177	397	/** @defgroup I2C_LL_EF_Configuration Configuration
<>	161:2cc1468da177	398	* @{
<>	161:2cc1468da177	399	*/
<>	161:2cc1468da177	400
<>	161:2cc1468da177	401	/**
<>	161:2cc1468da177	402	* @brief Enable I2C peripheral (PE = 1).
<>	161:2cc1468da177	403	* @rmtoll CR1 PE LL_I2C_Enable
<>	161:2cc1468da177	404	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	405	* @retval None
<>	161:2cc1468da177	406	*/
<>	161:2cc1468da177	407	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	408	{
<>	161:2cc1468da177	409	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	161:2cc1468da177	410	}
<>	161:2cc1468da177	411
<>	161:2cc1468da177	412	/**
<>	161:2cc1468da177	413	* @brief Disable I2C peripheral (PE = 0).
<>	161:2cc1468da177	414	* @note When PE = 0, the I2C SCL and SDA lines are released.
<>	161:2cc1468da177	415	* Internal state machines and status bits are put back to their reset value.
<>	161:2cc1468da177	416	* When cleared, PE must be kept low for at least 3 APB clock cycles.
<>	161:2cc1468da177	417	* @rmtoll CR1 PE LL_I2C_Disable
<>	161:2cc1468da177	418	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	419	* @retval None
<>	161:2cc1468da177	420	*/
<>	161:2cc1468da177	421	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	422	{
<>	161:2cc1468da177	423	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	161:2cc1468da177	424	}
<>	161:2cc1468da177	425
<>	161:2cc1468da177	426	/**
<>	161:2cc1468da177	427	* @brief Check if the I2C peripheral is enabled or disabled.
<>	161:2cc1468da177	428	* @rmtoll CR1 PE LL_I2C_IsEnabled
<>	161:2cc1468da177	429	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	430	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	431	*/
<>	161:2cc1468da177	432	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	433	{
<>	161:2cc1468da177	434	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
<>	161:2cc1468da177	435	}
<>	161:2cc1468da177	436
<>	161:2cc1468da177	437	/**
<>	161:2cc1468da177	438	* @brief Configure Noise Filters (Analog and Digital).
<>	161:2cc1468da177	439	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	161:2cc1468da177	440	* The filters can only be programmed when the I2C is disabled (PE = 0).
<>	161:2cc1468da177	441	* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
<>	161:2cc1468da177	442	* CR1 DNF LL_I2C_ConfigFilters
<>	161:2cc1468da177	443	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	444	* @param AnalogFilter This parameter can be one of the following values:
<>	161:2cc1468da177	445	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
<>	161:2cc1468da177	446	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
<>	161:2cc1468da177	447	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	161:2cc1468da177	448	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	161:2cc1468da177	449	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	161:2cc1468da177	450	* @retval None
<>	161:2cc1468da177	451	*/
<>	161:2cc1468da177	452	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
<>	161:2cc1468da177	453	{
<>	161:2cc1468da177	454	MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF \| I2C_CR1_DNF, AnalogFilter \| (DigitalFilter << I2C_CR1_DNF_Pos));
<>	161:2cc1468da177	455	}
<>	161:2cc1468da177	456
<>	161:2cc1468da177	457	/**
<>	161:2cc1468da177	458	* @brief Configure Digital Noise Filter.
<>	161:2cc1468da177	459	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	161:2cc1468da177	460	* This filter can only be programmed when the I2C is disabled (PE = 0).
<>	161:2cc1468da177	461	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
<>	161:2cc1468da177	462	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	463	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	161:2cc1468da177	464	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	161:2cc1468da177	465	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	161:2cc1468da177	466	* @retval None
<>	161:2cc1468da177	467	*/
<>	161:2cc1468da177	468	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
<>	161:2cc1468da177	469	{
<>	161:2cc1468da177	470	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
<>	161:2cc1468da177	471	}
<>	161:2cc1468da177	472
<>	161:2cc1468da177	473	/**
<>	161:2cc1468da177	474	* @brief Get the current Digital Noise Filter configuration.
<>	161:2cc1468da177	475	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
<>	161:2cc1468da177	476	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	477	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	161:2cc1468da177	478	*/
<>	161:2cc1468da177	479	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	480	{
<>	161:2cc1468da177	481	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
<>	161:2cc1468da177	482	}
<>	161:2cc1468da177	483
<>	161:2cc1468da177	484	/**
<>	161:2cc1468da177	485	* @brief Enable Analog Noise Filter.
<>	161:2cc1468da177	486	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	161:2cc1468da177	487	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
<>	161:2cc1468da177	488	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	489	* @retval None
<>	161:2cc1468da177	490	*/
<>	161:2cc1468da177	491	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	492	{
<>	161:2cc1468da177	493	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	161:2cc1468da177	494	}
<>	161:2cc1468da177	495
<>	161:2cc1468da177	496	/**
<>	161:2cc1468da177	497	* @brief Disable Analog Noise Filter.
<>	161:2cc1468da177	498	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	161:2cc1468da177	499	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
<>	161:2cc1468da177	500	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	501	* @retval None
<>	161:2cc1468da177	502	*/
<>	161:2cc1468da177	503	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	504	{
<>	161:2cc1468da177	505	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	161:2cc1468da177	506	}
<>	161:2cc1468da177	507
<>	161:2cc1468da177	508	/**
<>	161:2cc1468da177	509	* @brief Check if Analog Noise Filter is enabled or disabled.
<>	161:2cc1468da177	510	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
<>	161:2cc1468da177	511	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	512	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	513	*/
<>	161:2cc1468da177	514	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	515	{
<>	161:2cc1468da177	516	return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
<>	161:2cc1468da177	517	}
<>	161:2cc1468da177	518
<>	161:2cc1468da177	519	/**
<>	161:2cc1468da177	520	* @brief Enable DMA transmission requests.
<>	161:2cc1468da177	521	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
<>	161:2cc1468da177	522	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	523	* @retval None
<>	161:2cc1468da177	524	*/
<>	161:2cc1468da177	525	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	526	{
<>	161:2cc1468da177	527	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	161:2cc1468da177	528	}
<>	161:2cc1468da177	529
<>	161:2cc1468da177	530	/**
<>	161:2cc1468da177	531	* @brief Disable DMA transmission requests.
<>	161:2cc1468da177	532	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
<>	161:2cc1468da177	533	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	534	* @retval None
<>	161:2cc1468da177	535	*/
<>	161:2cc1468da177	536	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	537	{
<>	161:2cc1468da177	538	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	161:2cc1468da177	539	}
<>	161:2cc1468da177	540
<>	161:2cc1468da177	541	/**
<>	161:2cc1468da177	542	* @brief Check if DMA transmission requests are enabled or disabled.
<>	161:2cc1468da177	543	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
<>	161:2cc1468da177	544	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	545	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	546	*/
<>	161:2cc1468da177	547	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	548	{
<>	161:2cc1468da177	549	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
<>	161:2cc1468da177	550	}
<>	161:2cc1468da177	551
<>	161:2cc1468da177	552	/**
<>	161:2cc1468da177	553	* @brief Enable DMA reception requests.
<>	161:2cc1468da177	554	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
<>	161:2cc1468da177	555	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	556	* @retval None
<>	161:2cc1468da177	557	*/
<>	161:2cc1468da177	558	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	559	{
<>	161:2cc1468da177	560	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	161:2cc1468da177	561	}
<>	161:2cc1468da177	562
<>	161:2cc1468da177	563	/**
<>	161:2cc1468da177	564	* @brief Disable DMA reception requests.
<>	161:2cc1468da177	565	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
<>	161:2cc1468da177	566	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	567	* @retval None
<>	161:2cc1468da177	568	*/
<>	161:2cc1468da177	569	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	570	{
<>	161:2cc1468da177	571	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	161:2cc1468da177	572	}
<>	161:2cc1468da177	573
<>	161:2cc1468da177	574	/**
<>	161:2cc1468da177	575	* @brief Check if DMA reception requests are enabled or disabled.
<>	161:2cc1468da177	576	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
<>	161:2cc1468da177	577	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	578	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	579	*/
<>	161:2cc1468da177	580	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	581	{
<>	161:2cc1468da177	582	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
<>	161:2cc1468da177	583	}
<>	161:2cc1468da177	584
<>	161:2cc1468da177	585	/**
<>	161:2cc1468da177	586	* @brief Get the data register address used for DMA transfer
<>	161:2cc1468da177	587	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
<>	161:2cc1468da177	588	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
<>	161:2cc1468da177	589	* @param I2Cx I2C Instance
<>	161:2cc1468da177	590	* @param Direction This parameter can be one of the following values:
<>	161:2cc1468da177	591	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
<>	161:2cc1468da177	592	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
<>	161:2cc1468da177	593	* @retval Address of data register
<>	161:2cc1468da177	594	*/
<>	161:2cc1468da177	595	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
<>	161:2cc1468da177	596	{
<>	161:2cc1468da177	597	register uint32_t data_reg_addr = 0U;
<>	161:2cc1468da177	598
<>	161:2cc1468da177	599	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
<>	161:2cc1468da177	600	{
<>	161:2cc1468da177	601	/* return address of TXDR register */
<>	161:2cc1468da177	602	data_reg_addr = (uint32_t) & (I2Cx->TXDR);
<>	161:2cc1468da177	603	}
<>	161:2cc1468da177	604	else
<>	161:2cc1468da177	605	{
<>	161:2cc1468da177	606	/* return address of RXDR register */
<>	161:2cc1468da177	607	data_reg_addr = (uint32_t) & (I2Cx->RXDR);
<>	161:2cc1468da177	608	}
<>	161:2cc1468da177	609
<>	161:2cc1468da177	610	return data_reg_addr;
<>	161:2cc1468da177	611	}
<>	161:2cc1468da177	612
<>	161:2cc1468da177	613	/**
<>	161:2cc1468da177	614	* @brief Enable Clock stretching.
<>	161:2cc1468da177	615	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	161:2cc1468da177	616	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
<>	161:2cc1468da177	617	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	618	* @retval None
<>	161:2cc1468da177	619	*/
<>	161:2cc1468da177	620	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	621	{
<>	161:2cc1468da177	622	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	161:2cc1468da177	623	}
<>	161:2cc1468da177	624
<>	161:2cc1468da177	625	/**
<>	161:2cc1468da177	626	* @brief Disable Clock stretching.
<>	161:2cc1468da177	627	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	161:2cc1468da177	628	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
<>	161:2cc1468da177	629	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	630	* @retval None
<>	161:2cc1468da177	631	*/
<>	161:2cc1468da177	632	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	633	{
<>	161:2cc1468da177	634	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	161:2cc1468da177	635	}
<>	161:2cc1468da177	636
<>	161:2cc1468da177	637	/**
<>	161:2cc1468da177	638	* @brief Check if Clock stretching is enabled or disabled.
<>	161:2cc1468da177	639	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
<>	161:2cc1468da177	640	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	641	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	642	*/
<>	161:2cc1468da177	643	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	644	{
<>	161:2cc1468da177	645	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
<>	161:2cc1468da177	646	}
<>	161:2cc1468da177	647
<>	161:2cc1468da177	648	/**
<>	161:2cc1468da177	649	* @brief Enable hardware byte control in slave mode.
<>	161:2cc1468da177	650	* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
<>	161:2cc1468da177	651	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	652	* @retval None
<>	161:2cc1468da177	653	*/
<>	161:2cc1468da177	654	__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	655	{
<>	161:2cc1468da177	656	SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	161:2cc1468da177	657	}
<>	161:2cc1468da177	658
<>	161:2cc1468da177	659	/**
<>	161:2cc1468da177	660	* @brief Disable hardware byte control in slave mode.
<>	161:2cc1468da177	661	* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
<>	161:2cc1468da177	662	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	663	* @retval None
<>	161:2cc1468da177	664	*/
<>	161:2cc1468da177	665	__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	666	{
<>	161:2cc1468da177	667	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	161:2cc1468da177	668	}
<>	161:2cc1468da177	669
<>	161:2cc1468da177	670	/**
<>	161:2cc1468da177	671	* @brief Check if hardware byte control in slave mode is enabled or disabled.
<>	161:2cc1468da177	672	* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
<>	161:2cc1468da177	673	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	674	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	675	*/
<>	161:2cc1468da177	676	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	677	{
<>	161:2cc1468da177	678	return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
<>	161:2cc1468da177	679	}
<>	161:2cc1468da177	680
<>	161:2cc1468da177	681
<>	161:2cc1468da177	682	/**
<>	161:2cc1468da177	683	* @brief Enable General Call.
<>	161:2cc1468da177	684	* @note When enabled the Address 0x00 is ACKed.
<>	161:2cc1468da177	685	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
<>	161:2cc1468da177	686	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	687	* @retval None
<>	161:2cc1468da177	688	*/
<>	161:2cc1468da177	689	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	690	{
<>	161:2cc1468da177	691	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	161:2cc1468da177	692	}
<>	161:2cc1468da177	693
<>	161:2cc1468da177	694	/**
<>	161:2cc1468da177	695	* @brief Disable General Call.
<>	161:2cc1468da177	696	* @note When disabled the Address 0x00 is NACKed.
<>	161:2cc1468da177	697	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
<>	161:2cc1468da177	698	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	699	* @retval None
<>	161:2cc1468da177	700	*/
<>	161:2cc1468da177	701	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	702	{
<>	161:2cc1468da177	703	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	161:2cc1468da177	704	}
<>	161:2cc1468da177	705
<>	161:2cc1468da177	706	/**
<>	161:2cc1468da177	707	* @brief Check if General Call is enabled or disabled.
<>	161:2cc1468da177	708	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
<>	161:2cc1468da177	709	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	710	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	711	*/
<>	161:2cc1468da177	712	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	713	{
<>	161:2cc1468da177	714	return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
<>	161:2cc1468da177	715	}
<>	161:2cc1468da177	716
<>	161:2cc1468da177	717	/**
<>	161:2cc1468da177	718	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
<>	161:2cc1468da177	719	* @note Changing this bit is not allowed, when the START bit is set.
<>	161:2cc1468da177	720	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
<>	161:2cc1468da177	721	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	722	* @param AddressingMode This parameter can be one of the following values:
<>	161:2cc1468da177	723	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	161:2cc1468da177	724	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	161:2cc1468da177	725	* @retval None
<>	161:2cc1468da177	726	*/
<>	161:2cc1468da177	727	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
<>	161:2cc1468da177	728	{
<>	161:2cc1468da177	729	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
<>	161:2cc1468da177	730	}
<>	161:2cc1468da177	731
<>	161:2cc1468da177	732	/**
<>	161:2cc1468da177	733	* @brief Get the Master addressing mode.
<>	161:2cc1468da177	734	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
<>	161:2cc1468da177	735	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	736	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	737	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	161:2cc1468da177	738	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	161:2cc1468da177	739	*/
<>	161:2cc1468da177	740	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	741	{
<>	161:2cc1468da177	742	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
<>	161:2cc1468da177	743	}
<>	161:2cc1468da177	744
<>	161:2cc1468da177	745	/**
<>	161:2cc1468da177	746	* @brief Set the Own Address1.
<>	161:2cc1468da177	747	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
<>	161:2cc1468da177	748	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
<>	161:2cc1468da177	749	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	750	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
<>	161:2cc1468da177	751	* @param OwnAddrSize This parameter can be one of the following values:
<>	161:2cc1468da177	752	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
<>	161:2cc1468da177	753	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
<>	161:2cc1468da177	754	* @retval None
<>	161:2cc1468da177	755	*/
<>	161:2cc1468da177	756	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
<>	161:2cc1468da177	757	{
<>	161:2cc1468da177	758	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddress1 \| OwnAddrSize);
<>	161:2cc1468da177	759	}
<>	161:2cc1468da177	760
<>	161:2cc1468da177	761	/**
<>	161:2cc1468da177	762	* @brief Enable acknowledge on Own Address1 match address.
<>	161:2cc1468da177	763	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
<>	161:2cc1468da177	764	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	765	* @retval None
<>	161:2cc1468da177	766	*/
<>	161:2cc1468da177	767	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	768	{
<>	161:2cc1468da177	769	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	161:2cc1468da177	770	}
<>	161:2cc1468da177	771
<>	161:2cc1468da177	772	/**
<>	161:2cc1468da177	773	* @brief Disable acknowledge on Own Address1 match address.
<>	161:2cc1468da177	774	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
<>	161:2cc1468da177	775	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	776	* @retval None
<>	161:2cc1468da177	777	*/
<>	161:2cc1468da177	778	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	779	{
<>	161:2cc1468da177	780	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	161:2cc1468da177	781	}
<>	161:2cc1468da177	782
<>	161:2cc1468da177	783	/**
<>	161:2cc1468da177	784	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	161:2cc1468da177	785	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
<>	161:2cc1468da177	786	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	787	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	788	*/
<>	161:2cc1468da177	789	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	790	{
<>	161:2cc1468da177	791	return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
<>	161:2cc1468da177	792	}
<>	161:2cc1468da177	793
<>	161:2cc1468da177	794	/**
<>	161:2cc1468da177	795	* @brief Set the 7bits Own Address2.
<>	161:2cc1468da177	796	* @note This action has no effect if own address2 is enabled.
<>	161:2cc1468da177	797	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
<>	161:2cc1468da177	798	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
<>	161:2cc1468da177	799	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	800	* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
<>	161:2cc1468da177	801	* @param OwnAddrMask This parameter can be one of the following values:
<>	161:2cc1468da177	802	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
<>	161:2cc1468da177	803	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
<>	161:2cc1468da177	804	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
<>	161:2cc1468da177	805	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
<>	161:2cc1468da177	806	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
<>	161:2cc1468da177	807	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
<>	161:2cc1468da177	808	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
<>	161:2cc1468da177	809	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
<>	161:2cc1468da177	810	* @retval None
<>	161:2cc1468da177	811	*/
<>	161:2cc1468da177	812	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
<>	161:2cc1468da177	813	{
<>	161:2cc1468da177	814	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddress2 \| OwnAddrMask);
<>	161:2cc1468da177	815	}
<>	161:2cc1468da177	816
<>	161:2cc1468da177	817	/**
<>	161:2cc1468da177	818	* @brief Enable acknowledge on Own Address2 match address.
<>	161:2cc1468da177	819	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
<>	161:2cc1468da177	820	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	821	* @retval None
<>	161:2cc1468da177	822	*/
<>	161:2cc1468da177	823	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	824	{
<>	161:2cc1468da177	825	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	161:2cc1468da177	826	}
<>	161:2cc1468da177	827
<>	161:2cc1468da177	828	/**
<>	161:2cc1468da177	829	* @brief Disable acknowledge on Own Address2 match address.
<>	161:2cc1468da177	830	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
<>	161:2cc1468da177	831	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	832	* @retval None
<>	161:2cc1468da177	833	*/
<>	161:2cc1468da177	834	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	835	{
<>	161:2cc1468da177	836	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	161:2cc1468da177	837	}
<>	161:2cc1468da177	838
<>	161:2cc1468da177	839	/**
<>	161:2cc1468da177	840	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	161:2cc1468da177	841	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
<>	161:2cc1468da177	842	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	843	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	844	*/
<>	161:2cc1468da177	845	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	846	{
<>	161:2cc1468da177	847	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
<>	161:2cc1468da177	848	}
<>	161:2cc1468da177	849
<>	161:2cc1468da177	850	/**
<>	161:2cc1468da177	851	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	161:2cc1468da177	852	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	161:2cc1468da177	853	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
<>	161:2cc1468da177	854	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	855	* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
<>	161:2cc1468da177	856	* @note This parameter is computed with the STM32CubeMX Tool.
<>	161:2cc1468da177	857	* @retval None
<>	161:2cc1468da177	858	*/
<>	161:2cc1468da177	859	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
<>	161:2cc1468da177	860	{
<>	161:2cc1468da177	861	WRITE_REG(I2Cx->TIMINGR, Timing);
<>	161:2cc1468da177	862	}
<>	161:2cc1468da177	863
<>	161:2cc1468da177	864	/**
<>	161:2cc1468da177	865	* @brief Get the Timing Prescaler setting.
<>	161:2cc1468da177	866	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
<>	161:2cc1468da177	867	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	868	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	161:2cc1468da177	869	*/
<>	161:2cc1468da177	870	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	871	{
<>	161:2cc1468da177	872	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
<>	161:2cc1468da177	873	}
<>	161:2cc1468da177	874
<>	161:2cc1468da177	875	/**
<>	161:2cc1468da177	876	* @brief Get the SCL low period setting.
<>	161:2cc1468da177	877	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
<>	161:2cc1468da177	878	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	879	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	880	*/
<>	161:2cc1468da177	881	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	882	{
<>	161:2cc1468da177	883	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
<>	161:2cc1468da177	884	}
<>	161:2cc1468da177	885
<>	161:2cc1468da177	886	/**
<>	161:2cc1468da177	887	* @brief Get the SCL high period setting.
<>	161:2cc1468da177	888	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
<>	161:2cc1468da177	889	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	890	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	891	*/
<>	161:2cc1468da177	892	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	893	{
<>	161:2cc1468da177	894	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
<>	161:2cc1468da177	895	}
<>	161:2cc1468da177	896
<>	161:2cc1468da177	897	/**
<>	161:2cc1468da177	898	* @brief Get the SDA hold time.
<>	161:2cc1468da177	899	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
<>	161:2cc1468da177	900	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	901	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	161:2cc1468da177	902	*/
<>	161:2cc1468da177	903	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	904	{
<>	161:2cc1468da177	905	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
<>	161:2cc1468da177	906	}
<>	161:2cc1468da177	907
<>	161:2cc1468da177	908	/**
<>	161:2cc1468da177	909	* @brief Get the SDA setup time.
<>	161:2cc1468da177	910	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
<>	161:2cc1468da177	911	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	912	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	161:2cc1468da177	913	*/
<>	161:2cc1468da177	914	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	915	{
<>	161:2cc1468da177	916	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
<>	161:2cc1468da177	917	}
<>	161:2cc1468da177	918
<>	161:2cc1468da177	919	/**
<>	161:2cc1468da177	920	* @brief Configure peripheral mode.
<>	161:2cc1468da177	921	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	922	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	923	* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
<>	161:2cc1468da177	924	* CR1 SMBDEN LL_I2C_SetMode
<>	161:2cc1468da177	925	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	926	* @param PeripheralMode This parameter can be one of the following values:
<>	161:2cc1468da177	927	* @arg @ref LL_I2C_MODE_I2C
<>	161:2cc1468da177	928	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	161:2cc1468da177	929	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	161:2cc1468da177	930	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	161:2cc1468da177	931	* @retval None
<>	161:2cc1468da177	932	*/
<>	161:2cc1468da177	933	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
<>	161:2cc1468da177	934	{
<>	161:2cc1468da177	935	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN, PeripheralMode);
<>	161:2cc1468da177	936	}
<>	161:2cc1468da177	937
<>	161:2cc1468da177	938	/**
<>	161:2cc1468da177	939	* @brief Get peripheral mode.
<>	161:2cc1468da177	940	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	941	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	942	* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
<>	161:2cc1468da177	943	* CR1 SMBDEN LL_I2C_GetMode
<>	161:2cc1468da177	944	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	945	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	946	* @arg @ref LL_I2C_MODE_I2C
<>	161:2cc1468da177	947	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	161:2cc1468da177	948	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	161:2cc1468da177	949	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	161:2cc1468da177	950	*/
<>	161:2cc1468da177	951	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	952	{
<>	161:2cc1468da177	953	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN));
<>	161:2cc1468da177	954	}
<>	161:2cc1468da177	955
<>	161:2cc1468da177	956	/**
<>	161:2cc1468da177	957	* @brief Enable SMBus alert (Host or Device mode)
<>	161:2cc1468da177	958	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	959	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	960	* @note SMBus Device mode:
<>	161:2cc1468da177	961	* - SMBus Alert pin is drived low and
<>	161:2cc1468da177	962	* Alert Response Address Header acknowledge is enabled.
<>	161:2cc1468da177	963	* SMBus Host mode:
<>	161:2cc1468da177	964	* - SMBus Alert pin management is supported.
<>	161:2cc1468da177	965	* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
<>	161:2cc1468da177	966	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	967	* @retval None
<>	161:2cc1468da177	968	*/
<>	161:2cc1468da177	969	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	970	{
<>	161:2cc1468da177	971	SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	161:2cc1468da177	972	}
<>	161:2cc1468da177	973
<>	161:2cc1468da177	974	/**
<>	161:2cc1468da177	975	* @brief Disable SMBus alert (Host or Device mode)
<>	161:2cc1468da177	976	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	977	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	978	* @note SMBus Device mode:
<>	161:2cc1468da177	979	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
<>	161:2cc1468da177	980	* Alert Response Address Header acknowledge is disabled.
<>	161:2cc1468da177	981	* SMBus Host mode:
<>	161:2cc1468da177	982	* - SMBus Alert pin management is not supported.
<>	161:2cc1468da177	983	* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
<>	161:2cc1468da177	984	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	985	* @retval None
<>	161:2cc1468da177	986	*/
<>	161:2cc1468da177	987	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	988	{
<>	161:2cc1468da177	989	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	161:2cc1468da177	990	}
<>	161:2cc1468da177	991
<>	161:2cc1468da177	992	/**
<>	161:2cc1468da177	993	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
<>	161:2cc1468da177	994	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	995	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	996	* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
<>	161:2cc1468da177	997	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	998	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	999	*/
<>	161:2cc1468da177	1000	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1001	{
<>	161:2cc1468da177	1002	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
<>	161:2cc1468da177	1003	}
<>	161:2cc1468da177	1004
<>	161:2cc1468da177	1005	/**
<>	161:2cc1468da177	1006	* @brief Enable SMBus Packet Error Calculation (PEC).
<>	161:2cc1468da177	1007	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1008	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1009	* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
<>	161:2cc1468da177	1010	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1011	* @retval None
<>	161:2cc1468da177	1012	*/
<>	161:2cc1468da177	1013	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1014	{
<>	161:2cc1468da177	1015	SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	161:2cc1468da177	1016	}
<>	161:2cc1468da177	1017
<>	161:2cc1468da177	1018	/**
<>	161:2cc1468da177	1019	* @brief Disable SMBus Packet Error Calculation (PEC).
<>	161:2cc1468da177	1020	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1021	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1022	* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
<>	161:2cc1468da177	1023	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1024	* @retval None
<>	161:2cc1468da177	1025	*/
<>	161:2cc1468da177	1026	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1027	{
<>	161:2cc1468da177	1028	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	161:2cc1468da177	1029	}
<>	161:2cc1468da177	1030
<>	161:2cc1468da177	1031	/**
<>	161:2cc1468da177	1032	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
<>	161:2cc1468da177	1033	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1034	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1035	* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
<>	161:2cc1468da177	1036	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1037	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1038	*/
<>	161:2cc1468da177	1039	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1040	{
<>	161:2cc1468da177	1041	return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
<>	161:2cc1468da177	1042	}
<>	161:2cc1468da177	1043
<>	161:2cc1468da177	1044	/**
<>	161:2cc1468da177	1045	* @brief Configure the SMBus Clock Timeout.
<>	161:2cc1468da177	1046	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1047	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1048	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
<>	161:2cc1468da177	1049	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
<>	161:2cc1468da177	1050	* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
<>	161:2cc1468da177	1051	* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
<>	161:2cc1468da177	1052	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1053	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	161:2cc1468da177	1054	* @param TimeoutAMode This parameter can be one of the following values:
<>	161:2cc1468da177	1055	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	161:2cc1468da177	1056	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	161:2cc1468da177	1057	* @param TimeoutB
<>	161:2cc1468da177	1058	* @retval None
<>	161:2cc1468da177	1059	*/
<>	161:2cc1468da177	1060	__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
<>	161:2cc1468da177	1061	uint32_t TimeoutB)
<>	161:2cc1468da177	1062	{
<>	161:2cc1468da177	1063	MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA \| I2C_TIMEOUTR_TIDLE \| I2C_TIMEOUTR_TIMEOUTB,
<>	161:2cc1468da177	1064	TimeoutA \| TimeoutAMode \| (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
<>	161:2cc1468da177	1065	}
<>	161:2cc1468da177	1066
<>	161:2cc1468da177	1067	/**
<>	161:2cc1468da177	1068	* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
<>	161:2cc1468da177	1069	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1070	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1071	* @note These bits can only be programmed when TimeoutA is disabled.
<>	161:2cc1468da177	1072	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
<>	161:2cc1468da177	1073	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1074	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	161:2cc1468da177	1075	* @retval None
<>	161:2cc1468da177	1076	*/
<>	161:2cc1468da177	1077	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
<>	161:2cc1468da177	1078	{
<>	161:2cc1468da177	1079	WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
<>	161:2cc1468da177	1080	}
<>	161:2cc1468da177	1081
<>	161:2cc1468da177	1082	/**
<>	161:2cc1468da177	1083	* @brief Get the SMBus Clock TimeoutA setting.
<>	161:2cc1468da177	1084	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1085	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1086	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
<>	161:2cc1468da177	1087	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1088	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	161:2cc1468da177	1089	*/
<>	161:2cc1468da177	1090	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1091	{
<>	161:2cc1468da177	1092	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
<>	161:2cc1468da177	1093	}
<>	161:2cc1468da177	1094
<>	161:2cc1468da177	1095	/**
<>	161:2cc1468da177	1096	* @brief Set the SMBus Clock TimeoutA mode.
<>	161:2cc1468da177	1097	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1098	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1099	* @note This bit can only be programmed when TimeoutA is disabled.
<>	161:2cc1468da177	1100	* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
<>	161:2cc1468da177	1101	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1102	* @param TimeoutAMode This parameter can be one of the following values:
<>	161:2cc1468da177	1103	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	161:2cc1468da177	1104	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	161:2cc1468da177	1105	* @retval None
<>	161:2cc1468da177	1106	*/
<>	161:2cc1468da177	1107	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
<>	161:2cc1468da177	1108	{
<>	161:2cc1468da177	1109	WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
<>	161:2cc1468da177	1110	}
<>	161:2cc1468da177	1111
<>	161:2cc1468da177	1112	/**
<>	161:2cc1468da177	1113	* @brief Get the SMBus Clock TimeoutA mode.
<>	161:2cc1468da177	1114	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1115	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1116	* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
<>	161:2cc1468da177	1117	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1118	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1119	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	161:2cc1468da177	1120	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	161:2cc1468da177	1121	*/
<>	161:2cc1468da177	1122	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1123	{
<>	161:2cc1468da177	1124	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
<>	161:2cc1468da177	1125	}
<>	161:2cc1468da177	1126
<>	161:2cc1468da177	1127	/**
<>	161:2cc1468da177	1128	* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
<>	161:2cc1468da177	1129	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1130	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1131	* @note These bits can only be programmed when TimeoutB is disabled.
<>	161:2cc1468da177	1132	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
<>	161:2cc1468da177	1133	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1134	* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	161:2cc1468da177	1135	* @retval None
<>	161:2cc1468da177	1136	*/
<>	161:2cc1468da177	1137	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
<>	161:2cc1468da177	1138	{
<>	161:2cc1468da177	1139	WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
<>	161:2cc1468da177	1140	}
<>	161:2cc1468da177	1141
<>	161:2cc1468da177	1142	/**
<>	161:2cc1468da177	1143	* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
<>	161:2cc1468da177	1144	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1145	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1146	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
<>	161:2cc1468da177	1147	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1148	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	161:2cc1468da177	1149	*/
<>	161:2cc1468da177	1150	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1151	{
<>	161:2cc1468da177	1152	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
<>	161:2cc1468da177	1153	}
<>	161:2cc1468da177	1154
<>	161:2cc1468da177	1155	/**
<>	161:2cc1468da177	1156	* @brief Enable the SMBus Clock Timeout.
<>	161:2cc1468da177	1157	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1158	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1159	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
<>	161:2cc1468da177	1160	* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
<>	161:2cc1468da177	1161	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1162	* @param ClockTimeout This parameter can be one of the following values:
<>	161:2cc1468da177	1163	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	161:2cc1468da177	1164	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	161:2cc1468da177	1165	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	161:2cc1468da177	1166	* @retval None
<>	161:2cc1468da177	1167	*/
<>	161:2cc1468da177	1168	__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	161:2cc1468da177	1169	{
<>	161:2cc1468da177	1170	SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	161:2cc1468da177	1171	}
<>	161:2cc1468da177	1172
<>	161:2cc1468da177	1173	/**
<>	161:2cc1468da177	1174	* @brief Disable the SMBus Clock Timeout.
<>	161:2cc1468da177	1175	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1176	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1177	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
<>	161:2cc1468da177	1178	* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
<>	161:2cc1468da177	1179	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1180	* @param ClockTimeout This parameter can be one of the following values:
<>	161:2cc1468da177	1181	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	161:2cc1468da177	1182	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	161:2cc1468da177	1183	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	161:2cc1468da177	1184	* @retval None
<>	161:2cc1468da177	1185	*/
<>	161:2cc1468da177	1186	__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	161:2cc1468da177	1187	{
<>	161:2cc1468da177	1188	CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	161:2cc1468da177	1189	}
<>	161:2cc1468da177	1190
<>	161:2cc1468da177	1191	/**
<>	161:2cc1468da177	1192	* @brief Check if the SMBus Clock Timeout is enabled or disabled.
<>	161:2cc1468da177	1193	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1194	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1195	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
<>	161:2cc1468da177	1196	* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
<>	161:2cc1468da177	1197	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1198	* @param ClockTimeout This parameter can be one of the following values:
<>	161:2cc1468da177	1199	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	161:2cc1468da177	1200	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	161:2cc1468da177	1201	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	161:2cc1468da177	1202	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1203	*/
<>	161:2cc1468da177	1204	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	161:2cc1468da177	1205	{
<>	161:2cc1468da177	1206	return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
<>	161:2cc1468da177	1207	}
<>	161:2cc1468da177	1208
<>	161:2cc1468da177	1209	/**
<>	161:2cc1468da177	1210	* @}
<>	161:2cc1468da177	1211	*/
<>	161:2cc1468da177	1212
<>	161:2cc1468da177	1213	/** @defgroup I2C_LL_EF_IT_Management IT_Management
<>	161:2cc1468da177	1214	* @{
<>	161:2cc1468da177	1215	*/
<>	161:2cc1468da177	1216
<>	161:2cc1468da177	1217	/**
<>	161:2cc1468da177	1218	* @brief Enable TXIS interrupt.
<>	161:2cc1468da177	1219	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
<>	161:2cc1468da177	1220	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1221	* @retval None
<>	161:2cc1468da177	1222	*/
<>	161:2cc1468da177	1223	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1224	{
<>	161:2cc1468da177	1225	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	161:2cc1468da177	1226	}
<>	161:2cc1468da177	1227
<>	161:2cc1468da177	1228	/**
<>	161:2cc1468da177	1229	* @brief Disable TXIS interrupt.
<>	161:2cc1468da177	1230	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
<>	161:2cc1468da177	1231	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1232	* @retval None
<>	161:2cc1468da177	1233	*/
<>	161:2cc1468da177	1234	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1235	{
<>	161:2cc1468da177	1236	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	161:2cc1468da177	1237	}
<>	161:2cc1468da177	1238
<>	161:2cc1468da177	1239	/**
<>	161:2cc1468da177	1240	* @brief Check if the TXIS Interrupt is enabled or disabled.
<>	161:2cc1468da177	1241	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
<>	161:2cc1468da177	1242	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1243	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1244	*/
<>	161:2cc1468da177	1245	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1246	{
<>	161:2cc1468da177	1247	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
<>	161:2cc1468da177	1248	}
<>	161:2cc1468da177	1249
<>	161:2cc1468da177	1250	/**
<>	161:2cc1468da177	1251	* @brief Enable RXNE interrupt.
<>	161:2cc1468da177	1252	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
<>	161:2cc1468da177	1253	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1254	* @retval None
<>	161:2cc1468da177	1255	*/
<>	161:2cc1468da177	1256	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1257	{
<>	161:2cc1468da177	1258	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	161:2cc1468da177	1259	}
<>	161:2cc1468da177	1260
<>	161:2cc1468da177	1261	/**
<>	161:2cc1468da177	1262	* @brief Disable RXNE interrupt.
<>	161:2cc1468da177	1263	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
<>	161:2cc1468da177	1264	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1265	* @retval None
<>	161:2cc1468da177	1266	*/
<>	161:2cc1468da177	1267	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1268	{
<>	161:2cc1468da177	1269	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	161:2cc1468da177	1270	}
<>	161:2cc1468da177	1271
<>	161:2cc1468da177	1272	/**
<>	161:2cc1468da177	1273	* @brief Check if the RXNE Interrupt is enabled or disabled.
<>	161:2cc1468da177	1274	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
<>	161:2cc1468da177	1275	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1276	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1277	*/
<>	161:2cc1468da177	1278	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1279	{
<>	161:2cc1468da177	1280	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
<>	161:2cc1468da177	1281	}
<>	161:2cc1468da177	1282
<>	161:2cc1468da177	1283	/**
<>	161:2cc1468da177	1284	* @brief Enable Address match interrupt (slave mode only).
<>	161:2cc1468da177	1285	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
<>	161:2cc1468da177	1286	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1287	* @retval None
<>	161:2cc1468da177	1288	*/
<>	161:2cc1468da177	1289	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1290	{
<>	161:2cc1468da177	1291	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	161:2cc1468da177	1292	}
<>	161:2cc1468da177	1293
<>	161:2cc1468da177	1294	/**
<>	161:2cc1468da177	1295	* @brief Disable Address match interrupt (slave mode only).
<>	161:2cc1468da177	1296	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
<>	161:2cc1468da177	1297	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1298	* @retval None
<>	161:2cc1468da177	1299	*/
<>	161:2cc1468da177	1300	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1301	{
<>	161:2cc1468da177	1302	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	161:2cc1468da177	1303	}
<>	161:2cc1468da177	1304
<>	161:2cc1468da177	1305	/**
<>	161:2cc1468da177	1306	* @brief Check if Address match interrupt is enabled or disabled.
<>	161:2cc1468da177	1307	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
<>	161:2cc1468da177	1308	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1309	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1310	*/
<>	161:2cc1468da177	1311	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1312	{
<>	161:2cc1468da177	1313	return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
<>	161:2cc1468da177	1314	}
<>	161:2cc1468da177	1315
<>	161:2cc1468da177	1316	/**
<>	161:2cc1468da177	1317	* @brief Enable Not acknowledge received interrupt.
<>	161:2cc1468da177	1318	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
<>	161:2cc1468da177	1319	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1320	* @retval None
<>	161:2cc1468da177	1321	*/
<>	161:2cc1468da177	1322	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1323	{
<>	161:2cc1468da177	1324	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	161:2cc1468da177	1325	}
<>	161:2cc1468da177	1326
<>	161:2cc1468da177	1327	/**
<>	161:2cc1468da177	1328	* @brief Disable Not acknowledge received interrupt.
<>	161:2cc1468da177	1329	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
<>	161:2cc1468da177	1330	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1331	* @retval None
<>	161:2cc1468da177	1332	*/
<>	161:2cc1468da177	1333	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1334	{
<>	161:2cc1468da177	1335	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	161:2cc1468da177	1336	}
<>	161:2cc1468da177	1337
<>	161:2cc1468da177	1338	/**
<>	161:2cc1468da177	1339	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
<>	161:2cc1468da177	1340	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
<>	161:2cc1468da177	1341	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1342	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1343	*/
<>	161:2cc1468da177	1344	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1345	{
<>	161:2cc1468da177	1346	return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
<>	161:2cc1468da177	1347	}
<>	161:2cc1468da177	1348
<>	161:2cc1468da177	1349	/**
<>	161:2cc1468da177	1350	* @brief Enable STOP detection interrupt.
<>	161:2cc1468da177	1351	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
<>	161:2cc1468da177	1352	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1353	* @retval None
<>	161:2cc1468da177	1354	*/
<>	161:2cc1468da177	1355	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1356	{
<>	161:2cc1468da177	1357	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	161:2cc1468da177	1358	}
<>	161:2cc1468da177	1359
<>	161:2cc1468da177	1360	/**
<>	161:2cc1468da177	1361	* @brief Disable STOP detection interrupt.
<>	161:2cc1468da177	1362	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
<>	161:2cc1468da177	1363	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1364	* @retval None
<>	161:2cc1468da177	1365	*/
<>	161:2cc1468da177	1366	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1367	{
<>	161:2cc1468da177	1368	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	161:2cc1468da177	1369	}
<>	161:2cc1468da177	1370
<>	161:2cc1468da177	1371	/**
<>	161:2cc1468da177	1372	* @brief Check if STOP detection interrupt is enabled or disabled.
<>	161:2cc1468da177	1373	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
<>	161:2cc1468da177	1374	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1375	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1376	*/
<>	161:2cc1468da177	1377	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1378	{
<>	161:2cc1468da177	1379	return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
<>	161:2cc1468da177	1380	}
<>	161:2cc1468da177	1381
<>	161:2cc1468da177	1382	/**
<>	161:2cc1468da177	1383	* @brief Enable Transfer Complete interrupt.
<>	161:2cc1468da177	1384	* @note Any of these events will generate interrupt :
<>	161:2cc1468da177	1385	* Transfer Complete (TC)
<>	161:2cc1468da177	1386	* Transfer Complete Reload (TCR)
<>	161:2cc1468da177	1387	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
<>	161:2cc1468da177	1388	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1389	* @retval None
<>	161:2cc1468da177	1390	*/
<>	161:2cc1468da177	1391	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1392	{
<>	161:2cc1468da177	1393	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	161:2cc1468da177	1394	}
<>	161:2cc1468da177	1395
<>	161:2cc1468da177	1396	/**
<>	161:2cc1468da177	1397	* @brief Disable Transfer Complete interrupt.
<>	161:2cc1468da177	1398	* @note Any of these events will generate interrupt :
<>	161:2cc1468da177	1399	* Transfer Complete (TC)
<>	161:2cc1468da177	1400	* Transfer Complete Reload (TCR)
<>	161:2cc1468da177	1401	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
<>	161:2cc1468da177	1402	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1403	* @retval None
<>	161:2cc1468da177	1404	*/
<>	161:2cc1468da177	1405	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1406	{
<>	161:2cc1468da177	1407	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	161:2cc1468da177	1408	}
<>	161:2cc1468da177	1409
<>	161:2cc1468da177	1410	/**
<>	161:2cc1468da177	1411	* @brief Check if Transfer Complete interrupt is enabled or disabled.
<>	161:2cc1468da177	1412	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
<>	161:2cc1468da177	1413	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1414	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1415	*/
<>	161:2cc1468da177	1416	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1417	{
<>	161:2cc1468da177	1418	return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
<>	161:2cc1468da177	1419	}
<>	161:2cc1468da177	1420
<>	161:2cc1468da177	1421	/**
<>	161:2cc1468da177	1422	* @brief Enable Error interrupts.
<>	161:2cc1468da177	1423	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1424	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1425	* @note Any of these errors will generate interrupt :
<>	161:2cc1468da177	1426	* Arbitration Loss (ARLO)
<>	161:2cc1468da177	1427	* Bus Error detection (BERR)
<>	161:2cc1468da177	1428	* Overrun/Underrun (OVR)
<>	161:2cc1468da177	1429	* SMBus Timeout detection (TIMEOUT)
<>	161:2cc1468da177	1430	* SMBus PEC error detection (PECERR)
<>	161:2cc1468da177	1431	* SMBus Alert pin event detection (ALERT)
<>	161:2cc1468da177	1432	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
<>	161:2cc1468da177	1433	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1434	* @retval None
<>	161:2cc1468da177	1435	*/
<>	161:2cc1468da177	1436	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1437	{
<>	161:2cc1468da177	1438	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	161:2cc1468da177	1439	}
<>	161:2cc1468da177	1440
<>	161:2cc1468da177	1441	/**
<>	161:2cc1468da177	1442	* @brief Disable Error interrupts.
<>	161:2cc1468da177	1443	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1444	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1445	* @note Any of these errors will generate interrupt :
<>	161:2cc1468da177	1446	* Arbitration Loss (ARLO)
<>	161:2cc1468da177	1447	* Bus Error detection (BERR)
<>	161:2cc1468da177	1448	* Overrun/Underrun (OVR)
<>	161:2cc1468da177	1449	* SMBus Timeout detection (TIMEOUT)
<>	161:2cc1468da177	1450	* SMBus PEC error detection (PECERR)
<>	161:2cc1468da177	1451	* SMBus Alert pin event detection (ALERT)
<>	161:2cc1468da177	1452	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
<>	161:2cc1468da177	1453	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1454	* @retval None
<>	161:2cc1468da177	1455	*/
<>	161:2cc1468da177	1456	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1457	{
<>	161:2cc1468da177	1458	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	161:2cc1468da177	1459	}
<>	161:2cc1468da177	1460
<>	161:2cc1468da177	1461	/**
<>	161:2cc1468da177	1462	* @brief Check if Error interrupts are enabled or disabled.
<>	161:2cc1468da177	1463	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
<>	161:2cc1468da177	1464	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1465	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1466	*/
<>	161:2cc1468da177	1467	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1468	{
<>	161:2cc1468da177	1469	return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
<>	161:2cc1468da177	1470	}
<>	161:2cc1468da177	1471
<>	161:2cc1468da177	1472	/**
<>	161:2cc1468da177	1473	* @}
<>	161:2cc1468da177	1474	*/
<>	161:2cc1468da177	1475
<>	161:2cc1468da177	1476	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
<>	161:2cc1468da177	1477	* @{
<>	161:2cc1468da177	1478	*/
<>	161:2cc1468da177	1479
<>	161:2cc1468da177	1480	/**
<>	161:2cc1468da177	1481	* @brief Indicate the status of Transmit data register empty flag.
<>	161:2cc1468da177	1482	* @note RESET: When next data is written in Transmit data register.
<>	161:2cc1468da177	1483	* SET: When Transmit data register is empty.
<>	161:2cc1468da177	1484	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
<>	161:2cc1468da177	1485	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1486	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1487	*/
<>	161:2cc1468da177	1488	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1489	{
<>	161:2cc1468da177	1490	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
<>	161:2cc1468da177	1491	}
<>	161:2cc1468da177	1492
<>	161:2cc1468da177	1493	/**
<>	161:2cc1468da177	1494	* @brief Indicate the status of Transmit interrupt flag.
<>	161:2cc1468da177	1495	* @note RESET: When next data is written in Transmit data register.
<>	161:2cc1468da177	1496	* SET: When Transmit data register is empty.
<>	161:2cc1468da177	1497	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
<>	161:2cc1468da177	1498	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1499	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1500	*/
<>	161:2cc1468da177	1501	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1502	{
<>	161:2cc1468da177	1503	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
<>	161:2cc1468da177	1504	}
<>	161:2cc1468da177	1505
<>	161:2cc1468da177	1506	/**
<>	161:2cc1468da177	1507	* @brief Indicate the status of Receive data register not empty flag.
<>	161:2cc1468da177	1508	* @note RESET: When Receive data register is read.
<>	161:2cc1468da177	1509	* SET: When the received data is copied in Receive data register.
<>	161:2cc1468da177	1510	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
<>	161:2cc1468da177	1511	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1512	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1513	*/
<>	161:2cc1468da177	1514	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1515	{
<>	161:2cc1468da177	1516	return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
<>	161:2cc1468da177	1517	}
<>	161:2cc1468da177	1518
<>	161:2cc1468da177	1519	/**
<>	161:2cc1468da177	1520	* @brief Indicate the status of Address matched flag (slave mode).
<>	161:2cc1468da177	1521	* @note RESET: Clear default value.
<>	161:2cc1468da177	1522	* SET: When the received slave address matched with one of the enabled slave address.
<>	161:2cc1468da177	1523	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
<>	161:2cc1468da177	1524	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1525	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1526	*/
<>	161:2cc1468da177	1527	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1528	{
<>	161:2cc1468da177	1529	return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
<>	161:2cc1468da177	1530	}
<>	161:2cc1468da177	1531
<>	161:2cc1468da177	1532	/**
<>	161:2cc1468da177	1533	* @brief Indicate the status of Not Acknowledge received flag.
<>	161:2cc1468da177	1534	* @note RESET: Clear default value.
<>	161:2cc1468da177	1535	* SET: When a NACK is received after a byte transmission.
<>	161:2cc1468da177	1536	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
<>	161:2cc1468da177	1537	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1538	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1539	*/
<>	161:2cc1468da177	1540	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1541	{
<>	161:2cc1468da177	1542	return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
<>	161:2cc1468da177	1543	}
<>	161:2cc1468da177	1544
<>	161:2cc1468da177	1545	/**
<>	161:2cc1468da177	1546	* @brief Indicate the status of Stop detection flag.
<>	161:2cc1468da177	1547	* @note RESET: Clear default value.
<>	161:2cc1468da177	1548	* SET: When a Stop condition is detected.
<>	161:2cc1468da177	1549	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
<>	161:2cc1468da177	1550	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1551	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1552	*/
<>	161:2cc1468da177	1553	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1554	{
<>	161:2cc1468da177	1555	return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
<>	161:2cc1468da177	1556	}
<>	161:2cc1468da177	1557
<>	161:2cc1468da177	1558	/**
<>	161:2cc1468da177	1559	* @brief Indicate the status of Transfer complete flag (master mode).
<>	161:2cc1468da177	1560	* @note RESET: Clear default value.
<>	161:2cc1468da177	1561	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
<>	161:2cc1468da177	1562	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
<>	161:2cc1468da177	1563	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1564	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1565	*/
<>	161:2cc1468da177	1566	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1567	{
<>	161:2cc1468da177	1568	return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
<>	161:2cc1468da177	1569	}
<>	161:2cc1468da177	1570
<>	161:2cc1468da177	1571	/**
<>	161:2cc1468da177	1572	* @brief Indicate the status of Transfer complete flag (master mode).
<>	161:2cc1468da177	1573	* @note RESET: Clear default value.
<>	161:2cc1468da177	1574	* SET: When RELOAD=1 and NBYTES date have been transferred.
<>	161:2cc1468da177	1575	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
<>	161:2cc1468da177	1576	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1577	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1578	*/
<>	161:2cc1468da177	1579	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1580	{
<>	161:2cc1468da177	1581	return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
<>	161:2cc1468da177	1582	}
<>	161:2cc1468da177	1583
<>	161:2cc1468da177	1584	/**
<>	161:2cc1468da177	1585	* @brief Indicate the status of Bus error flag.
<>	161:2cc1468da177	1586	* @note RESET: Clear default value.
<>	161:2cc1468da177	1587	* SET: When a misplaced Start or Stop condition is detected.
<>	161:2cc1468da177	1588	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
<>	161:2cc1468da177	1589	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1590	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1591	*/
<>	161:2cc1468da177	1592	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1593	{
<>	161:2cc1468da177	1594	return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
<>	161:2cc1468da177	1595	}
<>	161:2cc1468da177	1596
<>	161:2cc1468da177	1597	/**
<>	161:2cc1468da177	1598	* @brief Indicate the status of Arbitration lost flag.
<>	161:2cc1468da177	1599	* @note RESET: Clear default value.
<>	161:2cc1468da177	1600	* SET: When arbitration lost.
<>	161:2cc1468da177	1601	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
<>	161:2cc1468da177	1602	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1603	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1604	*/
<>	161:2cc1468da177	1605	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1606	{
<>	161:2cc1468da177	1607	return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
<>	161:2cc1468da177	1608	}
<>	161:2cc1468da177	1609
<>	161:2cc1468da177	1610	/**
<>	161:2cc1468da177	1611	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
<>	161:2cc1468da177	1612	* @note RESET: Clear default value.
<>	161:2cc1468da177	1613	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
<>	161:2cc1468da177	1614	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
<>	161:2cc1468da177	1615	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1616	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1617	*/
<>	161:2cc1468da177	1618	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1619	{
<>	161:2cc1468da177	1620	return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
<>	161:2cc1468da177	1621	}
<>	161:2cc1468da177	1622
<>	161:2cc1468da177	1623	/**
<>	161:2cc1468da177	1624	* @brief Indicate the status of SMBus PEC error flag in reception.
<>	161:2cc1468da177	1625	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1626	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1627	* @note RESET: Clear default value.
<>	161:2cc1468da177	1628	* SET: When the received PEC does not match with the PEC register content.
<>	161:2cc1468da177	1629	* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
<>	161:2cc1468da177	1630	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1631	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1632	*/
<>	161:2cc1468da177	1633	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1634	{
<>	161:2cc1468da177	1635	return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
<>	161:2cc1468da177	1636	}
<>	161:2cc1468da177	1637
<>	161:2cc1468da177	1638	/**
<>	161:2cc1468da177	1639	* @brief Indicate the status of SMBus Timeout detection flag.
<>	161:2cc1468da177	1640	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1641	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1642	* @note RESET: Clear default value.
<>	161:2cc1468da177	1643	* SET: When a timeout or extended clock timeout occurs.
<>	161:2cc1468da177	1644	* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
<>	161:2cc1468da177	1645	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1646	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1647	*/
<>	161:2cc1468da177	1648	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1649	{
<>	161:2cc1468da177	1650	return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
<>	161:2cc1468da177	1651	}
<>	161:2cc1468da177	1652
<>	161:2cc1468da177	1653	/**
<>	161:2cc1468da177	1654	* @brief Indicate the status of SMBus alert flag.
<>	161:2cc1468da177	1655	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1656	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1657	* @note RESET: Clear default value.
<>	161:2cc1468da177	1658	* SET: When SMBus host configuration, SMBus alert enabled and
<>	161:2cc1468da177	1659	* a falling edge event occurs on SMBA pin.
<>	161:2cc1468da177	1660	* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
<>	161:2cc1468da177	1661	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1662	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1663	*/
<>	161:2cc1468da177	1664	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1665	{
<>	161:2cc1468da177	1666	return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
<>	161:2cc1468da177	1667	}
<>	161:2cc1468da177	1668
<>	161:2cc1468da177	1669	/**
<>	161:2cc1468da177	1670	* @brief Indicate the status of Bus Busy flag.
<>	161:2cc1468da177	1671	* @note RESET: Clear default value.
<>	161:2cc1468da177	1672	* SET: When a Start condition is detected.
<>	161:2cc1468da177	1673	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
<>	161:2cc1468da177	1674	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1675	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1676	*/
<>	161:2cc1468da177	1677	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1678	{
<>	161:2cc1468da177	1679	return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
<>	161:2cc1468da177	1680	}
<>	161:2cc1468da177	1681
<>	161:2cc1468da177	1682	/**
<>	161:2cc1468da177	1683	* @brief Clear Address Matched flag.
<>	161:2cc1468da177	1684	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
<>	161:2cc1468da177	1685	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1686	* @retval None
<>	161:2cc1468da177	1687	*/
<>	161:2cc1468da177	1688	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1689	{
<>	161:2cc1468da177	1690	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
<>	161:2cc1468da177	1691	}
<>	161:2cc1468da177	1692
<>	161:2cc1468da177	1693	/**
<>	161:2cc1468da177	1694	* @brief Clear Not Acknowledge flag.
<>	161:2cc1468da177	1695	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
<>	161:2cc1468da177	1696	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1697	* @retval None
<>	161:2cc1468da177	1698	*/
<>	161:2cc1468da177	1699	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1700	{
<>	161:2cc1468da177	1701	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
<>	161:2cc1468da177	1702	}
<>	161:2cc1468da177	1703
<>	161:2cc1468da177	1704	/**
<>	161:2cc1468da177	1705	* @brief Clear Stop detection flag.
<>	161:2cc1468da177	1706	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
<>	161:2cc1468da177	1707	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1708	* @retval None
<>	161:2cc1468da177	1709	*/
<>	161:2cc1468da177	1710	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1711	{
<>	161:2cc1468da177	1712	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
<>	161:2cc1468da177	1713	}
<>	161:2cc1468da177	1714
<>	161:2cc1468da177	1715	/**
<>	161:2cc1468da177	1716	* @brief Clear Transmit data register empty flag (TXE).
<>	161:2cc1468da177	1717	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
<>	161:2cc1468da177	1718	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
<>	161:2cc1468da177	1719	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1720	* @retval None
<>	161:2cc1468da177	1721	*/
<>	161:2cc1468da177	1722	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1723	{
<>	161:2cc1468da177	1724	WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
<>	161:2cc1468da177	1725	}
<>	161:2cc1468da177	1726
<>	161:2cc1468da177	1727	/**
<>	161:2cc1468da177	1728	* @brief Clear Bus error flag.
<>	161:2cc1468da177	1729	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
<>	161:2cc1468da177	1730	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1731	* @retval None
<>	161:2cc1468da177	1732	*/
<>	161:2cc1468da177	1733	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1734	{
<>	161:2cc1468da177	1735	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
<>	161:2cc1468da177	1736	}
<>	161:2cc1468da177	1737
<>	161:2cc1468da177	1738	/**
<>	161:2cc1468da177	1739	* @brief Clear Arbitration lost flag.
<>	161:2cc1468da177	1740	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
<>	161:2cc1468da177	1741	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1742	* @retval None
<>	161:2cc1468da177	1743	*/
<>	161:2cc1468da177	1744	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1745	{
<>	161:2cc1468da177	1746	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
<>	161:2cc1468da177	1747	}
<>	161:2cc1468da177	1748
<>	161:2cc1468da177	1749	/**
<>	161:2cc1468da177	1750	* @brief Clear Overrun/Underrun flag.
<>	161:2cc1468da177	1751	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
<>	161:2cc1468da177	1752	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1753	* @retval None
<>	161:2cc1468da177	1754	*/
<>	161:2cc1468da177	1755	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1756	{
<>	161:2cc1468da177	1757	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
<>	161:2cc1468da177	1758	}
<>	161:2cc1468da177	1759
<>	161:2cc1468da177	1760	/**
<>	161:2cc1468da177	1761	* @brief Clear SMBus PEC error flag.
<>	161:2cc1468da177	1762	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1763	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1764	* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
<>	161:2cc1468da177	1765	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1766	* @retval None
<>	161:2cc1468da177	1767	*/
<>	161:2cc1468da177	1768	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1769	{
<>	161:2cc1468da177	1770	SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
<>	161:2cc1468da177	1771	}
<>	161:2cc1468da177	1772
<>	161:2cc1468da177	1773	/**
<>	161:2cc1468da177	1774	* @brief Clear SMBus Timeout detection flag.
<>	161:2cc1468da177	1775	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1776	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1777	* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
<>	161:2cc1468da177	1778	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1779	* @retval None
<>	161:2cc1468da177	1780	*/
<>	161:2cc1468da177	1781	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1782	{
<>	161:2cc1468da177	1783	SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
<>	161:2cc1468da177	1784	}
<>	161:2cc1468da177	1785
<>	161:2cc1468da177	1786	/**
<>	161:2cc1468da177	1787	* @brief Clear SMBus Alert flag.
<>	161:2cc1468da177	1788	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	1789	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	1790	* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
<>	161:2cc1468da177	1791	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1792	* @retval None
<>	161:2cc1468da177	1793	*/
<>	161:2cc1468da177	1794	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1795	{
<>	161:2cc1468da177	1796	SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
<>	161:2cc1468da177	1797	}
<>	161:2cc1468da177	1798
<>	161:2cc1468da177	1799	/**
<>	161:2cc1468da177	1800	* @}
<>	161:2cc1468da177	1801	*/
<>	161:2cc1468da177	1802
<>	161:2cc1468da177	1803	/** @defgroup I2C_LL_EF_Data_Management Data_Management
<>	161:2cc1468da177	1804	* @{
<>	161:2cc1468da177	1805	*/
<>	161:2cc1468da177	1806
<>	161:2cc1468da177	1807	/**
<>	161:2cc1468da177	1808	* @brief Enable automatic STOP condition generation (master mode).
<>	161:2cc1468da177	1809	* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
<>	161:2cc1468da177	1810	* This bit has no effect in slave mode or when RELOAD bit is set.
<>	161:2cc1468da177	1811	* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
<>	161:2cc1468da177	1812	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1813	* @retval None
<>	161:2cc1468da177	1814	*/
<>	161:2cc1468da177	1815	__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1816	{
<>	161:2cc1468da177	1817	SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	161:2cc1468da177	1818	}
<>	161:2cc1468da177	1819
<>	161:2cc1468da177	1820	/**
<>	161:2cc1468da177	1821	* @brief Disable automatic STOP condition generation (master mode).
<>	161:2cc1468da177	1822	* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
<>	161:2cc1468da177	1823	* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
<>	161:2cc1468da177	1824	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1825	* @retval None
<>	161:2cc1468da177	1826	*/
<>	161:2cc1468da177	1827	__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1828	{
<>	161:2cc1468da177	1829	CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	161:2cc1468da177	1830	}
<>	161:2cc1468da177	1831
<>	161:2cc1468da177	1832	/**
<>	161:2cc1468da177	1833	* @brief Check if automatic STOP condition is enabled or disabled.
<>	161:2cc1468da177	1834	* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
<>	161:2cc1468da177	1835	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1836	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1837	*/
<>	161:2cc1468da177	1838	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1839	{
<>	161:2cc1468da177	1840	return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
<>	161:2cc1468da177	1841	}
<>	161:2cc1468da177	1842
<>	161:2cc1468da177	1843	/**
<>	161:2cc1468da177	1844	* @brief Enable reload mode (master mode).
<>	161:2cc1468da177	1845	* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
<>	161:2cc1468da177	1846	* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
<>	161:2cc1468da177	1847	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1848	* @retval None
<>	161:2cc1468da177	1849	*/
<>	161:2cc1468da177	1850	__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1851	{
<>	161:2cc1468da177	1852	SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	161:2cc1468da177	1853	}
<>	161:2cc1468da177	1854
<>	161:2cc1468da177	1855	/**
<>	161:2cc1468da177	1856	* @brief Disable reload mode (master mode).
<>	161:2cc1468da177	1857	* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
<>	161:2cc1468da177	1858	* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
<>	161:2cc1468da177	1859	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1860	* @retval None
<>	161:2cc1468da177	1861	*/
<>	161:2cc1468da177	1862	__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1863	{
<>	161:2cc1468da177	1864	CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	161:2cc1468da177	1865	}
<>	161:2cc1468da177	1866
<>	161:2cc1468da177	1867	/**
<>	161:2cc1468da177	1868	* @brief Check if reload mode is enabled or disabled.
<>	161:2cc1468da177	1869	* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
<>	161:2cc1468da177	1870	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1871	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1872	*/
<>	161:2cc1468da177	1873	__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1874	{
<>	161:2cc1468da177	1875	return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
<>	161:2cc1468da177	1876	}
<>	161:2cc1468da177	1877
<>	161:2cc1468da177	1878	/**
<>	161:2cc1468da177	1879	* @brief Configure the number of bytes for transfer.
<>	161:2cc1468da177	1880	* @note Changing these bits when START bit is set is not allowed.
<>	161:2cc1468da177	1881	* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
<>	161:2cc1468da177	1882	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1883	* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
<>	161:2cc1468da177	1884	* @retval None
<>	161:2cc1468da177	1885	*/
<>	161:2cc1468da177	1886	__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
<>	161:2cc1468da177	1887	{
<>	161:2cc1468da177	1888	MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
<>	161:2cc1468da177	1889	}
<>	161:2cc1468da177	1890
<>	161:2cc1468da177	1891	/**
<>	161:2cc1468da177	1892	* @brief Get the number of bytes configured for transfer.
<>	161:2cc1468da177	1893	* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
<>	161:2cc1468da177	1894	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1895	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
<>	161:2cc1468da177	1896	*/
<>	161:2cc1468da177	1897	__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1898	{
<>	161:2cc1468da177	1899	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
<>	161:2cc1468da177	1900	}
<>	161:2cc1468da177	1901
<>	161:2cc1468da177	1902	/**
<>	161:2cc1468da177	1903	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	161:2cc1468da177	1904	* @note Usage in Slave mode only.
<>	161:2cc1468da177	1905	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
<>	161:2cc1468da177	1906	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1907	* @param TypeAcknowledge This parameter can be one of the following values:
<>	161:2cc1468da177	1908	* @arg @ref LL_I2C_ACK
<>	161:2cc1468da177	1909	* @arg @ref LL_I2C_NACK
<>	161:2cc1468da177	1910	* @retval None
<>	161:2cc1468da177	1911	*/
<>	161:2cc1468da177	1912	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
<>	161:2cc1468da177	1913	{
<>	161:2cc1468da177	1914	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
<>	161:2cc1468da177	1915	}
<>	161:2cc1468da177	1916
<>	161:2cc1468da177	1917	/**
<>	161:2cc1468da177	1918	* @brief Generate a START or RESTART condition
<>	161:2cc1468da177	1919	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
<>	161:2cc1468da177	1920	* This action has no effect when RELOAD is set.
<>	161:2cc1468da177	1921	* @rmtoll CR2 START LL_I2C_GenerateStartCondition
<>	161:2cc1468da177	1922	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1923	* @retval None
<>	161:2cc1468da177	1924	*/
<>	161:2cc1468da177	1925	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1926	{
<>	161:2cc1468da177	1927	SET_BIT(I2Cx->CR2, I2C_CR2_START);
<>	161:2cc1468da177	1928	}
<>	161:2cc1468da177	1929
<>	161:2cc1468da177	1930	/**
<>	161:2cc1468da177	1931	* @brief Generate a STOP condition after the current byte transfer (master mode).
<>	161:2cc1468da177	1932	* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
<>	161:2cc1468da177	1933	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1934	* @retval None
<>	161:2cc1468da177	1935	*/
<>	161:2cc1468da177	1936	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1937	{
<>	161:2cc1468da177	1938	SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
<>	161:2cc1468da177	1939	}
<>	161:2cc1468da177	1940
<>	161:2cc1468da177	1941	/**
<>	161:2cc1468da177	1942	* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
<>	161:2cc1468da177	1943	* @note The master sends the complete 10bit slave address read sequence :
<>	161:2cc1468da177	1944	* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
<>	161:2cc1468da177	1945	* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
<>	161:2cc1468da177	1946	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1947	* @retval None
<>	161:2cc1468da177	1948	*/
<>	161:2cc1468da177	1949	__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1950	{
<>	161:2cc1468da177	1951	CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	161:2cc1468da177	1952	}
<>	161:2cc1468da177	1953
<>	161:2cc1468da177	1954	/**
<>	161:2cc1468da177	1955	* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
<>	161:2cc1468da177	1956	* @note The master only sends the first 7 bits of 10bit address in Read direction.
<>	161:2cc1468da177	1957	* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
<>	161:2cc1468da177	1958	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1959	* @retval None
<>	161:2cc1468da177	1960	*/
<>	161:2cc1468da177	1961	__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1962	{
<>	161:2cc1468da177	1963	SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	161:2cc1468da177	1964	}
<>	161:2cc1468da177	1965
<>	161:2cc1468da177	1966	/**
<>	161:2cc1468da177	1967	* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
<>	161:2cc1468da177	1968	* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
<>	161:2cc1468da177	1969	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1970	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	1971	*/
<>	161:2cc1468da177	1972	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	1973	{
<>	161:2cc1468da177	1974	return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
<>	161:2cc1468da177	1975	}
<>	161:2cc1468da177	1976
<>	161:2cc1468da177	1977	/**
<>	161:2cc1468da177	1978	* @brief Configure the transfer direction (master mode).
<>	161:2cc1468da177	1979	* @note Changing these bits when START bit is set is not allowed.
<>	161:2cc1468da177	1980	* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
<>	161:2cc1468da177	1981	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1982	* @param TransferRequest This parameter can be one of the following values:
<>	161:2cc1468da177	1983	* @arg @ref LL_I2C_REQUEST_WRITE
<>	161:2cc1468da177	1984	* @arg @ref LL_I2C_REQUEST_READ
<>	161:2cc1468da177	1985	* @retval None
<>	161:2cc1468da177	1986	*/
<>	161:2cc1468da177	1987	__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
<>	161:2cc1468da177	1988	{
<>	161:2cc1468da177	1989	MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
<>	161:2cc1468da177	1990	}
<>	161:2cc1468da177	1991
<>	161:2cc1468da177	1992	/**
<>	161:2cc1468da177	1993	* @brief Get the transfer direction requested (master mode).
<>	161:2cc1468da177	1994	* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
<>	161:2cc1468da177	1995	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	1996	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	1997	* @arg @ref LL_I2C_REQUEST_WRITE
<>	161:2cc1468da177	1998	* @arg @ref LL_I2C_REQUEST_READ
<>	161:2cc1468da177	1999	*/
<>	161:2cc1468da177	2000	__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2001	{
<>	161:2cc1468da177	2002	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
<>	161:2cc1468da177	2003	}
<>	161:2cc1468da177	2004
<>	161:2cc1468da177	2005	/**
<>	161:2cc1468da177	2006	* @brief Configure the slave address for transfer (master mode).
<>	161:2cc1468da177	2007	* @note Changing these bits when START bit is set is not allowed.
<>	161:2cc1468da177	2008	* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
<>	161:2cc1468da177	2009	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2010	* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
<>	161:2cc1468da177	2011	* @retval None
<>	161:2cc1468da177	2012	*/
<>	161:2cc1468da177	2013	__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
<>	161:2cc1468da177	2014	{
<>	161:2cc1468da177	2015	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
<>	161:2cc1468da177	2016	}
<>	161:2cc1468da177	2017
<>	161:2cc1468da177	2018	/**
<>	161:2cc1468da177	2019	* @brief Get the slave address programmed for transfer.
<>	161:2cc1468da177	2020	* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
<>	161:2cc1468da177	2021	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2022	* @retval Value between Min_Data=0x0 and Max_Data=0x3F
<>	161:2cc1468da177	2023	*/
<>	161:2cc1468da177	2024	__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2025	{
<>	161:2cc1468da177	2026	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
<>	161:2cc1468da177	2027	}
<>	161:2cc1468da177	2028
<>	161:2cc1468da177	2029	/**
<>	161:2cc1468da177	2030	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
<>	161:2cc1468da177	2031	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2032	* CR2 ADD10 LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2033	* CR2 RD_WRN LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2034	* CR2 START LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2035	* CR2 STOP LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2036	* CR2 RELOAD LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2037	* CR2 NBYTES LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2038	* CR2 AUTOEND LL_I2C_HandleTransfer\n
<>	161:2cc1468da177	2039	* CR2 HEAD10R LL_I2C_HandleTransfer
<>	161:2cc1468da177	2040	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2041	* @param SlaveAddr Specifies the slave address to be programmed.
<>	161:2cc1468da177	2042	* @param SlaveAddrSize This parameter can be one of the following values:
<>	161:2cc1468da177	2043	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
<>	161:2cc1468da177	2044	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
<>	161:2cc1468da177	2045	* @param TransferSize Specifies the number of bytes to be programmed.
<>	161:2cc1468da177	2046	* This parameter must be a value between Min_Data=0 and Max_Data=255.
<>	161:2cc1468da177	2047	* @param EndMode This parameter can be one of the following values:
<>	161:2cc1468da177	2048	* @arg @ref LL_I2C_MODE_RELOAD
<>	161:2cc1468da177	2049	* @arg @ref LL_I2C_MODE_AUTOEND
<>	161:2cc1468da177	2050	* @arg @ref LL_I2C_MODE_SOFTEND
<>	161:2cc1468da177	2051	* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
<>	161:2cc1468da177	2052	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
<>	161:2cc1468da177	2053	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
<>	161:2cc1468da177	2054	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
<>	161:2cc1468da177	2055	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
<>	161:2cc1468da177	2056	* @param Request This parameter can be one of the following values:
<>	161:2cc1468da177	2057	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
<>	161:2cc1468da177	2058	* @arg @ref LL_I2C_GENERATE_STOP
<>	161:2cc1468da177	2059	* @arg @ref LL_I2C_GENERATE_START_READ
<>	161:2cc1468da177	2060	* @arg @ref LL_I2C_GENERATE_START_WRITE
<>	161:2cc1468da177	2061	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
<>	161:2cc1468da177	2062	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
<>	161:2cc1468da177	2063	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
<>	161:2cc1468da177	2064	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
<>	161:2cc1468da177	2065	* @retval None
<>	161:2cc1468da177	2066	*/
<>	161:2cc1468da177	2067	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
<>	161:2cc1468da177	2068	uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
<>	161:2cc1468da177	2069	{
AnnaBridge	182:a56a73fd2a6f	2070	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \|
<>	161:2cc1468da177	2071	I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
<>	161:2cc1468da177	2072	SlaveAddr \| SlaveAddrSize \| TransferSize << I2C_CR2_NBYTES_Pos \| EndMode \| Request);
<>	161:2cc1468da177	2073	}
<>	161:2cc1468da177	2074
<>	161:2cc1468da177	2075	/**
<>	161:2cc1468da177	2076	* @brief Indicate the value of transfer direction (slave mode).
<>	161:2cc1468da177	2077	* @note RESET: Write transfer, Slave enters in receiver mode.
<>	161:2cc1468da177	2078	* SET: Read transfer, Slave enters in transmitter mode.
<>	161:2cc1468da177	2079	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
<>	161:2cc1468da177	2080	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2081	* @retval Returned value can be one of the following values:
<>	161:2cc1468da177	2082	* @arg @ref LL_I2C_DIRECTION_WRITE
<>	161:2cc1468da177	2083	* @arg @ref LL_I2C_DIRECTION_READ
<>	161:2cc1468da177	2084	*/
<>	161:2cc1468da177	2085	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2086	{
<>	161:2cc1468da177	2087	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
<>	161:2cc1468da177	2088	}
<>	161:2cc1468da177	2089
<>	161:2cc1468da177	2090	/**
<>	161:2cc1468da177	2091	* @brief Return the slave matched address.
<>	161:2cc1468da177	2092	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
<>	161:2cc1468da177	2093	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2094	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	161:2cc1468da177	2095	*/
<>	161:2cc1468da177	2096	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2097	{
<>	161:2cc1468da177	2098	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
<>	161:2cc1468da177	2099	}
<>	161:2cc1468da177	2100
<>	161:2cc1468da177	2101	/**
<>	161:2cc1468da177	2102	* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	161:2cc1468da177	2103	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	2104	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	2105	* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
<>	161:2cc1468da177	2106	* This bit has no effect when RELOAD bit is set.
<>	161:2cc1468da177	2107	* This bit has no effect in device mode when SBC bit is not set.
<>	161:2cc1468da177	2108	* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
<>	161:2cc1468da177	2109	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2110	* @retval None
<>	161:2cc1468da177	2111	*/
<>	161:2cc1468da177	2112	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2113	{
<>	161:2cc1468da177	2114	SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
<>	161:2cc1468da177	2115	}
<>	161:2cc1468da177	2116
<>	161:2cc1468da177	2117	/**
<>	161:2cc1468da177	2118	* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
<>	161:2cc1468da177	2119	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	2120	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	2121	* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
<>	161:2cc1468da177	2122	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2123	* @retval State of bit (1 or 0).
<>	161:2cc1468da177	2124	*/
<>	161:2cc1468da177	2125	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2126	{
<>	161:2cc1468da177	2127	return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
<>	161:2cc1468da177	2128	}
<>	161:2cc1468da177	2129
<>	161:2cc1468da177	2130	/**
<>	161:2cc1468da177	2131	* @brief Get the SMBus Packet Error byte calculated.
<>	161:2cc1468da177	2132	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	161:2cc1468da177	2133	* SMBus feature is supported by the I2Cx Instance.
<>	161:2cc1468da177	2134	* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
<>	161:2cc1468da177	2135	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2136	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	2137	*/
<>	161:2cc1468da177	2138	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2139	{
<>	161:2cc1468da177	2140	return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
<>	161:2cc1468da177	2141	}
<>	161:2cc1468da177	2142
<>	161:2cc1468da177	2143	/**
<>	161:2cc1468da177	2144	* @brief Read Receive Data register.
<>	161:2cc1468da177	2145	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
<>	161:2cc1468da177	2146	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2147	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	2148	*/
<>	161:2cc1468da177	2149	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
<>	161:2cc1468da177	2150	{
<>	161:2cc1468da177	2151	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
<>	161:2cc1468da177	2152	}
<>	161:2cc1468da177	2153
<>	161:2cc1468da177	2154	/**
<>	161:2cc1468da177	2155	* @brief Write in Transmit Data Register .
<>	161:2cc1468da177	2156	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
<>	161:2cc1468da177	2157	* @param I2Cx I2C Instance.
<>	161:2cc1468da177	2158	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<>	161:2cc1468da177	2159	* @retval None
<>	161:2cc1468da177	2160	*/
<>	161:2cc1468da177	2161	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
<>	161:2cc1468da177	2162	{
<>	161:2cc1468da177	2163	WRITE_REG(I2Cx->TXDR, Data);
<>	161:2cc1468da177	2164	}
<>	161:2cc1468da177	2165
<>	161:2cc1468da177	2166	/**
<>	161:2cc1468da177	2167	* @}
<>	161:2cc1468da177	2168	*/
<>	161:2cc1468da177	2169
<>	161:2cc1468da177	2170	#if defined(USE_FULL_LL_DRIVER)
<>	161:2cc1468da177	2171	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
<>	161:2cc1468da177	2172	* @{
<>	161:2cc1468da177	2173	*/
<>	161:2cc1468da177	2174
<>	161:2cc1468da177	2175	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
<>	161:2cc1468da177	2176	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
<>	161:2cc1468da177	2177	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
<>	161:2cc1468da177	2178
<>	161:2cc1468da177	2179
<>	161:2cc1468da177	2180	/**
<>	161:2cc1468da177	2181	* @}
<>	161:2cc1468da177	2182	*/
<>	161:2cc1468da177	2183	#endif /* USE_FULL_LL_DRIVER */
<>	161:2cc1468da177	2184
<>	161:2cc1468da177	2185	/**
<>	161:2cc1468da177	2186	* @}
<>	161:2cc1468da177	2187	*/
<>	161:2cc1468da177	2188
<>	161:2cc1468da177	2189	/**
<>	161:2cc1468da177	2190	* @}
<>	161:2cc1468da177	2191	*/
<>	161:2cc1468da177	2192
<>	161:2cc1468da177	2193	#endif /* I2C1 \|\| I2C2 \|\| I2C3 \|\| I2C4 */
<>	161:2cc1468da177	2194
<>	161:2cc1468da177	2195	/**
<>	161:2cc1468da177	2196	* @}
<>	161:2cc1468da177	2197	*/
<>	161:2cc1468da177	2198
<>	161:2cc1468da177	2199	#ifdef __cplusplus
<>	161:2cc1468da177	2200	}
<>	161:2cc1468da177	2201	#endif
<>	161:2cc1468da177	2202
<>	161:2cc1468da177	2203	#endif /* __STM32F7xx_LL_I2C_H */
<>	161:2cc1468da177	2204
<>	161:2cc1468da177	2205	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/