mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
19:112740acecfa
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f4xx_hal_rcc.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.2
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief Header file of RCC HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F4xx_HAL_RCC_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F4xx_HAL_RCC_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f4xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /* Include RCC HAL Extended module */
bogdanm 0:9b334a45a8ff 50 /* (include on top of file since RCC structures are defined in extended file) */
bogdanm 0:9b334a45a8ff 51 #include "stm32f4xx_hal_rcc_ex.h"
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /** @addtogroup RCC
bogdanm 0:9b334a45a8ff 58 * @{
bogdanm 0:9b334a45a8ff 59 */
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 62 /** @defgroup RCC_Exported_Types RCC Exported Types
bogdanm 0:9b334a45a8ff 63 * @{
bogdanm 0:9b334a45a8ff 64 */
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 /**
bogdanm 0:9b334a45a8ff 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69 typedef struct
bogdanm 0:9b334a45a8ff 70 {
bogdanm 0:9b334a45a8ff 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 0:9b334a45a8ff 72 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 0:9b334a45a8ff 75 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 0:9b334a45a8ff 78 This parameter can be a value of @ref RCC_LSE_Config */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 0:9b334a45a8ff 81 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm 0:9b334a45a8ff 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 0:9b334a45a8ff 87 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 }RCC_OscInitTypeDef;
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /**
bogdanm 0:9b334a45a8ff 94 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96 typedef struct
bogdanm 0:9b334a45a8ff 97 {
bogdanm 0:9b334a45a8ff 98 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 0:9b334a45a8ff 99 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 0:9b334a45a8ff 102 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 0:9b334a45a8ff 105 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 0:9b334a45a8ff 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 0:9b334a45a8ff 111 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 }RCC_ClkInitTypeDef;
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 /**
bogdanm 0:9b334a45a8ff 116 * @}
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 120 /** @defgroup RCC_Exported_Constants RCC Exported Constants
bogdanm 0:9b334a45a8ff 121 * @{
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /** @defgroup RCC_Oscillator_Type Oscillator Type
bogdanm 0:9b334a45a8ff 125 * @{
bogdanm 0:9b334a45a8ff 126 */
bogdanm 0:9b334a45a8ff 127 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 128 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 129 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 130 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 131 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 132 /**
bogdanm 0:9b334a45a8ff 133 * @}
bogdanm 0:9b334a45a8ff 134 */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /** @defgroup RCC_HSE_Config HSE Config
bogdanm 0:9b334a45a8ff 137 * @{
bogdanm 0:9b334a45a8ff 138 */
bogdanm 0:9b334a45a8ff 139 #define RCC_HSE_OFF ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 140 #define RCC_HSE_ON ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 141 #define RCC_HSE_BYPASS ((uint8_t)0x05)
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @}
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /** @defgroup RCC_LSE_Config LSE Config
bogdanm 0:9b334a45a8ff 147 * @{
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149 #define RCC_LSE_OFF ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 150 #define RCC_LSE_ON ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 151 #define RCC_LSE_BYPASS ((uint8_t)0x05)
bogdanm 0:9b334a45a8ff 152 /**
bogdanm 0:9b334a45a8ff 153 * @}
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /** @defgroup RCC_HSI_Config HSI Config
bogdanm 0:9b334a45a8ff 157 * @{
bogdanm 0:9b334a45a8ff 158 */
bogdanm 0:9b334a45a8ff 159 #define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 160 #define RCC_HSI_ON ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 161 /**
bogdanm 0:9b334a45a8ff 162 * @}
bogdanm 0:9b334a45a8ff 163 */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /** @defgroup RCC_LSI_Config LSI Config
bogdanm 0:9b334a45a8ff 166 * @{
bogdanm 0:9b334a45a8ff 167 */
bogdanm 0:9b334a45a8ff 168 #define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 169 #define RCC_LSI_ON ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 170 /**
bogdanm 0:9b334a45a8ff 171 * @}
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /** @defgroup RCC_PLL_Config PLL Config
bogdanm 0:9b334a45a8ff 175 * @{
bogdanm 0:9b334a45a8ff 176 */
bogdanm 0:9b334a45a8ff 177 #define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm 0:9b334a45a8ff 178 #define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 179 #define RCC_PLL_ON ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 180 /**
bogdanm 0:9b334a45a8ff 181 * @}
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
bogdanm 0:9b334a45a8ff 185 * @{
bogdanm 0:9b334a45a8ff 186 */
bogdanm 0:9b334a45a8ff 187 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 188 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 189 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
bogdanm 0:9b334a45a8ff 190 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 191 /**
bogdanm 0:9b334a45a8ff 192 * @}
bogdanm 0:9b334a45a8ff 193 */
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
bogdanm 0:9b334a45a8ff 196 * @{
bogdanm 0:9b334a45a8ff 197 */
bogdanm 0:9b334a45a8ff 198 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
bogdanm 0:9b334a45a8ff 199 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
bogdanm 0:9b334a45a8ff 200 /**
bogdanm 0:9b334a45a8ff 201 * @}
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /** @defgroup RCC_System_Clock_Type System Clock Type
bogdanm 0:9b334a45a8ff 205 * @{
bogdanm 0:9b334a45a8ff 206 */
bogdanm 0:9b334a45a8ff 207 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 208 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm 0:9b334a45a8ff 209 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm 0:9b334a45a8ff 210 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm 0:9b334a45a8ff 211 /**
bogdanm 0:9b334a45a8ff 212 * @}
bogdanm 0:9b334a45a8ff 213 */
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /** @defgroup RCC_System_Clock_Source System Clock Source
bogdanm 0:9b334a45a8ff 216 * @{
bogdanm 0:9b334a45a8ff 217 */
bogdanm 0:9b334a45a8ff 218 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 0:9b334a45a8ff 219 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 0:9b334a45a8ff 220 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm 0:9b334a45a8ff 221 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
bogdanm 0:9b334a45a8ff 222 /**
bogdanm 0:9b334a45a8ff 223 * @}
bogdanm 0:9b334a45a8ff 224 */
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
bogdanm 0:9b334a45a8ff 227 * @{
bogdanm 0:9b334a45a8ff 228 */
bogdanm 0:9b334a45a8ff 229 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
bogdanm 0:9b334a45a8ff 230 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
bogdanm 0:9b334a45a8ff 231 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
bogdanm 0:9b334a45a8ff 232 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
bogdanm 0:9b334a45a8ff 233 /**
bogdanm 0:9b334a45a8ff 234 * @}
bogdanm 0:9b334a45a8ff 235 */
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
bogdanm 0:9b334a45a8ff 238 * @{
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 0:9b334a45a8ff 241 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 0:9b334a45a8ff 242 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 0:9b334a45a8ff 243 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 0:9b334a45a8ff 244 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 0:9b334a45a8ff 245 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 0:9b334a45a8ff 246 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 0:9b334a45a8ff 247 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 0:9b334a45a8ff 248 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 0:9b334a45a8ff 249 /**
bogdanm 0:9b334a45a8ff 250 * @}
bogdanm 0:9b334a45a8ff 251 */
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
bogdanm 0:9b334a45a8ff 254 * @{
bogdanm 0:9b334a45a8ff 255 */
bogdanm 0:9b334a45a8ff 256 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 0:9b334a45a8ff 257 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 0:9b334a45a8ff 258 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 0:9b334a45a8ff 259 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 0:9b334a45a8ff 260 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 0:9b334a45a8ff 261 /**
bogdanm 0:9b334a45a8ff 262 * @}
bogdanm 0:9b334a45a8ff 263 */
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
bogdanm 0:9b334a45a8ff 266 * @{
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
bogdanm 0:9b334a45a8ff 269 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
bogdanm 0:9b334a45a8ff 270 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
bogdanm 0:9b334a45a8ff 271 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
bogdanm 0:9b334a45a8ff 272 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
bogdanm 0:9b334a45a8ff 273 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
bogdanm 0:9b334a45a8ff 274 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
bogdanm 0:9b334a45a8ff 275 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
bogdanm 0:9b334a45a8ff 276 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
bogdanm 0:9b334a45a8ff 277 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
bogdanm 0:9b334a45a8ff 278 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
bogdanm 0:9b334a45a8ff 279 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
bogdanm 0:9b334a45a8ff 280 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
bogdanm 0:9b334a45a8ff 281 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
bogdanm 0:9b334a45a8ff 282 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
bogdanm 0:9b334a45a8ff 283 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
bogdanm 0:9b334a45a8ff 284 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
bogdanm 0:9b334a45a8ff 285 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
bogdanm 0:9b334a45a8ff 286 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
bogdanm 0:9b334a45a8ff 287 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
bogdanm 0:9b334a45a8ff 288 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
bogdanm 0:9b334a45a8ff 289 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
bogdanm 0:9b334a45a8ff 290 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
bogdanm 0:9b334a45a8ff 291 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
bogdanm 0:9b334a45a8ff 292 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
bogdanm 0:9b334a45a8ff 293 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
bogdanm 0:9b334a45a8ff 294 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
bogdanm 0:9b334a45a8ff 295 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
bogdanm 0:9b334a45a8ff 296 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
bogdanm 0:9b334a45a8ff 297 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
bogdanm 0:9b334a45a8ff 298 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
bogdanm 0:9b334a45a8ff 299 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
bogdanm 0:9b334a45a8ff 300 /**
bogdanm 0:9b334a45a8ff 301 * @}
bogdanm 0:9b334a45a8ff 302 */
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /** @defgroup RCC_I2S_Clock_Source I2S Clock Source
bogdanm 0:9b334a45a8ff 305 * @{
bogdanm 0:9b334a45a8ff 306 */
bogdanm 0:9b334a45a8ff 307 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 308 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 309 /**
bogdanm 0:9b334a45a8ff 310 * @}
bogdanm 0:9b334a45a8ff 311 */
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 /** @defgroup RCC_MCO_Index MCO Index
bogdanm 0:9b334a45a8ff 314 * @{
bogdanm 0:9b334a45a8ff 315 */
bogdanm 0:9b334a45a8ff 316 #define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 317 #define RCC_MCO2 ((uint32_t)0x00000001)
bogdanm 0:9b334a45a8ff 318 /**
bogdanm 0:9b334a45a8ff 319 * @}
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
bogdanm 0:9b334a45a8ff 323 * @{
bogdanm 0:9b334a45a8ff 324 */
bogdanm 0:9b334a45a8ff 325 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 326 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
bogdanm 0:9b334a45a8ff 327 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
bogdanm 0:9b334a45a8ff 328 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
bogdanm 0:9b334a45a8ff 329 /**
bogdanm 0:9b334a45a8ff 330 * @}
bogdanm 0:9b334a45a8ff 331 */
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
bogdanm 0:9b334a45a8ff 334 * @{
bogdanm 0:9b334a45a8ff 335 */
bogdanm 0:9b334a45a8ff 336 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 337 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
bogdanm 0:9b334a45a8ff 338 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
bogdanm 0:9b334a45a8ff 339 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
bogdanm 0:9b334a45a8ff 340 /**
bogdanm 0:9b334a45a8ff 341 * @}
bogdanm 0:9b334a45a8ff 342 */
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
bogdanm 0:9b334a45a8ff 345 * @{
bogdanm 0:9b334a45a8ff 346 */
bogdanm 0:9b334a45a8ff 347 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 348 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
bogdanm 0:9b334a45a8ff 349 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
bogdanm 0:9b334a45a8ff 350 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
bogdanm 0:9b334a45a8ff 351 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
bogdanm 0:9b334a45a8ff 352 /**
bogdanm 0:9b334a45a8ff 353 * @}
bogdanm 0:9b334a45a8ff 354 */
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /** @defgroup RCC_Interrupt Interrupts
bogdanm 0:9b334a45a8ff 357 * @{
bogdanm 0:9b334a45a8ff 358 */
bogdanm 0:9b334a45a8ff 359 #define RCC_IT_LSIRDY ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 360 #define RCC_IT_LSERDY ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 361 #define RCC_IT_HSIRDY ((uint8_t)0x04)
bogdanm 0:9b334a45a8ff 362 #define RCC_IT_HSERDY ((uint8_t)0x08)
bogdanm 0:9b334a45a8ff 363 #define RCC_IT_PLLRDY ((uint8_t)0x10)
bogdanm 0:9b334a45a8ff 364 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
bogdanm 0:9b334a45a8ff 365 #define RCC_IT_CSS ((uint8_t)0x80)
bogdanm 0:9b334a45a8ff 366 /**
bogdanm 0:9b334a45a8ff 367 * @}
bogdanm 0:9b334a45a8ff 368 */
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /** @defgroup RCC_Flag Flags
bogdanm 0:9b334a45a8ff 371 * Elements values convention: 0XXYYYYYb
bogdanm 0:9b334a45a8ff 372 * - YYYYY : Flag position in the register
bogdanm 0:9b334a45a8ff 373 * - 0XX : Register index
bogdanm 0:9b334a45a8ff 374 * - 01: CR register
bogdanm 0:9b334a45a8ff 375 * - 10: BDCR register
bogdanm 0:9b334a45a8ff 376 * - 11: CSR register
bogdanm 0:9b334a45a8ff 377 * @{
bogdanm 0:9b334a45a8ff 378 */
bogdanm 0:9b334a45a8ff 379 /* Flags in the CR register */
bogdanm 0:9b334a45a8ff 380 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
bogdanm 0:9b334a45a8ff 381 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm 0:9b334a45a8ff 382 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm 0:9b334a45a8ff 383 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /* Flags in the BDCR register */
bogdanm 0:9b334a45a8ff 386 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /* Flags in the CSR register */
bogdanm 0:9b334a45a8ff 389 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
bogdanm 0:9b334a45a8ff 390 #define RCC_FLAG_BORRST ((uint8_t)0x79)
bogdanm 0:9b334a45a8ff 391 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
bogdanm 0:9b334a45a8ff 392 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
bogdanm 0:9b334a45a8ff 393 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
bogdanm 0:9b334a45a8ff 394 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
bogdanm 0:9b334a45a8ff 395 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
bogdanm 0:9b334a45a8ff 396 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
bogdanm 0:9b334a45a8ff 397 /**
bogdanm 0:9b334a45a8ff 398 * @}
bogdanm 0:9b334a45a8ff 399 */
bogdanm 0:9b334a45a8ff 400
bogdanm 0:9b334a45a8ff 401 /**
bogdanm 0:9b334a45a8ff 402 * @}
bogdanm 0:9b334a45a8ff 403 */
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 406 /** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm 0:9b334a45a8ff 407 * @{
bogdanm 0:9b334a45a8ff 408 */
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
bogdanm 0:9b334a45a8ff 411 * @brief Enable or disable the AHB1 peripheral clock.
bogdanm 0:9b334a45a8ff 412 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 413 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 414 * using it.
bogdanm 0:9b334a45a8ff 415 * @{
bogdanm 0:9b334a45a8ff 416 */
bogdanm 0:9b334a45a8ff 417 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 418 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 419 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
bogdanm 0:9b334a45a8ff 420 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 421 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
bogdanm 0:9b334a45a8ff 422 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 423 } while(0)
bogdanm 0:9b334a45a8ff 424 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 425 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 426 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
bogdanm 0:9b334a45a8ff 427 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 428 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
bogdanm 0:9b334a45a8ff 429 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 430 } while(0)
bogdanm 0:9b334a45a8ff 431 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 432 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 433 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
bogdanm 0:9b334a45a8ff 434 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 435 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
bogdanm 0:9b334a45a8ff 436 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 437 } while(0)
bogdanm 0:9b334a45a8ff 438 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 439 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 440 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
bogdanm 0:9b334a45a8ff 441 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 442 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
bogdanm 0:9b334a45a8ff 443 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 444 } while(0)
bogdanm 0:9b334a45a8ff 445 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 446 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 447 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
bogdanm 0:9b334a45a8ff 448 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 449 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
bogdanm 0:9b334a45a8ff 450 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 451 } while(0)
bogdanm 0:9b334a45a8ff 452 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 453 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
bogdanm 0:9b334a45a8ff 455 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
bogdanm 0:9b334a45a8ff 457 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 458 } while(0)
bogdanm 0:9b334a45a8ff 459 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 460 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 461 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
bogdanm 0:9b334a45a8ff 462 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 463 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
bogdanm 0:9b334a45a8ff 464 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 465 } while(0)
bogdanm 0:9b334a45a8ff 466 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 467 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 468 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
bogdanm 0:9b334a45a8ff 469 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 470 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
bogdanm 0:9b334a45a8ff 471 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 472 } while(0)
bogdanm 0:9b334a45a8ff 473 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 474 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 475 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
bogdanm 0:9b334a45a8ff 476 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 477 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
bogdanm 0:9b334a45a8ff 478 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 479 } while(0)
bogdanm 0:9b334a45a8ff 480 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 481 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 482 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
bogdanm 0:9b334a45a8ff 483 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 484 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
bogdanm 0:9b334a45a8ff 485 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 486 } while(0)
bogdanm 0:9b334a45a8ff 487 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 488 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 489 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
bogdanm 0:9b334a45a8ff 490 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 491 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
bogdanm 0:9b334a45a8ff 492 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 493 } while(0)
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
bogdanm 0:9b334a45a8ff 496 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
bogdanm 0:9b334a45a8ff 497 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
bogdanm 0:9b334a45a8ff 498 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
bogdanm 0:9b334a45a8ff 499 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
bogdanm 0:9b334a45a8ff 500 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
bogdanm 0:9b334a45a8ff 501 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm 0:9b334a45a8ff 502 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
bogdanm 0:9b334a45a8ff 503 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
bogdanm 0:9b334a45a8ff 504 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
bogdanm 0:9b334a45a8ff 505 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 /**
bogdanm 0:9b334a45a8ff 508 * @}
bogdanm 0:9b334a45a8ff 509 */
bogdanm 0:9b334a45a8ff 510
bogdanm 0:9b334a45a8ff 511 /** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
bogdanm 0:9b334a45a8ff 512 * @brief Enable or disable the AHB2 peripheral clock.
bogdanm 0:9b334a45a8ff 513 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 514 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 515 * using it.
bogdanm 0:9b334a45a8ff 516 * @{
bogdanm 0:9b334a45a8ff 517 */
bogdanm 0:9b334a45a8ff 518 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
bogdanm 0:9b334a45a8ff 519 __HAL_RCC_SYSCFG_CLK_ENABLE();\
bogdanm 0:9b334a45a8ff 520 }while(0)
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
bogdanm 0:9b334a45a8ff 523 __HAL_RCC_SYSCFG_CLK_DISABLE();\
bogdanm 0:9b334a45a8ff 524 }while(0)
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 #define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
bogdanm 0:9b334a45a8ff 527 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /**
bogdanm 0:9b334a45a8ff 530 * @}
bogdanm 0:9b334a45a8ff 531 */
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
bogdanm 0:9b334a45a8ff 534 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 0:9b334a45a8ff 535 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 536 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 537 * using it.
bogdanm 0:9b334a45a8ff 538 * @{
bogdanm 0:9b334a45a8ff 539 */
bogdanm 0:9b334a45a8ff 540 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 541 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 542 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm 0:9b334a45a8ff 543 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 544 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm 0:9b334a45a8ff 545 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 546 } while(0)
bogdanm 0:9b334a45a8ff 547 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 548 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 549 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm 0:9b334a45a8ff 550 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 551 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
bogdanm 0:9b334a45a8ff 552 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 553 } while(0)
bogdanm 0:9b334a45a8ff 554 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 555 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 556 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
bogdanm 0:9b334a45a8ff 557 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 558 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
bogdanm 0:9b334a45a8ff 559 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 560 } while(0)
bogdanm 0:9b334a45a8ff 561 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 562 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 563 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
bogdanm 0:9b334a45a8ff 564 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 565 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
bogdanm 0:9b334a45a8ff 566 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 567 } while(0)
bogdanm 0:9b334a45a8ff 568 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 569 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 570 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm 0:9b334a45a8ff 571 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 572 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
bogdanm 0:9b334a45a8ff 573 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 574 } while(0)
bogdanm 0:9b334a45a8ff 575 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 576 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 577 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
bogdanm 0:9b334a45a8ff 578 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 579 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
bogdanm 0:9b334a45a8ff 580 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 581 } while(0)
bogdanm 0:9b334a45a8ff 582 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 583 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 584 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
bogdanm 0:9b334a45a8ff 585 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 586 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
bogdanm 0:9b334a45a8ff 587 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 588 } while(0)
bogdanm 0:9b334a45a8ff 589 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 590 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 591 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm 0:9b334a45a8ff 592 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 593 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm 0:9b334a45a8ff 594 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 595 } while(0)
bogdanm 0:9b334a45a8ff 596 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 597 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 598 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm 0:9b334a45a8ff 599 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 600 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
bogdanm 0:9b334a45a8ff 601 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 602 } while(0)
bogdanm 0:9b334a45a8ff 603 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 604 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 605 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
bogdanm 0:9b334a45a8ff 606 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 607 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
bogdanm 0:9b334a45a8ff 608 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 609 } while(0)
bogdanm 0:9b334a45a8ff 610 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 611 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 612 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
bogdanm 0:9b334a45a8ff 613 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 614 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
bogdanm 0:9b334a45a8ff 615 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 616 } while(0)
bogdanm 0:9b334a45a8ff 617 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 618 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 619 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm 0:9b334a45a8ff 620 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 621 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
bogdanm 0:9b334a45a8ff 622 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 623 } while(0)
bogdanm 0:9b334a45a8ff 624 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm 0:9b334a45a8ff 625 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm 0:9b334a45a8ff 626 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm 0:9b334a45a8ff 627 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
bogdanm 0:9b334a45a8ff 628 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 0:9b334a45a8ff 629 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm 0:9b334a45a8ff 630 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm 0:9b334a45a8ff 631 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm 0:9b334a45a8ff 632 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm 0:9b334a45a8ff 633 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm 0:9b334a45a8ff 634 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm 0:9b334a45a8ff 635 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm 0:9b334a45a8ff 636 /**
bogdanm 0:9b334a45a8ff 637 * @}
bogdanm 0:9b334a45a8ff 638 */
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
bogdanm 0:9b334a45a8ff 641 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 0:9b334a45a8ff 642 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 0:9b334a45a8ff 643 * is disabled and the application software has to enable this clock before
bogdanm 0:9b334a45a8ff 644 * using it.
bogdanm 0:9b334a45a8ff 645 * @{
bogdanm 0:9b334a45a8ff 646 */
bogdanm 0:9b334a45a8ff 647 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 648 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 649 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm 0:9b334a45a8ff 650 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 651 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
bogdanm 0:9b334a45a8ff 652 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 653 } while(0)
bogdanm 0:9b334a45a8ff 654 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 655 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 656 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm 0:9b334a45a8ff 657 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 658 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
bogdanm 0:9b334a45a8ff 659 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 660 } while(0)
bogdanm 0:9b334a45a8ff 661 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 662 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 663 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
bogdanm 0:9b334a45a8ff 664 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 665 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
bogdanm 0:9b334a45a8ff 666 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 667 } while(0)
bogdanm 0:9b334a45a8ff 668 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 669 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 670 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm 0:9b334a45a8ff 671 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 672 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
bogdanm 0:9b334a45a8ff 673 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 674 } while(0)
bogdanm 0:9b334a45a8ff 675 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 676 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 677 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
bogdanm 0:9b334a45a8ff 678 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 679 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
bogdanm 0:9b334a45a8ff 680 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 681 } while(0)
bogdanm 0:9b334a45a8ff 682 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 683 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 684 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm 0:9b334a45a8ff 685 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 686 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
bogdanm 0:9b334a45a8ff 687 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 688 } while(0)
bogdanm 0:9b334a45a8ff 689 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 690 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 691 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
bogdanm 0:9b334a45a8ff 692 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 693 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
bogdanm 0:9b334a45a8ff 694 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 695 } while(0)
bogdanm 0:9b334a45a8ff 696 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 697 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 698 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
bogdanm 0:9b334a45a8ff 699 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 700 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
bogdanm 0:9b334a45a8ff 701 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 702 } while(0)
bogdanm 0:9b334a45a8ff 703 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 704 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 705 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
bogdanm 0:9b334a45a8ff 706 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 707 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
bogdanm 0:9b334a45a8ff 708 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 709 } while(0)
bogdanm 0:9b334a45a8ff 710 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 711 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 712 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
bogdanm 0:9b334a45a8ff 713 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 714 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
bogdanm 0:9b334a45a8ff 715 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 716 } while(0)
bogdanm 0:9b334a45a8ff 717 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
bogdanm 0:9b334a45a8ff 718 __IO uint32_t tmpreg; \
bogdanm 0:9b334a45a8ff 719 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
bogdanm 0:9b334a45a8ff 720 /* Delay after an RCC peripheral clock enabling */ \
bogdanm 0:9b334a45a8ff 721 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
bogdanm 0:9b334a45a8ff 722 UNUSED(tmpreg); \
bogdanm 0:9b334a45a8ff 723 } while(0)
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm 0:9b334a45a8ff 726 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm 0:9b334a45a8ff 727 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
bogdanm 0:9b334a45a8ff 728 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm 0:9b334a45a8ff 729 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
bogdanm 0:9b334a45a8ff 730 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm 0:9b334a45a8ff 731 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
bogdanm 0:9b334a45a8ff 732 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm 0:9b334a45a8ff 733 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
bogdanm 0:9b334a45a8ff 734 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
bogdanm 0:9b334a45a8ff 735 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
bogdanm 0:9b334a45a8ff 736 /**
bogdanm 0:9b334a45a8ff 737 * @}
bogdanm 0:9b334a45a8ff 738 */
bogdanm 0:9b334a45a8ff 739
bogdanm 0:9b334a45a8ff 740 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
bogdanm 0:9b334a45a8ff 741 * @brief Force or release AHB1 peripheral reset.
bogdanm 0:9b334a45a8ff 742 * @{
bogdanm 0:9b334a45a8ff 743 */
bogdanm 0:9b334a45a8ff 744 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 745 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
bogdanm 0:9b334a45a8ff 746 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
bogdanm 0:9b334a45a8ff 747 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
bogdanm 0:9b334a45a8ff 748 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
bogdanm 0:9b334a45a8ff 749 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
bogdanm 0:9b334a45a8ff 750 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
bogdanm 0:9b334a45a8ff 751 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
bogdanm 0:9b334a45a8ff 752 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
bogdanm 0:9b334a45a8ff 753 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
bogdanm 0:9b334a45a8ff 754
bogdanm 0:9b334a45a8ff 755 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
bogdanm 0:9b334a45a8ff 756 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
bogdanm 0:9b334a45a8ff 757 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
bogdanm 0:9b334a45a8ff 758 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
bogdanm 0:9b334a45a8ff 759 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
bogdanm 0:9b334a45a8ff 760 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
bogdanm 0:9b334a45a8ff 761 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm 0:9b334a45a8ff 762 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm 0:9b334a45a8ff 763 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
bogdanm 0:9b334a45a8ff 764 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm 0:9b334a45a8ff 765 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
bogdanm 0:9b334a45a8ff 766 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
bogdanm 0:9b334a45a8ff 767 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
bogdanm 0:9b334a45a8ff 768 /**
bogdanm 0:9b334a45a8ff 769 * @}
bogdanm 0:9b334a45a8ff 770 */
bogdanm 0:9b334a45a8ff 771
bogdanm 0:9b334a45a8ff 772 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
bogdanm 0:9b334a45a8ff 773 * @brief Force or release AHB2 peripheral reset.
bogdanm 0:9b334a45a8ff 774 * @{
bogdanm 0:9b334a45a8ff 775 */
bogdanm 0:9b334a45a8ff 776 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 777 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
bogdanm 0:9b334a45a8ff 780 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
bogdanm 0:9b334a45a8ff 781
bogdanm 0:9b334a45a8ff 782 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
bogdanm 0:9b334a45a8ff 783 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
bogdanm 0:9b334a45a8ff 784 /**
bogdanm 0:9b334a45a8ff 785 * @}
bogdanm 0:9b334a45a8ff 786 */
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
bogdanm 0:9b334a45a8ff 789 * @brief Force or release APB1 peripheral reset.
bogdanm 0:9b334a45a8ff 790 * @{
bogdanm 0:9b334a45a8ff 791 */
bogdanm 0:9b334a45a8ff 792 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 793 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
bogdanm 0:9b334a45a8ff 794 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
bogdanm 0:9b334a45a8ff 795 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
bogdanm 0:9b334a45a8ff 796 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
bogdanm 0:9b334a45a8ff 797 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
bogdanm 0:9b334a45a8ff 798 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
bogdanm 0:9b334a45a8ff 799 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
bogdanm 0:9b334a45a8ff 800 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
bogdanm 0:9b334a45a8ff 801 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
bogdanm 0:9b334a45a8ff 802 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
bogdanm 0:9b334a45a8ff 803 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
bogdanm 0:9b334a45a8ff 804 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 0:9b334a45a8ff 805
bogdanm 0:9b334a45a8ff 806 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm 0:9b334a45a8ff 807 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm 0:9b334a45a8ff 808 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm 0:9b334a45a8ff 809 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm 0:9b334a45a8ff 810 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
bogdanm 0:9b334a45a8ff 811 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm 0:9b334a45a8ff 812 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm 0:9b334a45a8ff 813 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm 0:9b334a45a8ff 814 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm 0:9b334a45a8ff 815 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm 0:9b334a45a8ff 816 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm 0:9b334a45a8ff 817 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm 0:9b334a45a8ff 818 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm 0:9b334a45a8ff 819 /**
bogdanm 0:9b334a45a8ff 820 * @}
bogdanm 0:9b334a45a8ff 821 */
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
bogdanm 0:9b334a45a8ff 824 * @brief Force or release APB2 peripheral reset.
bogdanm 0:9b334a45a8ff 825 * @{
bogdanm 0:9b334a45a8ff 826 */
bogdanm 0:9b334a45a8ff 827 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 828 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
bogdanm 0:9b334a45a8ff 829 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
bogdanm 0:9b334a45a8ff 830 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
bogdanm 0:9b334a45a8ff 831 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
bogdanm 0:9b334a45a8ff 832 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
bogdanm 0:9b334a45a8ff 833 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
bogdanm 0:9b334a45a8ff 834 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
bogdanm 0:9b334a45a8ff 835 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
bogdanm 0:9b334a45a8ff 836 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
bogdanm 0:9b334a45a8ff 837 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
bogdanm 0:9b334a45a8ff 838 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
bogdanm 0:9b334a45a8ff 839
bogdanm 0:9b334a45a8ff 840 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm 0:9b334a45a8ff 841 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm 0:9b334a45a8ff 842 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm 0:9b334a45a8ff 843 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
bogdanm 0:9b334a45a8ff 844 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
bogdanm 0:9b334a45a8ff 845 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
bogdanm 0:9b334a45a8ff 846 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm 0:9b334a45a8ff 847 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
bogdanm 0:9b334a45a8ff 848 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm 0:9b334a45a8ff 849 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
bogdanm 0:9b334a45a8ff 850 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
bogdanm 0:9b334a45a8ff 851 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
bogdanm 0:9b334a45a8ff 852 /**
bogdanm 0:9b334a45a8ff 853 * @}
bogdanm 0:9b334a45a8ff 854 */
bogdanm 0:9b334a45a8ff 855
bogdanm 0:9b334a45a8ff 856 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
bogdanm 0:9b334a45a8ff 857 * @brief Force or release AHB3 peripheral reset.
bogdanm 0:9b334a45a8ff 858 * @{
bogdanm 0:9b334a45a8ff 859 */
bogdanm 0:9b334a45a8ff 860 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
bogdanm 0:9b334a45a8ff 861 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
bogdanm 0:9b334a45a8ff 862 /**
bogdanm 0:9b334a45a8ff 863 * @}
bogdanm 0:9b334a45a8ff 864 */
bogdanm 0:9b334a45a8ff 865
bogdanm 0:9b334a45a8ff 866 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
bogdanm 0:9b334a45a8ff 867 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 868 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 869 * power consumption.
bogdanm 0:9b334a45a8ff 870 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 871 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 872 * @{
bogdanm 0:9b334a45a8ff 873 */
bogdanm 0:9b334a45a8ff 874 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
bogdanm 0:9b334a45a8ff 875 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
bogdanm 0:9b334a45a8ff 876 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
bogdanm 0:9b334a45a8ff 877 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
bogdanm 0:9b334a45a8ff 878 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
bogdanm 0:9b334a45a8ff 879 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
bogdanm 0:9b334a45a8ff 880 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
bogdanm 0:9b334a45a8ff 881 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
bogdanm 0:9b334a45a8ff 882 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
bogdanm 0:9b334a45a8ff 883 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm 0:9b334a45a8ff 884 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
bogdanm 0:9b334a45a8ff 885 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
bogdanm 0:9b334a45a8ff 886
bogdanm 0:9b334a45a8ff 887 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
bogdanm 0:9b334a45a8ff 888 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
bogdanm 0:9b334a45a8ff 889 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
bogdanm 0:9b334a45a8ff 890 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
bogdanm 0:9b334a45a8ff 891 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
bogdanm 0:9b334a45a8ff 892 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
bogdanm 0:9b334a45a8ff 893 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
bogdanm 0:9b334a45a8ff 894 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
bogdanm 0:9b334a45a8ff 895 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
bogdanm 0:9b334a45a8ff 896 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm 0:9b334a45a8ff 897 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
bogdanm 0:9b334a45a8ff 898 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
bogdanm 0:9b334a45a8ff 899 /**
bogdanm 0:9b334a45a8ff 900 * @}
bogdanm 0:9b334a45a8ff 901 */
bogdanm 0:9b334a45a8ff 902
bogdanm 0:9b334a45a8ff 903 /** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
bogdanm 0:9b334a45a8ff 904 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 906 * power consumption.
bogdanm 0:9b334a45a8ff 907 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 908 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 909 * @{
bogdanm 0:9b334a45a8ff 910 */
bogdanm 0:9b334a45a8ff 911 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
bogdanm 0:9b334a45a8ff 912
bogdanm 0:9b334a45a8ff 913 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
bogdanm 0:9b334a45a8ff 914
bogdanm 0:9b334a45a8ff 915 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
bogdanm 0:9b334a45a8ff 916 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
bogdanm 0:9b334a45a8ff 917 /**
bogdanm 0:9b334a45a8ff 918 * @}
bogdanm 0:9b334a45a8ff 919 */
bogdanm 0:9b334a45a8ff 920
bogdanm 0:9b334a45a8ff 921 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
bogdanm 0:9b334a45a8ff 922 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 923 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 924 * power consumption.
bogdanm 0:9b334a45a8ff 925 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 926 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 927 * @{
bogdanm 0:9b334a45a8ff 928 */
bogdanm 0:9b334a45a8ff 929 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
bogdanm 0:9b334a45a8ff 930 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
bogdanm 0:9b334a45a8ff 931 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
bogdanm 0:9b334a45a8ff 932 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
bogdanm 0:9b334a45a8ff 933 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
bogdanm 0:9b334a45a8ff 934 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
bogdanm 0:9b334a45a8ff 935 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
bogdanm 0:9b334a45a8ff 936 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
bogdanm 0:9b334a45a8ff 937 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
bogdanm 0:9b334a45a8ff 938 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
bogdanm 0:9b334a45a8ff 939 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
bogdanm 0:9b334a45a8ff 940 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
bogdanm 0:9b334a45a8ff 941
bogdanm 0:9b334a45a8ff 942 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
bogdanm 0:9b334a45a8ff 943 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
bogdanm 0:9b334a45a8ff 944 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
bogdanm 0:9b334a45a8ff 945 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
bogdanm 0:9b334a45a8ff 946 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
bogdanm 0:9b334a45a8ff 947 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
bogdanm 0:9b334a45a8ff 948 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
bogdanm 0:9b334a45a8ff 949 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
bogdanm 0:9b334a45a8ff 950 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
bogdanm 0:9b334a45a8ff 951 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
bogdanm 0:9b334a45a8ff 952 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
bogdanm 0:9b334a45a8ff 953 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
bogdanm 0:9b334a45a8ff 954 /**
bogdanm 0:9b334a45a8ff 955 * @}
bogdanm 0:9b334a45a8ff 956 */
bogdanm 0:9b334a45a8ff 957
bogdanm 0:9b334a45a8ff 958 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
bogdanm 0:9b334a45a8ff 959 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 0:9b334a45a8ff 960 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 0:9b334a45a8ff 961 * power consumption.
bogdanm 0:9b334a45a8ff 962 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
bogdanm 0:9b334a45a8ff 963 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 0:9b334a45a8ff 964 * @{
bogdanm 0:9b334a45a8ff 965 */
bogdanm 0:9b334a45a8ff 966 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
bogdanm 0:9b334a45a8ff 967 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
bogdanm 0:9b334a45a8ff 968 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
bogdanm 0:9b334a45a8ff 969 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
bogdanm 0:9b334a45a8ff 970 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
bogdanm 0:9b334a45a8ff 971 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
bogdanm 0:9b334a45a8ff 972 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
bogdanm 0:9b334a45a8ff 973 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
bogdanm 0:9b334a45a8ff 974 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
bogdanm 0:9b334a45a8ff 975 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
bogdanm 0:9b334a45a8ff 976 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
bogdanm 0:9b334a45a8ff 977
bogdanm 0:9b334a45a8ff 978 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
bogdanm 0:9b334a45a8ff 979 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
bogdanm 0:9b334a45a8ff 980 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
bogdanm 0:9b334a45a8ff 981 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
bogdanm 0:9b334a45a8ff 982 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
bogdanm 0:9b334a45a8ff 983 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
bogdanm 0:9b334a45a8ff 984 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
bogdanm 0:9b334a45a8ff 985 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
bogdanm 0:9b334a45a8ff 986 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
bogdanm 0:9b334a45a8ff 987 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
bogdanm 0:9b334a45a8ff 988 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
bogdanm 0:9b334a45a8ff 989 /**
bogdanm 0:9b334a45a8ff 990 * @}
bogdanm 0:9b334a45a8ff 991 */
bogdanm 0:9b334a45a8ff 992
bogdanm 0:9b334a45a8ff 993 /** @defgroup RCC_HSI_Configuration HSI Configuration
bogdanm 0:9b334a45a8ff 994 * @{
bogdanm 0:9b334a45a8ff 995 */
bogdanm 0:9b334a45a8ff 996
bogdanm 0:9b334a45a8ff 997 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 0:9b334a45a8ff 998 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 999 * It is used (enabled by hardware) as system clock source after startup
bogdanm 0:9b334a45a8ff 1000 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
bogdanm 0:9b334a45a8ff 1001 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 0:9b334a45a8ff 1002 * Security System CSS is enabled).
bogdanm 0:9b334a45a8ff 1003 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 0:9b334a45a8ff 1004 * you have to select another source of the system clock then stop the HSI.
bogdanm 0:9b334a45a8ff 1005 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 0:9b334a45a8ff 1006 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 0:9b334a45a8ff 1007 * system clock source.
bogdanm 0:9b334a45a8ff 1008 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 1009 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 0:9b334a45a8ff 1010 * clock cycles.
bogdanm 0:9b334a45a8ff 1011 */
bogdanm 0:9b334a45a8ff 1012 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
bogdanm 0:9b334a45a8ff 1013 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 0:9b334a45a8ff 1016 * @note The calibration is used to compensate for the variations in voltage
bogdanm 0:9b334a45a8ff 1017 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 0:9b334a45a8ff 1018 * @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm 0:9b334a45a8ff 1019 * This parameter must be a number between 0 and 0x1F.
bogdanm 0:9b334a45a8ff 1020 */
bogdanm 0:9b334a45a8ff 1021 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
bogdanm 0:9b334a45a8ff 1022 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
bogdanm 0:9b334a45a8ff 1023 /**
bogdanm 0:9b334a45a8ff 1024 * @}
bogdanm 0:9b334a45a8ff 1025 */
bogdanm 0:9b334a45a8ff 1026
bogdanm 0:9b334a45a8ff 1027 /** @defgroup RCC_LSI_Configuration LSI Configuration
bogdanm 0:9b334a45a8ff 1028 * @{
bogdanm 0:9b334a45a8ff 1029 */
bogdanm 0:9b334a45a8ff 1030
bogdanm 0:9b334a45a8ff 1031 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 0:9b334a45a8ff 1032 * @note After enabling the LSI, the application software should wait on
bogdanm 0:9b334a45a8ff 1033 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 0:9b334a45a8ff 1034 * be used to clock the IWDG and/or the RTC.
bogdanm 0:9b334a45a8ff 1035 * @note LSI can not be disabled if the IWDG is running.
bogdanm 0:9b334a45a8ff 1036 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 0:9b334a45a8ff 1037 * clock cycles.
bogdanm 0:9b334a45a8ff 1038 */
bogdanm 0:9b334a45a8ff 1039 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
bogdanm 0:9b334a45a8ff 1040 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
bogdanm 0:9b334a45a8ff 1041 /**
bogdanm 0:9b334a45a8ff 1042 * @}
bogdanm 0:9b334a45a8ff 1043 */
bogdanm 0:9b334a45a8ff 1044
bogdanm 0:9b334a45a8ff 1045 /** @defgroup RCC_HSE_Configuration HSE Configuration
bogdanm 0:9b334a45a8ff 1046 * @{
bogdanm 0:9b334a45a8ff 1047 */
bogdanm 0:9b334a45a8ff 1048
bogdanm 0:9b334a45a8ff 1049 /**
bogdanm 0:9b334a45a8ff 1050 * @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm 0:9b334a45a8ff 1051 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
bogdanm 0:9b334a45a8ff 1052 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
bogdanm 0:9b334a45a8ff 1053 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 0:9b334a45a8ff 1054 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 0:9b334a45a8ff 1055 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 0:9b334a45a8ff 1056 * @note HSE state can not be changed if it is used directly or through the
bogdanm 0:9b334a45a8ff 1057 * PLL as system clock. In this case, you have to select another source
bogdanm 0:9b334a45a8ff 1058 * of the system clock then change the HSE state (ex. disable it).
bogdanm 0:9b334a45a8ff 1059 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 1060 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 0:9b334a45a8ff 1061 * was previously enabled you have to enable it again after calling this
bogdanm 0:9b334a45a8ff 1062 * function.
bogdanm 0:9b334a45a8ff 1063 * @param __STATE__: specifies the new state of the HSE.
bogdanm 0:9b334a45a8ff 1064 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1065 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 0:9b334a45a8ff 1066 * 6 HSE oscillator clock cycles.
bogdanm 0:9b334a45a8ff 1067 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm 0:9b334a45a8ff 1068 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm 0:9b334a45a8ff 1069 */
bogdanm 0:9b334a45a8ff 1070 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
bogdanm 0:9b334a45a8ff 1071 /**
bogdanm 0:9b334a45a8ff 1072 * @}
bogdanm 0:9b334a45a8ff 1073 */
bogdanm 0:9b334a45a8ff 1074
bogdanm 0:9b334a45a8ff 1075 /** @defgroup RCC_LSE_Configuration LSE Configuration
bogdanm 0:9b334a45a8ff 1076 * @{
bogdanm 0:9b334a45a8ff 1077 */
bogdanm 0:9b334a45a8ff 1078
bogdanm 0:9b334a45a8ff 1079 /**
bogdanm 0:9b334a45a8ff 1080 * @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm 0:9b334a45a8ff 1081 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
bogdanm 0:9b334a45a8ff 1082 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
bogdanm 0:9b334a45a8ff 1083 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 0:9b334a45a8ff 1084 * this domain after reset, you have to enable write access using
bogdanm 0:9b334a45a8ff 1085 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 0:9b334a45a8ff 1086 * (to be done once after reset).
bogdanm 0:9b334a45a8ff 1087 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 0:9b334a45a8ff 1088 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 0:9b334a45a8ff 1089 * is stable and can be used to clock the RTC.
bogdanm 0:9b334a45a8ff 1090 * @param __STATE__: specifies the new state of the LSE.
bogdanm 0:9b334a45a8ff 1091 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1092 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 0:9b334a45a8ff 1093 * 6 LSE oscillator clock cycles.
bogdanm 0:9b334a45a8ff 1094 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm 0:9b334a45a8ff 1095 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm 0:9b334a45a8ff 1096 */
bogdanm 0:9b334a45a8ff 1097 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
bogdanm 0:9b334a45a8ff 1098
bogdanm 0:9b334a45a8ff 1099 /**
bogdanm 0:9b334a45a8ff 1100 * @}
bogdanm 0:9b334a45a8ff 1101 */
bogdanm 0:9b334a45a8ff 1102
bogdanm 0:9b334a45a8ff 1103 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
bogdanm 0:9b334a45a8ff 1104 * @{
bogdanm 0:9b334a45a8ff 1105 */
bogdanm 0:9b334a45a8ff 1106
bogdanm 0:9b334a45a8ff 1107 /** @brief Macros to enable or disable the RTC clock.
bogdanm 0:9b334a45a8ff 1108 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 0:9b334a45a8ff 1109 */
bogdanm 0:9b334a45a8ff 1110 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
bogdanm 0:9b334a45a8ff 1111 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
bogdanm 0:9b334a45a8ff 1112
bogdanm 0:9b334a45a8ff 1113 /** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm 0:9b334a45a8ff 1114 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 0:9b334a45a8ff 1115 * access is denied to this domain after reset, you have to enable write
bogdanm 0:9b334a45a8ff 1116 * access using the Power Backup Access macro before to configure
bogdanm 0:9b334a45a8ff 1117 * the RTC clock source (to be done once after reset).
bogdanm 0:9b334a45a8ff 1118 * @note Once the RTC clock is configured it can't be changed unless the
bogdanm 0:9b334a45a8ff 1119 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm 0:9b334a45a8ff 1120 * a Power On Reset (POR).
bogdanm 0:9b334a45a8ff 1121 * @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm 0:9b334a45a8ff 1122 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1123 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm 0:9b334a45a8ff 1124 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm 0:9b334a45a8ff 1125 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
bogdanm 0:9b334a45a8ff 1126 * as RTC clock, where x:[2,31]
bogdanm 0:9b334a45a8ff 1127 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm 0:9b334a45a8ff 1128 * work in STOP and STANDBY modes, and can be used as wake-up source.
bogdanm 0:9b334a45a8ff 1129 * However, when the HSE clock is used as RTC clock source, the RTC
bogdanm 0:9b334a45a8ff 1130 * cannot be used in STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 1131 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm 0:9b334a45a8ff 1132 * RTC clock source).
bogdanm 0:9b334a45a8ff 1133 */
bogdanm 0:9b334a45a8ff 1134 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm 0:9b334a45a8ff 1135 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm 0:9b334a45a8ff 1136
bogdanm 0:9b334a45a8ff 1137 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
bogdanm 0:9b334a45a8ff 1138 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
bogdanm 0:9b334a45a8ff 1139 } while (0)
bogdanm 0:9b334a45a8ff 1140
bogdanm 0:9b334a45a8ff 1141 /** @brief Macros to force or release the Backup domain reset.
bogdanm 0:9b334a45a8ff 1142 * @note This function resets the RTC peripheral (including the backup registers)
bogdanm 0:9b334a45a8ff 1143 * and the RTC clock source selection in RCC_CSR register.
bogdanm 0:9b334a45a8ff 1144 * @note The BKPSRAM is not affected by this reset.
bogdanm 0:9b334a45a8ff 1145 */
bogdanm 0:9b334a45a8ff 1146 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
bogdanm 0:9b334a45a8ff 1147 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
bogdanm 0:9b334a45a8ff 1148 /**
bogdanm 0:9b334a45a8ff 1149 * @}
bogdanm 0:9b334a45a8ff 1150 */
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 /** @defgroup RCC_PLL_Configuration PLL Configuration
bogdanm 0:9b334a45a8ff 1153 * @{
bogdanm 0:9b334a45a8ff 1154 */
bogdanm 0:9b334a45a8ff 1155
bogdanm 0:9b334a45a8ff 1156 /** @brief Macros to enable or disable the main PLL.
bogdanm 0:9b334a45a8ff 1157 * @note After enabling the main PLL, the application software should wait on
bogdanm 0:9b334a45a8ff 1158 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 0:9b334a45a8ff 1159 * be used as system clock source.
bogdanm 0:9b334a45a8ff 1160 * @note The main PLL can not be disabled if it is used as system clock source
bogdanm 0:9b334a45a8ff 1161 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 1162 */
bogdanm 0:9b334a45a8ff 1163 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
bogdanm 0:9b334a45a8ff 1164 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
bogdanm 0:9b334a45a8ff 1165 /**
bogdanm 0:9b334a45a8ff 1166 * @}
bogdanm 0:9b334a45a8ff 1167 */
bogdanm 0:9b334a45a8ff 1168
bogdanm 0:9b334a45a8ff 1169 /** @brief Macro to configure the PLL clock source.
bogdanm 0:9b334a45a8ff 1170 * @note This function must be used only when the main PLL is disabled.
bogdanm 0:9b334a45a8ff 1171 * @param __PLLSOURCE__: specifies the PLL entry clock source.
bogdanm 0:9b334a45a8ff 1172 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1173 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 0:9b334a45a8ff 1174 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm 0:9b334a45a8ff 1175 *
bogdanm 0:9b334a45a8ff 1176 */
bogdanm 0:9b334a45a8ff 1177 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
bogdanm 0:9b334a45a8ff 1178
bogdanm 0:9b334a45a8ff 1179 /** @brief Macro to configure the PLL multiplication factor.
bogdanm 0:9b334a45a8ff 1180 * @note This function must be used only when the main PLL is disabled.
bogdanm 0:9b334a45a8ff 1181 * @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm 0:9b334a45a8ff 1182 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm 0:9b334a45a8ff 1183 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm 0:9b334a45a8ff 1184 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm 0:9b334a45a8ff 1185 * of 2 MHz to limit PLL jitter.
bogdanm 0:9b334a45a8ff 1186 *
bogdanm 0:9b334a45a8ff 1187 */
bogdanm 0:9b334a45a8ff 1188 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
bogdanm 0:9b334a45a8ff 1189
bogdanm 0:9b334a45a8ff 1190 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
bogdanm 0:9b334a45a8ff 1191 * @{
bogdanm 0:9b334a45a8ff 1192 */
bogdanm 0:9b334a45a8ff 1193
bogdanm 0:9b334a45a8ff 1194 /** @brief Macros to enable or disable the PLLI2S.
bogdanm 0:9b334a45a8ff 1195 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 0:9b334a45a8ff 1196 */
bogdanm 0:9b334a45a8ff 1197 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
bogdanm 0:9b334a45a8ff 1198 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
bogdanm 0:9b334a45a8ff 1199 /**
bogdanm 0:9b334a45a8ff 1200 * @}
bogdanm 0:9b334a45a8ff 1201 */
bogdanm 0:9b334a45a8ff 1202
bogdanm 0:9b334a45a8ff 1203 /** @defgroup RCC_Get_Clock_source Get Clock source
bogdanm 0:9b334a45a8ff 1204 * @{
bogdanm 0:9b334a45a8ff 1205 */
bogdanm 0:9b334a45a8ff 1206 /**
bogdanm 0:9b334a45a8ff 1207 * @brief Macro to configure the system clock source.
bogdanm 0:9b334a45a8ff 1208 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
bogdanm 0:9b334a45a8ff 1209 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1210 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
bogdanm 0:9b334a45a8ff 1211 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
bogdanm 0:9b334a45a8ff 1212 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
bogdanm 0:9b334a45a8ff 1213 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
bogdanm 0:9b334a45a8ff 1214 */
bogdanm 0:9b334a45a8ff 1215 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 /** @brief Macro to get the clock source used as system clock.
bogdanm 0:9b334a45a8ff 1218 * @retval The clock source used as system clock. The returned value can be one
bogdanm 0:9b334a45a8ff 1219 * of the following:
bogdanm 0:9b334a45a8ff 1220 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
bogdanm 0:9b334a45a8ff 1221 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
bogdanm 0:9b334a45a8ff 1222 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
bogdanm 0:9b334a45a8ff 1223 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
bogdanm 0:9b334a45a8ff 1224 */
bogdanm 0:9b334a45a8ff 1225 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm 0:9b334a45a8ff 1226
bogdanm 0:9b334a45a8ff 1227 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 0:9b334a45a8ff 1228 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 0:9b334a45a8ff 1229 * of the following:
bogdanm 0:9b334a45a8ff 1230 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 0:9b334a45a8ff 1231 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 0:9b334a45a8ff 1232 */
bogdanm 0:9b334a45a8ff 1233 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
bogdanm 0:9b334a45a8ff 1234 /**
bogdanm 0:9b334a45a8ff 1235 * @}
bogdanm 0:9b334a45a8ff 1236 */
bogdanm 0:9b334a45a8ff 1237
bogdanm 0:9b334a45a8ff 1238 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
bogdanm 0:9b334a45a8ff 1239 * @brief macros to manage the specified RCC Flags and interrupts.
bogdanm 0:9b334a45a8ff 1240 * @{
bogdanm 0:9b334a45a8ff 1241 */
bogdanm 0:9b334a45a8ff 1242
bogdanm 0:9b334a45a8ff 1243 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm 0:9b334a45a8ff 1244 * the selected interrupts).
bogdanm 0:9b334a45a8ff 1245 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 0:9b334a45a8ff 1246 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1247 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1248 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1249 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1250 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1251 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1252 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1253 */
bogdanm 0:9b334a45a8ff 1254 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1255
bogdanm 0:9b334a45a8ff 1256 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm 0:9b334a45a8ff 1257 * the selected interrupts).
bogdanm 0:9b334a45a8ff 1258 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 0:9b334a45a8ff 1259 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1260 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1261 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1262 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1263 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1264 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1265 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1266 */
bogdanm 0:9b334a45a8ff 1267 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1268
bogdanm 0:9b334a45a8ff 1269 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm 0:9b334a45a8ff 1270 * bits to clear the selected interrupt pending bits.
bogdanm 0:9b334a45a8ff 1271 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 0:9b334a45a8ff 1272 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1273 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1274 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1275 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1276 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1277 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1278 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1279 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 0:9b334a45a8ff 1280 */
bogdanm 0:9b334a45a8ff 1281 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1282
bogdanm 0:9b334a45a8ff 1283 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 1284 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm 0:9b334a45a8ff 1285 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1286 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 0:9b334a45a8ff 1287 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 0:9b334a45a8ff 1288 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 0:9b334a45a8ff 1289 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 0:9b334a45a8ff 1290 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 0:9b334a45a8ff 1291 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 0:9b334a45a8ff 1292 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 0:9b334a45a8ff 1293 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 1294 */
bogdanm 0:9b334a45a8ff 1295 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 0:9b334a45a8ff 1296
bogdanm 0:9b334a45a8ff 1297 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm 0:9b334a45a8ff 1298 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm 0:9b334a45a8ff 1299 */
bogdanm 0:9b334a45a8ff 1300 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 0:9b334a45a8ff 1301
bogdanm 0:9b334a45a8ff 1302 /** @brief Check RCC flag is set or not.
bogdanm 0:9b334a45a8ff 1303 * @param __FLAG__: specifies the flag to check.
bogdanm 0:9b334a45a8ff 1304 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1305 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm 0:9b334a45a8ff 1306 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm 0:9b334a45a8ff 1307 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm 0:9b334a45a8ff 1308 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
bogdanm 0:9b334a45a8ff 1309 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm 0:9b334a45a8ff 1310 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm 0:9b334a45a8ff 1311 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
bogdanm 0:9b334a45a8ff 1312 * @arg RCC_FLAG_PINRST: Pin reset.
bogdanm 0:9b334a45a8ff 1313 * @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm 0:9b334a45a8ff 1314 * @arg RCC_FLAG_SFTRST: Software reset.
bogdanm 0:9b334a45a8ff 1315 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm 0:9b334a45a8ff 1316 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm 0:9b334a45a8ff 1317 * @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm 0:9b334a45a8ff 1318 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 1319 */
bogdanm 0:9b334a45a8ff 1320 #define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm 0:9b334a45a8ff 1321 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
bogdanm 0:9b334a45a8ff 1322
bogdanm 0:9b334a45a8ff 1323 /**
bogdanm 0:9b334a45a8ff 1324 * @}
bogdanm 0:9b334a45a8ff 1325 */
bogdanm 0:9b334a45a8ff 1326
bogdanm 0:9b334a45a8ff 1327 /**
bogdanm 0:9b334a45a8ff 1328 * @}
bogdanm 0:9b334a45a8ff 1329 */
bogdanm 0:9b334a45a8ff 1330
bogdanm 0:9b334a45a8ff 1331 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1332 /** @addtogroup RCC_Exported_Functions
bogdanm 0:9b334a45a8ff 1333 * @{
bogdanm 0:9b334a45a8ff 1334 */
bogdanm 0:9b334a45a8ff 1335
bogdanm 0:9b334a45a8ff 1336 /** @addtogroup RCC_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 1337 * @{
bogdanm 0:9b334a45a8ff 1338 */
bogdanm 0:9b334a45a8ff 1339 /* Initialization and de-initialization functions ******************************/
bogdanm 0:9b334a45a8ff 1340 void HAL_RCC_DeInit(void);
bogdanm 0:9b334a45a8ff 1341 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 1342 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm 0:9b334a45a8ff 1343 /**
bogdanm 0:9b334a45a8ff 1344 * @}
bogdanm 0:9b334a45a8ff 1345 */
bogdanm 0:9b334a45a8ff 1346
bogdanm 0:9b334a45a8ff 1347 /** @addtogroup RCC_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 1348 * @{
bogdanm 0:9b334a45a8ff 1349 */
bogdanm 0:9b334a45a8ff 1350 /* Peripheral Control functions ************************************************/
bogdanm 0:9b334a45a8ff 1351 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 0:9b334a45a8ff 1352 void HAL_RCC_EnableCSS(void);
bogdanm 0:9b334a45a8ff 1353 void HAL_RCC_DisableCSS(void);
bogdanm 0:9b334a45a8ff 1354 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 0:9b334a45a8ff 1355 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 0:9b334a45a8ff 1356 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 0:9b334a45a8ff 1357 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 0:9b334a45a8ff 1358 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 1359 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 0:9b334a45a8ff 1360
bogdanm 0:9b334a45a8ff 1361 /* CSS NMI IRQ handler */
bogdanm 0:9b334a45a8ff 1362 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 0:9b334a45a8ff 1363
bogdanm 0:9b334a45a8ff 1364 /* User Callbacks in non blocking mode (IT mode) */
bogdanm 0:9b334a45a8ff 1365 void HAL_RCC_CSSCallback(void);
bogdanm 0:9b334a45a8ff 1366
bogdanm 0:9b334a45a8ff 1367 /**
bogdanm 0:9b334a45a8ff 1368 * @}
bogdanm 0:9b334a45a8ff 1369 */
bogdanm 0:9b334a45a8ff 1370
bogdanm 0:9b334a45a8ff 1371 /**
bogdanm 0:9b334a45a8ff 1372 * @}
bogdanm 0:9b334a45a8ff 1373 */
bogdanm 0:9b334a45a8ff 1374
bogdanm 0:9b334a45a8ff 1375 /* Private types -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1376 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1377 /* Private constants ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1378 /** @defgroup RCC_Private_Constants RCC Private Constants
bogdanm 0:9b334a45a8ff 1379 * @{
bogdanm 0:9b334a45a8ff 1380 */
bogdanm 0:9b334a45a8ff 1381
bogdanm 0:9b334a45a8ff 1382 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
bogdanm 0:9b334a45a8ff 1383 * @brief RCC registers bit address in the alias region
bogdanm 0:9b334a45a8ff 1384 * @{
bogdanm 0:9b334a45a8ff 1385 */
bogdanm 0:9b334a45a8ff 1386 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm 0:9b334a45a8ff 1387 /* --- CR Register ---*/
bogdanm 0:9b334a45a8ff 1388 /* Alias word address of HSION bit */
bogdanm 0:9b334a45a8ff 1389 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm 0:9b334a45a8ff 1390 #define RCC_HSION_BIT_NUMBER 0x00
bogdanm 0:9b334a45a8ff 1391 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1392 /* Alias word address of CSSON bit */
bogdanm 0:9b334a45a8ff 1393 #define RCC_CSSON_BIT_NUMBER 0x13
bogdanm 0:9b334a45a8ff 1394 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1395 /* Alias word address of PLLON bit */
bogdanm 0:9b334a45a8ff 1396 #define RCC_PLLON_BIT_NUMBER 0x18
bogdanm 0:9b334a45a8ff 1397 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1398 /* Alias word address of PLLI2SON bit */
bogdanm 0:9b334a45a8ff 1399 #define RCC_PLLI2SON_BIT_NUMBER 0x1A
bogdanm 0:9b334a45a8ff 1400 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1401
bogdanm 0:9b334a45a8ff 1402 /* --- CFGR Register ---*/
bogdanm 0:9b334a45a8ff 1403 /* Alias word address of I2SSRC bit */
bogdanm 0:9b334a45a8ff 1404 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm 0:9b334a45a8ff 1405 #define RCC_I2SSRC_BIT_NUMBER 0x17
bogdanm 0:9b334a45a8ff 1406 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1407
bogdanm 0:9b334a45a8ff 1408 /* --- BDCR Register ---*/
bogdanm 0:9b334a45a8ff 1409 /* Alias word address of RTCEN bit */
bogdanm 0:9b334a45a8ff 1410 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
bogdanm 0:9b334a45a8ff 1411 #define RCC_RTCEN_BIT_NUMBER 0x0F
bogdanm 0:9b334a45a8ff 1412 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1413 /* Alias word address of BDRST bit */
bogdanm 0:9b334a45a8ff 1414 #define RCC_BDRST_BIT_NUMBER 0x10
bogdanm 0:9b334a45a8ff 1415 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1416
bogdanm 0:9b334a45a8ff 1417 /* --- CSR Register ---*/
bogdanm 0:9b334a45a8ff 1418 /* Alias word address of LSION bit */
bogdanm 0:9b334a45a8ff 1419 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm 0:9b334a45a8ff 1420 #define RCC_LSION_BIT_NUMBER 0x00
bogdanm 0:9b334a45a8ff 1421 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
bogdanm 0:9b334a45a8ff 1422
bogdanm 0:9b334a45a8ff 1423 /* CR register byte 3 (Bits[23:16]) base address */
bogdanm 0:9b334a45a8ff 1424 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm 0:9b334a45a8ff 1425
bogdanm 0:9b334a45a8ff 1426 /* CIR register byte 2 (Bits[15:8]) base address */
bogdanm 0:9b334a45a8ff 1427 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
bogdanm 0:9b334a45a8ff 1428
bogdanm 0:9b334a45a8ff 1429 /* CIR register byte 3 (Bits[23:16]) base address */
bogdanm 0:9b334a45a8ff 1430 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
bogdanm 0:9b334a45a8ff 1431
bogdanm 0:9b334a45a8ff 1432 /* BDCR register base address */
bogdanm 0:9b334a45a8ff 1433 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm 0:9b334a45a8ff 1434
bogdanm 0:9b334a45a8ff 1435 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
bogdanm 0:9b334a45a8ff 1436 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
bogdanm 0:9b334a45a8ff 1437
bogdanm 0:9b334a45a8ff 1438 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
bogdanm 0:9b334a45a8ff 1439 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 1440 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 1441
bogdanm 0:9b334a45a8ff 1442 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
bogdanm 0:9b334a45a8ff 1443 #define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
bogdanm 0:9b334a45a8ff 1444 /**
bogdanm 0:9b334a45a8ff 1445 * @}
bogdanm 0:9b334a45a8ff 1446 */
bogdanm 0:9b334a45a8ff 1447
bogdanm 0:9b334a45a8ff 1448 /**
bogdanm 0:9b334a45a8ff 1449 * @}
bogdanm 0:9b334a45a8ff 1450 */
bogdanm 0:9b334a45a8ff 1451
bogdanm 0:9b334a45a8ff 1452 /* Private macros ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1453 /** @addtogroup RCC_Private_Macros RCC Private Macros
bogdanm 0:9b334a45a8ff 1454 * @{
bogdanm 0:9b334a45a8ff 1455 */
bogdanm 0:9b334a45a8ff 1456
bogdanm 0:9b334a45a8ff 1457 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
bogdanm 0:9b334a45a8ff 1458 * @{
bogdanm 0:9b334a45a8ff 1459 */
bogdanm 0:9b334a45a8ff 1460 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
bogdanm 0:9b334a45a8ff 1461
bogdanm 0:9b334a45a8ff 1462 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
bogdanm 0:9b334a45a8ff 1463 ((HSE) == RCC_HSE_BYPASS))
bogdanm 0:9b334a45a8ff 1464
bogdanm 0:9b334a45a8ff 1465 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
bogdanm 0:9b334a45a8ff 1466 ((LSE) == RCC_LSE_BYPASS))
bogdanm 0:9b334a45a8ff 1467
bogdanm 0:9b334a45a8ff 1468 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 1469
bogdanm 0:9b334a45a8ff 1470 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
bogdanm 0:9b334a45a8ff 1471
bogdanm 0:9b334a45a8ff 1472 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
bogdanm 0:9b334a45a8ff 1473
bogdanm 0:9b334a45a8ff 1474 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
bogdanm 0:9b334a45a8ff 1475 ((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm 0:9b334a45a8ff 1476
bogdanm 0:9b334a45a8ff 1477 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 0:9b334a45a8ff 1478 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 0:9b334a45a8ff 1479 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
bogdanm 0:9b334a45a8ff 1480 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
bogdanm 0:9b334a45a8ff 1481
bogdanm 0:9b334a45a8ff 1482 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm 0:9b334a45a8ff 1483
bogdanm 0:9b334a45a8ff 1484 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm 0:9b334a45a8ff 1485
bogdanm 0:9b334a45a8ff 1486 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
bogdanm 0:9b334a45a8ff 1487
bogdanm 0:9b334a45a8ff 1488 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
bogdanm 0:9b334a45a8ff 1489
bogdanm 0:9b334a45a8ff 1490 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
bogdanm 0:9b334a45a8ff 1491 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
bogdanm 0:9b334a45a8ff 1492 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
bogdanm 0:9b334a45a8ff 1493 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
bogdanm 0:9b334a45a8ff 1494 ((HCLK) == RCC_SYSCLK_DIV512))
bogdanm 0:9b334a45a8ff 1495
bogdanm 0:9b334a45a8ff 1496 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
bogdanm 0:9b334a45a8ff 1497
bogdanm 0:9b334a45a8ff 1498 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
bogdanm 0:9b334a45a8ff 1499 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
bogdanm 0:9b334a45a8ff 1500 ((PCLK) == RCC_HCLK_DIV16))
bogdanm 0:9b334a45a8ff 1501
bogdanm 0:9b334a45a8ff 1502 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
bogdanm 0:9b334a45a8ff 1503
bogdanm 0:9b334a45a8ff 1504 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
bogdanm 0:9b334a45a8ff 1505 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
bogdanm 0:9b334a45a8ff 1506
bogdanm 0:9b334a45a8ff 1507 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
bogdanm 0:9b334a45a8ff 1508 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
bogdanm 0:9b334a45a8ff 1509
bogdanm 0:9b334a45a8ff 1510 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
bogdanm 0:9b334a45a8ff 1511 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
bogdanm 0:9b334a45a8ff 1512 ((DIV) == RCC_MCODIV_5))
bogdanm 0:9b334a45a8ff 1513 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm 0:9b334a45a8ff 1514
bogdanm 0:9b334a45a8ff 1515 /**
bogdanm 0:9b334a45a8ff 1516 * @}
bogdanm 0:9b334a45a8ff 1517 */
bogdanm 0:9b334a45a8ff 1518
bogdanm 0:9b334a45a8ff 1519 /**
bogdanm 0:9b334a45a8ff 1520 * @}
bogdanm 0:9b334a45a8ff 1521 */
bogdanm 0:9b334a45a8ff 1522
bogdanm 0:9b334a45a8ff 1523 /**
bogdanm 0:9b334a45a8ff 1524 * @}
bogdanm 0:9b334a45a8ff 1525 */
bogdanm 0:9b334a45a8ff 1526
bogdanm 0:9b334a45a8ff 1527 /**
bogdanm 0:9b334a45a8ff 1528 * @}
bogdanm 0:9b334a45a8ff 1529 */
bogdanm 0:9b334a45a8ff 1530
bogdanm 0:9b334a45a8ff 1531 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 1532 }
bogdanm 0:9b334a45a8ff 1533 #endif
bogdanm 0:9b334a45a8ff 1534
bogdanm 0:9b334a45a8ff 1535 #endif /* __STM32F4xx_HAL_RCC_H */
bogdanm 0:9b334a45a8ff 1536
bogdanm 0:9b334a45a8ff 1537 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/