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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_bus.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:: <>
Date:: Thu Mar 30 13:45:57 2017 +0100
Revision:: 161:2cc1468da177
Child:: 182:a56a73fd2a6f

This updates the lib to the mbed lib v139

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	161:2cc1468da177	1	/**
<>	161:2cc1468da177	2	******************************************************************************
<>	161:2cc1468da177	3	* @file stm32f7xx_ll_bus.h
<>	161:2cc1468da177	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	161:2cc1468da177	7	* @brief Header file of BUS LL module.
<>	161:2cc1468da177	8
<>	161:2cc1468da177	9	@verbatim
<>	161:2cc1468da177	10	##### RCC Limitations #####
<>	161:2cc1468da177	11	==============================================================================
<>	161:2cc1468da177	12	[..]
<>	161:2cc1468da177	13	A delay between an RCC peripheral clock enable and the effective peripheral
<>	161:2cc1468da177	14	enabling should be taken into account in order to manage the peripheral read/write
<>	161:2cc1468da177	15	from/to registers.
<>	161:2cc1468da177	16	(+) This delay depends on the peripheral mapping.
<>	161:2cc1468da177	17	(++) AHB & APB peripherals, 1 dummy read is necessary
<>	161:2cc1468da177	18
<>	161:2cc1468da177	19	[..]
<>	161:2cc1468da177	20	Workarounds:
<>	161:2cc1468da177	21	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<>	161:2cc1468da177	22	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
<>	161:2cc1468da177	23
<>	161:2cc1468da177	24	@endverbatim
<>	161:2cc1468da177	25	******************************************************************************
<>	161:2cc1468da177	26	* @attention
<>	161:2cc1468da177	27	*
<>	161:2cc1468da177	28	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	161:2cc1468da177	29	*
<>	161:2cc1468da177	30	* Redistribution and use in source and binary forms, with or without modification,
<>	161:2cc1468da177	31	* are permitted provided that the following conditions are met:
<>	161:2cc1468da177	32	* 1. Redistributions of source code must retain the above copyright notice,
<>	161:2cc1468da177	33	* this list of conditions and the following disclaimer.
<>	161:2cc1468da177	34	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	161:2cc1468da177	35	* this list of conditions and the following disclaimer in the documentation
<>	161:2cc1468da177	36	* and/or other materials provided with the distribution.
<>	161:2cc1468da177	37	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	161:2cc1468da177	38	* may be used to endorse or promote products derived from this software
<>	161:2cc1468da177	39	* without specific prior written permission.
<>	161:2cc1468da177	40	*
<>	161:2cc1468da177	41	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	161:2cc1468da177	42	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	161:2cc1468da177	43	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	161:2cc1468da177	44	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	161:2cc1468da177	45	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	161:2cc1468da177	46	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	161:2cc1468da177	47	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	161:2cc1468da177	48	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	161:2cc1468da177	49	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	161:2cc1468da177	50	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	161:2cc1468da177	51	*
<>	161:2cc1468da177	52	******************************************************************************
<>	161:2cc1468da177	53	*/
<>	161:2cc1468da177	54
<>	161:2cc1468da177	55	/* Define to prevent recursive inclusion -------------------------------------*/
<>	161:2cc1468da177	56	#ifndef __STM32F7xx_LL_BUS_H
<>	161:2cc1468da177	57	#define __STM32F7xx_LL_BUS_H
<>	161:2cc1468da177	58
<>	161:2cc1468da177	59	#ifdef __cplusplus
<>	161:2cc1468da177	60	extern "C" {
<>	161:2cc1468da177	61	#endif
<>	161:2cc1468da177	62
<>	161:2cc1468da177	63	/* Includes ------------------------------------------------------------------*/
<>	161:2cc1468da177	64	#include "stm32f7xx.h"
<>	161:2cc1468da177	65
<>	161:2cc1468da177	66	/** @addtogroup STM32F7xx_LL_Driver
<>	161:2cc1468da177	67	* @{
<>	161:2cc1468da177	68	*/
<>	161:2cc1468da177	69
<>	161:2cc1468da177	70	#if defined(RCC)
<>	161:2cc1468da177	71
<>	161:2cc1468da177	72	/** @defgroup BUS_LL BUS
<>	161:2cc1468da177	73	* @{
<>	161:2cc1468da177	74	*/
<>	161:2cc1468da177	75
<>	161:2cc1468da177	76	/* Private types -------------------------------------------------------------*/
<>	161:2cc1468da177	77	/* Private variables ---------------------------------------------------------*/
<>	161:2cc1468da177	78	/* Private constants ---------------------------------------------------------*/
<>	161:2cc1468da177	79	/* Private macros ------------------------------------------------------------*/
<>	161:2cc1468da177	80	/* Exported types ------------------------------------------------------------*/
<>	161:2cc1468da177	81	/* Exported constants --------------------------------------------------------*/
<>	161:2cc1468da177	82	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
<>	161:2cc1468da177	83	* @{
<>	161:2cc1468da177	84	*/
<>	161:2cc1468da177	85
<>	161:2cc1468da177	86	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
<>	161:2cc1468da177	87	* @{
<>	161:2cc1468da177	88	*/
<>	161:2cc1468da177	89	#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
<>	161:2cc1468da177	90	#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
<>	161:2cc1468da177	91	#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
<>	161:2cc1468da177	92	#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
<>	161:2cc1468da177	93	#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
<>	161:2cc1468da177	94	#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
<>	161:2cc1468da177	95	#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
<>	161:2cc1468da177	96	#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
<>	161:2cc1468da177	97	#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
<>	161:2cc1468da177	98	#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
<>	161:2cc1468da177	99	#if defined(GPIOJ)
<>	161:2cc1468da177	100	#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
<>	161:2cc1468da177	101	#endif /* GPIOJ */
<>	161:2cc1468da177	102	#if defined(GPIOK)
<>	161:2cc1468da177	103	#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
<>	161:2cc1468da177	104	#endif /* GPIOK */
<>	161:2cc1468da177	105	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
<>	161:2cc1468da177	106	#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
<>	161:2cc1468da177	107	#define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN
<>	161:2cc1468da177	108	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
<>	161:2cc1468da177	109	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
<>	161:2cc1468da177	110	#if defined(DMA2D)
<>	161:2cc1468da177	111	#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
<>	161:2cc1468da177	112	#endif /* DMA2D */
<>	161:2cc1468da177	113	#if defined(ETH)
<>	161:2cc1468da177	114	#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
<>	161:2cc1468da177	115	#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
<>	161:2cc1468da177	116	#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
<>	161:2cc1468da177	117	#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
<>	161:2cc1468da177	118	#endif /* ETH */
<>	161:2cc1468da177	119	#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
<>	161:2cc1468da177	120	#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
<>	161:2cc1468da177	121	#define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN
<>	161:2cc1468da177	122	#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
<>	161:2cc1468da177	123	#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
<>	161:2cc1468da177	124	#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
<>	161:2cc1468da177	125	/**
<>	161:2cc1468da177	126	* @}
<>	161:2cc1468da177	127	*/
<>	161:2cc1468da177	128
<>	161:2cc1468da177	129	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
<>	161:2cc1468da177	130	* @{
<>	161:2cc1468da177	131	*/
<>	161:2cc1468da177	132	#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
<>	161:2cc1468da177	133	#if defined(DCMI)
<>	161:2cc1468da177	134	#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
<>	161:2cc1468da177	135	#endif /* DCMI */
<>	161:2cc1468da177	136	#if defined(JPEG)
<>	161:2cc1468da177	137	#define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN
<>	161:2cc1468da177	138	#endif /* JPEG */
<>	161:2cc1468da177	139	#if defined(CRYP)
<>	161:2cc1468da177	140	#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
<>	161:2cc1468da177	141	#endif /* CRYP */
<>	161:2cc1468da177	142	#if defined(AES)
<>	161:2cc1468da177	143	#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
<>	161:2cc1468da177	144	#endif /* AES */
<>	161:2cc1468da177	145	#if defined(HASH)
<>	161:2cc1468da177	146	#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
<>	161:2cc1468da177	147	#endif /* HASH */
<>	161:2cc1468da177	148	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
<>	161:2cc1468da177	149	#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
<>	161:2cc1468da177	150	/**
<>	161:2cc1468da177	151	* @}
<>	161:2cc1468da177	152	*/
<>	161:2cc1468da177	153
<>	161:2cc1468da177	154	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
<>	161:2cc1468da177	155	* @{
<>	161:2cc1468da177	156	*/
<>	161:2cc1468da177	157	#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
<>	161:2cc1468da177	158	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
<>	161:2cc1468da177	159	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
<>	161:2cc1468da177	160	/**
<>	161:2cc1468da177	161	* @}
<>	161:2cc1468da177	162	*/
<>	161:2cc1468da177	163
<>	161:2cc1468da177	164	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
<>	161:2cc1468da177	165	* @{
<>	161:2cc1468da177	166	*/
<>	161:2cc1468da177	167	#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
<>	161:2cc1468da177	168	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
<>	161:2cc1468da177	169	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
<>	161:2cc1468da177	170	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
<>	161:2cc1468da177	171	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
<>	161:2cc1468da177	172	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
<>	161:2cc1468da177	173	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
<>	161:2cc1468da177	174	#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
<>	161:2cc1468da177	175	#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
<>	161:2cc1468da177	176	#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
<>	161:2cc1468da177	177	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
<>	161:2cc1468da177	178	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
<>	161:2cc1468da177	179	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
<>	161:2cc1468da177	180	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
<>	161:2cc1468da177	181	#if defined(SPDIFRX)
<>	161:2cc1468da177	182	#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
<>	161:2cc1468da177	183	#endif /* SPDIFRX */
<>	161:2cc1468da177	184	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
<>	161:2cc1468da177	185	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
<>	161:2cc1468da177	186	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
<>	161:2cc1468da177	187	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
<>	161:2cc1468da177	188	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
<>	161:2cc1468da177	189	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
<>	161:2cc1468da177	190	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
<>	161:2cc1468da177	191	#if defined(I2C4)
<>	161:2cc1468da177	192	#define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN
<>	161:2cc1468da177	193	#endif /* I2C4 */
<>	161:2cc1468da177	194	#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
<>	161:2cc1468da177	195	#if defined(CAN2)
<>	161:2cc1468da177	196	#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
<>	161:2cc1468da177	197	#endif /* CAN2 */
<>	161:2cc1468da177	198	#if defined(CAN3)
<>	161:2cc1468da177	199	#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
<>	161:2cc1468da177	200	#endif /* CAN3 */
<>	161:2cc1468da177	201	#if defined(CEC)
<>	161:2cc1468da177	202	#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
<>	161:2cc1468da177	203	#endif /* CEC */
<>	161:2cc1468da177	204	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
<>	161:2cc1468da177	205	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
<>	161:2cc1468da177	206	#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
<>	161:2cc1468da177	207	#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
<>	161:2cc1468da177	208	#if defined(RCC_APB1ENR_RTCEN)
<>	161:2cc1468da177	209	#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN
<>	161:2cc1468da177	210	#endif /* RCC_APB1ENR_RTCEN */
<>	161:2cc1468da177	211	/**
<>	161:2cc1468da177	212	* @}
<>	161:2cc1468da177	213	*/
<>	161:2cc1468da177	214
<>	161:2cc1468da177	215	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
<>	161:2cc1468da177	216	* @{
<>	161:2cc1468da177	217	*/
<>	161:2cc1468da177	218	#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
<>	161:2cc1468da177	219	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
<>	161:2cc1468da177	220	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
<>	161:2cc1468da177	221	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
<>	161:2cc1468da177	222	#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
<>	161:2cc1468da177	223	#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
<>	161:2cc1468da177	224	#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
<>	161:2cc1468da177	225	#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
<>	161:2cc1468da177	226	#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
<>	161:2cc1468da177	227	#if defined(SDMMC2)
<>	161:2cc1468da177	228	#define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN
<>	161:2cc1468da177	229	#endif /* SDMMC2 */
<>	161:2cc1468da177	230	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
<>	161:2cc1468da177	231	#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
<>	161:2cc1468da177	232	#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
<>	161:2cc1468da177	233	#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
<>	161:2cc1468da177	234	#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
<>	161:2cc1468da177	235	#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
<>	161:2cc1468da177	236	#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
<>	161:2cc1468da177	237	#if defined(SPI6)
<>	161:2cc1468da177	238	#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
<>	161:2cc1468da177	239	#endif /* SPI6 */
<>	161:2cc1468da177	240	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
<>	161:2cc1468da177	241	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
<>	161:2cc1468da177	242	#if defined(LTDC)
<>	161:2cc1468da177	243	#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
<>	161:2cc1468da177	244	#endif /* LTDC */
<>	161:2cc1468da177	245	#if defined(DSI)
<>	161:2cc1468da177	246	#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
<>	161:2cc1468da177	247	#endif /* DSI */
<>	161:2cc1468da177	248	#if defined(DFSDM1_Channel0)
<>	161:2cc1468da177	249	#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
<>	161:2cc1468da177	250	#endif /* DFSDM1_Channel0 */
<>	161:2cc1468da177	251	#if defined(MDIOS)
<>	161:2cc1468da177	252	#define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN
<>	161:2cc1468da177	253	#endif /* MDIOS */
<>	161:2cc1468da177	254	#if defined(USB_HS_PHYC)
<>	161:2cc1468da177	255	#define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN
<>	161:2cc1468da177	256	#endif /* USB_HS_PHYC */
<>	161:2cc1468da177	257	#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
<>	161:2cc1468da177	258	/**
<>	161:2cc1468da177	259	* @}
<>	161:2cc1468da177	260	*/
<>	161:2cc1468da177	261
<>	161:2cc1468da177	262	/**
<>	161:2cc1468da177	263	* @}
<>	161:2cc1468da177	264	*/
<>	161:2cc1468da177	265
<>	161:2cc1468da177	266	/* Exported macro ------------------------------------------------------------*/
<>	161:2cc1468da177	267	/* Exported functions --------------------------------------------------------*/
<>	161:2cc1468da177	268	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
<>	161:2cc1468da177	269	* @{
<>	161:2cc1468da177	270	*/
<>	161:2cc1468da177	271
<>	161:2cc1468da177	272	/** @defgroup BUS_LL_EF_AHB1 AHB1
<>	161:2cc1468da177	273	* @{
<>	161:2cc1468da177	274	*/
<>	161:2cc1468da177	275
<>	161:2cc1468da177	276	/**
<>	161:2cc1468da177	277	* @brief Enable AHB1 peripherals clock.
<>	161:2cc1468da177	278	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	279	* AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	280	* AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	281	* AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	282	* AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	283	* AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	284	* AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	285	* AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	286	* AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	287	* AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	288	* AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	289	* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	290	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	291	* AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	292	* AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	293	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	294	* AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	295	* AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	296	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	297	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	298	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	299	* AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
<>	161:2cc1468da177	300	* AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
<>	161:2cc1468da177	301	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	302	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<>	161:2cc1468da177	303	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<>	161:2cc1468da177	304	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<>	161:2cc1468da177	305	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<>	161:2cc1468da177	306	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
<>	161:2cc1468da177	307	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<>	161:2cc1468da177	308	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
<>	161:2cc1468da177	309	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<>	161:2cc1468da177	310	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
<>	161:2cc1468da177	311	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
<>	161:2cc1468da177	312	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
<>	161:2cc1468da177	313	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<>	161:2cc1468da177	314	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
<>	161:2cc1468da177	315	* @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
<>	161:2cc1468da177	316	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<>	161:2cc1468da177	317	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
<>	161:2cc1468da177	318	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
<>	161:2cc1468da177	319	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
<>	161:2cc1468da177	320	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
<>	161:2cc1468da177	321	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
<>	161:2cc1468da177	322	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
<>	161:2cc1468da177	323	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
<>	161:2cc1468da177	324	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
<>	161:2cc1468da177	325	*
<>	161:2cc1468da177	326	* (*) value not defined in all devices.
<>	161:2cc1468da177	327	* @retval None
<>	161:2cc1468da177	328	*/
<>	161:2cc1468da177	329	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
<>	161:2cc1468da177	330	{
<>	161:2cc1468da177	331	__IO uint32_t tmpreg;
<>	161:2cc1468da177	332	SET_BIT(RCC->AHB1ENR, Periphs);
<>	161:2cc1468da177	333	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	334	tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
<>	161:2cc1468da177	335	(void)tmpreg;
<>	161:2cc1468da177	336	}
<>	161:2cc1468da177	337
<>	161:2cc1468da177	338	/**
<>	161:2cc1468da177	339	* @brief Check if AHB1 peripheral clock is enabled or not
<>	161:2cc1468da177	340	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	341	* AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	342	* AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	343	* AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	344	* AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	345	* AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	346	* AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	347	* AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	348	* AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	349	* AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	350	* AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	351	* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	352	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	353	* AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	354	* AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	355	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	356	* AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	357	* AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	358	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	359	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	360	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	361	* AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	362	* AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock
<>	161:2cc1468da177	363	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	364	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<>	161:2cc1468da177	365	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<>	161:2cc1468da177	366	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<>	161:2cc1468da177	367	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<>	161:2cc1468da177	368	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
<>	161:2cc1468da177	369	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<>	161:2cc1468da177	370	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
<>	161:2cc1468da177	371	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<>	161:2cc1468da177	372	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
<>	161:2cc1468da177	373	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
<>	161:2cc1468da177	374	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
<>	161:2cc1468da177	375	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<>	161:2cc1468da177	376	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
<>	161:2cc1468da177	377	* @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
<>	161:2cc1468da177	378	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<>	161:2cc1468da177	379	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
<>	161:2cc1468da177	380	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
<>	161:2cc1468da177	381	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
<>	161:2cc1468da177	382	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
<>	161:2cc1468da177	383	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
<>	161:2cc1468da177	384	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
<>	161:2cc1468da177	385	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
<>	161:2cc1468da177	386	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
<>	161:2cc1468da177	387	*
<>	161:2cc1468da177	388	* (*) value not defined in all devices.
<>	161:2cc1468da177	389	* @retval State of Periphs (1 or 0).
<>	161:2cc1468da177	390	*/
<>	161:2cc1468da177	391	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
<>	161:2cc1468da177	392	{
<>	161:2cc1468da177	393	return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
<>	161:2cc1468da177	394	}
<>	161:2cc1468da177	395
<>	161:2cc1468da177	396	/**
<>	161:2cc1468da177	397	* @brief Disable AHB1 peripherals clock.
<>	161:2cc1468da177	398	* @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	399	* AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	400	* AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	401	* AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	402	* AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	403	* AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	404	* AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	405	* AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	406	* AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	407	* AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	408	* AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	409	* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	410	* AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	411	* AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	412	* AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	413	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	414	* AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	415	* AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	416	* AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	417	* AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	418	* AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	419	* AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
<>	161:2cc1468da177	420	* AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock
<>	161:2cc1468da177	421	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	422	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<>	161:2cc1468da177	423	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<>	161:2cc1468da177	424	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<>	161:2cc1468da177	425	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<>	161:2cc1468da177	426	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
<>	161:2cc1468da177	427	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<>	161:2cc1468da177	428	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
<>	161:2cc1468da177	429	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<>	161:2cc1468da177	430	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
<>	161:2cc1468da177	431	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
<>	161:2cc1468da177	432	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
<>	161:2cc1468da177	433	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<>	161:2cc1468da177	434	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
<>	161:2cc1468da177	435	* @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
<>	161:2cc1468da177	436	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<>	161:2cc1468da177	437	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
<>	161:2cc1468da177	438	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
<>	161:2cc1468da177	439	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
<>	161:2cc1468da177	440	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
<>	161:2cc1468da177	441	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
<>	161:2cc1468da177	442	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
<>	161:2cc1468da177	443	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
<>	161:2cc1468da177	444	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
<>	161:2cc1468da177	445	*
<>	161:2cc1468da177	446	* (*) value not defined in all devices.
<>	161:2cc1468da177	447	* @retval None
<>	161:2cc1468da177	448	*/
<>	161:2cc1468da177	449	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
<>	161:2cc1468da177	450	{
<>	161:2cc1468da177	451	CLEAR_BIT(RCC->AHB1ENR, Periphs);
<>	161:2cc1468da177	452	}
<>	161:2cc1468da177	453
<>	161:2cc1468da177	454	/**
<>	161:2cc1468da177	455	* @brief Force AHB1 peripherals reset.
<>	161:2cc1468da177	456	* @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	457	* AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	458	* AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	459	* AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	460	* AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	461	* AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	462	* AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	463	* AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	464	* AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	465	* AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	466	* AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	467	* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	468	* AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	469	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	470	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	471	* AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
<>	161:2cc1468da177	472	* AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
<>	161:2cc1468da177	473	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	474	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<>	161:2cc1468da177	475	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<>	161:2cc1468da177	476	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<>	161:2cc1468da177	477	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<>	161:2cc1468da177	478	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<>	161:2cc1468da177	479	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
<>	161:2cc1468da177	480	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<>	161:2cc1468da177	481	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
<>	161:2cc1468da177	482	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<>	161:2cc1468da177	483	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
<>	161:2cc1468da177	484	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
<>	161:2cc1468da177	485	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
<>	161:2cc1468da177	486	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<>	161:2cc1468da177	487	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<>	161:2cc1468da177	488	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
<>	161:2cc1468da177	489	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
<>	161:2cc1468da177	490	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
<>	161:2cc1468da177	491	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
<>	161:2cc1468da177	492	*
<>	161:2cc1468da177	493	* (*) value not defined in all devices.
<>	161:2cc1468da177	494	* @retval None
<>	161:2cc1468da177	495	*/
<>	161:2cc1468da177	496	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
<>	161:2cc1468da177	497	{
<>	161:2cc1468da177	498	SET_BIT(RCC->AHB1RSTR, Periphs);
<>	161:2cc1468da177	499	}
<>	161:2cc1468da177	500
<>	161:2cc1468da177	501	/**
<>	161:2cc1468da177	502	* @brief Release AHB1 peripherals reset.
<>	161:2cc1468da177	503	* @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	504	* AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	505	* AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	506	* AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	507	* AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	508	* AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	509	* AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	510	* AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	511	* AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	512	* AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	513	* AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	514	* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	515	* AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	516	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	517	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	518	* AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	519	* AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
<>	161:2cc1468da177	520	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	521	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<>	161:2cc1468da177	522	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<>	161:2cc1468da177	523	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<>	161:2cc1468da177	524	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<>	161:2cc1468da177	525	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<>	161:2cc1468da177	526	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
<>	161:2cc1468da177	527	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<>	161:2cc1468da177	528	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
<>	161:2cc1468da177	529	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<>	161:2cc1468da177	530	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
<>	161:2cc1468da177	531	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
<>	161:2cc1468da177	532	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
<>	161:2cc1468da177	533	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<>	161:2cc1468da177	534	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<>	161:2cc1468da177	535	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
<>	161:2cc1468da177	536	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
<>	161:2cc1468da177	537	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
<>	161:2cc1468da177	538	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
<>	161:2cc1468da177	539	*
<>	161:2cc1468da177	540	* (*) value not defined in all devices.
<>	161:2cc1468da177	541	* @retval None
<>	161:2cc1468da177	542	*/
<>	161:2cc1468da177	543	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
<>	161:2cc1468da177	544	{
<>	161:2cc1468da177	545	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
<>	161:2cc1468da177	546	}
<>	161:2cc1468da177	547
<>	161:2cc1468da177	548	/**
<>	161:2cc1468da177	549	* @brief Enable AHB1 peripheral clocks in low-power mode
<>	161:2cc1468da177	550	* @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	551	* AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	552	* AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	553	* AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	554	* AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	555	* AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	556	* AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	557	* AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	558	* AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	559	* AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	560	* AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	561	* AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	562	* AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	563	* AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	564	* AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	565	* AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	566	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	567	* AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	568	* AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	569	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	570	* AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	571	* AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	572	* AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	573	* AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	574	* AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	575	* AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	576	* AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
<>	161:2cc1468da177	577	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	578	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<>	161:2cc1468da177	579	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<>	161:2cc1468da177	580	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<>	161:2cc1468da177	581	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<>	161:2cc1468da177	582	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
<>	161:2cc1468da177	583	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<>	161:2cc1468da177	584	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
<>	161:2cc1468da177	585	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<>	161:2cc1468da177	586	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
<>	161:2cc1468da177	587	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
<>	161:2cc1468da177	588	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
<>	161:2cc1468da177	589	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<>	161:2cc1468da177	590	* @arg @ref LL_AHB1_GRP1_PERIPH_AXI
<>	161:2cc1468da177	591	* @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
<>	161:2cc1468da177	592	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
<>	161:2cc1468da177	593	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
<>	161:2cc1468da177	594	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
<>	161:2cc1468da177	595	* @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
<>	161:2cc1468da177	596	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<>	161:2cc1468da177	597	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
<>	161:2cc1468da177	598	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
<>	161:2cc1468da177	599	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
<>	161:2cc1468da177	600	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
<>	161:2cc1468da177	601	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
<>	161:2cc1468da177	602	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
<>	161:2cc1468da177	603	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
<>	161:2cc1468da177	604	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
<>	161:2cc1468da177	605	*
<>	161:2cc1468da177	606	* (*) value not defined in all devices.
<>	161:2cc1468da177	607	* @retval None
<>	161:2cc1468da177	608	*/
<>	161:2cc1468da177	609	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	610	{
<>	161:2cc1468da177	611	__IO uint32_t tmpreg;
<>	161:2cc1468da177	612	SET_BIT(RCC->AHB1LPENR, Periphs);
<>	161:2cc1468da177	613	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	614	tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
<>	161:2cc1468da177	615	(void)tmpreg;
<>	161:2cc1468da177	616	}
<>	161:2cc1468da177	617
<>	161:2cc1468da177	618	/**
<>	161:2cc1468da177	619	* @brief Disable AHB1 peripheral clocks in low-power mode
<>	161:2cc1468da177	620	* @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	621	* AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	622	* AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	623	* AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	624	* AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	625	* AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	626	* AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	627	* AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	628	* AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	629	* AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	630	* AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	631	* AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	632	* AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	633	* AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	634	* AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	635	* AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	636	* AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	637	* AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	638	* AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	639	* AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	640	* AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	641	* AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	642	* AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	643	* AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	644	* AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	645	* AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	646	* AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
<>	161:2cc1468da177	647	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	648	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<>	161:2cc1468da177	649	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<>	161:2cc1468da177	650	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<>	161:2cc1468da177	651	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<>	161:2cc1468da177	652	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
<>	161:2cc1468da177	653	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
<>	161:2cc1468da177	654	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
<>	161:2cc1468da177	655	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<>	161:2cc1468da177	656	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
<>	161:2cc1468da177	657	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
<>	161:2cc1468da177	658	* @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
<>	161:2cc1468da177	659	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<>	161:2cc1468da177	660	* @arg @ref LL_AHB1_GRP1_PERIPH_AXI
<>	161:2cc1468da177	661	* @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
<>	161:2cc1468da177	662	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
<>	161:2cc1468da177	663	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
<>	161:2cc1468da177	664	* @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
<>	161:2cc1468da177	665	* @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
<>	161:2cc1468da177	666	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<>	161:2cc1468da177	667	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
<>	161:2cc1468da177	668	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
<>	161:2cc1468da177	669	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
<>	161:2cc1468da177	670	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
<>	161:2cc1468da177	671	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
<>	161:2cc1468da177	672	* @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
<>	161:2cc1468da177	673	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
<>	161:2cc1468da177	674	* @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
<>	161:2cc1468da177	675	*
<>	161:2cc1468da177	676	* (*) value not defined in all devices.
<>	161:2cc1468da177	677	* @retval None
<>	161:2cc1468da177	678	*/
<>	161:2cc1468da177	679	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	680	{
<>	161:2cc1468da177	681	CLEAR_BIT(RCC->AHB1LPENR, Periphs);
<>	161:2cc1468da177	682	}
<>	161:2cc1468da177	683
<>	161:2cc1468da177	684	/**
<>	161:2cc1468da177	685	* @}
<>	161:2cc1468da177	686	*/
<>	161:2cc1468da177	687
<>	161:2cc1468da177	688	/** @defgroup BUS_LL_EF_AHB2 AHB2
<>	161:2cc1468da177	689	* @{
<>	161:2cc1468da177	690	*/
<>	161:2cc1468da177	691
<>	161:2cc1468da177	692	/**
<>	161:2cc1468da177	693	* @brief Enable AHB2 peripherals clock.
<>	161:2cc1468da177	694	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
<>	161:2cc1468da177	695	* AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n
<>	161:2cc1468da177	696	* AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
<>	161:2cc1468da177	697	* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
<>	161:2cc1468da177	698	* AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
<>	161:2cc1468da177	699	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
<>	161:2cc1468da177	700	* AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
<>	161:2cc1468da177	701	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	702	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
<>	161:2cc1468da177	703	* @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
<>	161:2cc1468da177	704	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
<>	161:2cc1468da177	705	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
<>	161:2cc1468da177	706	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
<>	161:2cc1468da177	707	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
<>	161:2cc1468da177	708	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
<>	161:2cc1468da177	709	*
<>	161:2cc1468da177	710	* (*) value not defined in all devices.
<>	161:2cc1468da177	711	* @retval None
<>	161:2cc1468da177	712	*/
<>	161:2cc1468da177	713	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
<>	161:2cc1468da177	714	{
<>	161:2cc1468da177	715	__IO uint32_t tmpreg;
<>	161:2cc1468da177	716	SET_BIT(RCC->AHB2ENR, Periphs);
<>	161:2cc1468da177	717	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	718	tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
<>	161:2cc1468da177	719	(void)tmpreg;
<>	161:2cc1468da177	720	}
<>	161:2cc1468da177	721
<>	161:2cc1468da177	722	/**
<>	161:2cc1468da177	723	* @brief Check if AHB2 peripheral clock is enabled or not
<>	161:2cc1468da177	724	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	725	* AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	726	* AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	727	* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	728	* AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	729	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	730	* AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
<>	161:2cc1468da177	731	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	732	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
<>	161:2cc1468da177	733	* @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
<>	161:2cc1468da177	734	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
<>	161:2cc1468da177	735	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
<>	161:2cc1468da177	736	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
<>	161:2cc1468da177	737	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
<>	161:2cc1468da177	738	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
<>	161:2cc1468da177	739	*
<>	161:2cc1468da177	740	* (*) value not defined in all devices.
<>	161:2cc1468da177	741	* @retval State of Periphs (1 or 0).
<>	161:2cc1468da177	742	*/
<>	161:2cc1468da177	743	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
<>	161:2cc1468da177	744	{
<>	161:2cc1468da177	745	return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
<>	161:2cc1468da177	746	}
<>	161:2cc1468da177	747
<>	161:2cc1468da177	748	/**
<>	161:2cc1468da177	749	* @brief Disable AHB2 peripherals clock.
<>	161:2cc1468da177	750	* @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
<>	161:2cc1468da177	751	* AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n
<>	161:2cc1468da177	752	* AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
<>	161:2cc1468da177	753	* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
<>	161:2cc1468da177	754	* AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
<>	161:2cc1468da177	755	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
<>	161:2cc1468da177	756	* AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
<>	161:2cc1468da177	757	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	758	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
<>	161:2cc1468da177	759	* @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
<>	161:2cc1468da177	760	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
<>	161:2cc1468da177	761	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
<>	161:2cc1468da177	762	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
<>	161:2cc1468da177	763	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
<>	161:2cc1468da177	764	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
<>	161:2cc1468da177	765	*
<>	161:2cc1468da177	766	* (*) value not defined in all devices.
<>	161:2cc1468da177	767	* @retval None
<>	161:2cc1468da177	768	*/
<>	161:2cc1468da177	769	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
<>	161:2cc1468da177	770	{
<>	161:2cc1468da177	771	CLEAR_BIT(RCC->AHB2ENR, Periphs);
<>	161:2cc1468da177	772	}
<>	161:2cc1468da177	773
<>	161:2cc1468da177	774	/**
<>	161:2cc1468da177	775	* @brief Force AHB2 peripherals reset.
<>	161:2cc1468da177	776	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
<>	161:2cc1468da177	777	* AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n
<>	161:2cc1468da177	778	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
<>	161:2cc1468da177	779	* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
<>	161:2cc1468da177	780	* AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
<>	161:2cc1468da177	781	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
<>	161:2cc1468da177	782	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
<>	161:2cc1468da177	783	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	784	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
<>	161:2cc1468da177	785	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
<>	161:2cc1468da177	786	* @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
<>	161:2cc1468da177	787	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
<>	161:2cc1468da177	788	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
<>	161:2cc1468da177	789	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
<>	161:2cc1468da177	790	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
<>	161:2cc1468da177	791	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
<>	161:2cc1468da177	792	*
<>	161:2cc1468da177	793	* (*) value not defined in all devices.
<>	161:2cc1468da177	794	* @retval None
<>	161:2cc1468da177	795	*/
<>	161:2cc1468da177	796	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
<>	161:2cc1468da177	797	{
<>	161:2cc1468da177	798	SET_BIT(RCC->AHB2RSTR, Periphs);
<>	161:2cc1468da177	799	}
<>	161:2cc1468da177	800
<>	161:2cc1468da177	801	/**
<>	161:2cc1468da177	802	* @brief Release AHB2 peripherals reset.
<>	161:2cc1468da177	803	* @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	804	* AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	805	* AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	806	* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	807	* AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	808	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	809	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
<>	161:2cc1468da177	810	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	811	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
<>	161:2cc1468da177	812	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
<>	161:2cc1468da177	813	* @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
<>	161:2cc1468da177	814	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
<>	161:2cc1468da177	815	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
<>	161:2cc1468da177	816	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
<>	161:2cc1468da177	817	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
<>	161:2cc1468da177	818	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
<>	161:2cc1468da177	819	*
<>	161:2cc1468da177	820	* (*) value not defined in all devices.
<>	161:2cc1468da177	821	* @retval None
<>	161:2cc1468da177	822	*/
<>	161:2cc1468da177	823	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
<>	161:2cc1468da177	824	{
<>	161:2cc1468da177	825	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
<>	161:2cc1468da177	826	}
<>	161:2cc1468da177	827
<>	161:2cc1468da177	828	/**
<>	161:2cc1468da177	829	* @brief Enable AHB2 peripheral clocks in low-power mode
<>	161:2cc1468da177	830	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	831	* AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	832	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	833	* AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	834	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	835	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	836	* AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
<>	161:2cc1468da177	837	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	838	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
<>	161:2cc1468da177	839	* @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
<>	161:2cc1468da177	840	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
<>	161:2cc1468da177	841	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
<>	161:2cc1468da177	842	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
<>	161:2cc1468da177	843	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
<>	161:2cc1468da177	844	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
<>	161:2cc1468da177	845	*
<>	161:2cc1468da177	846	* (*) value not defined in all devices.
<>	161:2cc1468da177	847	* @retval None
<>	161:2cc1468da177	848	*/
<>	161:2cc1468da177	849	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	850	{
<>	161:2cc1468da177	851	__IO uint32_t tmpreg;
<>	161:2cc1468da177	852	SET_BIT(RCC->AHB2LPENR, Periphs);
<>	161:2cc1468da177	853	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	854	tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
<>	161:2cc1468da177	855	(void)tmpreg;
<>	161:2cc1468da177	856	}
<>	161:2cc1468da177	857
<>	161:2cc1468da177	858	/**
<>	161:2cc1468da177	859	* @brief Disable AHB2 peripheral clocks in low-power mode
<>	161:2cc1468da177	860	* @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	861	* AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	862	* AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	863	* AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	864	* AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	865	* AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	866	* AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
<>	161:2cc1468da177	867	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	868	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
<>	161:2cc1468da177	869	* @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
<>	161:2cc1468da177	870	* @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
<>	161:2cc1468da177	871	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
<>	161:2cc1468da177	872	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
<>	161:2cc1468da177	873	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
<>	161:2cc1468da177	874	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
<>	161:2cc1468da177	875	*
<>	161:2cc1468da177	876	* (*) value not defined in all devices.
<>	161:2cc1468da177	877	* @retval None
<>	161:2cc1468da177	878	*/
<>	161:2cc1468da177	879	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	880	{
<>	161:2cc1468da177	881	CLEAR_BIT(RCC->AHB2LPENR, Periphs);
<>	161:2cc1468da177	882	}
<>	161:2cc1468da177	883
<>	161:2cc1468da177	884	/**
<>	161:2cc1468da177	885	* @}
<>	161:2cc1468da177	886	*/
<>	161:2cc1468da177	887
<>	161:2cc1468da177	888	/** @defgroup BUS_LL_EF_AHB3 AHB3
<>	161:2cc1468da177	889	* @{
<>	161:2cc1468da177	890	*/
<>	161:2cc1468da177	891
<>	161:2cc1468da177	892	/**
<>	161:2cc1468da177	893	* @brief Enable AHB3 peripherals clock.
<>	161:2cc1468da177	894	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
<>	161:2cc1468da177	895	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
<>	161:2cc1468da177	896	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	897	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
<>	161:2cc1468da177	898	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
<>	161:2cc1468da177	899	*
<>	161:2cc1468da177	900	* (*) value not defined in all devices.
<>	161:2cc1468da177	901	* @retval None
<>	161:2cc1468da177	902	*/
<>	161:2cc1468da177	903	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
<>	161:2cc1468da177	904	{
<>	161:2cc1468da177	905	__IO uint32_t tmpreg;
<>	161:2cc1468da177	906	SET_BIT(RCC->AHB3ENR, Periphs);
<>	161:2cc1468da177	907	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	908	tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
<>	161:2cc1468da177	909	(void)tmpreg;
<>	161:2cc1468da177	910	}
<>	161:2cc1468da177	911
<>	161:2cc1468da177	912	/**
<>	161:2cc1468da177	913	* @brief Check if AHB3 peripheral clock is enabled or not
<>	161:2cc1468da177	914	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	915	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
<>	161:2cc1468da177	916	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	917	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
<>	161:2cc1468da177	918	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
<>	161:2cc1468da177	919	*
<>	161:2cc1468da177	920	* (*) value not defined in all devices.
<>	161:2cc1468da177	921	* @retval State of Periphs (1 or 0).
<>	161:2cc1468da177	922	*/
<>	161:2cc1468da177	923	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
<>	161:2cc1468da177	924	{
<>	161:2cc1468da177	925	return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
<>	161:2cc1468da177	926	}
<>	161:2cc1468da177	927
<>	161:2cc1468da177	928	/**
<>	161:2cc1468da177	929	* @brief Disable AHB3 peripherals clock.
<>	161:2cc1468da177	930	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
<>	161:2cc1468da177	931	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
<>	161:2cc1468da177	932	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	933	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
<>	161:2cc1468da177	934	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
<>	161:2cc1468da177	935	*
<>	161:2cc1468da177	936	* (*) value not defined in all devices.
<>	161:2cc1468da177	937	* @retval None
<>	161:2cc1468da177	938	*/
<>	161:2cc1468da177	939	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
<>	161:2cc1468da177	940	{
<>	161:2cc1468da177	941	CLEAR_BIT(RCC->AHB3ENR, Periphs);
<>	161:2cc1468da177	942	}
<>	161:2cc1468da177	943
<>	161:2cc1468da177	944	/**
<>	161:2cc1468da177	945	* @brief Force AHB3 peripherals reset.
<>	161:2cc1468da177	946	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
<>	161:2cc1468da177	947	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
<>	161:2cc1468da177	948	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	949	* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
<>	161:2cc1468da177	950	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
<>	161:2cc1468da177	951	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
<>	161:2cc1468da177	952	*
<>	161:2cc1468da177	953	* (*) value not defined in all devices.
<>	161:2cc1468da177	954	* @retval None
<>	161:2cc1468da177	955	*/
<>	161:2cc1468da177	956	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
<>	161:2cc1468da177	957	{
<>	161:2cc1468da177	958	SET_BIT(RCC->AHB3RSTR, Periphs);
<>	161:2cc1468da177	959	}
<>	161:2cc1468da177	960
<>	161:2cc1468da177	961	/**
<>	161:2cc1468da177	962	* @brief Release AHB3 peripherals reset.
<>	161:2cc1468da177	963	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
<>	161:2cc1468da177	964	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
<>	161:2cc1468da177	965	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	966	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
<>	161:2cc1468da177	967	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
<>	161:2cc1468da177	968	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
<>	161:2cc1468da177	969	*
<>	161:2cc1468da177	970	* (*) value not defined in all devices.
<>	161:2cc1468da177	971	* @retval None
<>	161:2cc1468da177	972	*/
<>	161:2cc1468da177	973	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
<>	161:2cc1468da177	974	{
<>	161:2cc1468da177	975	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
<>	161:2cc1468da177	976	}
<>	161:2cc1468da177	977
<>	161:2cc1468da177	978	/**
<>	161:2cc1468da177	979	* @brief Enable AHB3 peripheral clocks in low-power mode
<>	161:2cc1468da177	980	* @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	981	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
<>	161:2cc1468da177	982	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	983	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
<>	161:2cc1468da177	984	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
<>	161:2cc1468da177	985	*
<>	161:2cc1468da177	986	* (*) value not defined in all devices.
<>	161:2cc1468da177	987	* @retval None
<>	161:2cc1468da177	988	*/
<>	161:2cc1468da177	989	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	990	{
<>	161:2cc1468da177	991	__IO uint32_t tmpreg;
<>	161:2cc1468da177	992	SET_BIT(RCC->AHB3LPENR, Periphs);
<>	161:2cc1468da177	993	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	994	tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
<>	161:2cc1468da177	995	(void)tmpreg;
<>	161:2cc1468da177	996	}
<>	161:2cc1468da177	997
<>	161:2cc1468da177	998	/**
<>	161:2cc1468da177	999	* @brief Disable AHB3 peripheral clocks in low-power mode
<>	161:2cc1468da177	1000	* @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1001	* AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
<>	161:2cc1468da177	1002	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1003	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
<>	161:2cc1468da177	1004	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
<>	161:2cc1468da177	1005	*
<>	161:2cc1468da177	1006	* (*) value not defined in all devices.
<>	161:2cc1468da177	1007	* @retval None
<>	161:2cc1468da177	1008	*/
<>	161:2cc1468da177	1009	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	1010	{
<>	161:2cc1468da177	1011	CLEAR_BIT(RCC->AHB3LPENR, Periphs);
<>	161:2cc1468da177	1012	}
<>	161:2cc1468da177	1013
<>	161:2cc1468da177	1014	/**
<>	161:2cc1468da177	1015	* @}
<>	161:2cc1468da177	1016	*/
<>	161:2cc1468da177	1017
<>	161:2cc1468da177	1018	/** @defgroup BUS_LL_EF_APB1 APB1
<>	161:2cc1468da177	1019	* @{
<>	161:2cc1468da177	1020	*/
<>	161:2cc1468da177	1021
<>	161:2cc1468da177	1022	/**
<>	161:2cc1468da177	1023	* @brief Enable APB1 peripherals clock.
<>	161:2cc1468da177	1024	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1025	* APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1026	* APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1027	* APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1028	* APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1029	* APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1030	* APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1031	* APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1032	* APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1033	* APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1034	* APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1035	* APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1036	* APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1037	* APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1038	* APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1039	* APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1040	* APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1041	* APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1042	* APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1043	* APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1044	* APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1045	* APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1046	* APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1047	* APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1048	* APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1049	* APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1050	* APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1051	* APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1052	* APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1053	* APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
<>	161:2cc1468da177	1054	* APB1ENR RTCEN LL_APB1_GRP1_EnableClock
<>	161:2cc1468da177	1055	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1056	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<>	161:2cc1468da177	1057	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<>	161:2cc1468da177	1058	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<>	161:2cc1468da177	1059	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
<>	161:2cc1468da177	1060	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<>	161:2cc1468da177	1061	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<>	161:2cc1468da177	1062	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
<>	161:2cc1468da177	1063	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
<>	161:2cc1468da177	1064	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<>	161:2cc1468da177	1065	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
<>	161:2cc1468da177	1066	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<>	161:2cc1468da177	1067	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<>	161:2cc1468da177	1068	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
<>	161:2cc1468da177	1069	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
<>	161:2cc1468da177	1070	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
<>	161:2cc1468da177	1071	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
<>	161:2cc1468da177	1072	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
<>	161:2cc1468da177	1073	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
<>	161:2cc1468da177	1074	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<>	161:2cc1468da177	1075	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<>	161:2cc1468da177	1076	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
<>	161:2cc1468da177	1077	* @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
<>	161:2cc1468da177	1078	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
<>	161:2cc1468da177	1079	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
<>	161:2cc1468da177	1080	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
<>	161:2cc1468da177	1081	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<>	161:2cc1468da177	1082	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
<>	161:2cc1468da177	1083	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<>	161:2cc1468da177	1084	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
<>	161:2cc1468da177	1085	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
<>	161:2cc1468da177	1086	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
<>	161:2cc1468da177	1087	*
<>	161:2cc1468da177	1088	* (*) value not defined in all devices.
<>	161:2cc1468da177	1089	* @retval None
<>	161:2cc1468da177	1090	*/
<>	161:2cc1468da177	1091	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
<>	161:2cc1468da177	1092	{
<>	161:2cc1468da177	1093	__IO uint32_t tmpreg;
<>	161:2cc1468da177	1094	SET_BIT(RCC->APB1ENR, Periphs);
<>	161:2cc1468da177	1095	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	1096	tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
<>	161:2cc1468da177	1097	(void)tmpreg;
<>	161:2cc1468da177	1098	}
<>	161:2cc1468da177	1099
<>	161:2cc1468da177	1100	/**
<>	161:2cc1468da177	1101	* @brief Check if APB1 peripheral clock is enabled or not
<>	161:2cc1468da177	1102	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1103	* APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1104	* APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1105	* APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1106	* APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1107	* APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1108	* APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1109	* APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1110	* APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1111	* APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1112	* APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1113	* APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1114	* APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1115	* APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1116	* APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1117	* APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1118	* APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1119	* APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1120	* APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1121	* APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1122	* APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1123	* APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1124	* APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1125	* APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1126	* APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1127	* APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1128	* APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1129	* APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1130	* APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1131	* APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1132	* APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock
<>	161:2cc1468da177	1133	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1134	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<>	161:2cc1468da177	1135	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<>	161:2cc1468da177	1136	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<>	161:2cc1468da177	1137	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
<>	161:2cc1468da177	1138	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<>	161:2cc1468da177	1139	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<>	161:2cc1468da177	1140	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
<>	161:2cc1468da177	1141	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
<>	161:2cc1468da177	1142	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<>	161:2cc1468da177	1143	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
<>	161:2cc1468da177	1144	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<>	161:2cc1468da177	1145	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<>	161:2cc1468da177	1146	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
<>	161:2cc1468da177	1147	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
<>	161:2cc1468da177	1148	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
<>	161:2cc1468da177	1149	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
<>	161:2cc1468da177	1150	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
<>	161:2cc1468da177	1151	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
<>	161:2cc1468da177	1152	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<>	161:2cc1468da177	1153	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<>	161:2cc1468da177	1154	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
<>	161:2cc1468da177	1155	* @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
<>	161:2cc1468da177	1156	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
<>	161:2cc1468da177	1157	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
<>	161:2cc1468da177	1158	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
<>	161:2cc1468da177	1159	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<>	161:2cc1468da177	1160	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
<>	161:2cc1468da177	1161	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<>	161:2cc1468da177	1162	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
<>	161:2cc1468da177	1163	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
<>	161:2cc1468da177	1164	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
<>	161:2cc1468da177	1165	*
<>	161:2cc1468da177	1166	* (*) value not defined in all devices.
<>	161:2cc1468da177	1167	* @retval State of Periphs (1 or 0).
<>	161:2cc1468da177	1168	*/
<>	161:2cc1468da177	1169	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
<>	161:2cc1468da177	1170	{
<>	161:2cc1468da177	1171	return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
<>	161:2cc1468da177	1172	}
<>	161:2cc1468da177	1173
<>	161:2cc1468da177	1174	/**
<>	161:2cc1468da177	1175	* @brief Disable APB1 peripherals clock.
<>	161:2cc1468da177	1176	* @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1177	* APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1178	* APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1179	* APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1180	* APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1181	* APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1182	* APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1183	* APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1184	* APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1185	* APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1186	* APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1187	* APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1188	* APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1189	* APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1190	* APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1191	* APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1192	* APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1193	* APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1194	* APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1195	* APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1196	* APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1197	* APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1198	* APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1199	* APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1200	* APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1201	* APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1202	* APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1203	* APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1204	* APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1205	* APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
<>	161:2cc1468da177	1206	* APB1ENR RTCEN LL_APB1_GRP1_DisableClock
<>	161:2cc1468da177	1207	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1208	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<>	161:2cc1468da177	1209	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<>	161:2cc1468da177	1210	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<>	161:2cc1468da177	1211	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
<>	161:2cc1468da177	1212	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<>	161:2cc1468da177	1213	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<>	161:2cc1468da177	1214	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
<>	161:2cc1468da177	1215	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
<>	161:2cc1468da177	1216	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<>	161:2cc1468da177	1217	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
<>	161:2cc1468da177	1218	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<>	161:2cc1468da177	1219	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<>	161:2cc1468da177	1220	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
<>	161:2cc1468da177	1221	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
<>	161:2cc1468da177	1222	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
<>	161:2cc1468da177	1223	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
<>	161:2cc1468da177	1224	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
<>	161:2cc1468da177	1225	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
<>	161:2cc1468da177	1226	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<>	161:2cc1468da177	1227	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<>	161:2cc1468da177	1228	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
<>	161:2cc1468da177	1229	* @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
<>	161:2cc1468da177	1230	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
<>	161:2cc1468da177	1231	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
<>	161:2cc1468da177	1232	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
<>	161:2cc1468da177	1233	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<>	161:2cc1468da177	1234	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
<>	161:2cc1468da177	1235	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<>	161:2cc1468da177	1236	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
<>	161:2cc1468da177	1237	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
<>	161:2cc1468da177	1238	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
<>	161:2cc1468da177	1239	*
<>	161:2cc1468da177	1240	* (*) value not defined in all devices.
<>	161:2cc1468da177	1241	* @retval None
<>	161:2cc1468da177	1242	*/
<>	161:2cc1468da177	1243	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
<>	161:2cc1468da177	1244	{
<>	161:2cc1468da177	1245	CLEAR_BIT(RCC->APB1ENR, Periphs);
<>	161:2cc1468da177	1246	}
<>	161:2cc1468da177	1247
<>	161:2cc1468da177	1248	/**
<>	161:2cc1468da177	1249	* @brief Force APB1 peripherals reset.
<>	161:2cc1468da177	1250	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1251	* APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1252	* APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1253	* APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1254	* APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1255	* APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1256	* APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1257	* APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1258	* APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1259	* APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1260	* APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1261	* APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1262	* APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1263	* APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1264	* APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1265	* APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1266	* APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1267	* APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1268	* APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1269	* APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1270	* APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1271	* APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1272	* APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1273	* APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1274	* APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1275	* APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1276	* APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1277	* APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1278	* APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
<>	161:2cc1468da177	1279	* APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
<>	161:2cc1468da177	1280	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1281	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<>	161:2cc1468da177	1282	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<>	161:2cc1468da177	1283	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<>	161:2cc1468da177	1284	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
<>	161:2cc1468da177	1285	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<>	161:2cc1468da177	1286	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<>	161:2cc1468da177	1287	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
<>	161:2cc1468da177	1288	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
<>	161:2cc1468da177	1289	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<>	161:2cc1468da177	1290	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
<>	161:2cc1468da177	1291	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<>	161:2cc1468da177	1292	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<>	161:2cc1468da177	1293	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
<>	161:2cc1468da177	1294	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
<>	161:2cc1468da177	1295	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
<>	161:2cc1468da177	1296	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
<>	161:2cc1468da177	1297	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
<>	161:2cc1468da177	1298	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
<>	161:2cc1468da177	1299	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<>	161:2cc1468da177	1300	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<>	161:2cc1468da177	1301	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
<>	161:2cc1468da177	1302	* @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
<>	161:2cc1468da177	1303	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
<>	161:2cc1468da177	1304	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
<>	161:2cc1468da177	1305	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
<>	161:2cc1468da177	1306	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<>	161:2cc1468da177	1307	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
<>	161:2cc1468da177	1308	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<>	161:2cc1468da177	1309	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
<>	161:2cc1468da177	1310	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
<>	161:2cc1468da177	1311	*
<>	161:2cc1468da177	1312	* (*) value not defined in all devices.
<>	161:2cc1468da177	1313	* @retval None
<>	161:2cc1468da177	1314	*/
<>	161:2cc1468da177	1315	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
<>	161:2cc1468da177	1316	{
<>	161:2cc1468da177	1317	SET_BIT(RCC->APB1RSTR, Periphs);
<>	161:2cc1468da177	1318	}
<>	161:2cc1468da177	1319
<>	161:2cc1468da177	1320	/**
<>	161:2cc1468da177	1321	* @brief Release APB1 peripherals reset.
<>	161:2cc1468da177	1322	* @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1323	* APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1324	* APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1325	* APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1326	* APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1327	* APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1328	* APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1329	* APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1330	* APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1331	* APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1332	* APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1333	* APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1334	* APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1335	* APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1336	* APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1337	* APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1338	* APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1339	* APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1340	* APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1341	* APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1342	* APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1343	* APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1344	* APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1345	* APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1346	* APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1347	* APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1348	* APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1349	* APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1350	* APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1351	* APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
<>	161:2cc1468da177	1352	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1353	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<>	161:2cc1468da177	1354	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<>	161:2cc1468da177	1355	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<>	161:2cc1468da177	1356	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
<>	161:2cc1468da177	1357	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<>	161:2cc1468da177	1358	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<>	161:2cc1468da177	1359	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
<>	161:2cc1468da177	1360	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
<>	161:2cc1468da177	1361	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<>	161:2cc1468da177	1362	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
<>	161:2cc1468da177	1363	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<>	161:2cc1468da177	1364	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<>	161:2cc1468da177	1365	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
<>	161:2cc1468da177	1366	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
<>	161:2cc1468da177	1367	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
<>	161:2cc1468da177	1368	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
<>	161:2cc1468da177	1369	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
<>	161:2cc1468da177	1370	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
<>	161:2cc1468da177	1371	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<>	161:2cc1468da177	1372	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<>	161:2cc1468da177	1373	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
<>	161:2cc1468da177	1374	* @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
<>	161:2cc1468da177	1375	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
<>	161:2cc1468da177	1376	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
<>	161:2cc1468da177	1377	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
<>	161:2cc1468da177	1378	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<>	161:2cc1468da177	1379	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
<>	161:2cc1468da177	1380	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<>	161:2cc1468da177	1381	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
<>	161:2cc1468da177	1382	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
<>	161:2cc1468da177	1383	*
<>	161:2cc1468da177	1384	* (*) value not defined in all devices.
<>	161:2cc1468da177	1385	* @retval None
<>	161:2cc1468da177	1386	*/
<>	161:2cc1468da177	1387	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
<>	161:2cc1468da177	1388	{
<>	161:2cc1468da177	1389	CLEAR_BIT(RCC->APB1RSTR, Periphs);
<>	161:2cc1468da177	1390	}
<>	161:2cc1468da177	1391
<>	161:2cc1468da177	1392	/**
<>	161:2cc1468da177	1393	* @brief Enable APB1 peripheral clocks in low-power mode
<>	161:2cc1468da177	1394	* @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1395	* APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1396	* APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1397	* APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1398	* APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1399	* APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1400	* APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1401	* APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1402	* APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1403	* APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1404	* APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1405	* APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1406	* APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1407	* APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1408	* APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1409	* APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1410	* APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1411	* APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1412	* APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1413	* APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1414	* APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1415	* APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1416	* APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1417	* APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1418	* APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1419	* APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1420	* APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1421	* APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1422	* APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1423	* APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1424	* APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower
<>	161:2cc1468da177	1425	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1426	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<>	161:2cc1468da177	1427	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<>	161:2cc1468da177	1428	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<>	161:2cc1468da177	1429	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
<>	161:2cc1468da177	1430	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<>	161:2cc1468da177	1431	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<>	161:2cc1468da177	1432	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
<>	161:2cc1468da177	1433	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
<>	161:2cc1468da177	1434	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<>	161:2cc1468da177	1435	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
<>	161:2cc1468da177	1436	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<>	161:2cc1468da177	1437	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<>	161:2cc1468da177	1438	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
<>	161:2cc1468da177	1439	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
<>	161:2cc1468da177	1440	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
<>	161:2cc1468da177	1441	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
<>	161:2cc1468da177	1442	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
<>	161:2cc1468da177	1443	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
<>	161:2cc1468da177	1444	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<>	161:2cc1468da177	1445	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<>	161:2cc1468da177	1446	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
<>	161:2cc1468da177	1447	* @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
<>	161:2cc1468da177	1448	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
<>	161:2cc1468da177	1449	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
<>	161:2cc1468da177	1450	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
<>	161:2cc1468da177	1451	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<>	161:2cc1468da177	1452	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
<>	161:2cc1468da177	1453	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<>	161:2cc1468da177	1454	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
<>	161:2cc1468da177	1455	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
<>	161:2cc1468da177	1456	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
<>	161:2cc1468da177	1457	*
<>	161:2cc1468da177	1458	* (*) value not defined in all devices.
<>	161:2cc1468da177	1459	* @retval None
<>	161:2cc1468da177	1460	*/
<>	161:2cc1468da177	1461	__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	1462	{
<>	161:2cc1468da177	1463	__IO uint32_t tmpreg;
<>	161:2cc1468da177	1464	SET_BIT(RCC->APB1LPENR, Periphs);
<>	161:2cc1468da177	1465	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	1466	tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
<>	161:2cc1468da177	1467	(void)tmpreg;
<>	161:2cc1468da177	1468	}
<>	161:2cc1468da177	1469
<>	161:2cc1468da177	1470	/**
<>	161:2cc1468da177	1471	* @brief Disable APB1 peripheral clocks in low-power mode
<>	161:2cc1468da177	1472	* @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1473	* APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1474	* APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1475	* APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1476	* APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1477	* APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1478	* APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1479	* APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1480	* APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1481	* APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1482	* APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1483	* APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1484	* APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1485	* APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1486	* APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1487	* APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1488	* APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1489	* APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1490	* APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1491	* APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1492	* APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1493	* APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1494	* APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1495	* APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1496	* APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1497	* APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1498	* APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1499	* APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1500	* APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1501	* APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1502	* APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower
<>	161:2cc1468da177	1503	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1504	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<>	161:2cc1468da177	1505	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<>	161:2cc1468da177	1506	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<>	161:2cc1468da177	1507	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
<>	161:2cc1468da177	1508	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<>	161:2cc1468da177	1509	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<>	161:2cc1468da177	1510	* @arg @ref LL_APB1_GRP1_PERIPH_TIM12
<>	161:2cc1468da177	1511	* @arg @ref LL_APB1_GRP1_PERIPH_TIM13
<>	161:2cc1468da177	1512	* @arg @ref LL_APB1_GRP1_PERIPH_TIM14
<>	161:2cc1468da177	1513	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
<>	161:2cc1468da177	1514	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<>	161:2cc1468da177	1515	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<>	161:2cc1468da177	1516	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
<>	161:2cc1468da177	1517	* @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
<>	161:2cc1468da177	1518	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
<>	161:2cc1468da177	1519	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
<>	161:2cc1468da177	1520	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
<>	161:2cc1468da177	1521	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
<>	161:2cc1468da177	1522	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<>	161:2cc1468da177	1523	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<>	161:2cc1468da177	1524	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
<>	161:2cc1468da177	1525	* @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
<>	161:2cc1468da177	1526	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
<>	161:2cc1468da177	1527	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
<>	161:2cc1468da177	1528	* @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
<>	161:2cc1468da177	1529	* @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
<>	161:2cc1468da177	1530	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
<>	161:2cc1468da177	1531	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<>	161:2cc1468da177	1532	* @arg @ref LL_APB1_GRP1_PERIPH_UART7
<>	161:2cc1468da177	1533	* @arg @ref LL_APB1_GRP1_PERIPH_UART8
<>	161:2cc1468da177	1534	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
<>	161:2cc1468da177	1535	*
<>	161:2cc1468da177	1536	* (*) value not defined in all devices.
<>	161:2cc1468da177	1537	* @retval None
<>	161:2cc1468da177	1538	*/
<>	161:2cc1468da177	1539	__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	1540	{
<>	161:2cc1468da177	1541	CLEAR_BIT(RCC->APB1LPENR, Periphs);
<>	161:2cc1468da177	1542	}
<>	161:2cc1468da177	1543
<>	161:2cc1468da177	1544	/**
<>	161:2cc1468da177	1545	* @}
<>	161:2cc1468da177	1546	*/
<>	161:2cc1468da177	1547
<>	161:2cc1468da177	1548	/** @defgroup BUS_LL_EF_APB2 APB2
<>	161:2cc1468da177	1549	* @{
<>	161:2cc1468da177	1550	*/
<>	161:2cc1468da177	1551
<>	161:2cc1468da177	1552	/**
<>	161:2cc1468da177	1553	* @brief Enable APB2 peripherals clock.
<>	161:2cc1468da177	1554	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1555	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1556	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1557	* APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1558	* APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1559	* APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1560	* APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1561	* APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1562	* APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1563	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1564	* APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1565	* APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1566	* APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1567	* APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1568	* APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1569	* APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1570	* APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1571	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1572	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1573	* APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1574	* APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1575	* APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1576	* APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n
<>	161:2cc1468da177	1577	* APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock
<>	161:2cc1468da177	1578	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1579	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
<>	161:2cc1468da177	1580	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
<>	161:2cc1468da177	1581	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
<>	161:2cc1468da177	1582	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
<>	161:2cc1468da177	1583	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<>	161:2cc1468da177	1584	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
<>	161:2cc1468da177	1585	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
<>	161:2cc1468da177	1586	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
<>	161:2cc1468da177	1587	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
<>	161:2cc1468da177	1588	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<>	161:2cc1468da177	1589	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
<>	161:2cc1468da177	1590	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<>	161:2cc1468da177	1591	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<>	161:2cc1468da177	1592	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<>	161:2cc1468da177	1593	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<>	161:2cc1468da177	1594	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
<>	161:2cc1468da177	1595	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
<>	161:2cc1468da177	1596	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
<>	161:2cc1468da177	1597	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
<>	161:2cc1468da177	1598	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
<>	161:2cc1468da177	1599	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
<>	161:2cc1468da177	1600	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
<>	161:2cc1468da177	1601	* @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
<>	161:2cc1468da177	1602	* @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
<>	161:2cc1468da177	1603	*
<>	161:2cc1468da177	1604	* (*) value not defined in all devices.
<>	161:2cc1468da177	1605	* @retval None
<>	161:2cc1468da177	1606	*/
<>	161:2cc1468da177	1607	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
<>	161:2cc1468da177	1608	{
<>	161:2cc1468da177	1609	__IO uint32_t tmpreg;
<>	161:2cc1468da177	1610	SET_BIT(RCC->APB2ENR, Periphs);
<>	161:2cc1468da177	1611	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	1612	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
<>	161:2cc1468da177	1613	(void)tmpreg;
<>	161:2cc1468da177	1614	}
<>	161:2cc1468da177	1615
<>	161:2cc1468da177	1616	/**
<>	161:2cc1468da177	1617	* @brief Check if APB2 peripheral clock is enabled or not
<>	161:2cc1468da177	1618	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1619	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1620	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1621	* APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1622	* APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1623	* APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1624	* APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1625	* APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1626	* APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1627	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1628	* APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1629	* APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1630	* APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1631	* APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1632	* APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1633	* APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1634	* APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1635	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1636	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1637	* APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1638	* APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1639	* APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1640	* APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n
<>	161:2cc1468da177	1641	* APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock
<>	161:2cc1468da177	1642	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1643	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
<>	161:2cc1468da177	1644	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
<>	161:2cc1468da177	1645	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
<>	161:2cc1468da177	1646	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
<>	161:2cc1468da177	1647	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<>	161:2cc1468da177	1648	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
<>	161:2cc1468da177	1649	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
<>	161:2cc1468da177	1650	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
<>	161:2cc1468da177	1651	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
<>	161:2cc1468da177	1652	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<>	161:2cc1468da177	1653	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
<>	161:2cc1468da177	1654	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<>	161:2cc1468da177	1655	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<>	161:2cc1468da177	1656	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<>	161:2cc1468da177	1657	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<>	161:2cc1468da177	1658	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
<>	161:2cc1468da177	1659	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
<>	161:2cc1468da177	1660	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
<>	161:2cc1468da177	1661	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
<>	161:2cc1468da177	1662	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
<>	161:2cc1468da177	1663	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
<>	161:2cc1468da177	1664	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
<>	161:2cc1468da177	1665	* @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
<>	161:2cc1468da177	1666	* @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
<>	161:2cc1468da177	1667	*
<>	161:2cc1468da177	1668	* (*) value not defined in all devices.
<>	161:2cc1468da177	1669	* @retval State of Periphs (1 or 0).
<>	161:2cc1468da177	1670	*/
<>	161:2cc1468da177	1671	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
<>	161:2cc1468da177	1672	{
<>	161:2cc1468da177	1673	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
<>	161:2cc1468da177	1674	}
<>	161:2cc1468da177	1675
<>	161:2cc1468da177	1676	/**
<>	161:2cc1468da177	1677	* @brief Disable APB2 peripherals clock.
<>	161:2cc1468da177	1678	* @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1679	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1680	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1681	* APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1682	* APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1683	* APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1684	* APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1685	* APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1686	* APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1687	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1688	* APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1689	* APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1690	* APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1691	* APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1692	* APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1693	* APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1694	* APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1695	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1696	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1697	* APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1698	* APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1699	* APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1700	* APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n
<>	161:2cc1468da177	1701	* APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock
<>	161:2cc1468da177	1702	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1703	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
<>	161:2cc1468da177	1704	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
<>	161:2cc1468da177	1705	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
<>	161:2cc1468da177	1706	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
<>	161:2cc1468da177	1707	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<>	161:2cc1468da177	1708	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
<>	161:2cc1468da177	1709	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
<>	161:2cc1468da177	1710	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
<>	161:2cc1468da177	1711	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
<>	161:2cc1468da177	1712	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<>	161:2cc1468da177	1713	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
<>	161:2cc1468da177	1714	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<>	161:2cc1468da177	1715	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<>	161:2cc1468da177	1716	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<>	161:2cc1468da177	1717	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<>	161:2cc1468da177	1718	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
<>	161:2cc1468da177	1719	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
<>	161:2cc1468da177	1720	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
<>	161:2cc1468da177	1721	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
<>	161:2cc1468da177	1722	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
<>	161:2cc1468da177	1723	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
<>	161:2cc1468da177	1724	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
<>	161:2cc1468da177	1725	* @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
<>	161:2cc1468da177	1726	* @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
<>	161:2cc1468da177	1727	*
<>	161:2cc1468da177	1728	* (*) value not defined in all devices.
<>	161:2cc1468da177	1729	* @retval None
<>	161:2cc1468da177	1730	*/
<>	161:2cc1468da177	1731	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
<>	161:2cc1468da177	1732	{
<>	161:2cc1468da177	1733	CLEAR_BIT(RCC->APB2ENR, Periphs);
<>	161:2cc1468da177	1734	}
<>	161:2cc1468da177	1735
<>	161:2cc1468da177	1736	/**
<>	161:2cc1468da177	1737	* @brief Force APB2 peripherals reset.
<>	161:2cc1468da177	1738	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1739	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1740	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1741	* APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1742	* APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1743	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1744	* APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1745	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1746	* APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1747	* APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1748	* APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1749	* APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1750	* APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1751	* APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1752	* APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1753	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1754	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1755	* APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1756	* APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1757	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1758	* APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n
<>	161:2cc1468da177	1759	* APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset
<>	161:2cc1468da177	1760	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1761	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
<>	161:2cc1468da177	1762	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
<>	161:2cc1468da177	1763	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
<>	161:2cc1468da177	1764	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
<>	161:2cc1468da177	1765	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
<>	161:2cc1468da177	1766	* @arg @ref LL_APB2_GRP1_PERIPH_ADC
<>	161:2cc1468da177	1767	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
<>	161:2cc1468da177	1768	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
<>	161:2cc1468da177	1769	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<>	161:2cc1468da177	1770	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
<>	161:2cc1468da177	1771	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<>	161:2cc1468da177	1772	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<>	161:2cc1468da177	1773	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<>	161:2cc1468da177	1774	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<>	161:2cc1468da177	1775	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
<>	161:2cc1468da177	1776	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
<>	161:2cc1468da177	1777	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
<>	161:2cc1468da177	1778	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
<>	161:2cc1468da177	1779	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
<>	161:2cc1468da177	1780	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
<>	161:2cc1468da177	1781	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
<>	161:2cc1468da177	1782	* @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
<>	161:2cc1468da177	1783	* @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
<>	161:2cc1468da177	1784	*
<>	161:2cc1468da177	1785	* (*) value not defined in all devices.
<>	161:2cc1468da177	1786	* @retval None
<>	161:2cc1468da177	1787	*/
<>	161:2cc1468da177	1788	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
<>	161:2cc1468da177	1789	{
<>	161:2cc1468da177	1790	SET_BIT(RCC->APB2RSTR, Periphs);
<>	161:2cc1468da177	1791	}
<>	161:2cc1468da177	1792
<>	161:2cc1468da177	1793	/**
<>	161:2cc1468da177	1794	* @brief Release APB2 peripherals reset.
<>	161:2cc1468da177	1795	* @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1796	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1797	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1798	* APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1799	* APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1800	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1801	* APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1802	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1803	* APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1804	* APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1805	* APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1806	* APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1807	* APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1808	* APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1809	* APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1810	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1811	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1812	* APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1813	* APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1814	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1815	* APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n
<>	161:2cc1468da177	1816	* APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset
<>	161:2cc1468da177	1817	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1818	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
<>	161:2cc1468da177	1819	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
<>	161:2cc1468da177	1820	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
<>	161:2cc1468da177	1821	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
<>	161:2cc1468da177	1822	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
<>	161:2cc1468da177	1823	* @arg @ref LL_APB2_GRP1_PERIPH_ADC
<>	161:2cc1468da177	1824	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
<>	161:2cc1468da177	1825	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
<>	161:2cc1468da177	1826	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<>	161:2cc1468da177	1827	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
<>	161:2cc1468da177	1828	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<>	161:2cc1468da177	1829	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<>	161:2cc1468da177	1830	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<>	161:2cc1468da177	1831	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<>	161:2cc1468da177	1832	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
<>	161:2cc1468da177	1833	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
<>	161:2cc1468da177	1834	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
<>	161:2cc1468da177	1835	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
<>	161:2cc1468da177	1836	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
<>	161:2cc1468da177	1837	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
<>	161:2cc1468da177	1838	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
<>	161:2cc1468da177	1839	* @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
<>	161:2cc1468da177	1840	* @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
<>	161:2cc1468da177	1841	*
<>	161:2cc1468da177	1842	* (*) value not defined in all devices.
<>	161:2cc1468da177	1843	* @retval None
<>	161:2cc1468da177	1844	*/
<>	161:2cc1468da177	1845	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
<>	161:2cc1468da177	1846	{
<>	161:2cc1468da177	1847	CLEAR_BIT(RCC->APB2RSTR, Periphs);
<>	161:2cc1468da177	1848	}
<>	161:2cc1468da177	1849
<>	161:2cc1468da177	1850	/**
<>	161:2cc1468da177	1851	* @brief Enable APB2 peripheral clocks in low-power mode
<>	161:2cc1468da177	1852	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1853	* APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1854	* APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1855	* APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1856	* APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1857	* APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1858	* APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1859	* APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1860	* APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1861	* APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1862	* APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1863	* APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1864	* APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1865	* APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1866	* APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1867	* APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1868	* APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1869	* APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1870	* APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1871	* APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1872	* APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1873	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
<>	161:2cc1468da177	1874	* APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower
<>	161:2cc1468da177	1875	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1876	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
<>	161:2cc1468da177	1877	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
<>	161:2cc1468da177	1878	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
<>	161:2cc1468da177	1879	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
<>	161:2cc1468da177	1880	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<>	161:2cc1468da177	1881	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
<>	161:2cc1468da177	1882	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
<>	161:2cc1468da177	1883	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
<>	161:2cc1468da177	1884	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
<>	161:2cc1468da177	1885	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<>	161:2cc1468da177	1886	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
<>	161:2cc1468da177	1887	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<>	161:2cc1468da177	1888	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<>	161:2cc1468da177	1889	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<>	161:2cc1468da177	1890	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<>	161:2cc1468da177	1891	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
<>	161:2cc1468da177	1892	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
<>	161:2cc1468da177	1893	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
<>	161:2cc1468da177	1894	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
<>	161:2cc1468da177	1895	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
<>	161:2cc1468da177	1896	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
<>	161:2cc1468da177	1897	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
<>	161:2cc1468da177	1898	* @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
<>	161:2cc1468da177	1899	*
<>	161:2cc1468da177	1900	* (*) value not defined in all devices.
<>	161:2cc1468da177	1901	* @retval None
<>	161:2cc1468da177	1902	*/
<>	161:2cc1468da177	1903	__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	1904	{
<>	161:2cc1468da177	1905	__IO uint32_t tmpreg;
<>	161:2cc1468da177	1906	SET_BIT(RCC->APB2LPENR, Periphs);
<>	161:2cc1468da177	1907	/* Delay after an RCC peripheral clock enabling */
<>	161:2cc1468da177	1908	tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
<>	161:2cc1468da177	1909	(void)tmpreg;
<>	161:2cc1468da177	1910	}
<>	161:2cc1468da177	1911
<>	161:2cc1468da177	1912	/**
<>	161:2cc1468da177	1913	* @brief Disable APB2 peripheral clocks in low-power mode
<>	161:2cc1468da177	1914	* @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1915	* APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1916	* APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1917	* APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1918	* APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1919	* APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1920	* APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1921	* APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1922	* APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1923	* APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1924	* APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1925	* APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1926	* APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1927	* APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1928	* APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1929	* APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1930	* APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1931	* APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1932	* APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1933	* APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1934	* APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1935	* APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
<>	161:2cc1468da177	1936	* APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower
<>	161:2cc1468da177	1937	* @param Periphs This parameter can be a combination of the following values:
<>	161:2cc1468da177	1938	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
<>	161:2cc1468da177	1939	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
<>	161:2cc1468da177	1940	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
<>	161:2cc1468da177	1941	* @arg @ref LL_APB2_GRP1_PERIPH_USART6
<>	161:2cc1468da177	1942	* @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<>	161:2cc1468da177	1943	* @arg @ref LL_APB2_GRP1_PERIPH_ADC2
<>	161:2cc1468da177	1944	* @arg @ref LL_APB2_GRP1_PERIPH_ADC3
<>	161:2cc1468da177	1945	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
<>	161:2cc1468da177	1946	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
<>	161:2cc1468da177	1947	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<>	161:2cc1468da177	1948	* @arg @ref LL_APB2_GRP1_PERIPH_SPI4
<>	161:2cc1468da177	1949	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<>	161:2cc1468da177	1950	* @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<>	161:2cc1468da177	1951	* @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<>	161:2cc1468da177	1952	* @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<>	161:2cc1468da177	1953	* @arg @ref LL_APB2_GRP1_PERIPH_SPI5
<>	161:2cc1468da177	1954	* @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
<>	161:2cc1468da177	1955	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
<>	161:2cc1468da177	1956	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
<>	161:2cc1468da177	1957	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
<>	161:2cc1468da177	1958	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
<>	161:2cc1468da177	1959	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
<>	161:2cc1468da177	1960	* @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
<>	161:2cc1468da177	1961	*
<>	161:2cc1468da177	1962	* (*) value not defined in all devices.
<>	161:2cc1468da177	1963	* @retval None
<>	161:2cc1468da177	1964	*/
<>	161:2cc1468da177	1965	__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
<>	161:2cc1468da177	1966	{
<>	161:2cc1468da177	1967	CLEAR_BIT(RCC->APB2LPENR, Periphs);
<>	161:2cc1468da177	1968	}
<>	161:2cc1468da177	1969
<>	161:2cc1468da177	1970	/**
<>	161:2cc1468da177	1971	* @}
<>	161:2cc1468da177	1972	*/
<>	161:2cc1468da177	1973
<>	161:2cc1468da177	1974	/**
<>	161:2cc1468da177	1975	* @}
<>	161:2cc1468da177	1976	*/
<>	161:2cc1468da177	1977
<>	161:2cc1468da177	1978	/**
<>	161:2cc1468da177	1979	* @}
<>	161:2cc1468da177	1980	*/
<>	161:2cc1468da177	1981
<>	161:2cc1468da177	1982	#endif /* defined(RCC) */
<>	161:2cc1468da177	1983
<>	161:2cc1468da177	1984	/**
<>	161:2cc1468da177	1985	* @}
<>	161:2cc1468da177	1986	*/
<>	161:2cc1468da177	1987
<>	161:2cc1468da177	1988	#ifdef __cplusplus
<>	161:2cc1468da177	1989	}
<>	161:2cc1468da177	1990	#endif
<>	161:2cc1468da177	1991
<>	161:2cc1468da177	1992	#endif /* __STM32F7xx_LL_BUS_H */
<>	161:2cc1468da177	1993
<>	161:2cc1468da177	1994	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/