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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Child:
182:a56a73fd2a6f
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**
<> 161:2cc1468da177 2 ******************************************************************************
<> 161:2cc1468da177 3 * @file stm32f7xx_hal_smbus.h
<> 161:2cc1468da177 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 161:2cc1468da177 7 * @brief Header file of SMBUS HAL module.
<> 161:2cc1468da177 8 ******************************************************************************
<> 161:2cc1468da177 9 * @attention
<> 161:2cc1468da177 10 *
<> 161:2cc1468da177 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 161:2cc1468da177 12 *
<> 161:2cc1468da177 13 * Redistribution and use in source and binary forms, with or without modification,
<> 161:2cc1468da177 14 * are permitted provided that the following conditions are met:
<> 161:2cc1468da177 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 161:2cc1468da177 16 * this list of conditions and the following disclaimer.
<> 161:2cc1468da177 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 161:2cc1468da177 18 * this list of conditions and the following disclaimer in the documentation
<> 161:2cc1468da177 19 * and/or other materials provided with the distribution.
<> 161:2cc1468da177 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 161:2cc1468da177 21 * may be used to endorse or promote products derived from this software
<> 161:2cc1468da177 22 * without specific prior written permission.
<> 161:2cc1468da177 23 *
<> 161:2cc1468da177 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 161:2cc1468da177 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 161:2cc1468da177 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 161:2cc1468da177 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 161:2cc1468da177 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 161:2cc1468da177 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 161:2cc1468da177 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 161:2cc1468da177 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 34 *
<> 161:2cc1468da177 35 ******************************************************************************
<> 161:2cc1468da177 36 */
<> 161:2cc1468da177 37
<> 161:2cc1468da177 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 161:2cc1468da177 39 #ifndef __STM32F7xx_HAL_SMBUS_H
<> 161:2cc1468da177 40 #define __STM32F7xx_HAL_SMBUS_H
<> 161:2cc1468da177 41
<> 161:2cc1468da177 42 #ifdef __cplusplus
<> 161:2cc1468da177 43 extern "C" {
<> 161:2cc1468da177 44 #endif
<> 161:2cc1468da177 45
<> 161:2cc1468da177 46 /* Includes ------------------------------------------------------------------*/
<> 161:2cc1468da177 47 #include "stm32f7xx_hal_def.h"
<> 161:2cc1468da177 48
<> 161:2cc1468da177 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 161:2cc1468da177 50 * @{
<> 161:2cc1468da177 51 */
<> 161:2cc1468da177 52
<> 161:2cc1468da177 53 /** @addtogroup SMBUS
<> 161:2cc1468da177 54 * @{
<> 161:2cc1468da177 55 */
<> 161:2cc1468da177 56
<> 161:2cc1468da177 57 /* Exported types ------------------------------------------------------------*/
<> 161:2cc1468da177 58 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
<> 161:2cc1468da177 59 * @{
<> 161:2cc1468da177 60 */
<> 161:2cc1468da177 61
<> 161:2cc1468da177 62 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
<> 161:2cc1468da177 63 * @brief SMBUS Configuration Structure definition
<> 161:2cc1468da177 64 * @{
<> 161:2cc1468da177 65 */
<> 161:2cc1468da177 66 typedef struct
<> 161:2cc1468da177 67 {
<> 161:2cc1468da177 68 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
<> 161:2cc1468da177 69 This parameter calculated by referring to SMBUS initialization
<> 161:2cc1468da177 70 section in Reference manual */
<> 161:2cc1468da177 71 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
<> 161:2cc1468da177 72 This parameter can be a value of @ref SMBUS_Analog_Filter */
<> 161:2cc1468da177 73
<> 161:2cc1468da177 74 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 161:2cc1468da177 75 This parameter can be a 7-bit or 10-bit address. */
<> 161:2cc1468da177 76
<> 161:2cc1468da177 77 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
<> 161:2cc1468da177 78 This parameter can be a value of @ref SMBUS_addressing_mode */
<> 161:2cc1468da177 79
<> 161:2cc1468da177 80 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 161:2cc1468da177 81 This parameter can be a value of @ref SMBUS_dual_addressing_mode */
<> 161:2cc1468da177 82
<> 161:2cc1468da177 83 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 161:2cc1468da177 84 This parameter can be a 7-bit address. */
<> 161:2cc1468da177 85
<> 161:2cc1468da177 86 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
<> 161:2cc1468da177 87 This parameter can be a value of @ref SMBUS_own_address2_masks. */
<> 161:2cc1468da177 88
<> 161:2cc1468da177 89 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 161:2cc1468da177 90 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
<> 161:2cc1468da177 91
<> 161:2cc1468da177 92 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 161:2cc1468da177 93 This parameter can be a value of @ref SMBUS_nostretch_mode */
<> 161:2cc1468da177 94
<> 161:2cc1468da177 95 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
<> 161:2cc1468da177 96 This parameter can be a value of @ref SMBUS_packet_error_check_mode */
<> 161:2cc1468da177 97
<> 161:2cc1468da177 98 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
<> 161:2cc1468da177 99 This parameter can be a value of @ref SMBUS_peripheral_mode */
<> 161:2cc1468da177 100
<> 161:2cc1468da177 101 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
<> 161:2cc1468da177 102 (Enable bits and different timeout values)
<> 161:2cc1468da177 103 This parameter calculated by referring to SMBUS initialization
<> 161:2cc1468da177 104 section in Reference manual */
<> 161:2cc1468da177 105 } SMBUS_InitTypeDef;
<> 161:2cc1468da177 106 /**
<> 161:2cc1468da177 107 * @}
<> 161:2cc1468da177 108 */
<> 161:2cc1468da177 109
<> 161:2cc1468da177 110 /** @defgroup HAL_state_definition HAL state definition
<> 161:2cc1468da177 111 * @brief HAL State definition
<> 161:2cc1468da177 112 * @{
<> 161:2cc1468da177 113 */
<> 161:2cc1468da177 114 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
<> 161:2cc1468da177 115 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
<> 161:2cc1468da177 116 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
<> 161:2cc1468da177 117 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
<> 161:2cc1468da177 118 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
<> 161:2cc1468da177 119 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
<> 161:2cc1468da177 120 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
<> 161:2cc1468da177 121 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
<> 161:2cc1468da177 122 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
<> 161:2cc1468da177 123 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
<> 161:2cc1468da177 124 /**
<> 161:2cc1468da177 125 * @}
<> 161:2cc1468da177 126 */
<> 161:2cc1468da177 127
<> 161:2cc1468da177 128 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
<> 161:2cc1468da177 129 * @brief SMBUS Error Code definition
<> 161:2cc1468da177 130 * @{
<> 161:2cc1468da177 131 */
<> 161:2cc1468da177 132 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
<> 161:2cc1468da177 133 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
<> 161:2cc1468da177 134 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
<> 161:2cc1468da177 135 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
<> 161:2cc1468da177 136 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
<> 161:2cc1468da177 137 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
<> 161:2cc1468da177 138 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
<> 161:2cc1468da177 139 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
<> 161:2cc1468da177 140 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
<> 161:2cc1468da177 141 /**
<> 161:2cc1468da177 142 * @}
<> 161:2cc1468da177 143 */
<> 161:2cc1468da177 144
<> 161:2cc1468da177 145 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
<> 161:2cc1468da177 146 * @brief SMBUS handle Structure definition
<> 161:2cc1468da177 147 * @{
<> 161:2cc1468da177 148 */
<> 161:2cc1468da177 149 typedef struct
<> 161:2cc1468da177 150 {
<> 161:2cc1468da177 151 I2C_TypeDef *Instance; /*!< SMBUS registers base address */
<> 161:2cc1468da177 152
<> 161:2cc1468da177 153 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
<> 161:2cc1468da177 154
<> 161:2cc1468da177 155 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
<> 161:2cc1468da177 156
<> 161:2cc1468da177 157 uint16_t XferSize; /*!< SMBUS transfer size */
<> 161:2cc1468da177 158
<> 161:2cc1468da177 159 __IO uint16_t XferCount; /*!< SMBUS transfer counter */
<> 161:2cc1468da177 160
<> 161:2cc1468da177 161 __IO uint32_t XferOptions; /*!< SMBUS transfer options */
<> 161:2cc1468da177 162
<> 161:2cc1468da177 163 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
<> 161:2cc1468da177 164
<> 161:2cc1468da177 165 HAL_LockTypeDef Lock; /*!< SMBUS locking object */
<> 161:2cc1468da177 166
<> 161:2cc1468da177 167 __IO uint32_t State; /*!< SMBUS communication state */
<> 161:2cc1468da177 168
<> 161:2cc1468da177 169 __IO uint32_t ErrorCode; /*!< SMBUS Error code */
<> 161:2cc1468da177 170
<> 161:2cc1468da177 171 }SMBUS_HandleTypeDef;
<> 161:2cc1468da177 172 /**
<> 161:2cc1468da177 173 * @}
<> 161:2cc1468da177 174 */
<> 161:2cc1468da177 175
<> 161:2cc1468da177 176 /**
<> 161:2cc1468da177 177 * @}
<> 161:2cc1468da177 178 */
<> 161:2cc1468da177 179 /* Exported constants --------------------------------------------------------*/
<> 161:2cc1468da177 180
<> 161:2cc1468da177 181 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
<> 161:2cc1468da177 182 * @{
<> 161:2cc1468da177 183 */
<> 161:2cc1468da177 184
<> 161:2cc1468da177 185 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
<> 161:2cc1468da177 186 * @{
<> 161:2cc1468da177 187 */
<> 161:2cc1468da177 188 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
<> 161:2cc1468da177 189 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
<> 161:2cc1468da177 190 /**
<> 161:2cc1468da177 191 * @}
<> 161:2cc1468da177 192 */
<> 161:2cc1468da177 193
<> 161:2cc1468da177 194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
<> 161:2cc1468da177 195 * @{
<> 161:2cc1468da177 196 */
<> 161:2cc1468da177 197 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
<> 161:2cc1468da177 198 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
<> 161:2cc1468da177 199 /**
<> 161:2cc1468da177 200 * @}
<> 161:2cc1468da177 201 */
<> 161:2cc1468da177 202
<> 161:2cc1468da177 203 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
<> 161:2cc1468da177 204 * @{
<> 161:2cc1468da177 205 */
<> 161:2cc1468da177 206
<> 161:2cc1468da177 207 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
<> 161:2cc1468da177 208 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
<> 161:2cc1468da177 209 /**
<> 161:2cc1468da177 210 * @}
<> 161:2cc1468da177 211 */
<> 161:2cc1468da177 212
<> 161:2cc1468da177 213 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
<> 161:2cc1468da177 214 * @{
<> 161:2cc1468da177 215 */
<> 161:2cc1468da177 216
<> 161:2cc1468da177 217 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
<> 161:2cc1468da177 218 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
<> 161:2cc1468da177 219 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
<> 161:2cc1468da177 220 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
<> 161:2cc1468da177 221 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
<> 161:2cc1468da177 222 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
<> 161:2cc1468da177 223 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
<> 161:2cc1468da177 224 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
<> 161:2cc1468da177 225 /**
<> 161:2cc1468da177 226 * @}
<> 161:2cc1468da177 227 */
<> 161:2cc1468da177 228
<> 161:2cc1468da177 229
<> 161:2cc1468da177 230 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
<> 161:2cc1468da177 231 * @{
<> 161:2cc1468da177 232 */
<> 161:2cc1468da177 233 #define SMBUS_GENERALCALL_DISABLE (0x00000000U)
<> 161:2cc1468da177 234 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
<> 161:2cc1468da177 235 /**
<> 161:2cc1468da177 236 * @}
<> 161:2cc1468da177 237 */
<> 161:2cc1468da177 238
<> 161:2cc1468da177 239 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
<> 161:2cc1468da177 240 * @{
<> 161:2cc1468da177 241 */
<> 161:2cc1468da177 242 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
<> 161:2cc1468da177 243 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 161:2cc1468da177 244 /**
<> 161:2cc1468da177 245 * @}
<> 161:2cc1468da177 246 */
<> 161:2cc1468da177 247
<> 161:2cc1468da177 248 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
<> 161:2cc1468da177 249 * @{
<> 161:2cc1468da177 250 */
<> 161:2cc1468da177 251 #define SMBUS_PEC_DISABLE (0x00000000U)
<> 161:2cc1468da177 252 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN
<> 161:2cc1468da177 253 /**
<> 161:2cc1468da177 254 * @}
<> 161:2cc1468da177 255 */
<> 161:2cc1468da177 256
<> 161:2cc1468da177 257 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
<> 161:2cc1468da177 258 * @{
<> 161:2cc1468da177 259 */
<> 161:2cc1468da177 260 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
<> 161:2cc1468da177 261 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
<> 161:2cc1468da177 262 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
<> 161:2cc1468da177 263 /**
<> 161:2cc1468da177 264 * @}
<> 161:2cc1468da177 265 */
<> 161:2cc1468da177 266
<> 161:2cc1468da177 267 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
<> 161:2cc1468da177 268 * @{
<> 161:2cc1468da177 269 */
<> 161:2cc1468da177 270
<> 161:2cc1468da177 271 #define SMBUS_SOFTEND_MODE (0x00000000U)
<> 161:2cc1468da177 272 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
<> 161:2cc1468da177 273 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
<> 161:2cc1468da177 274 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
<> 161:2cc1468da177 275 /**
<> 161:2cc1468da177 276 * @}
<> 161:2cc1468da177 277 */
<> 161:2cc1468da177 278
<> 161:2cc1468da177 279 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
<> 161:2cc1468da177 280 * @{
<> 161:2cc1468da177 281 */
<> 161:2cc1468da177 282
<> 161:2cc1468da177 283 #define SMBUS_NO_STARTSTOP (0x00000000U)
<> 161:2cc1468da177 284 #define SMBUS_GENERATE_STOP I2C_CR2_STOP
<> 161:2cc1468da177 285 #define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
<> 161:2cc1468da177 286 #define SMBUS_GENERATE_START_WRITE I2C_CR2_START
<> 161:2cc1468da177 287 /**
<> 161:2cc1468da177 288 * @}
<> 161:2cc1468da177 289 */
<> 161:2cc1468da177 290
<> 161:2cc1468da177 291 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
<> 161:2cc1468da177 292 * @{
<> 161:2cc1468da177 293 */
<> 161:2cc1468da177 294
<> 161:2cc1468da177 295 /* List of XferOptions in usage of :
<> 161:2cc1468da177 296 * 1- Restart condition when direction change
<> 161:2cc1468da177 297 * 2- No Restart condition in other use cases
<> 161:2cc1468da177 298 */
<> 161:2cc1468da177 299 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
<> 161:2cc1468da177 300 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
<> 161:2cc1468da177 301 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
<> 161:2cc1468da177 302 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
<> 161:2cc1468da177 303 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
<> 161:2cc1468da177 304 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
<> 161:2cc1468da177 305
<> 161:2cc1468da177 306 /* List of XferOptions in usage of :
<> 161:2cc1468da177 307 * 1- Restart condition in all use cases (direction change or not)
<> 161:2cc1468da177 308 */
<> 161:2cc1468da177 309 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
<> 161:2cc1468da177 310 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
<> 161:2cc1468da177 311 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
<> 161:2cc1468da177 312 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
<> 161:2cc1468da177 313 /**
<> 161:2cc1468da177 314 * @}
<> 161:2cc1468da177 315 */
<> 161:2cc1468da177 316
<> 161:2cc1468da177 317 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
<> 161:2cc1468da177 318 * @brief SMBUS Interrupt definition
<> 161:2cc1468da177 319 * Elements values convention: 0xXXXXXXXX
<> 161:2cc1468da177 320 * - XXXXXXXX : Interrupt control mask
<> 161:2cc1468da177 321 * @{
<> 161:2cc1468da177 322 */
<> 161:2cc1468da177 323 #define SMBUS_IT_ERRI I2C_CR1_ERRIE
<> 161:2cc1468da177 324 #define SMBUS_IT_TCI I2C_CR1_TCIE
<> 161:2cc1468da177 325 #define SMBUS_IT_STOPI I2C_CR1_STOPIE
<> 161:2cc1468da177 326 #define SMBUS_IT_NACKI I2C_CR1_NACKIE
<> 161:2cc1468da177 327 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
<> 161:2cc1468da177 328 #define SMBUS_IT_RXI I2C_CR1_RXIE
<> 161:2cc1468da177 329 #define SMBUS_IT_TXI I2C_CR1_TXIE
<> 161:2cc1468da177 330 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
<> 161:2cc1468da177 331 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
<> 161:2cc1468da177 332 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
<> 161:2cc1468da177 333 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
<> 161:2cc1468da177 334 /**
<> 161:2cc1468da177 335 * @}
<> 161:2cc1468da177 336 */
<> 161:2cc1468da177 337
<> 161:2cc1468da177 338 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
<> 161:2cc1468da177 339 * @brief Flag definition
<> 161:2cc1468da177 340 * Elements values convention: 0xXXXXYYYY
<> 161:2cc1468da177 341 * - XXXXXXXX : Flag mask
<> 161:2cc1468da177 342 * @{
<> 161:2cc1468da177 343 */
<> 161:2cc1468da177 344
<> 161:2cc1468da177 345 #define SMBUS_FLAG_TXE I2C_ISR_TXE
<> 161:2cc1468da177 346 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS
<> 161:2cc1468da177 347 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE
<> 161:2cc1468da177 348 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR
<> 161:2cc1468da177 349 #define SMBUS_FLAG_AF I2C_ISR_NACKF
<> 161:2cc1468da177 350 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF
<> 161:2cc1468da177 351 #define SMBUS_FLAG_TC I2C_ISR_TC
<> 161:2cc1468da177 352 #define SMBUS_FLAG_TCR I2C_ISR_TCR
<> 161:2cc1468da177 353 #define SMBUS_FLAG_BERR I2C_ISR_BERR
<> 161:2cc1468da177 354 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO
<> 161:2cc1468da177 355 #define SMBUS_FLAG_OVR I2C_ISR_OVR
<> 161:2cc1468da177 356 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR
<> 161:2cc1468da177 357 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
<> 161:2cc1468da177 358 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT
<> 161:2cc1468da177 359 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY
<> 161:2cc1468da177 360 #define SMBUS_FLAG_DIR I2C_ISR_DIR
<> 161:2cc1468da177 361 /**
<> 161:2cc1468da177 362 * @}
<> 161:2cc1468da177 363 */
<> 161:2cc1468da177 364
<> 161:2cc1468da177 365 /**
<> 161:2cc1468da177 366 * @}
<> 161:2cc1468da177 367 */
<> 161:2cc1468da177 368
<> 161:2cc1468da177 369 /* Exported macros ------------------------------------------------------------*/
<> 161:2cc1468da177 370 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
<> 161:2cc1468da177 371 * @{
<> 161:2cc1468da177 372 */
<> 161:2cc1468da177 373
<> 161:2cc1468da177 374 /** @brief Reset SMBUS handle state.
<> 161:2cc1468da177 375 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 376 * @retval None
<> 161:2cc1468da177 377 */
<> 161:2cc1468da177 378 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
<> 161:2cc1468da177 379
<> 161:2cc1468da177 380 /** @brief Enable the specified SMBUS interrupts.
<> 161:2cc1468da177 381 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 382 * @param __INTERRUPT__ specifies the interrupt source to enable.
<> 161:2cc1468da177 383 * This parameter can be one of the following values:
<> 161:2cc1468da177 384 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 161:2cc1468da177 385 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 161:2cc1468da177 386 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 161:2cc1468da177 387 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 161:2cc1468da177 388 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 161:2cc1468da177 389 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 161:2cc1468da177 390 * @arg @ref SMBUS_IT_TXI TX interrupt enable
<> 161:2cc1468da177 391 *
<> 161:2cc1468da177 392 * @retval None
<> 161:2cc1468da177 393 */
<> 161:2cc1468da177 394 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
<> 161:2cc1468da177 395
<> 161:2cc1468da177 396 /** @brief Disable the specified SMBUS interrupts.
<> 161:2cc1468da177 397 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 398 * @param __INTERRUPT__ specifies the interrupt source to disable.
<> 161:2cc1468da177 399 * This parameter can be one of the following values:
<> 161:2cc1468da177 400 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 161:2cc1468da177 401 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 161:2cc1468da177 402 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 161:2cc1468da177 403 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 161:2cc1468da177 404 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 161:2cc1468da177 405 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 161:2cc1468da177 406 * @arg @ref SMBUS_IT_TXI TX interrupt enable
<> 161:2cc1468da177 407 *
<> 161:2cc1468da177 408 * @retval None
<> 161:2cc1468da177 409 */
<> 161:2cc1468da177 410 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
<> 161:2cc1468da177 411
<> 161:2cc1468da177 412 /** @brief Check whether the specified SMBUS interrupt source is enabled or not.
<> 161:2cc1468da177 413 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 414 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
<> 161:2cc1468da177 415 * This parameter can be one of the following values:
<> 161:2cc1468da177 416 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable
<> 161:2cc1468da177 417 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
<> 161:2cc1468da177 418 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
<> 161:2cc1468da177 419 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
<> 161:2cc1468da177 420 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
<> 161:2cc1468da177 421 * @arg @ref SMBUS_IT_RXI RX interrupt enable
<> 161:2cc1468da177 422 * @arg @ref SMBUS_IT_TXI TX interrupt enable
<> 161:2cc1468da177 423 *
<> 161:2cc1468da177 424 * @retval The new state of __IT__ (TRUE or FALSE).
<> 161:2cc1468da177 425 */
<> 161:2cc1468da177 426 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 161:2cc1468da177 427
<> 161:2cc1468da177 428 /** @brief Check whether the specified SMBUS flag is set or not.
<> 161:2cc1468da177 429 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 430 * @param __FLAG__ specifies the flag to check.
<> 161:2cc1468da177 431 * This parameter can be one of the following values:
<> 161:2cc1468da177 432 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
<> 161:2cc1468da177 433 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
<> 161:2cc1468da177 434 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
<> 161:2cc1468da177 435 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
<> 161:2cc1468da177 436 * @arg @ref SMBUS_FLAG_AF NACK received flag
<> 161:2cc1468da177 437 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
<> 161:2cc1468da177 438 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
<> 161:2cc1468da177 439 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
<> 161:2cc1468da177 440 * @arg @ref SMBUS_FLAG_BERR Bus error
<> 161:2cc1468da177 441 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
<> 161:2cc1468da177 442 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
<> 161:2cc1468da177 443 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
<> 161:2cc1468da177 444 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 161:2cc1468da177 445 * @arg @ref SMBUS_FLAG_ALERT SMBus alert
<> 161:2cc1468da177 446 * @arg @ref SMBUS_FLAG_BUSY Bus busy
<> 161:2cc1468da177 447 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
<> 161:2cc1468da177 448 *
<> 161:2cc1468da177 449 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 161:2cc1468da177 450 */
<> 161:2cc1468da177 451 #define SMBUS_FLAG_MASK (0x0001FFFFU)
<> 161:2cc1468da177 452 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
<> 161:2cc1468da177 453
<> 161:2cc1468da177 454 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
<> 161:2cc1468da177 455 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 456 * @param __FLAG__ specifies the flag to clear.
<> 161:2cc1468da177 457 * This parameter can be any combination of the following values:
<> 161:2cc1468da177 458 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
<> 161:2cc1468da177 459 * @arg @ref SMBUS_FLAG_AF NACK received flag
<> 161:2cc1468da177 460 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag
<> 161:2cc1468da177 461 * @arg @ref SMBUS_FLAG_BERR Bus error
<> 161:2cc1468da177 462 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost
<> 161:2cc1468da177 463 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
<> 161:2cc1468da177 464 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception
<> 161:2cc1468da177 465 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
<> 161:2cc1468da177 466 * @arg @ref SMBUS_FLAG_ALERT SMBus alert
<> 161:2cc1468da177 467 *
<> 161:2cc1468da177 468 * @retval None
<> 161:2cc1468da177 469 */
<> 161:2cc1468da177 470 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 161:2cc1468da177 471
<> 161:2cc1468da177 472 /** @brief Enable the specified SMBUS peripheral.
<> 161:2cc1468da177 473 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 474 * @retval None
<> 161:2cc1468da177 475 */
<> 161:2cc1468da177 476 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 161:2cc1468da177 477
<> 161:2cc1468da177 478 /** @brief Disable the specified SMBUS peripheral.
<> 161:2cc1468da177 479 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 480 * @retval None
<> 161:2cc1468da177 481 */
<> 161:2cc1468da177 482 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 161:2cc1468da177 483
<> 161:2cc1468da177 484 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
<> 161:2cc1468da177 485 * @param __HANDLE__ specifies the SMBUS Handle.
<> 161:2cc1468da177 486 * @retval None
<> 161:2cc1468da177 487 */
<> 161:2cc1468da177 488 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
<> 161:2cc1468da177 489
<> 161:2cc1468da177 490 /**
<> 161:2cc1468da177 491 * @}
<> 161:2cc1468da177 492 */
<> 161:2cc1468da177 493
<> 161:2cc1468da177 494
<> 161:2cc1468da177 495 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 496
<> 161:2cc1468da177 497 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 498 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
<> 161:2cc1468da177 499 * @{
<> 161:2cc1468da177 500 */
<> 161:2cc1468da177 501
<> 161:2cc1468da177 502 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
<> 161:2cc1468da177 503 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
<> 161:2cc1468da177 504
<> 161:2cc1468da177 505 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
<> 161:2cc1468da177 506 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
<> 161:2cc1468da177 507
<> 161:2cc1468da177 508 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
<> 161:2cc1468da177 509 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
<> 161:2cc1468da177 510
<> 161:2cc1468da177 511 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
<> 161:2cc1468da177 512 ((MASK) == SMBUS_OA2_MASK01) || \
<> 161:2cc1468da177 513 ((MASK) == SMBUS_OA2_MASK02) || \
<> 161:2cc1468da177 514 ((MASK) == SMBUS_OA2_MASK03) || \
<> 161:2cc1468da177 515 ((MASK) == SMBUS_OA2_MASK04) || \
<> 161:2cc1468da177 516 ((MASK) == SMBUS_OA2_MASK05) || \
<> 161:2cc1468da177 517 ((MASK) == SMBUS_OA2_MASK06) || \
<> 161:2cc1468da177 518 ((MASK) == SMBUS_OA2_MASK07))
<> 161:2cc1468da177 519
<> 161:2cc1468da177 520 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
<> 161:2cc1468da177 521 ((CALL) == SMBUS_GENERALCALL_ENABLE))
<> 161:2cc1468da177 522
<> 161:2cc1468da177 523 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
<> 161:2cc1468da177 524 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
<> 161:2cc1468da177 525
<> 161:2cc1468da177 526 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
<> 161:2cc1468da177 527 ((PEC) == SMBUS_PEC_ENABLE))
<> 161:2cc1468da177 528
<> 161:2cc1468da177 529 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
<> 161:2cc1468da177 530 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
<> 161:2cc1468da177 531 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
<> 161:2cc1468da177 532
<> 161:2cc1468da177 533 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
<> 161:2cc1468da177 534 ((MODE) == SMBUS_AUTOEND_MODE) || \
<> 161:2cc1468da177 535 ((MODE) == SMBUS_SOFTEND_MODE) || \
<> 161:2cc1468da177 536 ((MODE) == SMBUS_SENDPEC_MODE) || \
<> 161:2cc1468da177 537 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
<> 161:2cc1468da177 538 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
<> 161:2cc1468da177 539 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
<> 161:2cc1468da177 540 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
<> 161:2cc1468da177 541
<> 161:2cc1468da177 542
<> 161:2cc1468da177 543 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
<> 161:2cc1468da177 544 ((REQUEST) == SMBUS_GENERATE_START_READ) || \
<> 161:2cc1468da177 545 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
<> 161:2cc1468da177 546 ((REQUEST) == SMBUS_NO_STARTSTOP))
<> 161:2cc1468da177 547
<> 161:2cc1468da177 548
<> 161:2cc1468da177 549 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
<> 161:2cc1468da177 550 ((REQUEST) == SMBUS_NEXT_FRAME) || \
<> 161:2cc1468da177 551 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
<> 161:2cc1468da177 552 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
<> 161:2cc1468da177 553 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
<> 161:2cc1468da177 554 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
<> 161:2cc1468da177 555 IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
<> 161:2cc1468da177 556
<> 161:2cc1468da177 557 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
<> 161:2cc1468da177 558 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
<> 161:2cc1468da177 559 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
<> 161:2cc1468da177 560 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
<> 161:2cc1468da177 561
<> 161:2cc1468da177 562 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
<> 161:2cc1468da177 563 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
<> 161:2cc1468da177 564
<> 161:2cc1468da177 565 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
<> 161:2cc1468da177 566 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
<> 161:2cc1468da177 567
<> 161:2cc1468da177 568 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
<> 161:2cc1468da177 569 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
<> 161:2cc1468da177 570 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
<> 161:2cc1468da177 571 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
<> 161:2cc1468da177 572 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
<> 161:2cc1468da177 573
<> 161:2cc1468da177 574 #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
<> 161:2cc1468da177 575 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
<> 161:2cc1468da177 576
<> 161:2cc1468da177 577 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
<> 161:2cc1468da177 578 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
<> 161:2cc1468da177 579
<> 161:2cc1468da177 580 /**
<> 161:2cc1468da177 581 * @}
<> 161:2cc1468da177 582 */
<> 161:2cc1468da177 583
<> 161:2cc1468da177 584 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 585 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
<> 161:2cc1468da177 586 * @{
<> 161:2cc1468da177 587 */
<> 161:2cc1468da177 588
<> 161:2cc1468da177 589 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
<> 161:2cc1468da177 590 * @{
<> 161:2cc1468da177 591 */
<> 161:2cc1468da177 592
<> 161:2cc1468da177 593 /* Initialization and de-initialization functions **********************************/
<> 161:2cc1468da177 594 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 595 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 596 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 597 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 598
<> 161:2cc1468da177 599 /**
<> 161:2cc1468da177 600 * @}
<> 161:2cc1468da177 601 */
<> 161:2cc1468da177 602
<> 161:2cc1468da177 603 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
<> 161:2cc1468da177 604 * @{
<> 161:2cc1468da177 605 */
<> 161:2cc1468da177 606
<> 161:2cc1468da177 607 /* IO operation functions *****************************************************/
<> 161:2cc1468da177 608 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
<> 161:2cc1468da177 609 * @{
<> 161:2cc1468da177 610 */
<> 161:2cc1468da177 611 /******* Blocking mode: Polling */
<> 161:2cc1468da177 612 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 161:2cc1468da177 613 /**
<> 161:2cc1468da177 614 * @}
<> 161:2cc1468da177 615 */
<> 161:2cc1468da177 616
<> 161:2cc1468da177 617 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
<> 161:2cc1468da177 618 * @{
<> 161:2cc1468da177 619 */
<> 161:2cc1468da177 620 /******* Non-Blocking mode: Interrupt */
<> 161:2cc1468da177 621 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 161:2cc1468da177 622 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 161:2cc1468da177 623 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
<> 161:2cc1468da177 624 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 161:2cc1468da177 625 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 161:2cc1468da177 626
<> 161:2cc1468da177 627 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 628 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 629 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 630 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 631 /**
<> 161:2cc1468da177 632 * @}
<> 161:2cc1468da177 633 */
<> 161:2cc1468da177 634
<> 161:2cc1468da177 635 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
<> 161:2cc1468da177 636 * @{
<> 161:2cc1468da177 637 */
<> 161:2cc1468da177 638 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
<> 161:2cc1468da177 639 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 640 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 641 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 642 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 643 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 644 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 645 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 161:2cc1468da177 646 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 647 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 648
<> 161:2cc1468da177 649 /**
<> 161:2cc1468da177 650 * @}
<> 161:2cc1468da177 651 */
<> 161:2cc1468da177 652
<> 161:2cc1468da177 653 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
<> 161:2cc1468da177 654 * @{
<> 161:2cc1468da177 655 */
<> 161:2cc1468da177 656
<> 161:2cc1468da177 657 /* Peripheral State and Errors functions **************************************************/
<> 161:2cc1468da177 658 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 659 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
<> 161:2cc1468da177 660
<> 161:2cc1468da177 661 /**
<> 161:2cc1468da177 662 * @}
<> 161:2cc1468da177 663 */
<> 161:2cc1468da177 664
<> 161:2cc1468da177 665 /**
<> 161:2cc1468da177 666 * @}
<> 161:2cc1468da177 667 */
<> 161:2cc1468da177 668
<> 161:2cc1468da177 669 /* Private Functions ---------------------------------------------------------*/
<> 161:2cc1468da177 670 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
<> 161:2cc1468da177 671 * @{
<> 161:2cc1468da177 672 */
<> 161:2cc1468da177 673 /* Private functions are defined in stm32f7xx_hal_smbus.c file */
<> 161:2cc1468da177 674 /**
<> 161:2cc1468da177 675 * @}
<> 161:2cc1468da177 676 */
<> 161:2cc1468da177 677
<> 161:2cc1468da177 678 /**
<> 161:2cc1468da177 679 * @}
<> 161:2cc1468da177 680 */
<> 161:2cc1468da177 681
<> 161:2cc1468da177 682 /**
<> 161:2cc1468da177 683 * @}
<> 161:2cc1468da177 684 */
<> 161:2cc1468da177 685
<> 161:2cc1468da177 686 /**
<> 161:2cc1468da177 687 * @}
<> 161:2cc1468da177 688 */
<> 161:2cc1468da177 689
<> 161:2cc1468da177 690 #ifdef __cplusplus
<> 161:2cc1468da177 691 }
<> 161:2cc1468da177 692 #endif
<> 161:2cc1468da177 693
<> 161:2cc1468da177 694
<> 161:2cc1468da177 695 #endif /* __STM32F7xx_HAL_SMBUS_H */
<> 161:2cc1468da177 696
<> 161:2cc1468da177 697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/