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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:: <>
Date:: Thu Mar 30 13:45:57 2017 +0100
Revision:: 161:2cc1468da177
Parent:: 157:ff67d9f36b67
Child:: 168:9672193075cf

This updates the lib to the mbed lib v139

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of RCC HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F7xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F7xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f7xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/* Include RCC HAL Extended module */
<>	144:ef7eb2e8f9f7	50	/* (include on top of file since RCC structures are defined in extended file) */
<>	144:ef7eb2e8f9f7	51	#include "stm32f7xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/** @addtogroup RCC
<>	144:ef7eb2e8f9f7	58	* @{
<>	144:ef7eb2e8f9f7	59	*/
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	/** @defgroup RCC_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	64	* @{
<>	144:ef7eb2e8f9f7	65	*/
<>	144:ef7eb2e8f9f7	66
<>	144:ef7eb2e8f9f7	67	/**
<>	144:ef7eb2e8f9f7	68	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<>	144:ef7eb2e8f9f7	69	*/
<>	144:ef7eb2e8f9f7	70	typedef struct
<>	144:ef7eb2e8f9f7	71	{
<>	144:ef7eb2e8f9f7	72	uint32_t OscillatorType; /*!< The oscillators to be configured.
<>	144:ef7eb2e8f9f7	73	This parameter can be a value of @ref RCC_Oscillator_Type */
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	uint32_t HSEState; /*!< The new state of the HSE.
<>	144:ef7eb2e8f9f7	76	This parameter can be a value of @ref RCC_HSE_Config */
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	uint32_t LSEState; /*!< The new state of the LSE.
<>	144:ef7eb2e8f9f7	79	This parameter can be a value of @ref RCC_LSE_Config */
<>	144:ef7eb2e8f9f7	80
<>	144:ef7eb2e8f9f7	81	uint32_t HSIState; /*!< The new state of the HSI.
<>	144:ef7eb2e8f9f7	82	This parameter can be a value of @ref RCC_HSI_Config */
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	85	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
<>	144:ef7eb2e8f9f7	86
<>	144:ef7eb2e8f9f7	87	uint32_t LSIState; /*!< The new state of the LSI.
<>	144:ef7eb2e8f9f7	88	This parameter can be a value of @ref RCC_LSI_Config */
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	}RCC_OscInitTypeDef;
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	/**
<>	144:ef7eb2e8f9f7	95	* @brief RCC System, AHB and APB busses clock configuration structure definition
<>	144:ef7eb2e8f9f7	96	*/
<>	144:ef7eb2e8f9f7	97	typedef struct
<>	144:ef7eb2e8f9f7	98	{
<>	144:ef7eb2e8f9f7	99	uint32_t ClockType; /*!< The clock to be configured.
<>	144:ef7eb2e8f9f7	100	This parameter can be a value of @ref RCC_System_Clock_Type */
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<>	144:ef7eb2e8f9f7	103	This parameter can be a value of @ref RCC_System_Clock_Source */
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	106	This parameter can be a value of @ref RCC_AHB_Clock_Source */
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	109	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	110
<>	144:ef7eb2e8f9f7	111	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	112	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	}RCC_ClkInitTypeDef;
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	/**
<>	144:ef7eb2e8f9f7	117	* @}
<>	144:ef7eb2e8f9f7	118	*/
<>	144:ef7eb2e8f9f7	119
<>	144:ef7eb2e8f9f7	120	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	121	/** @defgroup RCC_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	122	* @{
<>	144:ef7eb2e8f9f7	123	*/
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	/** @defgroup RCC_Oscillator_Type Oscillator Type
<>	144:ef7eb2e8f9f7	126	* @{
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	129	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	130	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	131	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	132	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	133	/**
<>	144:ef7eb2e8f9f7	134	* @}
<>	144:ef7eb2e8f9f7	135	*/
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	/** @defgroup RCC_HSE_Config RCC HSE Config
<>	144:ef7eb2e8f9f7	138	* @{
<>	144:ef7eb2e8f9f7	139	*/
<>	144:ef7eb2e8f9f7	140	#define RCC_HSE_OFF ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	141	#define RCC_HSE_ON RCC_CR_HSEON
<>	144:ef7eb2e8f9f7	142	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
<>	144:ef7eb2e8f9f7	143	/**
<>	144:ef7eb2e8f9f7	144	* @}
<>	144:ef7eb2e8f9f7	145	*/
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	/** @defgroup RCC_LSE_Config RCC LSE Config
<>	144:ef7eb2e8f9f7	148	* @{
<>	144:ef7eb2e8f9f7	149	*/
<>	144:ef7eb2e8f9f7	150	#define RCC_LSE_OFF ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	151	#define RCC_LSE_ON RCC_BDCR_LSEON
<>	144:ef7eb2e8f9f7	152	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON))
<>	144:ef7eb2e8f9f7	153	/**
<>	144:ef7eb2e8f9f7	154	* @}
<>	144:ef7eb2e8f9f7	155	*/
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	/** @defgroup RCC_HSI_Config RCC HSI Config
<>	144:ef7eb2e8f9f7	158	* @{
<>	144:ef7eb2e8f9f7	159	*/
<>	144:ef7eb2e8f9f7	160	#define RCC_HSI_OFF ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	161	#define RCC_HSI_ON RCC_CR_HSION
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
<>	144:ef7eb2e8f9f7	164	/**
<>	144:ef7eb2e8f9f7	165	* @}
<>	144:ef7eb2e8f9f7	166	*/
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	/** @defgroup RCC_LSI_Config RCC LSI Config
<>	144:ef7eb2e8f9f7	169	* @{
<>	144:ef7eb2e8f9f7	170	*/
<>	144:ef7eb2e8f9f7	171	#define RCC_LSI_OFF ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	172	#define RCC_LSI_ON RCC_CSR_LSION
<>	144:ef7eb2e8f9f7	173	/**
<>	144:ef7eb2e8f9f7	174	* @}
<>	144:ef7eb2e8f9f7	175	*/
<>	144:ef7eb2e8f9f7	176
<>	144:ef7eb2e8f9f7	177	/** @defgroup RCC_PLL_Config RCC PLL Config
<>	144:ef7eb2e8f9f7	178	* @{
<>	144:ef7eb2e8f9f7	179	*/
<>	144:ef7eb2e8f9f7	180	#define RCC_PLL_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	181	#define RCC_PLL_OFF ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	182	#define RCC_PLL_ON ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	183	/**
<>	144:ef7eb2e8f9f7	184	* @}
<>	144:ef7eb2e8f9f7	185	*/
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
<>	144:ef7eb2e8f9f7	188	* @{
<>	144:ef7eb2e8f9f7	189	*/
<>	144:ef7eb2e8f9f7	190	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	191	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	192	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
<>	144:ef7eb2e8f9f7	193	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	194	/**
<>	144:ef7eb2e8f9f7	195	* @}
<>	144:ef7eb2e8f9f7	196	*/
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
<>	144:ef7eb2e8f9f7	199	* @{
<>	144:ef7eb2e8f9f7	200	*/
<>	144:ef7eb2e8f9f7	201	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
<>	144:ef7eb2e8f9f7	202	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
<>	144:ef7eb2e8f9f7	203	/**
<>	144:ef7eb2e8f9f7	204	* @}
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
<>	144:ef7eb2e8f9f7	208	* @{
<>	144:ef7eb2e8f9f7	209	*/
<>	144:ef7eb2e8f9f7	210	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	211	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	212	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
<>	144:ef7eb2e8f9f7	213	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	214	/**
<>	144:ef7eb2e8f9f7	215	* @}
<>	144:ef7eb2e8f9f7	216	*/
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
<>	144:ef7eb2e8f9f7	219	* @{
<>	144:ef7eb2e8f9f7	220	*/
<>	144:ef7eb2e8f9f7	221	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
<>	144:ef7eb2e8f9f7	222	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
<>	144:ef7eb2e8f9f7	223	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
<>	144:ef7eb2e8f9f7	224	/**
<>	144:ef7eb2e8f9f7	225	* @}
<>	144:ef7eb2e8f9f7	226	*/
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
<>	144:ef7eb2e8f9f7	230	* @{
<>	144:ef7eb2e8f9f7	231	*/
<>	144:ef7eb2e8f9f7	232	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	144:ef7eb2e8f9f7	233	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	144:ef7eb2e8f9f7	234	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	235	/**
<>	144:ef7eb2e8f9f7	236	* @}
<>	144:ef7eb2e8f9f7	237	*/
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
<>	144:ef7eb2e8f9f7	240	* @{
<>	144:ef7eb2e8f9f7	241	*/
<>	144:ef7eb2e8f9f7	242	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
<>	144:ef7eb2e8f9f7	243	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
<>	144:ef7eb2e8f9f7	244	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
<>	144:ef7eb2e8f9f7	245	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
<>	144:ef7eb2e8f9f7	246	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
<>	144:ef7eb2e8f9f7	247	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
<>	144:ef7eb2e8f9f7	248	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
<>	144:ef7eb2e8f9f7	249	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
<>	144:ef7eb2e8f9f7	250	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
<>	144:ef7eb2e8f9f7	251	/**
<>	144:ef7eb2e8f9f7	252	* @}
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
<>	144:ef7eb2e8f9f7	256	* @{
<>	144:ef7eb2e8f9f7	257	*/
<>	144:ef7eb2e8f9f7	258	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
<>	144:ef7eb2e8f9f7	259	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
<>	144:ef7eb2e8f9f7	260	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
<>	144:ef7eb2e8f9f7	261	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
<>	144:ef7eb2e8f9f7	262	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
<>	144:ef7eb2e8f9f7	263	/**
<>	144:ef7eb2e8f9f7	264	* @}
<>	144:ef7eb2e8f9f7	265	*/
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
<>	144:ef7eb2e8f9f7	268	* @{
<>	144:ef7eb2e8f9f7	269	*/
<>	144:ef7eb2e8f9f7	270	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	271	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	272	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
<>	144:ef7eb2e8f9f7	273	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
<>	144:ef7eb2e8f9f7	274	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
<>	144:ef7eb2e8f9f7	275	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
<>	144:ef7eb2e8f9f7	276	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
<>	144:ef7eb2e8f9f7	277	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
<>	144:ef7eb2e8f9f7	278	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
<>	144:ef7eb2e8f9f7	279	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
<>	144:ef7eb2e8f9f7	280	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
<>	144:ef7eb2e8f9f7	281	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
<>	144:ef7eb2e8f9f7	282	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
<>	144:ef7eb2e8f9f7	283	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
<>	144:ef7eb2e8f9f7	284	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
<>	144:ef7eb2e8f9f7	285	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
<>	144:ef7eb2e8f9f7	286	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
<>	144:ef7eb2e8f9f7	287	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
<>	144:ef7eb2e8f9f7	288	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
<>	144:ef7eb2e8f9f7	289	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
<>	144:ef7eb2e8f9f7	290	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
<>	144:ef7eb2e8f9f7	291	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
<>	144:ef7eb2e8f9f7	292	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
<>	144:ef7eb2e8f9f7	293	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
<>	144:ef7eb2e8f9f7	294	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
<>	144:ef7eb2e8f9f7	295	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
<>	144:ef7eb2e8f9f7	296	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
<>	144:ef7eb2e8f9f7	297	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
<>	144:ef7eb2e8f9f7	298	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
<>	144:ef7eb2e8f9f7	299	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
<>	144:ef7eb2e8f9f7	300	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
<>	144:ef7eb2e8f9f7	301	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
<>	144:ef7eb2e8f9f7	302	/**
<>	144:ef7eb2e8f9f7	303	* @}
<>	144:ef7eb2e8f9f7	304	*/
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/** @defgroup RCC_MCO_Index RCC MCO Index
<>	144:ef7eb2e8f9f7	309	* @{
<>	144:ef7eb2e8f9f7	310	*/
<>	144:ef7eb2e8f9f7	311	#define RCC_MCO1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	312	#define RCC_MCO2 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	313	/**
<>	144:ef7eb2e8f9f7	314	* @}
<>	144:ef7eb2e8f9f7	315	*/
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
<>	144:ef7eb2e8f9f7	318	* @{
<>	144:ef7eb2e8f9f7	319	*/
<>	144:ef7eb2e8f9f7	320	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	321	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
<>	144:ef7eb2e8f9f7	322	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
<>	144:ef7eb2e8f9f7	323	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
<>	144:ef7eb2e8f9f7	324	/**
<>	144:ef7eb2e8f9f7	325	* @}
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
<>	144:ef7eb2e8f9f7	329	* @{
<>	144:ef7eb2e8f9f7	330	*/
<>	144:ef7eb2e8f9f7	331	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	332	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
<>	144:ef7eb2e8f9f7	333	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
<>	144:ef7eb2e8f9f7	334	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
<>	144:ef7eb2e8f9f7	335	/**
<>	144:ef7eb2e8f9f7	336	* @}
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
<>	144:ef7eb2e8f9f7	340	* @{
<>	144:ef7eb2e8f9f7	341	*/
<>	144:ef7eb2e8f9f7	342	#define RCC_MCODIV_1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	343	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
<>	144:ef7eb2e8f9f7	344	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
<>	144:ef7eb2e8f9f7	345	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
<>	144:ef7eb2e8f9f7	346	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
<>	144:ef7eb2e8f9f7	347	/**
<>	144:ef7eb2e8f9f7	348	* @}
<>	144:ef7eb2e8f9f7	349	*/
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/** @defgroup RCC_Interrupt RCC Interrupt
<>	144:ef7eb2e8f9f7	352	* @{
<>	144:ef7eb2e8f9f7	353	*/
<>	144:ef7eb2e8f9f7	354	#define RCC_IT_LSIRDY ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	355	#define RCC_IT_LSERDY ((uint8_t)0x02U)
<>	144:ef7eb2e8f9f7	356	#define RCC_IT_HSIRDY ((uint8_t)0x04U)
<>	144:ef7eb2e8f9f7	357	#define RCC_IT_HSERDY ((uint8_t)0x08U)
<>	144:ef7eb2e8f9f7	358	#define RCC_IT_PLLRDY ((uint8_t)0x10U)
<>	144:ef7eb2e8f9f7	359	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
<>	144:ef7eb2e8f9f7	360	#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)
<>	144:ef7eb2e8f9f7	361	#define RCC_IT_CSS ((uint8_t)0x80U)
<>	144:ef7eb2e8f9f7	362	/**
<>	144:ef7eb2e8f9f7	363	* @}
<>	144:ef7eb2e8f9f7	364	*/
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/** @defgroup RCC_Flag RCC Flags
<>	144:ef7eb2e8f9f7	367	* Elements values convention: 0XXYYYYYb
<>	144:ef7eb2e8f9f7	368	* - YYYYY : Flag position in the register
<>	144:ef7eb2e8f9f7	369	* - 0XX : Register index
<>	144:ef7eb2e8f9f7	370	* - 01: CR register
<>	144:ef7eb2e8f9f7	371	* - 10: BDCR register
<>	144:ef7eb2e8f9f7	372	* - 11: CSR register
<>	144:ef7eb2e8f9f7	373	* @{
<>	144:ef7eb2e8f9f7	374	*/
<>	144:ef7eb2e8f9f7	375	/* Flags in the CR register */
<>	144:ef7eb2e8f9f7	376	#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
<>	144:ef7eb2e8f9f7	377	#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
<>	144:ef7eb2e8f9f7	378	#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
<>	144:ef7eb2e8f9f7	379	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
<>	144:ef7eb2e8f9f7	380	#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/* Flags in the BDCR register */
<>	144:ef7eb2e8f9f7	383	#define RCC_FLAG_LSERDY ((uint8_t)0x41U)
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/* Flags in the CSR register */
<>	144:ef7eb2e8f9f7	386	#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
<>	144:ef7eb2e8f9f7	387	#define RCC_FLAG_BORRST ((uint8_t)0x79U)
<>	144:ef7eb2e8f9f7	388	#define RCC_FLAG_PINRST ((uint8_t)0x7AU)
<>	144:ef7eb2e8f9f7	389	#define RCC_FLAG_PORRST ((uint8_t)0x7BU)
<>	144:ef7eb2e8f9f7	390	#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
<>	144:ef7eb2e8f9f7	391	#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
<>	144:ef7eb2e8f9f7	392	#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
<>	144:ef7eb2e8f9f7	393	#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
<>	144:ef7eb2e8f9f7	394	/**
<>	144:ef7eb2e8f9f7	395	* @}
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
<>	144:ef7eb2e8f9f7	399	* @{
<>	144:ef7eb2e8f9f7	400	*/
<>	144:ef7eb2e8f9f7	401	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	402	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
<>	144:ef7eb2e8f9f7	403	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
<>	144:ef7eb2e8f9f7	404	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
<>	144:ef7eb2e8f9f7	405	/**
<>	144:ef7eb2e8f9f7	406	* @}
<>	144:ef7eb2e8f9f7	407	*/
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/**
<>	144:ef7eb2e8f9f7	410	* @}
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	414	/** @defgroup RCC_Exported_Macros RCC Exported Macros
<>	144:ef7eb2e8f9f7	415	* @{
<>	144:ef7eb2e8f9f7	416	*/
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	419	* @brief Enable or disable the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	420	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	421	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	422	* using it.
<>	144:ef7eb2e8f9f7	423	* @{
<>	144:ef7eb2e8f9f7	424	*/
<>	144:ef7eb2e8f9f7	425	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	426	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	427	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
<>	144:ef7eb2e8f9f7	428	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	429	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
<>	144:ef7eb2e8f9f7	430	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	431	} while(0)
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	434	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	435	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	436	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	437	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	438	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	439	} while(0)
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
<>	144:ef7eb2e8f9f7	442	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	/**
<>	144:ef7eb2e8f9f7	445	* @}
<>	144:ef7eb2e8f9f7	446	*/
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	449	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<>	144:ef7eb2e8f9f7	450	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	451	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	452	* using it.
<>	144:ef7eb2e8f9f7	453	* @{
<>	144:ef7eb2e8f9f7	454	*/
<>	144:ef7eb2e8f9f7	455	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	456	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	457	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	458	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	459	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
<>	144:ef7eb2e8f9f7	460	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	461	} while(0)
<>	144:ef7eb2e8f9f7	462
<>	144:ef7eb2e8f9f7	463	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	464	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	465	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	466	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	467	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
<>	144:ef7eb2e8f9f7	468	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	469	} while(0)
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	472	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	473	/**
<>	144:ef7eb2e8f9f7	474	* @}
<>	144:ef7eb2e8f9f7	475	*/
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	478	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<>	144:ef7eb2e8f9f7	479	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	480	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	481	* using it.
<>	144:ef7eb2e8f9f7	482	* @{
<>	144:ef7eb2e8f9f7	483	*/
<>	144:ef7eb2e8f9f7	484	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	485	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	486	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<>	144:ef7eb2e8f9f7	487	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	488	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
<>	144:ef7eb2e8f9f7	489	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	490	} while(0)
<>	144:ef7eb2e8f9f7	491
<>	144:ef7eb2e8f9f7	492	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	/**
<>	144:ef7eb2e8f9f7	495	* @}
<>	144:ef7eb2e8f9f7	496	*/
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	499	* @brief Get the enable or disable status of the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	500	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	501	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	502	* using it.
<>	144:ef7eb2e8f9f7	503	* @{
<>	144:ef7eb2e8f9f7	504	*/
<>	144:ef7eb2e8f9f7	505	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
<>	144:ef7eb2e8f9f7	506	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
<>	144:ef7eb2e8f9f7	507
<>	144:ef7eb2e8f9f7	508	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
<>	144:ef7eb2e8f9f7	509	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
<>	144:ef7eb2e8f9f7	510	/**
<>	144:ef7eb2e8f9f7	511	* @}
<>	144:ef7eb2e8f9f7	512	*/
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	515	* @brief Get the enable or disable status of the APB1 peripheral clock.
<>	144:ef7eb2e8f9f7	516	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	517	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	518	* using it.
<>	144:ef7eb2e8f9f7	519	* @{
<>	144:ef7eb2e8f9f7	520	*/
<>	144:ef7eb2e8f9f7	521	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
<>	144:ef7eb2e8f9f7	522	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
<>	144:ef7eb2e8f9f7	523
<>	144:ef7eb2e8f9f7	524	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
<>	144:ef7eb2e8f9f7	525	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
<>	144:ef7eb2e8f9f7	526	/**
<>	144:ef7eb2e8f9f7	527	* @}
<>	144:ef7eb2e8f9f7	528	*/
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	531	* @brief EGet the enable or disable status of the APB2 peripheral clock.
<>	144:ef7eb2e8f9f7	532	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	533	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	534	* using it.
<>	144:ef7eb2e8f9f7	535	* @{
<>	144:ef7eb2e8f9f7	536	*/
<>	144:ef7eb2e8f9f7	537	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
<>	144:ef7eb2e8f9f7	538	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
<>	144:ef7eb2e8f9f7	539	/**
<>	144:ef7eb2e8f9f7	540	* @}
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
<>	144:ef7eb2e8f9f7	544	* @brief Force or release AHB peripheral reset.
<>	144:ef7eb2e8f9f7	545	* @{
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	548	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
<>	144:ef7eb2e8f9f7	549	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	552	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
<>	144:ef7eb2e8f9f7	553	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	554	/**
<>	144:ef7eb2e8f9f7	555	* @}
<>	144:ef7eb2e8f9f7	556	*/
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
<>	144:ef7eb2e8f9f7	559	* @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	560	* @{
<>	144:ef7eb2e8f9f7	561	*/
<>	144:ef7eb2e8f9f7	562	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	563	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	564	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	567	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	568	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	569	/**
<>	144:ef7eb2e8f9f7	570	* @}
<>	144:ef7eb2e8f9f7	571	*/
<>	144:ef7eb2e8f9f7	572
<>	144:ef7eb2e8f9f7	573	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
<>	144:ef7eb2e8f9f7	574	* @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	575	* @{
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	578	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	579
<>	144:ef7eb2e8f9f7	580	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	581	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	/**
<>	144:ef7eb2e8f9f7	584	* @}
<>	144:ef7eb2e8f9f7	585	*/
<>	144:ef7eb2e8f9f7	586
<>	144:ef7eb2e8f9f7	587	/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	588	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	589	* power consumption.
<>	144:ef7eb2e8f9f7	590	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	591	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	592	* @{
<>	144:ef7eb2e8f9f7	593	*/
<>	144:ef7eb2e8f9f7	594	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
<>	144:ef7eb2e8f9f7	595	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
<>	144:ef7eb2e8f9f7	598	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	601	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	602	* power consumption.
<>	144:ef7eb2e8f9f7	603	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	604	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	605	*/
<>	144:ef7eb2e8f9f7	606	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
<>	144:ef7eb2e8f9f7	607	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
<>	144:ef7eb2e8f9f7	610	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	613	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	614	* power consumption.
<>	144:ef7eb2e8f9f7	615	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	616	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	617	*/
<>	144:ef7eb2e8f9f7	618	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
<>	144:ef7eb2e8f9f7	619	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	/**
<>	144:ef7eb2e8f9f7	622	* @}
<>	144:ef7eb2e8f9f7	623	*/
<>	144:ef7eb2e8f9f7	624
<>	144:ef7eb2e8f9f7	625	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
<>	144:ef7eb2e8f9f7	626	* @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	627	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	628	* power consumption.
<>	144:ef7eb2e8f9f7	629	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	630	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	631	* @{
<>	144:ef7eb2e8f9f7	632	*/
<>	144:ef7eb2e8f9f7	633	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	634	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	635
<>	144:ef7eb2e8f9f7	636	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	637	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	638	/**
<>	144:ef7eb2e8f9f7	639	* @}
<>	144:ef7eb2e8f9f7	640	*/
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
<>	144:ef7eb2e8f9f7	643	* @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	644	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	645	* power consumption.
<>	144:ef7eb2e8f9f7	646	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	647	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	648	* @{
<>	144:ef7eb2e8f9f7	649	*/
<>	144:ef7eb2e8f9f7	650	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	651	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	654	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	655	/**
<>	144:ef7eb2e8f9f7	656	* @}
<>	144:ef7eb2e8f9f7	657	*/
<>	144:ef7eb2e8f9f7	658
<>	144:ef7eb2e8f9f7	659	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
<>	144:ef7eb2e8f9f7	660	* @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	661	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	662	* power consumption.
<>	144:ef7eb2e8f9f7	663	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	664	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	665	* @{
<>	144:ef7eb2e8f9f7	666	*/
<>	144:ef7eb2e8f9f7	667	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	668	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	669	/**
<>	144:ef7eb2e8f9f7	670	* @}
<>	144:ef7eb2e8f9f7	671	*/
<>	144:ef7eb2e8f9f7	672
<>	144:ef7eb2e8f9f7	673	/** @defgroup RCC_HSI_Configuration HSI Configuration
<>	144:ef7eb2e8f9f7	674	* @{
<>	144:ef7eb2e8f9f7	675	*/
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<>	144:ef7eb2e8f9f7	678	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	679	* It is used (enabled by hardware) as system clock source after startup
<>	144:ef7eb2e8f9f7	680	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
<>	144:ef7eb2e8f9f7	681	* of the HSE used directly or indirectly as system clock (if the Clock
<>	144:ef7eb2e8f9f7	682	* Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	683	* @note HSI can not be stopped if it is used as system clock source. In this case,
<>	144:ef7eb2e8f9f7	684	* you have to select another source of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	685	* @note After enabling the HSI, the application software should wait on HSIRDY
<>	144:ef7eb2e8f9f7	686	* flag to be set indicating that HSI clock is stable and can be used as
<>	144:ef7eb2e8f9f7	687	* system clock source.
<>	144:ef7eb2e8f9f7	688	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	689	* clock cycles.
<>	144:ef7eb2e8f9f7	690	*/
<>	144:ef7eb2e8f9f7	691	#define __HAL_RCC_HSI_ENABLE() (RCC->CR \|= (RCC_CR_HSION))
<>	144:ef7eb2e8f9f7	692	#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<>	144:ef7eb2e8f9f7	695	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	696	* and temperature that influence the frequency of the internal HSI RC.
<>	144:ef7eb2e8f9f7	697	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
<>	144:ef7eb2e8f9f7	698	* (default is RCC_HSICALIBRATION_DEFAULT).
<>	144:ef7eb2e8f9f7	699	*/
<>	144:ef7eb2e8f9f7	700	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
<>	144:ef7eb2e8f9f7	701	RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
<>	144:ef7eb2e8f9f7	702	/**
<>	144:ef7eb2e8f9f7	703	* @}
<>	144:ef7eb2e8f9f7	704	*/
<>	144:ef7eb2e8f9f7	705
<>	144:ef7eb2e8f9f7	706	/** @defgroup RCC_LSI_Configuration LSI Configuration
<>	144:ef7eb2e8f9f7	707	* @{
<>	144:ef7eb2e8f9f7	708	*/
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	711	* @note After enabling the LSI, the application software should wait on
<>	144:ef7eb2e8f9f7	712	* LSIRDY flag to be set indicating that LSI clock is stable and can
<>	144:ef7eb2e8f9f7	713	* be used to clock the IWDG and/or the RTC.
<>	144:ef7eb2e8f9f7	714	* @note LSI can not be disabled if the IWDG is running.
<>	144:ef7eb2e8f9f7	715	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<>	144:ef7eb2e8f9f7	716	* clock cycles.
<>	144:ef7eb2e8f9f7	717	*/
<>	144:ef7eb2e8f9f7	718	#define __HAL_RCC_LSI_ENABLE() (RCC->CSR \|= (RCC_CSR_LSION))
<>	144:ef7eb2e8f9f7	719	#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
<>	144:ef7eb2e8f9f7	720	/**
<>	144:ef7eb2e8f9f7	721	* @}
<>	144:ef7eb2e8f9f7	722	*/
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/** @defgroup RCC_HSE_Configuration HSE Configuration
<>	144:ef7eb2e8f9f7	725	* @{
<>	144:ef7eb2e8f9f7	726	*/
<>	144:ef7eb2e8f9f7	727	/**
<>	144:ef7eb2e8f9f7	728	* @brief Macro to configure the External High Speed oscillator (HSE).
<>	144:ef7eb2e8f9f7	729	* @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not
<>	144:ef7eb2e8f9f7	730	* supported by this macro. User should request a transition to HSE Off
<>	144:ef7eb2e8f9f7	731	* first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	732	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<>	144:ef7eb2e8f9f7	733	* software should wait on HSERDY flag to be set indicating that HSE clock
<>	144:ef7eb2e8f9f7	734	* is stable and can be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	735	* @note HSE state can not be changed if it is used directly or through the
<>	144:ef7eb2e8f9f7	736	* PLL as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	737	* of the system clock then change the HSE state (ex. disable it).
<>	144:ef7eb2e8f9f7	738	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	739	* @note This function reset the CSSON bit, so if the clock security system(CSS)
<>	144:ef7eb2e8f9f7	740	* was previously enabled you have to enable it again after calling this
<>	144:ef7eb2e8f9f7	741	* function.
<>	144:ef7eb2e8f9f7	742	* @param __STATE__: specifies the new state of the HSE.
<>	144:ef7eb2e8f9f7	743	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	744	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
<>	144:ef7eb2e8f9f7	745	* 6 HSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	746	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
<>	144:ef7eb2e8f9f7	747	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	748	*/
<>	144:ef7eb2e8f9f7	749	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	750	do { \
<>	144:ef7eb2e8f9f7	751	if ((__STATE__) == RCC_HSE_ON) \
<>	144:ef7eb2e8f9f7	752	{ \
<>	144:ef7eb2e8f9f7	753	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	754	} \
<>	144:ef7eb2e8f9f7	755	else if ((__STATE__) == RCC_HSE_OFF) \
<>	144:ef7eb2e8f9f7	756	{ \
<>	144:ef7eb2e8f9f7	757	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	758	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	759	} \
<>	144:ef7eb2e8f9f7	760	else if ((__STATE__) == RCC_HSE_BYPASS) \
<>	144:ef7eb2e8f9f7	761	{ \
<>	144:ef7eb2e8f9f7	762	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	763	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	764	} \
<>	144:ef7eb2e8f9f7	765	else \
<>	144:ef7eb2e8f9f7	766	{ \
<>	144:ef7eb2e8f9f7	767	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	768	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	769	} \
<>	144:ef7eb2e8f9f7	770	} while(0)
<>	144:ef7eb2e8f9f7	771	/**
<>	144:ef7eb2e8f9f7	772	* @}
<>	144:ef7eb2e8f9f7	773	*/
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	/** @defgroup RCC_LSE_Configuration LSE Configuration
<>	144:ef7eb2e8f9f7	776	* @{
<>	144:ef7eb2e8f9f7	777	*/
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	/**
<>	144:ef7eb2e8f9f7	780	* @brief Macro to configure the External Low Speed oscillator (LSE).
<>	144:ef7eb2e8f9f7	781	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
<>	144:ef7eb2e8f9f7	782	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
<>	144:ef7eb2e8f9f7	783	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	784	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	785	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	786	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	787	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<>	144:ef7eb2e8f9f7	788	* software should wait on LSERDY flag to be set indicating that LSE clock
<>	144:ef7eb2e8f9f7	789	* is stable and can be used to clock the RTC.
<>	144:ef7eb2e8f9f7	790	* @param __STATE__: specifies the new state of the LSE.
<>	144:ef7eb2e8f9f7	791	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	792	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
<>	144:ef7eb2e8f9f7	793	* 6 LSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	794	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
<>	144:ef7eb2e8f9f7	795	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	796	*/
<>	144:ef7eb2e8f9f7	797	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	798	do { \
<>	144:ef7eb2e8f9f7	799	if((__STATE__) == RCC_LSE_ON) \
<>	144:ef7eb2e8f9f7	800	{ \
<>	144:ef7eb2e8f9f7	801	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	802	} \
<>	144:ef7eb2e8f9f7	803	else if((__STATE__) == RCC_LSE_OFF) \
<>	144:ef7eb2e8f9f7	804	{ \
<>	144:ef7eb2e8f9f7	805	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	806	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	807	} \
<>	144:ef7eb2e8f9f7	808	else if((__STATE__) == RCC_LSE_BYPASS) \
<>	144:ef7eb2e8f9f7	809	{ \
<>	144:ef7eb2e8f9f7	810	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	811	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	812	} \
<>	144:ef7eb2e8f9f7	813	else \
<>	144:ef7eb2e8f9f7	814	{ \
<>	144:ef7eb2e8f9f7	815	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
<>	144:ef7eb2e8f9f7	816	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
<>	144:ef7eb2e8f9f7	817	} \
<>	144:ef7eb2e8f9f7	818	} while(0)
<>	144:ef7eb2e8f9f7	819	/**
<>	144:ef7eb2e8f9f7	820	* @}
<>	144:ef7eb2e8f9f7	821	*/
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
<>	144:ef7eb2e8f9f7	824	* @{
<>	144:ef7eb2e8f9f7	825	*/
<>	144:ef7eb2e8f9f7	826
<>	144:ef7eb2e8f9f7	827	/** @brief Macros to enable or disable the RTC clock.
<>	144:ef7eb2e8f9f7	828	* @note These macros must be used only after the RTC clock source was selected.
<>	144:ef7eb2e8f9f7	829	*/
<>	144:ef7eb2e8f9f7	830	#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR \|= (RCC_BDCR_RTCEN))
<>	144:ef7eb2e8f9f7	831	#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
<>	144:ef7eb2e8f9f7	832
<>	144:ef7eb2e8f9f7	833	/** @brief Macros to configure the RTC clock (RTCCLK).
<>	144:ef7eb2e8f9f7	834	* @note As the RTC clock configuration bits are in the Backup domain and write
<>	144:ef7eb2e8f9f7	835	* access is denied to this domain after reset, you have to enable write
<>	144:ef7eb2e8f9f7	836	* access using the Power Backup Access macro before to configure
<>	144:ef7eb2e8f9f7	837	* the RTC clock source (to be done once after reset).
<>	144:ef7eb2e8f9f7	838	* @note Once the RTC clock is configured it can't be changed unless the
<>	144:ef7eb2e8f9f7	839	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
<>	144:ef7eb2e8f9f7	840	* a Power On Reset (POR).
<>	144:ef7eb2e8f9f7	841	* @param __RTCCLKSource__: specifies the RTC clock source.
<>	144:ef7eb2e8f9f7	842	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	843	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
<>	144:ef7eb2e8f9f7	844	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
<>	144:ef7eb2e8f9f7	845	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
<>	144:ef7eb2e8f9f7	846	* as RTC clock, where x:[2,31]
<>	144:ef7eb2e8f9f7	847	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<>	144:ef7eb2e8f9f7	848	* work in STOP and STANDBY modes, and can be used as wakeup source.
<>	144:ef7eb2e8f9f7	849	* However, when the HSE clock is used as RTC clock source, the RTC
<>	144:ef7eb2e8f9f7	850	* cannot be used in STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	851	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
<>	144:ef7eb2e8f9f7	852	* RTC clock source).
<>	144:ef7eb2e8f9f7	853	*/
<>	144:ef7eb2e8f9f7	854	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
<>	144:ef7eb2e8f9f7	855	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
<>	144:ef7eb2e8f9f7	858	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
<>	144:ef7eb2e8f9f7	859	} while (0)
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/** @brief Macros to force or release the Backup domain reset.
<>	144:ef7eb2e8f9f7	862	* @note This function resets the RTC peripheral (including the backup registers)
<>	144:ef7eb2e8f9f7	863	* and the RTC clock source selection in RCC_CSR register.
<>	144:ef7eb2e8f9f7	864	* @note The BKPSRAM is not affected by this reset.
<>	144:ef7eb2e8f9f7	865	*/
<>	144:ef7eb2e8f9f7	866	#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR \|= (RCC_BDCR_BDRST))
<>	144:ef7eb2e8f9f7	867	#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
<>	144:ef7eb2e8f9f7	868	/**
<>	144:ef7eb2e8f9f7	869	* @}
<>	144:ef7eb2e8f9f7	870	*/
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	/** @defgroup RCC_PLL_Configuration PLL Configuration
<>	144:ef7eb2e8f9f7	873	* @{
<>	144:ef7eb2e8f9f7	874	*/
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/** @brief Macros to enable or disable the main PLL.
<>	144:ef7eb2e8f9f7	877	* @note After enabling the main PLL, the application software should wait on
<>	144:ef7eb2e8f9f7	878	* PLLRDY flag to be set indicating that PLL clock is stable and can
<>	144:ef7eb2e8f9f7	879	* be used as system clock source.
<>	144:ef7eb2e8f9f7	880	* @note The main PLL can not be disabled if it is used as system clock source
<>	144:ef7eb2e8f9f7	881	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	882	*/
<>	144:ef7eb2e8f9f7	883	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	884	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/** @brief Macro to configure the PLL clock source.
<>	144:ef7eb2e8f9f7	887	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	888	* @param __PLLSOURCE__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	889	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	890	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	891	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	892	*
<>	144:ef7eb2e8f9f7	893	*/
<>	144:ef7eb2e8f9f7	894	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
<>	144:ef7eb2e8f9f7	895
<>	144:ef7eb2e8f9f7	896	/** @brief Macro to configure the PLL multiplication factor.
<>	144:ef7eb2e8f9f7	897	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	898	* @param __PLLM__: specifies the division factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	899	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<>	144:ef7eb2e8f9f7	900	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	901	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	902	* of 2 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	903	*
<>	144:ef7eb2e8f9f7	904	*/
<>	144:ef7eb2e8f9f7	905	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
<>	144:ef7eb2e8f9f7	906	/**
<>	144:ef7eb2e8f9f7	907	* @}
<>	144:ef7eb2e8f9f7	908	*/
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
<>	144:ef7eb2e8f9f7	911	* @{
<>	144:ef7eb2e8f9f7	912	*/
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	/** @brief Macro to configure the I2S clock source (I2SCLK).
<>	144:ef7eb2e8f9f7	915	* @note This function must be called before enabling the I2S APB clock.
<>	144:ef7eb2e8f9f7	916	* @param __SOURCE__: specifies the I2S clock source.
<>	144:ef7eb2e8f9f7	917	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	918	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
<>	144:ef7eb2e8f9f7	919	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
<>	144:ef7eb2e8f9f7	920	* used as I2S clock source.
<>	144:ef7eb2e8f9f7	921	*/
<>	144:ef7eb2e8f9f7	922	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
<>	144:ef7eb2e8f9f7	923	RCC->CFGR \|= (__SOURCE__); \
<>	144:ef7eb2e8f9f7	924	}while(0)
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/** @brief Macros to enable or disable the PLLI2S.
<>	144:ef7eb2e8f9f7	927	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	928	*/
<>	144:ef7eb2e8f9f7	929	#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR \|= (RCC_CR_PLLI2SON))
<>	144:ef7eb2e8f9f7	930	#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
<>	144:ef7eb2e8f9f7	931	/**
<>	144:ef7eb2e8f9f7	932	* @}
<>	144:ef7eb2e8f9f7	933	*/
<>	144:ef7eb2e8f9f7	934
<>	144:ef7eb2e8f9f7	935	/** @defgroup RCC_Get_Clock_source Get Clock source
<>	144:ef7eb2e8f9f7	936	* @{
<>	144:ef7eb2e8f9f7	937	*/
<>	144:ef7eb2e8f9f7	938	/**
<>	144:ef7eb2e8f9f7	939	* @brief Macro to configure the system clock source.
<>	144:ef7eb2e8f9f7	940	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
<>	144:ef7eb2e8f9f7	941	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	942	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	943	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	944	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
<>	144:ef7eb2e8f9f7	945	*/
<>	144:ef7eb2e8f9f7	946	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	/** @brief Macro to get the clock source used as system clock.
<>	144:ef7eb2e8f9f7	949	* @retval The clock source used as system clock. The returned value can be one
<>	144:ef7eb2e8f9f7	950	* of the following:
<>	144:ef7eb2e8f9f7	951	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
<>	144:ef7eb2e8f9f7	952	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
<>	144:ef7eb2e8f9f7	953	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
<>	144:ef7eb2e8f9f7	954	*/
<>	144:ef7eb2e8f9f7	955	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	/**
<>	144:ef7eb2e8f9f7	958	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
<>	144:ef7eb2e8f9f7	959	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	960	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	961	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	962	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	963	* @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
<>	144:ef7eb2e8f9f7	964	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	965	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
<>	144:ef7eb2e8f9f7	966	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
<>	144:ef7eb2e8f9f7	967	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
<>	144:ef7eb2e8f9f7	968	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
<>	144:ef7eb2e8f9f7	969	* @retval None
<>	144:ef7eb2e8f9f7	970	*/
<>	144:ef7eb2e8f9f7	971	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
<>	144:ef7eb2e8f9f7	972	(MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	/** @brief Macro to get the oscillator used as PLL clock source.
<>	144:ef7eb2e8f9f7	975	* @retval The oscillator used as PLL clock source. The returned value can be one
<>	144:ef7eb2e8f9f7	976	* of the following:
<>	144:ef7eb2e8f9f7	977	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	978	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	979	*/
<>	144:ef7eb2e8f9f7	980	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
<>	144:ef7eb2e8f9f7	981	/**
<>	144:ef7eb2e8f9f7	982	* @}
<>	144:ef7eb2e8f9f7	983	*/
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
<>	144:ef7eb2e8f9f7	986	* @{
<>	144:ef7eb2e8f9f7	987	*/
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	/** @brief Macro to configure the MCO1 clock.
<>	144:ef7eb2e8f9f7	990	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	991	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	992	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	993	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	994	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	995	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
<>	144:ef7eb2e8f9f7	996	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	997	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	998	* @arg RCC_MCODIV_1: no division applied to MCOx clock
<>	144:ef7eb2e8f9f7	999	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1000	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1001	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1002	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1003	*/
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1006	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	/** @brief Macro to configure the MCO2 clock.
<>	144:ef7eb2e8f9f7	1009	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	1010	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1011	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
<>	144:ef7eb2e8f9f7	1012	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1013	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1014	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
<>	144:ef7eb2e8f9f7	1015	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	1016	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1017	* @arg RCC_MCODIV_1: no division applied to MCOx clock
<>	144:ef7eb2e8f9f7	1018	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1019	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1020	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1021	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<>	144:ef7eb2e8f9f7	1022	*/
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1025	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 3)));
<>	144:ef7eb2e8f9f7	1026	/**
<>	144:ef7eb2e8f9f7	1027	* @}
<>	144:ef7eb2e8f9f7	1028	*/
<>	144:ef7eb2e8f9f7	1029
<>	144:ef7eb2e8f9f7	1030	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
<>	144:ef7eb2e8f9f7	1031	* @brief macros to manage the specified RCC Flags and interrupts.
<>	144:ef7eb2e8f9f7	1032	* @{
<>	144:ef7eb2e8f9f7	1033	*/
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
<>	144:ef7eb2e8f9f7	1036	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1037	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	1038	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1039	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1040	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1041	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1042	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1043	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1044	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1045	*/
<>	144:ef7eb2e8f9f7	1046	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1047
<>	144:ef7eb2e8f9f7	1048	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
<>	144:ef7eb2e8f9f7	1049	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1050	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	1051	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1052	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1053	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1054	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1055	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1056	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1057	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1058	*/
<>	144:ef7eb2e8f9f7	1059	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
<>	144:ef7eb2e8f9f7	1062	* bits to clear the selected interrupt pending bits.
<>	144:ef7eb2e8f9f7	1063	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	1064	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1065	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1066	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1067	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1068	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1069	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1070	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1071	* @arg RCC_IT_CSS: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1072	*/
<>	144:ef7eb2e8f9f7	1073	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1074
<>	144:ef7eb2e8f9f7	1075	/** @brief Check the RCC's interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	1076	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
<>	144:ef7eb2e8f9f7	1077	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1078	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
<>	144:ef7eb2e8f9f7	1079	* @arg RCC_IT_LSERDY: LSE ready interrupt.
<>	144:ef7eb2e8f9f7	1080	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
<>	144:ef7eb2e8f9f7	1081	* @arg RCC_IT_HSERDY: HSE ready interrupt.
<>	144:ef7eb2e8f9f7	1082	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
<>	144:ef7eb2e8f9f7	1083	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
<>	144:ef7eb2e8f9f7	1084	* @arg RCC_IT_CSS: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1085	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1086	*/
<>	144:ef7eb2e8f9f7	1087	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1088
<>	144:ef7eb2e8f9f7	1089	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
<>	144:ef7eb2e8f9f7	1090	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
<>	144:ef7eb2e8f9f7	1091	*/
<>	144:ef7eb2e8f9f7	1092	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	/** @brief Check RCC flag is set or not.
<>	144:ef7eb2e8f9f7	1095	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	1096	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1097	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1098	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1099	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
<>	144:ef7eb2e8f9f7	1100	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
<>	144:ef7eb2e8f9f7	1101	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
<>	144:ef7eb2e8f9f7	1102	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
<>	144:ef7eb2e8f9f7	1103	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
<>	144:ef7eb2e8f9f7	1104	* @arg RCC_FLAG_PINRST: Pin reset.
<>	144:ef7eb2e8f9f7	1105	* @arg RCC_FLAG_PORRST: POR/PDR reset.
<>	144:ef7eb2e8f9f7	1106	* @arg RCC_FLAG_SFTRST: Software reset.
<>	144:ef7eb2e8f9f7	1107	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
<>	144:ef7eb2e8f9f7	1108	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
<>	144:ef7eb2e8f9f7	1109	* @arg RCC_FLAG_LPWRRST: Low Power reset.
<>	144:ef7eb2e8f9f7	1110	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1111	*/
<>	144:ef7eb2e8f9f7	1112	#define RCC_FLAG_MASK ((uint8_t)0x1F)
<>	144:ef7eb2e8f9f7	1113	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
<>	144:ef7eb2e8f9f7	1114
<>	144:ef7eb2e8f9f7	1115	/**
<>	144:ef7eb2e8f9f7	1116	* @}
<>	144:ef7eb2e8f9f7	1117	*/
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	/**
<>	144:ef7eb2e8f9f7	1120	* @}
<>	144:ef7eb2e8f9f7	1121	*/
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/* Include RCC HAL Extension module */
<>	144:ef7eb2e8f9f7	1124	#include "stm32f7xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1127	/** @addtogroup RCC_Exported_Functions
<>	144:ef7eb2e8f9f7	1128	* @{
<>	144:ef7eb2e8f9f7	1129	*/
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	/** @addtogroup RCC_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1132	* @{
<>	144:ef7eb2e8f9f7	1133	*/
<>	144:ef7eb2e8f9f7	1134	/* Initialization and de-initialization functions ******************************/
<>	144:ef7eb2e8f9f7	1135	void HAL_RCC_DeInit(void);
<>	144:ef7eb2e8f9f7	1136	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1137	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<>	144:ef7eb2e8f9f7	1138	/**
<>	144:ef7eb2e8f9f7	1139	* @}
<>	144:ef7eb2e8f9f7	1140	*/
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	/** @addtogroup RCC_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	1143	* @{
<>	144:ef7eb2e8f9f7	1144	*/
<>	144:ef7eb2e8f9f7	1145	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1146	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<>	144:ef7eb2e8f9f7	1147	void HAL_RCC_EnableCSS(void);
<>	144:ef7eb2e8f9f7	1148	void HAL_RCC_DisableCSS(void);
<>	144:ef7eb2e8f9f7	1149	uint32_t HAL_RCC_GetSysClockFreq(void);
<>	144:ef7eb2e8f9f7	1150	uint32_t HAL_RCC_GetHCLKFreq(void);
<>	144:ef7eb2e8f9f7	1151	uint32_t HAL_RCC_GetPCLK1Freq(void);
<>	144:ef7eb2e8f9f7	1152	uint32_t HAL_RCC_GetPCLK2Freq(void);
<>	144:ef7eb2e8f9f7	1153	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1154	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
<>	144:ef7eb2e8f9f7	1155
<>	144:ef7eb2e8f9f7	1156	/* CSS NMI IRQ handler */
<>	144:ef7eb2e8f9f7	1157	void HAL_RCC_NMI_IRQHandler(void);
<>	144:ef7eb2e8f9f7	1158
<>	144:ef7eb2e8f9f7	1159	/* User Callbacks in non blocking mode (IT mode) */
<>	144:ef7eb2e8f9f7	1160	void HAL_RCC_CSSCallback(void);
<>	144:ef7eb2e8f9f7	1161	/**
<>	144:ef7eb2e8f9f7	1162	* @}
<>	144:ef7eb2e8f9f7	1163	*/
<>	144:ef7eb2e8f9f7	1164
<>	144:ef7eb2e8f9f7	1165	/**
<>	144:ef7eb2e8f9f7	1166	* @}
<>	144:ef7eb2e8f9f7	1167	*/
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1170	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1171	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1172	/** @defgroup RCC_Private_Constants RCC Private Constants
<>	144:ef7eb2e8f9f7	1173	* @{
<>	144:ef7eb2e8f9f7	1174	*/
<>	144:ef7eb2e8f9f7	1175	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	1176	#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
<>	144:ef7eb2e8f9f7	1177	#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
<>	144:ef7eb2e8f9f7	1178	#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
<>	144:ef7eb2e8f9f7	1179	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
<>	144:ef7eb2e8f9f7	1180
<>	144:ef7eb2e8f9f7	1181	/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
<>	144:ef7eb2e8f9f7	1182	* @brief RCC registers bit address alias
<>	144:ef7eb2e8f9f7	1183	* @{
<>	144:ef7eb2e8f9f7	1184	*/
<>	144:ef7eb2e8f9f7	1185	/* CIR register byte 2 (Bits[15:8]) base address */
<>	144:ef7eb2e8f9f7	1186	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
<>	144:ef7eb2e8f9f7	1187
<>	144:ef7eb2e8f9f7	1188	/* CIR register byte 3 (Bits[23:16]) base address */
<>	144:ef7eb2e8f9f7	1189	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
<>	144:ef7eb2e8f9f7	1192	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	1193	/**
<>	144:ef7eb2e8f9f7	1194	* @}
<>	144:ef7eb2e8f9f7	1195	*/
<>	144:ef7eb2e8f9f7	1196	/**
<>	144:ef7eb2e8f9f7	1197	* @}
<>	144:ef7eb2e8f9f7	1198	*/
<>	144:ef7eb2e8f9f7	1199
<>	144:ef7eb2e8f9f7	1200	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1201	/** @addtogroup RCC_Private_Macros RCC Private Macros
<>	144:ef7eb2e8f9f7	1202	* @{
<>	144:ef7eb2e8f9f7	1203	*/
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
<>	144:ef7eb2e8f9f7	1206	* @{
<>	144:ef7eb2e8f9f7	1207	*/
<>	144:ef7eb2e8f9f7	1208	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
<>	144:ef7eb2e8f9f7	1209
<>	144:ef7eb2e8f9f7	1210	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1211	((HSE) == RCC_HSE_BYPASS))
<>	144:ef7eb2e8f9f7	1212
<>	144:ef7eb2e8f9f7	1213	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1214	((LSE) == RCC_LSE_BYPASS))
<>	144:ef7eb2e8f9f7	1215
<>	144:ef7eb2e8f9f7	1216	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
<>	144:ef7eb2e8f9f7	1221
<>	144:ef7eb2e8f9f7	1222	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1223	((SOURCE) == RCC_PLLSOURCE_HSE))
<>	144:ef7eb2e8f9f7	1224
<>	144:ef7eb2e8f9f7	1225	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1226	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	1227	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	1228	#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
<>	144:ef7eb2e8f9f7	1231
<>	144:ef7eb2e8f9f7	1232	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) \|\| ((VALUE) == RCC_PLLP_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1233	((VALUE) == RCC_PLLP_DIV6) \|\| ((VALUE) == RCC_PLLP_DIV8))
<>	144:ef7eb2e8f9f7	1234	#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
<>	144:ef7eb2e8f9f7	1235
<>	144:ef7eb2e8f9f7	1236	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1237	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1238	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
<>	144:ef7eb2e8f9f7	1239	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
<>	144:ef7eb2e8f9f7	1240	((HCLK) == RCC_SYSCLK_DIV512))
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1245	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1246	((PCLK) == RCC_HCLK_DIV16))
<>	144:ef7eb2e8f9f7	1247
<>	144:ef7eb2e8f9f7	1248	#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) \|\| ((MCOX) == RCC_MCO2))
<>	144:ef7eb2e8f9f7	1249
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	1252	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	1253
<>	144:ef7eb2e8f9f7	1254	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
<>	144:ef7eb2e8f9f7	1255	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
<>	144:ef7eb2e8f9f7	1258	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
<>	144:ef7eb2e8f9f7	1259	((DIV) == RCC_MCODIV_5))
<>	144:ef7eb2e8f9f7	1260	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	1263	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) \|\| \
<>	144:ef7eb2e8f9f7	1264	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) \|\| \
<>	144:ef7eb2e8f9f7	1265	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) \|\| \
<>	144:ef7eb2e8f9f7	1266	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) \|\| \
<>	144:ef7eb2e8f9f7	1267	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) \|\| \
<>	144:ef7eb2e8f9f7	1268	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) \|\| \
<>	144:ef7eb2e8f9f7	1269	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) \|\| \
<>	144:ef7eb2e8f9f7	1270	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) \|\| \
<>	144:ef7eb2e8f9f7	1271	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) \|\| \
<>	144:ef7eb2e8f9f7	1272	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) \|\| \
<>	144:ef7eb2e8f9f7	1273	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) \|\| \
<>	144:ef7eb2e8f9f7	1274	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) \|\| \
<>	144:ef7eb2e8f9f7	1275	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) \|\| \
<>	144:ef7eb2e8f9f7	1276	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) \|\| \
<>	144:ef7eb2e8f9f7	1277	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
<>	144:ef7eb2e8f9f7	1278
<>	144:ef7eb2e8f9f7	1279
<>	144:ef7eb2e8f9f7	1280	#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) \|\| \
<>	144:ef7eb2e8f9f7	1281	((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
<>	144:ef7eb2e8f9f7	1282	((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
<>	144:ef7eb2e8f9f7	1283	((DRIVE) == RCC_LSEDRIVE_HIGH))
<>	144:ef7eb2e8f9f7	1284	/**
<>	144:ef7eb2e8f9f7	1285	* @}
<>	144:ef7eb2e8f9f7	1286	*/
<>	144:ef7eb2e8f9f7	1287
<>	144:ef7eb2e8f9f7	1288	/**
<>	144:ef7eb2e8f9f7	1289	* @}
<>	144:ef7eb2e8f9f7	1290	*/
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/**
<>	144:ef7eb2e8f9f7	1293	* @}
<>	144:ef7eb2e8f9f7	1294	*/
<>	144:ef7eb2e8f9f7	1295
<>	144:ef7eb2e8f9f7	1296	/**
<>	144:ef7eb2e8f9f7	1297	* @}
<>	144:ef7eb2e8f9f7	1298	*/
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1301	}
<>	144:ef7eb2e8f9f7	1302	#endif
<>	144:ef7eb2e8f9f7	1303
<>	144:ef7eb2e8f9f7	1304	#endif /* __STM32F7xx_HAL_RCC_H */
<>	144:ef7eb2e8f9f7	1305
<>	144:ef7eb2e8f9f7	1306	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/