mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c@161:2cc1468da177, 2017-03-30 (annotated)

Committer:: <>
Date:: Thu Mar 30 13:45:57 2017 +0100
Revision:: 161:2cc1468da177
Parent:: 157:ff67d9f36b67
Child:: 168:9672193075cf

This updates the lib to the mbed lib v139

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_qspi.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	161:2cc1468da177	5	* @version V1.2.0
<>	161:2cc1468da177	6	* @date 30-December-2016
<>	144:ef7eb2e8f9f7	7	* @brief QSPI HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the QuadSPI interface (QSPI).
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + Indirect functional mode management
<>	144:ef7eb2e8f9f7	12	* + Memory-mapped functional mode management
<>	144:ef7eb2e8f9f7	13	* + Auto-polling functional mode management
<>	144:ef7eb2e8f9f7	14	* + Interrupts and flags management
<>	144:ef7eb2e8f9f7	15	* + DMA channel configuration for indirect functional mode
<>	144:ef7eb2e8f9f7	16	* + Errors management and abort functionality
<>	144:ef7eb2e8f9f7	17	*
<>	144:ef7eb2e8f9f7	18	*
<>	144:ef7eb2e8f9f7	19	@verbatim
<>	144:ef7eb2e8f9f7	20	===============================================================================
<>	144:ef7eb2e8f9f7	21	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	22	===============================================================================
<>	144:ef7eb2e8f9f7	23	[..]
<>	144:ef7eb2e8f9f7	24	* Initialization *
<>	144:ef7eb2e8f9f7	25	======================
<>	144:ef7eb2e8f9f7	26	[..]
<>	144:ef7eb2e8f9f7	27	(#) As prerequisite, fill in the HAL_QSPI_MspInit() :
<>	144:ef7eb2e8f9f7	28	(++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
<>	144:ef7eb2e8f9f7	29	(++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
<>	144:ef7eb2e8f9f7	30	(++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
<>	144:ef7eb2e8f9f7	31	(++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
<>	144:ef7eb2e8f9f7	32	(++) If interrupt mode is used, enable and configure QuadSPI global
<>	144:ef7eb2e8f9f7	33	interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<>	144:ef7eb2e8f9f7	34	(++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
<>	144:ef7eb2e8f9f7	35	with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
<>	144:ef7eb2e8f9f7	36	link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
<>	144:ef7eb2e8f9f7	37	DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
<>	144:ef7eb2e8f9f7	38	(#) Configure the flash size, the clock prescaler, the fifo threshold, the
<>	144:ef7eb2e8f9f7	39	clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	* Indirect functional mode *
<>	144:ef7eb2e8f9f7	42	================================
<>	144:ef7eb2e8f9f7	43	[..]
<>	144:ef7eb2e8f9f7	44	(#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
<>	144:ef7eb2e8f9f7	45	functions :
<>	144:ef7eb2e8f9f7	46	(++) Instruction phase : the mode used and if present the instruction opcode.
<>	144:ef7eb2e8f9f7	47	(++) Address phase : the mode used and if present the size and the address value.
<>	144:ef7eb2e8f9f7	48	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
<>	144:ef7eb2e8f9f7	49	bytes values.
<>	144:ef7eb2e8f9f7	50	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
<>	144:ef7eb2e8f9f7	51	(++) Data phase : the mode used and if present the number of bytes.
<>	144:ef7eb2e8f9f7	52	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
<>	144:ef7eb2e8f9f7	53	if activated.
<>	144:ef7eb2e8f9f7	54	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
<>	144:ef7eb2e8f9f7	55	(#) If no data is required for the command, it is sent directly to the memory :
<>	144:ef7eb2e8f9f7	56	(++) In polling mode, the output of the function is done when the transfer is complete.
<>	144:ef7eb2e8f9f7	57	(++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	58	(#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
<>	144:ef7eb2e8f9f7	59	HAL_QSPI_Transmit_IT() after the command configuration :
<>	144:ef7eb2e8f9f7	60	(++) In polling mode, the output of the function is done when the transfer is complete.
<>	144:ef7eb2e8f9f7	61	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
<>	144:ef7eb2e8f9f7	62	is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	63	(++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
<>	144:ef7eb2e8f9f7	64	HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	65	(#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
<>	144:ef7eb2e8f9f7	66	HAL_QSPI_Receive_IT() after the command configuration :
<>	144:ef7eb2e8f9f7	67	(++) In polling mode, the output of the function is done when the transfer is complete.
<>	144:ef7eb2e8f9f7	68	(++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
<>	144:ef7eb2e8f9f7	69	is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	70	(++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
<>	144:ef7eb2e8f9f7	71	HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	* Auto-polling functional mode *
<>	144:ef7eb2e8f9f7	74	====================================
<>	144:ef7eb2e8f9f7	75	[..]
<>	144:ef7eb2e8f9f7	76	(#) Configure the command sequence and the auto-polling functional mode using the
<>	144:ef7eb2e8f9f7	77	HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
<>	144:ef7eb2e8f9f7	78	(++) Instruction phase : the mode used and if present the instruction opcode.
<>	144:ef7eb2e8f9f7	79	(++) Address phase : the mode used and if present the size and the address value.
<>	144:ef7eb2e8f9f7	80	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
<>	144:ef7eb2e8f9f7	81	bytes values.
<>	144:ef7eb2e8f9f7	82	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
<>	144:ef7eb2e8f9f7	83	(++) Data phase : the mode used.
<>	144:ef7eb2e8f9f7	84	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
<>	144:ef7eb2e8f9f7	85	if activated.
<>	144:ef7eb2e8f9f7	86	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
<>	144:ef7eb2e8f9f7	87	(++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
<>	144:ef7eb2e8f9f7	88	the polling interval and the automatic stop activation.
<>	144:ef7eb2e8f9f7	89	(#) After the configuration :
<>	144:ef7eb2e8f9f7	90	(++) In polling mode, the output of the function is done when the status match is reached. The
<>	144:ef7eb2e8f9f7	91	automatic stop is activated to avoid an infinite loop.
<>	144:ef7eb2e8f9f7	92	(++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	* Memory-mapped functional mode *
<>	144:ef7eb2e8f9f7	95	=====================================
<>	144:ef7eb2e8f9f7	96	[..]
<>	144:ef7eb2e8f9f7	97	(#) Configure the command sequence and the memory-mapped functional mode using the
<>	144:ef7eb2e8f9f7	98	HAL_QSPI_MemoryMapped() functions :
<>	144:ef7eb2e8f9f7	99	(++) Instruction phase : the mode used and if present the instruction opcode.
<>	144:ef7eb2e8f9f7	100	(++) Address phase : the mode used and the size.
<>	144:ef7eb2e8f9f7	101	(++) Alternate-bytes phase : the mode used and if present the size and the alternate
<>	144:ef7eb2e8f9f7	102	bytes values.
<>	144:ef7eb2e8f9f7	103	(++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
<>	144:ef7eb2e8f9f7	104	(++) Data phase : the mode used.
<>	144:ef7eb2e8f9f7	105	(++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
<>	144:ef7eb2e8f9f7	106	if activated.
<>	144:ef7eb2e8f9f7	107	(++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
<>	144:ef7eb2e8f9f7	108	(++) The timeout activation and the timeout period.
<>	144:ef7eb2e8f9f7	109	(#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
<>	144:ef7eb2e8f9f7	110	the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	* Errors management and abort functionality *
<>	144:ef7eb2e8f9f7	113	==================================================
<>	144:ef7eb2e8f9f7	114	[..]
<>	144:ef7eb2e8f9f7	115	(#) HAL_QSPI_GetError() function gives the error raised during the last operation.
<>	144:ef7eb2e8f9f7	116	(#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
<>	144:ef7eb2e8f9f7	117	flushes the fifo :
<>	144:ef7eb2e8f9f7	118	(++) In polling mode, the output of the function is done when the transfer
<>	144:ef7eb2e8f9f7	119	complete bit is set and the busy bit cleared.
<>	144:ef7eb2e8f9f7	120	(++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
<>	144:ef7eb2e8f9f7	121	the transfer complete bi is set.
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	* Control functions *
<>	144:ef7eb2e8f9f7	124	=========================
<>	144:ef7eb2e8f9f7	125	[..]
<>	144:ef7eb2e8f9f7	126	(#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
<>	144:ef7eb2e8f9f7	127	(#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
<>	144:ef7eb2e8f9f7	128	(#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
<>	144:ef7eb2e8f9f7	129	(#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	* Workarounds linked to Silicon Limitation *
<>	144:ef7eb2e8f9f7	132	====================================================
<>	144:ef7eb2e8f9f7	133	[..]
<>	144:ef7eb2e8f9f7	134	(#) Workarounds Implemented inside HAL Driver
<>	144:ef7eb2e8f9f7	135	(++) Extra data written in the FIFO at the end of a read transfer
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	@endverbatim
<>	144:ef7eb2e8f9f7	138	******************************************************************************
<>	144:ef7eb2e8f9f7	139	* @attention
<>	144:ef7eb2e8f9f7	140	*
<>	144:ef7eb2e8f9f7	141	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	142	*
<>	144:ef7eb2e8f9f7	143	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	144	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	145	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	146	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	147	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	148	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	149	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	150	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	151	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	152	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	153	*
<>	144:ef7eb2e8f9f7	154	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	155	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	156	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	157	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	158	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	159	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	160	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	161	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	162	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	163	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	164	*
<>	144:ef7eb2e8f9f7	165	******************************************************************************
<>	144:ef7eb2e8f9f7	166	*/
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	169	#include "stm32f7xx_hal.h"
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	172	* @{
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	/** @defgroup QSPI QSPI
<>	144:ef7eb2e8f9f7	176	* @brief HAL QSPI module driver
<>	144:ef7eb2e8f9f7	177	* @{
<>	144:ef7eb2e8f9f7	178	*/
<>	144:ef7eb2e8f9f7	179	#ifdef HAL_QSPI_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	182	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	183	/** @addtogroup QSPI_Private_Constants
<>	144:ef7eb2e8f9f7	184	* @{
<>	144:ef7eb2e8f9f7	185	*/
<>	144:ef7eb2e8f9f7	186	#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U) /!<Indirect write mode/
<>	144:ef7eb2e8f9f7	187	#define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /!<Indirect read mode/
<>	144:ef7eb2e8f9f7	188	#define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /!<Automatic polling mode/
<>	144:ef7eb2e8f9f7	189	#define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /!<Memory-mapped mode/
<>	144:ef7eb2e8f9f7	190	/**
<>	144:ef7eb2e8f9f7	191	* @}
<>	144:ef7eb2e8f9f7	192	*/
<>	144:ef7eb2e8f9f7	193
<>	144:ef7eb2e8f9f7	194	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	195	/** @addtogroup QSPI_Private_Macros QSPI Private Macros
<>	144:ef7eb2e8f9f7	196	* @{
<>	144:ef7eb2e8f9f7	197	*/
<>	144:ef7eb2e8f9f7	198	#define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) \|\| \
<>	144:ef7eb2e8f9f7	199	((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) \|\| \
<>	144:ef7eb2e8f9f7	200	((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) \|\| \
<>	144:ef7eb2e8f9f7	201	((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
<>	144:ef7eb2e8f9f7	202	/**
<>	144:ef7eb2e8f9f7	203	* @}
<>	144:ef7eb2e8f9f7	204	*/
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	207	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	208	/** @addtogroup QSPI_Private_Functions QSPI Private Functions
<>	144:ef7eb2e8f9f7	209	* @{
<>	144:ef7eb2e8f9f7	210	*/
<>	144:ef7eb2e8f9f7	211	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	212	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	213	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	214	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	215	static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	216	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	217	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	218	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode);
<>	144:ef7eb2e8f9f7	219	/**
<>	144:ef7eb2e8f9f7	220	* @}
<>	144:ef7eb2e8f9f7	221	*/
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	224
<>	144:ef7eb2e8f9f7	225	/** @defgroup QSPI_Exported_Functions QSPI Exported Functions
<>	144:ef7eb2e8f9f7	226	* @{
<>	144:ef7eb2e8f9f7	227	*/
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
<>	144:ef7eb2e8f9f7	230	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	231	*
<>	144:ef7eb2e8f9f7	232	@verbatim
<>	144:ef7eb2e8f9f7	233	===============================================================================
<>	144:ef7eb2e8f9f7	234	##### Initialization and Configuration functions #####
<>	144:ef7eb2e8f9f7	235	===============================================================================
<>	144:ef7eb2e8f9f7	236	[..]
<>	144:ef7eb2e8f9f7	237	This subsection provides a set of functions allowing to :
<>	144:ef7eb2e8f9f7	238	(+) Initialize the QuadSPI.
<>	144:ef7eb2e8f9f7	239	(+) De-initialize the QuadSPI.
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241	@endverbatim
<>	144:ef7eb2e8f9f7	242	* @{
<>	144:ef7eb2e8f9f7	243	*/
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	/**
<>	144:ef7eb2e8f9f7	246	* @brief Initializes the QSPI mode according to the specified parameters
<>	144:ef7eb2e8f9f7	247	* in the QSPI_InitTypeDef and creates the associated handle.
<>	144:ef7eb2e8f9f7	248	* @param hqspi: qspi handle
<>	144:ef7eb2e8f9f7	249	* @retval HAL status
<>	144:ef7eb2e8f9f7	250	*/
<>	144:ef7eb2e8f9f7	251	HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	252	{
<>	144:ef7eb2e8f9f7	253	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	254	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/* Check the QSPI handle allocation */
<>	144:ef7eb2e8f9f7	257	if(hqspi == NULL)
<>	144:ef7eb2e8f9f7	258	{
<>	144:ef7eb2e8f9f7	259	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	260	}
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/* Check the parameters */
<>	144:ef7eb2e8f9f7	263	assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
<>	144:ef7eb2e8f9f7	264	assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
<>	144:ef7eb2e8f9f7	265	assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
<>	144:ef7eb2e8f9f7	266	assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
<>	144:ef7eb2e8f9f7	267	assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
<>	144:ef7eb2e8f9f7	268	assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
<>	144:ef7eb2e8f9f7	269	assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
<>	144:ef7eb2e8f9f7	270	assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
<>	144:ef7eb2e8f9f7	273	{
<>	144:ef7eb2e8f9f7	274	assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
<>	144:ef7eb2e8f9f7	275	}
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/* Process locked */
<>	144:ef7eb2e8f9f7	278	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	if(hqspi->State == HAL_QSPI_STATE_RESET)
<>	144:ef7eb2e8f9f7	281	{
<>	144:ef7eb2e8f9f7	282	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	283	hqspi->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	284
<>	144:ef7eb2e8f9f7	285	/* Init the low level hardware : GPIO, CLOCK */
<>	144:ef7eb2e8f9f7	286	HAL_QSPI_MspInit(hqspi);
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	/* Configure the default timeout for the QSPI memory access */
<>	144:ef7eb2e8f9f7	289	HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
<>	144:ef7eb2e8f9f7	290	}
<>	144:ef7eb2e8f9f7	291
<>	144:ef7eb2e8f9f7	292	/* Configure QSPI FIFO Threshold */
<>	144:ef7eb2e8f9f7	293	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
<>	144:ef7eb2e8f9f7	294
<>	144:ef7eb2e8f9f7	295	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	296	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	297
<>	144:ef7eb2e8f9f7	298	if(status == HAL_OK)
<>	144:ef7eb2e8f9f7	299	{
<>	144:ef7eb2e8f9f7	300
<>	144:ef7eb2e8f9f7	301	/* Configure QSPI Clock Prescaler and Sample Shift */
<>	144:ef7eb2e8f9f7	302	MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER \| QUADSPI_CR_SSHIFT \| QUADSPI_CR_FSEL \| QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)\| hqspi->Init.SampleShifting \| hqspi->Init.FlashID\| hqspi->Init.DualFlash ));
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/* Configure QSPI Flash Size, CS High Time and Clock Mode */
<>	144:ef7eb2e8f9f7	305	MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE \| QUADSPI_DCR_CSHT \| QUADSPI_DCR_CKMODE),
<>	144:ef7eb2e8f9f7	306	((hqspi->Init.FlashSize << 16) \| hqspi->Init.ChipSelectHighTime \| hqspi->Init.ClockMode));
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308	/* Enable the QSPI peripheral */
<>	144:ef7eb2e8f9f7	309	__HAL_QSPI_ENABLE(hqspi);
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	/* Set QSPI error code to none */
<>	144:ef7eb2e8f9f7	312	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* Initialize the QSPI state */
<>	144:ef7eb2e8f9f7	315	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	316	}
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/* Release Lock */
<>	144:ef7eb2e8f9f7	319	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/* Return function status */
<>	144:ef7eb2e8f9f7	322	return status;
<>	144:ef7eb2e8f9f7	323	}
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/**
<>	144:ef7eb2e8f9f7	326	* @brief DeInitializes the QSPI peripheral
<>	144:ef7eb2e8f9f7	327	* @param hqspi: qspi handle
<>	144:ef7eb2e8f9f7	328	* @retval HAL status
<>	144:ef7eb2e8f9f7	329	*/
<>	144:ef7eb2e8f9f7	330	HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	331	{
<>	144:ef7eb2e8f9f7	332	/* Check the QSPI handle allocation */
<>	144:ef7eb2e8f9f7	333	if(hqspi == NULL)
<>	144:ef7eb2e8f9f7	334	{
<>	144:ef7eb2e8f9f7	335	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	336	}
<>	144:ef7eb2e8f9f7	337
<>	144:ef7eb2e8f9f7	338	/* Process locked */
<>	144:ef7eb2e8f9f7	339	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	340
<>	144:ef7eb2e8f9f7	341	/* Disable the QSPI Peripheral Clock */
<>	144:ef7eb2e8f9f7	342	__HAL_QSPI_DISABLE(hqspi);
<>	144:ef7eb2e8f9f7	343
<>	144:ef7eb2e8f9f7	344	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
<>	144:ef7eb2e8f9f7	345	HAL_QSPI_MspDeInit(hqspi);
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	/* Set QSPI error code to none */
<>	144:ef7eb2e8f9f7	348	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	/* Initialize the QSPI state */
<>	144:ef7eb2e8f9f7	351	hqspi->State = HAL_QSPI_STATE_RESET;
<>	144:ef7eb2e8f9f7	352
<>	144:ef7eb2e8f9f7	353	/* Release Lock */
<>	144:ef7eb2e8f9f7	354	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	return HAL_OK;
<>	144:ef7eb2e8f9f7	357	}
<>	144:ef7eb2e8f9f7	358
<>	144:ef7eb2e8f9f7	359	/**
<>	144:ef7eb2e8f9f7	360	* @brief QSPI MSP Init
<>	144:ef7eb2e8f9f7	361	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	362	* @retval None
<>	144:ef7eb2e8f9f7	363	*/
<>	144:ef7eb2e8f9f7	364	__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	365	{
<>	144:ef7eb2e8f9f7	366	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	367	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	370	the HAL_QSPI_MspInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	371	*/
<>	144:ef7eb2e8f9f7	372	}
<>	144:ef7eb2e8f9f7	373
<>	144:ef7eb2e8f9f7	374	/**
<>	144:ef7eb2e8f9f7	375	* @brief QSPI MSP DeInit
<>	144:ef7eb2e8f9f7	376	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	377	* @retval None
<>	144:ef7eb2e8f9f7	378	*/
<>	144:ef7eb2e8f9f7	379	__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	380	{
<>	144:ef7eb2e8f9f7	381	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	382	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	383
<>	144:ef7eb2e8f9f7	384	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	385	the HAL_QSPI_MspDeInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	386	*/
<>	144:ef7eb2e8f9f7	387	}
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/**
<>	144:ef7eb2e8f9f7	390	* @}
<>	144:ef7eb2e8f9f7	391	*/
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	394	* @brief QSPI Transmit/Receive functions
<>	144:ef7eb2e8f9f7	395	*
<>	144:ef7eb2e8f9f7	396	@verbatim
<>	144:ef7eb2e8f9f7	397	===============================================================================
<>	144:ef7eb2e8f9f7	398	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	399	===============================================================================
<>	144:ef7eb2e8f9f7	400	[..]
<>	144:ef7eb2e8f9f7	401	This subsection provides a set of functions allowing to :
<>	144:ef7eb2e8f9f7	402	(+) Handle the interrupts.
<>	144:ef7eb2e8f9f7	403	(+) Handle the command sequence.
<>	144:ef7eb2e8f9f7	404	(+) Transmit data in blocking, interrupt or DMA mode.
<>	144:ef7eb2e8f9f7	405	(+) Receive data in blocking, interrupt or DMA mode.
<>	144:ef7eb2e8f9f7	406	(+) Manage the auto-polling functional mode.
<>	144:ef7eb2e8f9f7	407	(+) Manage the memory-mapped functional mode.
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	@endverbatim
<>	144:ef7eb2e8f9f7	410	* @{
<>	144:ef7eb2e8f9f7	411	*/
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/**
<>	144:ef7eb2e8f9f7	414	* @brief This function handles QSPI interrupt request.
<>	144:ef7eb2e8f9f7	415	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	416	* @retval None.
<>	144:ef7eb2e8f9f7	417	*/
<>	144:ef7eb2e8f9f7	418	void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	419	{
<>	144:ef7eb2e8f9f7	420	__IO uint32_t *data_reg;
<>	144:ef7eb2e8f9f7	421	uint32_t flag = READ_REG(hqspi->Instance->SR);
<>	144:ef7eb2e8f9f7	422	uint32_t itsource = READ_REG(hqspi->Instance->CR);
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
<>	144:ef7eb2e8f9f7	425	if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
<>	144:ef7eb2e8f9f7	426	{
<>	144:ef7eb2e8f9f7	427	data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
<>	144:ef7eb2e8f9f7	430	{
<>	144:ef7eb2e8f9f7	431	/* Transmission process */
<>	144:ef7eb2e8f9f7	432	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
<>	144:ef7eb2e8f9f7	433	{
<>	144:ef7eb2e8f9f7	434	if (hqspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	435	{
<>	144:ef7eb2e8f9f7	436	/* Fill the FIFO until it is full */
<>	144:ef7eb2e8f9f7	437	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
<>	144:ef7eb2e8f9f7	438	hqspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	439	}
<>	144:ef7eb2e8f9f7	440	else
<>	144:ef7eb2e8f9f7	441	{
<>	144:ef7eb2e8f9f7	442	/* No more data available for the transfer */
<>	144:ef7eb2e8f9f7	443	/* Disable the QSPI FIFO Threshold Interrupt */
<>	144:ef7eb2e8f9f7	444	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	445	break;
<>	144:ef7eb2e8f9f7	446	}
<>	144:ef7eb2e8f9f7	447	}
<>	144:ef7eb2e8f9f7	448	}
<>	144:ef7eb2e8f9f7	449	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
<>	144:ef7eb2e8f9f7	450	{
<>	144:ef7eb2e8f9f7	451	/* Receiving Process */
<>	144:ef7eb2e8f9f7	452	while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
<>	144:ef7eb2e8f9f7	453	{
<>	144:ef7eb2e8f9f7	454	if (hqspi->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	455	{
<>	144:ef7eb2e8f9f7	456	/* Read the FIFO until it is empty */
<>	144:ef7eb2e8f9f7	457	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
<>	144:ef7eb2e8f9f7	458	hqspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	459	}
<>	144:ef7eb2e8f9f7	460	else
<>	144:ef7eb2e8f9f7	461	{
<>	144:ef7eb2e8f9f7	462	/* All data have been received for the transfer */
<>	144:ef7eb2e8f9f7	463	/* Disable the QSPI FIFO Threshold Interrupt */
<>	144:ef7eb2e8f9f7	464	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	465	break;
<>	144:ef7eb2e8f9f7	466	}
<>	144:ef7eb2e8f9f7	467	}
<>	144:ef7eb2e8f9f7	468	}
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	/* FIFO Threshold callback */
<>	144:ef7eb2e8f9f7	471	HAL_QSPI_FifoThresholdCallback(hqspi);
<>	144:ef7eb2e8f9f7	472	}
<>	144:ef7eb2e8f9f7	473
<>	144:ef7eb2e8f9f7	474	/* QSPI Transfer Complete interrupt occurred -------------------------------*/
<>	144:ef7eb2e8f9f7	475	else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
<>	144:ef7eb2e8f9f7	476	{
<>	144:ef7eb2e8f9f7	477	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	478	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
<>	144:ef7eb2e8f9f7	481	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/* Transfer complete callback */
<>	144:ef7eb2e8f9f7	484	if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
<>	144:ef7eb2e8f9f7	485	{
<>	144:ef7eb2e8f9f7	486	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
<>	144:ef7eb2e8f9f7	487	{
<>	144:ef7eb2e8f9f7	488	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	489	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	490
<>	144:ef7eb2e8f9f7	491	/* Disable the DMA channel */
<>	144:ef7eb2e8f9f7	492	__HAL_DMA_DISABLE(hqspi->hdma);
<>	144:ef7eb2e8f9f7	493	}
<>	144:ef7eb2e8f9f7	494
<>	144:ef7eb2e8f9f7	495	#if defined(QSPI1_V1_0)
<>	144:ef7eb2e8f9f7	496	/* Clear Busy bit */
<>	144:ef7eb2e8f9f7	497	HAL_QSPI_Abort_IT(hqspi);
<>	144:ef7eb2e8f9f7	498	#endif
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	501	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/* TX Complete callback */
<>	144:ef7eb2e8f9f7	504	HAL_QSPI_TxCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	505	}
<>	144:ef7eb2e8f9f7	506	else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
<>	144:ef7eb2e8f9f7	507	{
<>	144:ef7eb2e8f9f7	508	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
<>	144:ef7eb2e8f9f7	509	{
<>	144:ef7eb2e8f9f7	510	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	511	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	/* Disable the DMA channel */
<>	144:ef7eb2e8f9f7	514	__HAL_DMA_DISABLE(hqspi->hdma);
<>	144:ef7eb2e8f9f7	515	}
<>	144:ef7eb2e8f9f7	516	else
<>	144:ef7eb2e8f9f7	517	{
<>	144:ef7eb2e8f9f7	518	data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	519	while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
<>	144:ef7eb2e8f9f7	520	{
<>	144:ef7eb2e8f9f7	521	if (hqspi->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	522	{
<>	144:ef7eb2e8f9f7	523	/* Read the last data received in the FIFO until it is empty */
<>	144:ef7eb2e8f9f7	524	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
<>	144:ef7eb2e8f9f7	525	hqspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	526	}
<>	144:ef7eb2e8f9f7	527	else
<>	144:ef7eb2e8f9f7	528	{
<>	144:ef7eb2e8f9f7	529	/* All data have been received for the transfer */
<>	144:ef7eb2e8f9f7	530	break;
<>	144:ef7eb2e8f9f7	531	}
<>	144:ef7eb2e8f9f7	532	}
<>	144:ef7eb2e8f9f7	533	}
<>	144:ef7eb2e8f9f7	534	#if defined(QSPI1_V1_0)
<>	144:ef7eb2e8f9f7	535	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
<>	144:ef7eb2e8f9f7	536	HAL_QSPI_Abort_IT(hqspi);
<>	144:ef7eb2e8f9f7	537	#endif /* QSPI_V1_0*/
<>	144:ef7eb2e8f9f7	538
<>	144:ef7eb2e8f9f7	539	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	540	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	/* RX Complete callback */
<>	144:ef7eb2e8f9f7	543	HAL_QSPI_RxCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	544	}
<>	144:ef7eb2e8f9f7	545	else if(hqspi->State == HAL_QSPI_STATE_BUSY)
<>	144:ef7eb2e8f9f7	546	{
<>	144:ef7eb2e8f9f7	547	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	548	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	/* Command Complete callback */
<>	144:ef7eb2e8f9f7	551	HAL_QSPI_CmdCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	552	}
<>	144:ef7eb2e8f9f7	553	else if(hqspi->State == HAL_QSPI_STATE_ABORT)
<>	144:ef7eb2e8f9f7	554	{
<>	144:ef7eb2e8f9f7	555	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	556	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
<>	144:ef7eb2e8f9f7	559	{
<>	144:ef7eb2e8f9f7	560	/* Abort called by the user */
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	/* Abort Complete callback */
<>	144:ef7eb2e8f9f7	563	HAL_QSPI_AbortCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	564	}
<>	144:ef7eb2e8f9f7	565	else
<>	144:ef7eb2e8f9f7	566	{
<>	144:ef7eb2e8f9f7	567	/* Abort due to an error (eg : DMA error) */
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	/* Error callback */
<>	144:ef7eb2e8f9f7	570	HAL_QSPI_ErrorCallback(hqspi);
<>	144:ef7eb2e8f9f7	571	}
<>	144:ef7eb2e8f9f7	572	}
<>	144:ef7eb2e8f9f7	573	}
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/* QSPI Status Match interrupt occurred ------------------------------------*/
<>	144:ef7eb2e8f9f7	576	else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
<>	144:ef7eb2e8f9f7	577	{
<>	144:ef7eb2e8f9f7	578	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	579	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/* Check if the automatic poll mode stop is activated */
<>	144:ef7eb2e8f9f7	582	if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
<>	144:ef7eb2e8f9f7	583	{
<>	144:ef7eb2e8f9f7	584	/* Disable the QSPI Transfer Error and Status Match Interrupts */
<>	144:ef7eb2e8f9f7	585	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
<>	144:ef7eb2e8f9f7	586
<>	144:ef7eb2e8f9f7	587	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	588	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	589	}
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/* Status match callback */
<>	144:ef7eb2e8f9f7	592	HAL_QSPI_StatusMatchCallback(hqspi);
<>	144:ef7eb2e8f9f7	593	}
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	/* QSPI Transfer Error interrupt occurred ----------------------------------*/
<>	144:ef7eb2e8f9f7	596	else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
<>	144:ef7eb2e8f9f7	597	{
<>	144:ef7eb2e8f9f7	598	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	599	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/* Disable all the QSPI Interrupts */
<>	144:ef7eb2e8f9f7	602	__HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM \| QSPI_IT_TC \| QSPI_IT_TE \| QSPI_IT_FT);
<>	144:ef7eb2e8f9f7	603
<>	144:ef7eb2e8f9f7	604	/* Set error code */
<>	144:ef7eb2e8f9f7	605	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TRANSFER;
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
<>	144:ef7eb2e8f9f7	608	{
<>	144:ef7eb2e8f9f7	609	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	610	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/* Disable the DMA channel */
<>	144:ef7eb2e8f9f7	613	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
<>	144:ef7eb2e8f9f7	614	HAL_DMA_Abort_IT(hqspi->hdma);
<>	144:ef7eb2e8f9f7	615	}
<>	144:ef7eb2e8f9f7	616	else
<>	144:ef7eb2e8f9f7	617	{
<>	144:ef7eb2e8f9f7	618	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	619	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	/* Error callback */
<>	144:ef7eb2e8f9f7	622	HAL_QSPI_ErrorCallback(hqspi);
<>	144:ef7eb2e8f9f7	623	}
<>	144:ef7eb2e8f9f7	624	}
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/* QSPI Timeout interrupt occurred -----------------------------------------*/
<>	144:ef7eb2e8f9f7	627	else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
<>	144:ef7eb2e8f9f7	628	{
<>	144:ef7eb2e8f9f7	629	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	630	WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
<>	144:ef7eb2e8f9f7	631
<>	144:ef7eb2e8f9f7	632	/* Time out callback */
<>	144:ef7eb2e8f9f7	633	HAL_QSPI_TimeOutCallback(hqspi);
<>	144:ef7eb2e8f9f7	634	}
<>	144:ef7eb2e8f9f7	635	}
<>	144:ef7eb2e8f9f7	636
<>	144:ef7eb2e8f9f7	637	/**
<>	144:ef7eb2e8f9f7	638	* @brief Sets the command configuration.
<>	144:ef7eb2e8f9f7	639	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	640	* @param cmd : structure that contains the command configuration information
<>	144:ef7eb2e8f9f7	641	* @param Timeout : Time out duration
<>	144:ef7eb2e8f9f7	642	* @note This function is used only in Indirect Read or Write Modes
<>	144:ef7eb2e8f9f7	643	* @retval HAL status
<>	144:ef7eb2e8f9f7	644	*/
<>	144:ef7eb2e8f9f7	645	HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	646	{
<>	144:ef7eb2e8f9f7	647	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	648	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	/* Check the parameters */
<>	144:ef7eb2e8f9f7	651	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	652	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	653	{
<>	144:ef7eb2e8f9f7	654	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	655	}
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	658	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	659	{
<>	144:ef7eb2e8f9f7	660	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	661	}
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	664	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	665	{
<>	144:ef7eb2e8f9f7	666	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	667	}
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	670	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	671
<>	144:ef7eb2e8f9f7	672	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	673	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	674	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	/* Process locked */
<>	144:ef7eb2e8f9f7	677	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	678
<>	144:ef7eb2e8f9f7	679	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	680	{
<>	144:ef7eb2e8f9f7	681	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	684	hqspi->State = HAL_QSPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	687	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	690	{
<>	144:ef7eb2e8f9f7	691	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	692	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	if (cmd->DataMode == QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	695	{
<>	144:ef7eb2e8f9f7	696	/* When there is no data phase, the transfer start as soon as the configuration is done
<>	144:ef7eb2e8f9f7	697	so wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	698	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	701	{
<>	144:ef7eb2e8f9f7	702	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	705	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	706	}
<>	144:ef7eb2e8f9f7	707
<>	144:ef7eb2e8f9f7	708	}
<>	144:ef7eb2e8f9f7	709	else
<>	144:ef7eb2e8f9f7	710	{
<>	144:ef7eb2e8f9f7	711	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	712	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	713	}
<>	144:ef7eb2e8f9f7	714	}
<>	144:ef7eb2e8f9f7	715	}
<>	144:ef7eb2e8f9f7	716	else
<>	144:ef7eb2e8f9f7	717	{
<>	144:ef7eb2e8f9f7	718	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	719	}
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	/* Process unlocked */
<>	144:ef7eb2e8f9f7	722	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/* Return function status */
<>	144:ef7eb2e8f9f7	725	return status;
<>	144:ef7eb2e8f9f7	726	}
<>	144:ef7eb2e8f9f7	727
<>	144:ef7eb2e8f9f7	728	/**
<>	144:ef7eb2e8f9f7	729	* @brief Sets the command configuration in interrupt mode.
<>	144:ef7eb2e8f9f7	730	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	731	* @param cmd : structure that contains the command configuration information
<>	144:ef7eb2e8f9f7	732	* @note This function is used only in Indirect Read or Write Modes
<>	144:ef7eb2e8f9f7	733	* @retval HAL status
<>	144:ef7eb2e8f9f7	734	*/
<>	144:ef7eb2e8f9f7	735	HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd)
<>	144:ef7eb2e8f9f7	736	{
<>	144:ef7eb2e8f9f7	737	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	738	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	/* Check the parameters */
<>	144:ef7eb2e8f9f7	741	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	742	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	745	}
<>	144:ef7eb2e8f9f7	746
<>	144:ef7eb2e8f9f7	747	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	748	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	749	{
<>	144:ef7eb2e8f9f7	750	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	751	}
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	754	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	755	{
<>	144:ef7eb2e8f9f7	756	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	757	}
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	760	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	763	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	764	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/* Process locked */
<>	144:ef7eb2e8f9f7	767	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	768
<>	144:ef7eb2e8f9f7	769	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	770	{
<>	144:ef7eb2e8f9f7	771	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	772
<>	144:ef7eb2e8f9f7	773	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	774	hqspi->State = HAL_QSPI_STATE_BUSY;
<>	144:ef7eb2e8f9f7	775
<>	144:ef7eb2e8f9f7	776	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	777	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	780	{
<>	144:ef7eb2e8f9f7	781	if (cmd->DataMode == QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	782	{
<>	144:ef7eb2e8f9f7	783	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	784	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	785	}
<>	144:ef7eb2e8f9f7	786
<>	144:ef7eb2e8f9f7	787	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	788	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	789
<>	144:ef7eb2e8f9f7	790	if (cmd->DataMode == QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	791	{
<>	144:ef7eb2e8f9f7	792	/* When there is no data phase, the transfer start as soon as the configuration is done
<>	144:ef7eb2e8f9f7	793	so activate TC and TE interrupts */
<>	144:ef7eb2e8f9f7	794	/* Process unlocked */
<>	144:ef7eb2e8f9f7	795	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797	/* Enable the QSPI Transfer Error Interrupt */
<>	144:ef7eb2e8f9f7	798	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	799	}
<>	144:ef7eb2e8f9f7	800	else
<>	144:ef7eb2e8f9f7	801	{
<>	144:ef7eb2e8f9f7	802	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	803	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	804
<>	144:ef7eb2e8f9f7	805	/* Process unlocked */
<>	144:ef7eb2e8f9f7	806	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	807	}
<>	144:ef7eb2e8f9f7	808	}
<>	144:ef7eb2e8f9f7	809	else
<>	144:ef7eb2e8f9f7	810	{
<>	144:ef7eb2e8f9f7	811	/* Process unlocked */
<>	144:ef7eb2e8f9f7	812	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	813	}
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	else
<>	144:ef7eb2e8f9f7	816	{
<>	144:ef7eb2e8f9f7	817	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	818
<>	144:ef7eb2e8f9f7	819	/* Process unlocked */
<>	144:ef7eb2e8f9f7	820	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	821	}
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	/* Return function status */
<>	144:ef7eb2e8f9f7	824	return status;
<>	144:ef7eb2e8f9f7	825	}
<>	144:ef7eb2e8f9f7	826
<>	144:ef7eb2e8f9f7	827	/**
<>	144:ef7eb2e8f9f7	828	* @brief Transmit an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	829	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	830	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	831	* @param Timeout : Time out duration
<>	144:ef7eb2e8f9f7	832	* @note This function is used only in Indirect Write Mode
<>	144:ef7eb2e8f9f7	833	* @retval HAL status
<>	144:ef7eb2e8f9f7	834	*/
<>	144:ef7eb2e8f9f7	835	HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	836	{
<>	144:ef7eb2e8f9f7	837	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	838	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	839	__IO uint32_t *data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/* Process locked */
<>	144:ef7eb2e8f9f7	842	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	843
<>	144:ef7eb2e8f9f7	844	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	845	{
<>	144:ef7eb2e8f9f7	846	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	if(pData != NULL )
<>	144:ef7eb2e8f9f7	849	{
<>	144:ef7eb2e8f9f7	850	/* Update state */
<>	144:ef7eb2e8f9f7	851	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
<>	144:ef7eb2e8f9f7	852
<>	144:ef7eb2e8f9f7	853	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	854	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	855	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	856	hqspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	/* Configure QSPI: CCR register with functional as indirect write */
<>	144:ef7eb2e8f9f7	859	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	while(hqspi->TxXferCount > 0)
<>	144:ef7eb2e8f9f7	862	{
<>	144:ef7eb2e8f9f7	863	/* Wait until FT flag is set to send data */
<>	144:ef7eb2e8f9f7	864	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	865
<>	144:ef7eb2e8f9f7	866	if (status != HAL_OK)
<>	144:ef7eb2e8f9f7	867	{
<>	144:ef7eb2e8f9f7	868	break;
<>	144:ef7eb2e8f9f7	869	}
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	(__IO uint8_t )data_reg = *hqspi->pTxBuffPtr++;
<>	144:ef7eb2e8f9f7	872	hqspi->TxXferCount--;
<>	144:ef7eb2e8f9f7	873	}
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	876	{
<>	144:ef7eb2e8f9f7	877	/* Wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	878	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	879
<>	144:ef7eb2e8f9f7	880	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	881	{
<>	144:ef7eb2e8f9f7	882	/* Clear Transfer Complete bit */
<>	144:ef7eb2e8f9f7	883	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	884
<>	144:ef7eb2e8f9f7	885	#if defined(QSPI1_V1_0)
<>	144:ef7eb2e8f9f7	886	/* Clear Busy bit */
<>	144:ef7eb2e8f9f7	887	status = HAL_QSPI_Abort(hqspi);
<>	144:ef7eb2e8f9f7	888	#endif /* QSPI_V1_0 */
<>	144:ef7eb2e8f9f7	889	}
<>	144:ef7eb2e8f9f7	890	}
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	893	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	894	}
<>	144:ef7eb2e8f9f7	895	else
<>	144:ef7eb2e8f9f7	896	{
<>	144:ef7eb2e8f9f7	897	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	898	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	899	}
<>	144:ef7eb2e8f9f7	900	}
<>	144:ef7eb2e8f9f7	901	else
<>	144:ef7eb2e8f9f7	902	{
<>	144:ef7eb2e8f9f7	903	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	904	}
<>	144:ef7eb2e8f9f7	905
<>	144:ef7eb2e8f9f7	906	/* Process unlocked */
<>	144:ef7eb2e8f9f7	907	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	return status;
<>	144:ef7eb2e8f9f7	910	}
<>	144:ef7eb2e8f9f7	911
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/**
<>	144:ef7eb2e8f9f7	914	* @brief Receive an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	915	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	916	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	917	* @param Timeout : Time out duration
<>	144:ef7eb2e8f9f7	918	* @note This function is used only in Indirect Read Mode
<>	144:ef7eb2e8f9f7	919	* @retval HAL status
<>	144:ef7eb2e8f9f7	920	*/
<>	144:ef7eb2e8f9f7	921	HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef hqspi, uint8_t pData, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	922	{
<>	144:ef7eb2e8f9f7	923	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	924	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	925	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
<>	144:ef7eb2e8f9f7	926	__IO uint32_t *data_reg = &hqspi->Instance->DR;
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	/* Process locked */
<>	144:ef7eb2e8f9f7	929	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	932	{
<>	144:ef7eb2e8f9f7	933	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	934	if(pData != NULL )
<>	144:ef7eb2e8f9f7	935	{
<>	144:ef7eb2e8f9f7	936	/* Update state */
<>	144:ef7eb2e8f9f7	937	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
<>	144:ef7eb2e8f9f7	938
<>	144:ef7eb2e8f9f7	939	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	940	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	941	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	942	hqspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Configure QSPI: CCR register with functional as indirect read */
<>	144:ef7eb2e8f9f7	945	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* Start the transfer by re-writing the address in AR register */
<>	144:ef7eb2e8f9f7	948	WRITE_REG(hqspi->Instance->AR, addr_reg);
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	while(hqspi->RxXferCount > 0)
<>	144:ef7eb2e8f9f7	951	{
<>	144:ef7eb2e8f9f7	952	/* Wait until FT or TC flag is set to read received data */
<>	144:ef7eb2e8f9f7	953	status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT \| QSPI_FLAG_TC), SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	if (status != HAL_OK)
<>	144:ef7eb2e8f9f7	956	{
<>	144:ef7eb2e8f9f7	957	break;
<>	144:ef7eb2e8f9f7	958	}
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	hqspi->pRxBuffPtr++ = (__IO uint8_t *)data_reg;
<>	144:ef7eb2e8f9f7	961	hqspi->RxXferCount--;
<>	144:ef7eb2e8f9f7	962	}
<>	144:ef7eb2e8f9f7	963
<>	144:ef7eb2e8f9f7	964	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	965	{
<>	144:ef7eb2e8f9f7	966	/* Wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	967	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	968
<>	144:ef7eb2e8f9f7	969	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	970	{
<>	144:ef7eb2e8f9f7	971	/* Clear Transfer Complete bit */
<>	144:ef7eb2e8f9f7	972	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	#if defined(QSPI1_V1_0)
<>	144:ef7eb2e8f9f7	975	/* Workaround - Extra data written in the FIFO at the end of a read transfer */
<>	144:ef7eb2e8f9f7	976	status = HAL_QSPI_Abort(hqspi);
<>	144:ef7eb2e8f9f7	977	#endif /* QSPI_V1_0 */
<>	144:ef7eb2e8f9f7	978	}
<>	144:ef7eb2e8f9f7	979	}
<>	144:ef7eb2e8f9f7	980
<>	144:ef7eb2e8f9f7	981	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	982	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	983	}
<>	144:ef7eb2e8f9f7	984	else
<>	144:ef7eb2e8f9f7	985	{
<>	144:ef7eb2e8f9f7	986	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	987	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	988	}
<>	144:ef7eb2e8f9f7	989	}
<>	144:ef7eb2e8f9f7	990	else
<>	144:ef7eb2e8f9f7	991	{
<>	144:ef7eb2e8f9f7	992	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	993	}
<>	144:ef7eb2e8f9f7	994
<>	144:ef7eb2e8f9f7	995	/* Process unlocked */
<>	144:ef7eb2e8f9f7	996	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	997
<>	144:ef7eb2e8f9f7	998	return status;
<>	144:ef7eb2e8f9f7	999	}
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	/**
<>	144:ef7eb2e8f9f7	1002	* @brief Send an amount of data in interrupt mode
<>	144:ef7eb2e8f9f7	1003	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1004	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1005	* @note This function is used only in Indirect Write Mode
<>	144:ef7eb2e8f9f7	1006	* @retval HAL status
<>	144:ef7eb2e8f9f7	1007	*/
<>	144:ef7eb2e8f9f7	1008	HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1009	{
<>	144:ef7eb2e8f9f7	1010	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	/* Process locked */
<>	144:ef7eb2e8f9f7	1013	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1014
<>	144:ef7eb2e8f9f7	1015	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1016	{
<>	144:ef7eb2e8f9f7	1017	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1018	if(pData != NULL )
<>	144:ef7eb2e8f9f7	1019	{
<>	144:ef7eb2e8f9f7	1020	/* Update state */
<>	144:ef7eb2e8f9f7	1021	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	1024	hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1025	hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1026	hqspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1027
<>	144:ef7eb2e8f9f7	1028	/* Configure QSPI: CCR register with functional as indirect write */
<>	144:ef7eb2e8f9f7	1029	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	1030
<>	144:ef7eb2e8f9f7	1031	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1032	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1035	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
<>	144:ef7eb2e8f9f7	1038	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	}
<>	144:ef7eb2e8f9f7	1041	else
<>	144:ef7eb2e8f9f7	1042	{
<>	144:ef7eb2e8f9f7	1043	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1044	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1045
<>	144:ef7eb2e8f9f7	1046	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1047	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1048	}
<>	144:ef7eb2e8f9f7	1049	}
<>	144:ef7eb2e8f9f7	1050	else
<>	144:ef7eb2e8f9f7	1051	{
<>	144:ef7eb2e8f9f7	1052	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1053
<>	144:ef7eb2e8f9f7	1054	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1055	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1056	}
<>	144:ef7eb2e8f9f7	1057
<>	144:ef7eb2e8f9f7	1058	return status;
<>	144:ef7eb2e8f9f7	1059	}
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	/**
<>	144:ef7eb2e8f9f7	1062	* @brief Receive an amount of data in no-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1063	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1064	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1065	* @note This function is used only in Indirect Read Mode
<>	144:ef7eb2e8f9f7	1066	* @retval HAL status
<>	144:ef7eb2e8f9f7	1067	*/
<>	144:ef7eb2e8f9f7	1068	HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1069	{
<>	144:ef7eb2e8f9f7	1070	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1071	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
<>	144:ef7eb2e8f9f7	1072
<>	144:ef7eb2e8f9f7	1073	/* Process locked */
<>	144:ef7eb2e8f9f7	1074	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1075
<>	144:ef7eb2e8f9f7	1076	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1077	{
<>	144:ef7eb2e8f9f7	1078	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	if(pData != NULL )
<>	144:ef7eb2e8f9f7	1081	{
<>	144:ef7eb2e8f9f7	1082	/* Update state */
<>	144:ef7eb2e8f9f7	1083	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
<>	144:ef7eb2e8f9f7	1084
<>	144:ef7eb2e8f9f7	1085	/* Configure counters and size of the handle */
<>	144:ef7eb2e8f9f7	1086	hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1087	hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
<>	144:ef7eb2e8f9f7	1088	hqspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1089
<>	144:ef7eb2e8f9f7	1090	/* Configure QSPI: CCR register with functional as indirect read */
<>	144:ef7eb2e8f9f7	1091	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
<>	144:ef7eb2e8f9f7	1092
<>	144:ef7eb2e8f9f7	1093	/* Start the transfer by re-writing the address in AR register */
<>	144:ef7eb2e8f9f7	1094	WRITE_REG(hqspi->Instance->AR, addr_reg);
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1097	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1098
<>	144:ef7eb2e8f9f7	1099	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1100	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	/* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
<>	144:ef7eb2e8f9f7	1103	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE \| QSPI_IT_FT \| QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	1104	}
<>	144:ef7eb2e8f9f7	1105	else
<>	144:ef7eb2e8f9f7	1106	{
<>	144:ef7eb2e8f9f7	1107	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1108	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1109
<>	144:ef7eb2e8f9f7	1110	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1111	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1112	}
<>	144:ef7eb2e8f9f7	1113	}
<>	144:ef7eb2e8f9f7	1114	else
<>	144:ef7eb2e8f9f7	1115	{
<>	144:ef7eb2e8f9f7	1116	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1117
<>	144:ef7eb2e8f9f7	1118	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1119	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1120	}
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	return status;
<>	144:ef7eb2e8f9f7	1123	}
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	/**
<>	144:ef7eb2e8f9f7	1126	* @brief Sends an amount of data in non blocking mode with DMA.
<>	144:ef7eb2e8f9f7	1127	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1128	* @param pData: pointer to data buffer
<>	144:ef7eb2e8f9f7	1129	* @note This function is used only in Indirect Write Mode
<>	144:ef7eb2e8f9f7	1130	* @note If DMA peripheral access is configured as halfword, the number
<>	144:ef7eb2e8f9f7	1131	* of data and the fifo threshold should be aligned on halfword
<>	144:ef7eb2e8f9f7	1132	* @note If DMA peripheral access is configured as word, the number
<>	144:ef7eb2e8f9f7	1133	* of data and the fifo threshold should be aligned on word
<>	144:ef7eb2e8f9f7	1134	* @retval HAL status
<>	144:ef7eb2e8f9f7	1135	*/
<>	144:ef7eb2e8f9f7	1136	HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1137	{
<>	144:ef7eb2e8f9f7	1138	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1139	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	1140	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	/* Process locked */
<>	144:ef7eb2e8f9f7	1143	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1146	{
<>	144:ef7eb2e8f9f7	1147	/* Clear the error code */
<>	144:ef7eb2e8f9f7	1148	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	if(pData != NULL )
<>	144:ef7eb2e8f9f7	1151	{
<>	144:ef7eb2e8f9f7	1152	/* Configure counters of the handle */
<>	144:ef7eb2e8f9f7	1153	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
<>	144:ef7eb2e8f9f7	1154	{
<>	144:ef7eb2e8f9f7	1155	hqspi->TxXferCount = data_size;
<>	144:ef7eb2e8f9f7	1156	}
<>	144:ef7eb2e8f9f7	1157	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
<>	144:ef7eb2e8f9f7	1158	{
<>	144:ef7eb2e8f9f7	1159	if (((data_size % 2) != 0) \|\| ((hqspi->Init.FifoThreshold % 2) != 0))
<>	144:ef7eb2e8f9f7	1160	{
<>	144:ef7eb2e8f9f7	1161	/* The number of data or the fifo threshold is not aligned on halfword
<>	144:ef7eb2e8f9f7	1162	=> no transfer possible with DMA peripheral access configured as halfword */
<>	144:ef7eb2e8f9f7	1163	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1164	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1167	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1168	}
<>	144:ef7eb2e8f9f7	1169	else
<>	144:ef7eb2e8f9f7	1170	{
<>	144:ef7eb2e8f9f7	1171	hqspi->TxXferCount = (data_size >> 1);
<>	144:ef7eb2e8f9f7	1172	}
<>	144:ef7eb2e8f9f7	1173	}
<>	144:ef7eb2e8f9f7	1174	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
<>	144:ef7eb2e8f9f7	1175	{
<>	144:ef7eb2e8f9f7	1176	if (((data_size % 4) != 0) \|\| ((hqspi->Init.FifoThreshold % 4) != 0))
<>	144:ef7eb2e8f9f7	1177	{
<>	144:ef7eb2e8f9f7	1178	/* The number of data or the fifo threshold is not aligned on word
<>	144:ef7eb2e8f9f7	1179	=> no transfer possible with DMA peripheral access configured as word */
<>	144:ef7eb2e8f9f7	1180	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1181	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1184	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1185	}
<>	144:ef7eb2e8f9f7	1186	else
<>	144:ef7eb2e8f9f7	1187	{
<>	144:ef7eb2e8f9f7	1188	hqspi->TxXferCount = (data_size >> 2);
<>	144:ef7eb2e8f9f7	1189	}
<>	144:ef7eb2e8f9f7	1190	}
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1193	{
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	/* Update state */
<>	144:ef7eb2e8f9f7	1196	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1199	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/* Configure size and pointer of the handle */
<>	144:ef7eb2e8f9f7	1202	hqspi->TxXferSize = hqspi->TxXferCount;
<>	144:ef7eb2e8f9f7	1203	hqspi->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/* Configure QSPI: CCR register with functional mode as indirect write */
<>	144:ef7eb2e8f9f7	1206	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
<>	144:ef7eb2e8f9f7	1207
<>	144:ef7eb2e8f9f7	1208	/* Set the QSPI DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1209	hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
<>	144:ef7eb2e8f9f7	1210
<>	144:ef7eb2e8f9f7	1211	/* Set the QSPI DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1212	hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	1213
<>	144:ef7eb2e8f9f7	1214	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1215	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/* Clear the DMA abort callback */
<>	144:ef7eb2e8f9f7	1218	hqspi->hdma->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/* Configure the direction of the DMA */
<>	144:ef7eb2e8f9f7	1221	hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
<>	144:ef7eb2e8f9f7	1222	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
<>	144:ef7eb2e8f9f7	1223
<>	144:ef7eb2e8f9f7	1224	/* Enable the QSPI transmit DMA Channel */
<>	144:ef7eb2e8f9f7	1225	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	1226	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
<>	144:ef7eb2e8f9f7	1227
<>	144:ef7eb2e8f9f7	1228	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1229	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	/* Enable the QSPI transfer error Interrupt */
<>	144:ef7eb2e8f9f7	1232	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
<>	144:ef7eb2e8f9f7	1233
<>	144:ef7eb2e8f9f7	1234	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1235	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1236	}
<>	144:ef7eb2e8f9f7	1237	}
<>	144:ef7eb2e8f9f7	1238	else
<>	144:ef7eb2e8f9f7	1239	{
<>	144:ef7eb2e8f9f7	1240	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1245	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1246	}
<>	144:ef7eb2e8f9f7	1247	}
<>	144:ef7eb2e8f9f7	1248	else
<>	144:ef7eb2e8f9f7	1249	{
<>	144:ef7eb2e8f9f7	1250	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1251
<>	144:ef7eb2e8f9f7	1252	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1253	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1254	}
<>	144:ef7eb2e8f9f7	1255
<>	144:ef7eb2e8f9f7	1256	return status;
<>	144:ef7eb2e8f9f7	1257	}
<>	144:ef7eb2e8f9f7	1258
<>	144:ef7eb2e8f9f7	1259	/**
<>	144:ef7eb2e8f9f7	1260	* @brief Receives an amount of data in non blocking mode with DMA.
<>	144:ef7eb2e8f9f7	1261	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1262	* @param pData: pointer to data buffer.
<>	144:ef7eb2e8f9f7	1263	* @note This function is used only in Indirect Read Mode
<>	144:ef7eb2e8f9f7	1264	* @note If DMA peripheral access is configured as halfword, the number
<>	144:ef7eb2e8f9f7	1265	* of data and the fifo threshold should be aligned on halfword
<>	144:ef7eb2e8f9f7	1266	* @note If DMA peripheral access is configured as word, the number
<>	144:ef7eb2e8f9f7	1267	* of data and the fifo threshold should be aligned on word
<>	144:ef7eb2e8f9f7	1268	* @retval HAL status
<>	144:ef7eb2e8f9f7	1269	*/
<>	144:ef7eb2e8f9f7	1270	HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef hqspi, uint8_t pData)
<>	144:ef7eb2e8f9f7	1271	{
<>	144:ef7eb2e8f9f7	1272	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1273	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	1274	uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
<>	144:ef7eb2e8f9f7	1275	uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277	/* Process locked */
<>	144:ef7eb2e8f9f7	1278	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1279
<>	144:ef7eb2e8f9f7	1280	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1281	{
<>	144:ef7eb2e8f9f7	1282	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	if(pData != NULL )
<>	144:ef7eb2e8f9f7	1285	{
<>	144:ef7eb2e8f9f7	1286	/* Configure counters of the handle */
<>	144:ef7eb2e8f9f7	1287	if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
<>	144:ef7eb2e8f9f7	1288	{
<>	144:ef7eb2e8f9f7	1289	hqspi->RxXferCount = data_size;
<>	144:ef7eb2e8f9f7	1290	}
<>	144:ef7eb2e8f9f7	1291	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
<>	144:ef7eb2e8f9f7	1292	{
<>	144:ef7eb2e8f9f7	1293	if (((data_size % 2) != 0) \|\| ((hqspi->Init.FifoThreshold % 2) != 0))
<>	144:ef7eb2e8f9f7	1294	{
<>	144:ef7eb2e8f9f7	1295	/* The number of data or the fifo threshold is not aligned on halfword
<>	144:ef7eb2e8f9f7	1296	=> no transfer possible with DMA peripheral access configured as halfword */
<>	144:ef7eb2e8f9f7	1297	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1298	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1301	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1302	}
<>	144:ef7eb2e8f9f7	1303	else
<>	144:ef7eb2e8f9f7	1304	{
<>	144:ef7eb2e8f9f7	1305	hqspi->RxXferCount = (data_size >> 1);
<>	144:ef7eb2e8f9f7	1306	}
<>	144:ef7eb2e8f9f7	1307	}
<>	144:ef7eb2e8f9f7	1308	else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
<>	144:ef7eb2e8f9f7	1309	{
<>	144:ef7eb2e8f9f7	1310	if (((data_size % 4) != 0) \|\| ((hqspi->Init.FifoThreshold % 4) != 0))
<>	144:ef7eb2e8f9f7	1311	{
<>	144:ef7eb2e8f9f7	1312	/* The number of data or the fifo threshold is not aligned on word
<>	144:ef7eb2e8f9f7	1313	=> no transfer possible with DMA peripheral access configured as word */
<>	144:ef7eb2e8f9f7	1314	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1315	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1318	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1319	}
<>	144:ef7eb2e8f9f7	1320	else
<>	144:ef7eb2e8f9f7	1321	{
<>	144:ef7eb2e8f9f7	1322	hqspi->RxXferCount = (data_size >> 2);
<>	144:ef7eb2e8f9f7	1323	}
<>	144:ef7eb2e8f9f7	1324	}
<>	144:ef7eb2e8f9f7	1325
<>	144:ef7eb2e8f9f7	1326	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1327	{
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	/* Update state */
<>	144:ef7eb2e8f9f7	1330	hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
<>	144:ef7eb2e8f9f7	1331
<>	144:ef7eb2e8f9f7	1332	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1333	__HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE \| QSPI_FLAG_TC));
<>	144:ef7eb2e8f9f7	1334
<>	144:ef7eb2e8f9f7	1335	/* Configure size and pointer of the handle */
<>	144:ef7eb2e8f9f7	1336	hqspi->RxXferSize = hqspi->RxXferCount;
<>	144:ef7eb2e8f9f7	1337	hqspi->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	/* Set the QSPI DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1340	hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
<>	144:ef7eb2e8f9f7	1341
<>	144:ef7eb2e8f9f7	1342	/* Set the QSPI DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1343	hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	1344
<>	144:ef7eb2e8f9f7	1345	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1346	hqspi->hdma->XferErrorCallback = QSPI_DMAError;
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Clear the DMA abort callback */
<>	144:ef7eb2e8f9f7	1349	hqspi->hdma->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1350
<>	144:ef7eb2e8f9f7	1351	/* Configure the direction of the DMA */
<>	144:ef7eb2e8f9f7	1352	hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
<>	144:ef7eb2e8f9f7	1353	MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	/* Enable the DMA Channel */
<>	144:ef7eb2e8f9f7	1356	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	1357	HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)tmp, hqspi->RxXferSize);
<>	144:ef7eb2e8f9f7	1358
<>	144:ef7eb2e8f9f7	1359	/* Configure QSPI: CCR register with functional as indirect read */
<>	144:ef7eb2e8f9f7	1360	MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
<>	144:ef7eb2e8f9f7	1361
<>	144:ef7eb2e8f9f7	1362	/* Start the transfer by re-writing the address in AR register */
<>	144:ef7eb2e8f9f7	1363	WRITE_REG(hqspi->Instance->AR, addr_reg);
<>	144:ef7eb2e8f9f7	1364
<>	144:ef7eb2e8f9f7	1365	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1366	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1367
<>	144:ef7eb2e8f9f7	1368	/* Enable the QSPI transfer error Interrupt */
<>	144:ef7eb2e8f9f7	1369	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371	/* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1372	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1373	}
<>	144:ef7eb2e8f9f7	1374	}
<>	144:ef7eb2e8f9f7	1375	else
<>	144:ef7eb2e8f9f7	1376	{
<>	144:ef7eb2e8f9f7	1377	hqspi->ErrorCode \|= HAL_QSPI_ERROR_INVALID_PARAM;
<>	144:ef7eb2e8f9f7	1378	status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1379
<>	144:ef7eb2e8f9f7	1380	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1381	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1382	}
<>	144:ef7eb2e8f9f7	1383	}
<>	144:ef7eb2e8f9f7	1384	else
<>	144:ef7eb2e8f9f7	1385	{
<>	144:ef7eb2e8f9f7	1386	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1389	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1390	}
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	return status;
<>	144:ef7eb2e8f9f7	1393	}
<>	144:ef7eb2e8f9f7	1394
<>	144:ef7eb2e8f9f7	1395	/**
<>	144:ef7eb2e8f9f7	1396	* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
<>	144:ef7eb2e8f9f7	1397	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1398	* @param cmd: structure that contains the command configuration information.
<>	144:ef7eb2e8f9f7	1399	* @param cfg: structure that contains the polling configuration information.
<>	144:ef7eb2e8f9f7	1400	* @param Timeout : Time out duration
<>	144:ef7eb2e8f9f7	1401	* @note This function is used only in Automatic Polling Mode
<>	144:ef7eb2e8f9f7	1402	* @retval HAL status
<>	144:ef7eb2e8f9f7	1403	*/
<>	144:ef7eb2e8f9f7	1404	HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1405	{
<>	144:ef7eb2e8f9f7	1406	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1407	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1408
<>	144:ef7eb2e8f9f7	1409	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1410	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	1411	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	1412	{
<>	144:ef7eb2e8f9f7	1413	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	1414	}
<>	144:ef7eb2e8f9f7	1415
<>	144:ef7eb2e8f9f7	1416	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	1417	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	1418	{
<>	144:ef7eb2e8f9f7	1419	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	1420	}
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	1423	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	1424	{
<>	144:ef7eb2e8f9f7	1425	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	1426	}
<>	144:ef7eb2e8f9f7	1427
<>	144:ef7eb2e8f9f7	1428	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	1429	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	1430
<>	144:ef7eb2e8f9f7	1431	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	1432	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	1433	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
<>	144:ef7eb2e8f9f7	1436	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
<>	144:ef7eb2e8f9f7	1437	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
<>	144:ef7eb2e8f9f7	1438
<>	144:ef7eb2e8f9f7	1439	/* Process locked */
<>	144:ef7eb2e8f9f7	1440	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1441
<>	144:ef7eb2e8f9f7	1442	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1443	{
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1446
<>	144:ef7eb2e8f9f7	1447	/* Update state */
<>	144:ef7eb2e8f9f7	1448	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	1451	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	1452
<>	144:ef7eb2e8f9f7	1453	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1454	{
<>	144:ef7eb2e8f9f7	1455	/* Configure QSPI: PSMAR register with the status match value */
<>	144:ef7eb2e8f9f7	1456	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
<>	144:ef7eb2e8f9f7	1457
<>	144:ef7eb2e8f9f7	1458	/* Configure QSPI: PSMKR register with the status mask value */
<>	144:ef7eb2e8f9f7	1459	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
<>	144:ef7eb2e8f9f7	1460
<>	144:ef7eb2e8f9f7	1461	/* Configure QSPI: PIR register with the interval value */
<>	144:ef7eb2e8f9f7	1462	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
<>	144:ef7eb2e8f9f7	1463
<>	144:ef7eb2e8f9f7	1464	/* Configure QSPI: CR register with Match mode and Automatic stop enabled
<>	144:ef7eb2e8f9f7	1465	(otherwise there will be an infinite loop in blocking mode) */
<>	144:ef7eb2e8f9f7	1466	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
<>	144:ef7eb2e8f9f7	1467	(cfg->MatchMode \| QSPI_AUTOMATIC_STOP_ENABLE));
<>	144:ef7eb2e8f9f7	1468
<>	144:ef7eb2e8f9f7	1469	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	1470	cmd->NbData = cfg->StatusBytesSize;
<>	144:ef7eb2e8f9f7	1471	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
<>	144:ef7eb2e8f9f7	1472
<>	144:ef7eb2e8f9f7	1473	/* Wait until SM flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	1474	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
<>	144:ef7eb2e8f9f7	1475
<>	144:ef7eb2e8f9f7	1476	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1477	{
<>	144:ef7eb2e8f9f7	1478	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
<>	144:ef7eb2e8f9f7	1479
<>	144:ef7eb2e8f9f7	1480	/* Update state */
<>	144:ef7eb2e8f9f7	1481	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1482	}
<>	144:ef7eb2e8f9f7	1483	}
<>	144:ef7eb2e8f9f7	1484	}
<>	144:ef7eb2e8f9f7	1485	else
<>	144:ef7eb2e8f9f7	1486	{
<>	144:ef7eb2e8f9f7	1487	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1488	}
<>	144:ef7eb2e8f9f7	1489	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1490	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1491
<>	144:ef7eb2e8f9f7	1492	/* Return function status */
<>	144:ef7eb2e8f9f7	1493	return status;
<>	144:ef7eb2e8f9f7	1494	}
<>	144:ef7eb2e8f9f7	1495
<>	144:ef7eb2e8f9f7	1496	/**
<>	144:ef7eb2e8f9f7	1497	* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
<>	144:ef7eb2e8f9f7	1498	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1499	* @param cmd: structure that contains the command configuration information.
<>	144:ef7eb2e8f9f7	1500	* @param cfg: structure that contains the polling configuration information.
<>	144:ef7eb2e8f9f7	1501	* @note This function is used only in Automatic Polling Mode
<>	144:ef7eb2e8f9f7	1502	* @retval HAL status
<>	144:ef7eb2e8f9f7	1503	*/
<>	144:ef7eb2e8f9f7	1504	HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_AutoPollingTypeDef *cfg)
<>	144:ef7eb2e8f9f7	1505	{
<>	144:ef7eb2e8f9f7	1506	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1507	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1508
<>	144:ef7eb2e8f9f7	1509	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1510	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	1511	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	1512	{
<>	144:ef7eb2e8f9f7	1513	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	1514	}
<>	144:ef7eb2e8f9f7	1515
<>	144:ef7eb2e8f9f7	1516	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	1517	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	1518	{
<>	144:ef7eb2e8f9f7	1519	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	1520	}
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	1523	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	1524	{
<>	144:ef7eb2e8f9f7	1525	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	1526	}
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	1529	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	1532	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	1533	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	1534
<>	144:ef7eb2e8f9f7	1535	assert_param(IS_QSPI_INTERVAL(cfg->Interval));
<>	144:ef7eb2e8f9f7	1536	assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
<>	144:ef7eb2e8f9f7	1537	assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
<>	144:ef7eb2e8f9f7	1538	assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
<>	144:ef7eb2e8f9f7	1539
<>	144:ef7eb2e8f9f7	1540	/* Process locked */
<>	144:ef7eb2e8f9f7	1541	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1542
<>	144:ef7eb2e8f9f7	1543	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1544	{
<>	144:ef7eb2e8f9f7	1545	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1546
<>	144:ef7eb2e8f9f7	1547	/* Update state */
<>	144:ef7eb2e8f9f7	1548	hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
<>	144:ef7eb2e8f9f7	1549
<>	144:ef7eb2e8f9f7	1550	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	1551	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1552
<>	144:ef7eb2e8f9f7	1553	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1554	{
<>	144:ef7eb2e8f9f7	1555	/* Configure QSPI: PSMAR register with the status match value */
<>	144:ef7eb2e8f9f7	1556	WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
<>	144:ef7eb2e8f9f7	1557
<>	144:ef7eb2e8f9f7	1558	/* Configure QSPI: PSMKR register with the status mask value */
<>	144:ef7eb2e8f9f7	1559	WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	/* Configure QSPI: PIR register with the interval value */
<>	144:ef7eb2e8f9f7	1562	WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
<>	144:ef7eb2e8f9f7	1563
<>	144:ef7eb2e8f9f7	1564	/* Configure QSPI: CR register with Match mode and Automatic stop mode */
<>	144:ef7eb2e8f9f7	1565	MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM \| QUADSPI_CR_APMS),
<>	144:ef7eb2e8f9f7	1566	(cfg->MatchMode \| cfg->AutomaticStop));
<>	144:ef7eb2e8f9f7	1567
<>	144:ef7eb2e8f9f7	1568	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1569	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE \| QSPI_FLAG_SM);
<>	144:ef7eb2e8f9f7	1570
<>	144:ef7eb2e8f9f7	1571	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	1572	cmd->NbData = cfg->StatusBytesSize;
<>	144:ef7eb2e8f9f7	1573	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
<>	144:ef7eb2e8f9f7	1574
<>	144:ef7eb2e8f9f7	1575	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1576	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	/* Enable the QSPI Transfer Error and status match Interrupt */
<>	144:ef7eb2e8f9f7	1579	__HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM \| QSPI_IT_TE));
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	}
<>	144:ef7eb2e8f9f7	1582	else
<>	144:ef7eb2e8f9f7	1583	{
<>	144:ef7eb2e8f9f7	1584	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1585	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1586	}
<>	144:ef7eb2e8f9f7	1587	}
<>	144:ef7eb2e8f9f7	1588	else
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1591
<>	144:ef7eb2e8f9f7	1592	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1593	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1594	}
<>	144:ef7eb2e8f9f7	1595
<>	144:ef7eb2e8f9f7	1596	/* Return function status */
<>	144:ef7eb2e8f9f7	1597	return status;
<>	144:ef7eb2e8f9f7	1598	}
<>	144:ef7eb2e8f9f7	1599
<>	144:ef7eb2e8f9f7	1600	/**
<>	144:ef7eb2e8f9f7	1601	* @brief Configure the Memory Mapped mode.
<>	144:ef7eb2e8f9f7	1602	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1603	* @param cmd: structure that contains the command configuration information.
<>	144:ef7eb2e8f9f7	1604	* @param cfg: structure that contains the memory mapped configuration information.
<>	144:ef7eb2e8f9f7	1605	* @note This function is used only in Memory mapped Mode
<>	144:ef7eb2e8f9f7	1606	* @retval HAL status
<>	144:ef7eb2e8f9f7	1607	*/
<>	144:ef7eb2e8f9f7	1608	HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, QSPI_MemoryMappedTypeDef *cfg)
<>	144:ef7eb2e8f9f7	1609	{
<>	144:ef7eb2e8f9f7	1610	HAL_StatusTypeDef status = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1611	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1612
<>	144:ef7eb2e8f9f7	1613	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1614	assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
<>	144:ef7eb2e8f9f7	1615	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	1616	{
<>	144:ef7eb2e8f9f7	1617	assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
<>	144:ef7eb2e8f9f7	1618	}
<>	144:ef7eb2e8f9f7	1619
<>	144:ef7eb2e8f9f7	1620	assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
<>	144:ef7eb2e8f9f7	1621	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	1622	{
<>	144:ef7eb2e8f9f7	1623	assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
<>	144:ef7eb2e8f9f7	1624	}
<>	144:ef7eb2e8f9f7	1625
<>	144:ef7eb2e8f9f7	1626	assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
<>	144:ef7eb2e8f9f7	1627	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	1628	{
<>	144:ef7eb2e8f9f7	1629	assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
<>	144:ef7eb2e8f9f7	1630	}
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
<>	144:ef7eb2e8f9f7	1633	assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
<>	144:ef7eb2e8f9f7	1636	assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
<>	144:ef7eb2e8f9f7	1637	assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
<>	144:ef7eb2e8f9f7	1638
<>	144:ef7eb2e8f9f7	1639	assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
<>	144:ef7eb2e8f9f7	1640
<>	144:ef7eb2e8f9f7	1641	/* Process locked */
<>	144:ef7eb2e8f9f7	1642	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	1643
<>	144:ef7eb2e8f9f7	1644	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	1645	{
<>	144:ef7eb2e8f9f7	1646	hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1647
<>	144:ef7eb2e8f9f7	1648	/* Update state */
<>	144:ef7eb2e8f9f7	1649	hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
<>	144:ef7eb2e8f9f7	1650
<>	144:ef7eb2e8f9f7	1651	/* Wait till BUSY flag reset */
<>	144:ef7eb2e8f9f7	1652	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1653
<>	144:ef7eb2e8f9f7	1654	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1655	{
<>	144:ef7eb2e8f9f7	1656	/* Configure QSPI: CR register with timeout counter enable */
<>	144:ef7eb2e8f9f7	1657	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
<>	144:ef7eb2e8f9f7	1658
<>	144:ef7eb2e8f9f7	1659	if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
<>	144:ef7eb2e8f9f7	1660	{
<>	144:ef7eb2e8f9f7	1661	assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
<>	144:ef7eb2e8f9f7	1662
<>	144:ef7eb2e8f9f7	1663	/* Configure QSPI: LPTR register with the low-power timeout value */
<>	144:ef7eb2e8f9f7	1664	WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
<>	144:ef7eb2e8f9f7	1665
<>	144:ef7eb2e8f9f7	1666	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1667	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
<>	144:ef7eb2e8f9f7	1668
<>	144:ef7eb2e8f9f7	1669	/* Enable the QSPI TimeOut Interrupt */
<>	144:ef7eb2e8f9f7	1670	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
<>	144:ef7eb2e8f9f7	1671	}
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673	/* Call the configuration function */
<>	144:ef7eb2e8f9f7	1674	QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
<>	144:ef7eb2e8f9f7	1675	}
<>	144:ef7eb2e8f9f7	1676	}
<>	144:ef7eb2e8f9f7	1677	else
<>	144:ef7eb2e8f9f7	1678	{
<>	144:ef7eb2e8f9f7	1679	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	1680	}
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1683	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1684
<>	144:ef7eb2e8f9f7	1685	/* Return function status */
<>	144:ef7eb2e8f9f7	1686	return status;
<>	144:ef7eb2e8f9f7	1687	}
<>	144:ef7eb2e8f9f7	1688
<>	144:ef7eb2e8f9f7	1689	/**
<>	144:ef7eb2e8f9f7	1690	* @brief Transfer Error callbacks
<>	144:ef7eb2e8f9f7	1691	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1692	* @retval None
<>	144:ef7eb2e8f9f7	1693	*/
<>	144:ef7eb2e8f9f7	1694	__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1695	{
<>	144:ef7eb2e8f9f7	1696	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1697	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1698
<>	144:ef7eb2e8f9f7	1699	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1700	the HAL_QSPI_ErrorCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1701	*/
<>	144:ef7eb2e8f9f7	1702	}
<>	144:ef7eb2e8f9f7	1703
<>	144:ef7eb2e8f9f7	1704	/**
<>	144:ef7eb2e8f9f7	1705	* @brief Abort completed callback.
<>	144:ef7eb2e8f9f7	1706	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1707	* @retval None
<>	144:ef7eb2e8f9f7	1708	*/
<>	144:ef7eb2e8f9f7	1709	__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1710	{
<>	144:ef7eb2e8f9f7	1711	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1712	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1713
<>	144:ef7eb2e8f9f7	1714	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1715	the HAL_QSPI_AbortCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1716	*/
<>	144:ef7eb2e8f9f7	1717	}
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719	/**
<>	144:ef7eb2e8f9f7	1720	* @brief Command completed callback.
<>	144:ef7eb2e8f9f7	1721	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1722	* @retval None
<>	144:ef7eb2e8f9f7	1723	*/
<>	144:ef7eb2e8f9f7	1724	__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1725	{
<>	144:ef7eb2e8f9f7	1726	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1727	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1728
<>	144:ef7eb2e8f9f7	1729	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1730	the HAL_QSPI_CmdCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1731	*/
<>	144:ef7eb2e8f9f7	1732	}
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	/**
<>	144:ef7eb2e8f9f7	1735	* @brief Rx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1736	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1737	* @retval None
<>	144:ef7eb2e8f9f7	1738	*/
<>	144:ef7eb2e8f9f7	1739	__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1740	{
<>	144:ef7eb2e8f9f7	1741	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1742	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1743
<>	144:ef7eb2e8f9f7	1744	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1745	the HAL_QSPI_RxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1746	*/
<>	144:ef7eb2e8f9f7	1747	}
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	/**
<>	144:ef7eb2e8f9f7	1750	* @brief Tx Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1751	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1752	* @retval None
<>	144:ef7eb2e8f9f7	1753	*/
<>	144:ef7eb2e8f9f7	1754	__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1755	{
<>	144:ef7eb2e8f9f7	1756	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1757	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1760	the HAL_QSPI_TxCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1761	*/
<>	144:ef7eb2e8f9f7	1762	}
<>	144:ef7eb2e8f9f7	1763
<>	144:ef7eb2e8f9f7	1764	/**
<>	144:ef7eb2e8f9f7	1765	* @brief Rx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1766	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1767	* @retval None
<>	144:ef7eb2e8f9f7	1768	*/
<>	144:ef7eb2e8f9f7	1769	__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1770	{
<>	144:ef7eb2e8f9f7	1771	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1772	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1773
<>	144:ef7eb2e8f9f7	1774	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1775	the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1776	*/
<>	144:ef7eb2e8f9f7	1777	}
<>	144:ef7eb2e8f9f7	1778
<>	144:ef7eb2e8f9f7	1779	/**
<>	144:ef7eb2e8f9f7	1780	* @brief Tx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1781	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1782	* @retval None
<>	144:ef7eb2e8f9f7	1783	*/
<>	144:ef7eb2e8f9f7	1784	__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1785	{
<>	144:ef7eb2e8f9f7	1786	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1787	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1788
<>	144:ef7eb2e8f9f7	1789	/* NOTE: This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1790	the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1791	*/
<>	144:ef7eb2e8f9f7	1792	}
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	/**
<>	144:ef7eb2e8f9f7	1795	* @brief FIFO Threshold callbacks
<>	144:ef7eb2e8f9f7	1796	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1797	* @retval None
<>	144:ef7eb2e8f9f7	1798	*/
<>	144:ef7eb2e8f9f7	1799	__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1800	{
<>	144:ef7eb2e8f9f7	1801	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1802	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1803
<>	144:ef7eb2e8f9f7	1804	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1805	the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1806	*/
<>	144:ef7eb2e8f9f7	1807	}
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	/**
<>	144:ef7eb2e8f9f7	1810	* @brief Status Match callbacks
<>	144:ef7eb2e8f9f7	1811	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1812	* @retval None
<>	144:ef7eb2e8f9f7	1813	*/
<>	144:ef7eb2e8f9f7	1814	__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1815	{
<>	144:ef7eb2e8f9f7	1816	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1817	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1818
<>	144:ef7eb2e8f9f7	1819	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1820	the HAL_QSPI_StatusMatchCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1821	*/
<>	144:ef7eb2e8f9f7	1822	}
<>	144:ef7eb2e8f9f7	1823
<>	144:ef7eb2e8f9f7	1824	/**
<>	144:ef7eb2e8f9f7	1825	* @brief Timeout callbacks
<>	144:ef7eb2e8f9f7	1826	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1827	* @retval None
<>	144:ef7eb2e8f9f7	1828	*/
<>	144:ef7eb2e8f9f7	1829	__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1830	{
<>	144:ef7eb2e8f9f7	1831	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1832	UNUSED(hqspi);
<>	144:ef7eb2e8f9f7	1833
<>	144:ef7eb2e8f9f7	1834	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1835	the HAL_QSPI_TimeOutCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	1836	*/
<>	144:ef7eb2e8f9f7	1837	}
<>	144:ef7eb2e8f9f7	1838
<>	144:ef7eb2e8f9f7	1839	/**
<>	144:ef7eb2e8f9f7	1840	* @}
<>	144:ef7eb2e8f9f7	1841	*/
<>	144:ef7eb2e8f9f7	1842
<>	144:ef7eb2e8f9f7	1843	/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
<>	144:ef7eb2e8f9f7	1844	* @brief QSPI control and State functions
<>	144:ef7eb2e8f9f7	1845	*
<>	144:ef7eb2e8f9f7	1846	@verbatim
<>	144:ef7eb2e8f9f7	1847	===============================================================================
<>	144:ef7eb2e8f9f7	1848	##### Peripheral Control and State functions #####
<>	144:ef7eb2e8f9f7	1849	===============================================================================
<>	144:ef7eb2e8f9f7	1850	[..]
<>	144:ef7eb2e8f9f7	1851	This subsection provides a set of functions allowing to :
<>	144:ef7eb2e8f9f7	1852	(+) Check in run-time the state of the driver.
<>	144:ef7eb2e8f9f7	1853	(+) Check the error code set during last operation.
<>	144:ef7eb2e8f9f7	1854	(+) Abort any operation.
<>	144:ef7eb2e8f9f7	1855	.....
<>	144:ef7eb2e8f9f7	1856	@endverbatim
<>	144:ef7eb2e8f9f7	1857	* @{
<>	144:ef7eb2e8f9f7	1858	*/
<>	144:ef7eb2e8f9f7	1859
<>	144:ef7eb2e8f9f7	1860	/**
<>	144:ef7eb2e8f9f7	1861	* @brief Return the QSPI handle state.
<>	144:ef7eb2e8f9f7	1862	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1863	* @retval HAL state
<>	144:ef7eb2e8f9f7	1864	*/
<>	144:ef7eb2e8f9f7	1865	HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1866	{
<>	144:ef7eb2e8f9f7	1867	/* Return QSPI handle state */
<>	144:ef7eb2e8f9f7	1868	return hqspi->State;
<>	144:ef7eb2e8f9f7	1869	}
<>	144:ef7eb2e8f9f7	1870
<>	144:ef7eb2e8f9f7	1871	/**
<>	144:ef7eb2e8f9f7	1872	* @brief Return the QSPI error code
<>	144:ef7eb2e8f9f7	1873	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1874	* @retval QSPI Error Code
<>	144:ef7eb2e8f9f7	1875	*/
<>	144:ef7eb2e8f9f7	1876	uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1877	{
<>	144:ef7eb2e8f9f7	1878	return hqspi->ErrorCode;
<>	144:ef7eb2e8f9f7	1879	}
<>	144:ef7eb2e8f9f7	1880
<>	144:ef7eb2e8f9f7	1881	/**
<>	144:ef7eb2e8f9f7	1882	* @brief Abort the current transmission
<>	144:ef7eb2e8f9f7	1883	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1884	* @retval HAL status
<>	144:ef7eb2e8f9f7	1885	*/
<>	144:ef7eb2e8f9f7	1886	HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1887	{
<>	144:ef7eb2e8f9f7	1888	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1889	uint32_t tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1890
<>	144:ef7eb2e8f9f7	1891	/* Check if the state is in one of the busy states */
<>	144:ef7eb2e8f9f7	1892	if ((hqspi->State & 0x2) != 0)
<>	144:ef7eb2e8f9f7	1893	{
<>	144:ef7eb2e8f9f7	1894	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1895	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
<>	144:ef7eb2e8f9f7	1898	{
<>	144:ef7eb2e8f9f7	1899	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1900	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902	/* Abort DMA channel */
<>	144:ef7eb2e8f9f7	1903	status = HAL_DMA_Abort(hqspi->hdma);
<>	144:ef7eb2e8f9f7	1904	if(status != HAL_OK)
<>	144:ef7eb2e8f9f7	1905	{
<>	144:ef7eb2e8f9f7	1906	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
<>	144:ef7eb2e8f9f7	1907	}
<>	144:ef7eb2e8f9f7	1908	}
<>	144:ef7eb2e8f9f7	1909
<>	144:ef7eb2e8f9f7	1910	/* Configure QSPI: CR register with Abort request */
<>	144:ef7eb2e8f9f7	1911	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
<>	144:ef7eb2e8f9f7	1912
<>	144:ef7eb2e8f9f7	1913	/* Wait until TC flag is set to go back in idle state */
<>	144:ef7eb2e8f9f7	1914	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1915
<>	144:ef7eb2e8f9f7	1916	if(status == HAL_OK)
<>	144:ef7eb2e8f9f7	1917	{
<>	144:ef7eb2e8f9f7	1918	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/* Wait until BUSY flag is reset */
<>	144:ef7eb2e8f9f7	1921	status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
<>	144:ef7eb2e8f9f7	1922	}
<>	144:ef7eb2e8f9f7	1923
<>	144:ef7eb2e8f9f7	1924	if (status == HAL_OK)
<>	144:ef7eb2e8f9f7	1925	{
<>	144:ef7eb2e8f9f7	1926	/* Update state */
<>	144:ef7eb2e8f9f7	1927	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	1928	}
<>	144:ef7eb2e8f9f7	1929	}
<>	144:ef7eb2e8f9f7	1930
<>	144:ef7eb2e8f9f7	1931	return status;
<>	144:ef7eb2e8f9f7	1932	}
<>	144:ef7eb2e8f9f7	1933
<>	144:ef7eb2e8f9f7	1934	/**
<>	144:ef7eb2e8f9f7	1935	* @brief Abort the current transmission (non-blocking function)
<>	144:ef7eb2e8f9f7	1936	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	1937	* @retval HAL status
<>	144:ef7eb2e8f9f7	1938	*/
<>	144:ef7eb2e8f9f7	1939	HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	1940	{
<>	144:ef7eb2e8f9f7	1941	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1942
<>	144:ef7eb2e8f9f7	1943	/* Check if the state is in one of the busy states */
<>	144:ef7eb2e8f9f7	1944	if ((hqspi->State & 0x2) != 0)
<>	144:ef7eb2e8f9f7	1945	{
<>	144:ef7eb2e8f9f7	1946	/* Process unlocked */
<>	144:ef7eb2e8f9f7	1947	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	1948
<>	144:ef7eb2e8f9f7	1949	/* Update QSPI state */
<>	144:ef7eb2e8f9f7	1950	hqspi->State = HAL_QSPI_STATE_ABORT;
<>	144:ef7eb2e8f9f7	1951
<>	144:ef7eb2e8f9f7	1952	/* Disable all interrupts */
<>	144:ef7eb2e8f9f7	1953	__HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO \| QSPI_IT_SM \| QSPI_IT_FT \| QSPI_IT_TC \| QSPI_IT_TE));
<>	144:ef7eb2e8f9f7	1954
<>	144:ef7eb2e8f9f7	1955	if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
<>	144:ef7eb2e8f9f7	1956	{
<>	144:ef7eb2e8f9f7	1957	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	1958	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	1959
<>	144:ef7eb2e8f9f7	1960	/* Abort DMA channel */
<>	144:ef7eb2e8f9f7	1961	hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
<>	144:ef7eb2e8f9f7	1962	HAL_DMA_Abort_IT(hqspi->hdma);
<>	144:ef7eb2e8f9f7	1963	}
<>	144:ef7eb2e8f9f7	1964	else
<>	144:ef7eb2e8f9f7	1965	{
<>	144:ef7eb2e8f9f7	1966	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	1967	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	1968
<>	144:ef7eb2e8f9f7	1969	/* Enable the QSPI Transfer Complete Interrupt */
<>	144:ef7eb2e8f9f7	1970	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	/* Configure QSPI: CR register with Abort request */
<>	144:ef7eb2e8f9f7	1973	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
<>	144:ef7eb2e8f9f7	1974	}
<>	144:ef7eb2e8f9f7	1975	}
<>	144:ef7eb2e8f9f7	1976
<>	144:ef7eb2e8f9f7	1977	return status;
<>	144:ef7eb2e8f9f7	1978	}
<>	144:ef7eb2e8f9f7	1979
<>	144:ef7eb2e8f9f7	1980	/** @brief Set QSPI timeout
<>	144:ef7eb2e8f9f7	1981	* @param hqspi: QSPI handle.
<>	144:ef7eb2e8f9f7	1982	* @param Timeout: Timeout for the QSPI memory access.
<>	144:ef7eb2e8f9f7	1983	* @retval None
<>	144:ef7eb2e8f9f7	1984	*/
<>	144:ef7eb2e8f9f7	1985	void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1986	{
<>	144:ef7eb2e8f9f7	1987	hqspi->Timeout = Timeout;
<>	144:ef7eb2e8f9f7	1988	}
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	/** @brief Set QSPI Fifo threshold.
<>	144:ef7eb2e8f9f7	1991	* @param hqspi: QSPI handle.
<>	144:ef7eb2e8f9f7	1992	* @param Threshold: Threshold of the Fifo (value between 1 and 16).
<>	144:ef7eb2e8f9f7	1993	* @retval HAL status
<>	144:ef7eb2e8f9f7	1994	*/
<>	144:ef7eb2e8f9f7	1995	HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
<>	144:ef7eb2e8f9f7	1996	{
<>	144:ef7eb2e8f9f7	1997	HAL_StatusTypeDef status = HAL_OK;
<>	144:ef7eb2e8f9f7	1998
<>	144:ef7eb2e8f9f7	1999	/* Process locked */
<>	144:ef7eb2e8f9f7	2000	__HAL_LOCK(hqspi);
<>	144:ef7eb2e8f9f7	2001
<>	144:ef7eb2e8f9f7	2002	if(hqspi->State == HAL_QSPI_STATE_READY)
<>	144:ef7eb2e8f9f7	2003	{
<>	144:ef7eb2e8f9f7	2004	/* Synchronize init structure with new FIFO threshold value */
<>	144:ef7eb2e8f9f7	2005	hqspi->Init.FifoThreshold = Threshold;
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007	/* Configure QSPI FIFO Threshold */
<>	144:ef7eb2e8f9f7	2008	MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
<>	144:ef7eb2e8f9f7	2009	((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
<>	144:ef7eb2e8f9f7	2010	}
<>	144:ef7eb2e8f9f7	2011	else
<>	144:ef7eb2e8f9f7	2012	{
<>	144:ef7eb2e8f9f7	2013	status = HAL_BUSY;
<>	144:ef7eb2e8f9f7	2014	}
<>	144:ef7eb2e8f9f7	2015
<>	144:ef7eb2e8f9f7	2016	/* Process unlocked */
<>	144:ef7eb2e8f9f7	2017	__HAL_UNLOCK(hqspi);
<>	144:ef7eb2e8f9f7	2018
<>	144:ef7eb2e8f9f7	2019	/* Return function status */
<>	144:ef7eb2e8f9f7	2020	return status;
<>	144:ef7eb2e8f9f7	2021	}
<>	144:ef7eb2e8f9f7	2022
<>	144:ef7eb2e8f9f7	2023	/** @brief Get QSPI Fifo threshold.
<>	144:ef7eb2e8f9f7	2024	* @param hqspi: QSPI handle.
<>	144:ef7eb2e8f9f7	2025	* @retval Fifo threshold (value between 1 and 16)
<>	144:ef7eb2e8f9f7	2026	*/
<>	144:ef7eb2e8f9f7	2027	uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
<>	144:ef7eb2e8f9f7	2028	{
<>	144:ef7eb2e8f9f7	2029	return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
<>	144:ef7eb2e8f9f7	2030	}
<>	144:ef7eb2e8f9f7	2031
<>	144:ef7eb2e8f9f7	2032	/**
<>	144:ef7eb2e8f9f7	2033	* @}
<>	144:ef7eb2e8f9f7	2034	*/
<>	144:ef7eb2e8f9f7	2035
<>	144:ef7eb2e8f9f7	2036	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2037
<>	144:ef7eb2e8f9f7	2038	/**
<>	144:ef7eb2e8f9f7	2039	* @brief DMA QSPI receive process complete callback.
<>	144:ef7eb2e8f9f7	2040	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2041	* @retval None
<>	144:ef7eb2e8f9f7	2042	*/
<>	144:ef7eb2e8f9f7	2043	static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2044	{
<>	144:ef7eb2e8f9f7	2045	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2046	hqspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2047
<>	144:ef7eb2e8f9f7	2048	/* Enable the QSPI transfer complete Interrupt */
<>	144:ef7eb2e8f9f7	2049	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	2050	}
<>	144:ef7eb2e8f9f7	2051
<>	144:ef7eb2e8f9f7	2052	/**
<>	144:ef7eb2e8f9f7	2053	* @brief DMA QSPI transmit process complete callback.
<>	144:ef7eb2e8f9f7	2054	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2055	* @retval None
<>	144:ef7eb2e8f9f7	2056	*/
<>	144:ef7eb2e8f9f7	2057	static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2058	{
<>	144:ef7eb2e8f9f7	2059	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2060	hqspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2061
<>	144:ef7eb2e8f9f7	2062	/* Enable the QSPI transfer complete Interrupt */
<>	144:ef7eb2e8f9f7	2063	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	2064	}
<>	144:ef7eb2e8f9f7	2065
<>	144:ef7eb2e8f9f7	2066	/**
<>	144:ef7eb2e8f9f7	2067	* @brief DMA QSPI receive process half complete callback
<>	144:ef7eb2e8f9f7	2068	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	2069	* @retval None
<>	144:ef7eb2e8f9f7	2070	*/
<>	144:ef7eb2e8f9f7	2071	static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2072	{
<>	144:ef7eb2e8f9f7	2073	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2074
<>	144:ef7eb2e8f9f7	2075	HAL_QSPI_RxHalfCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	2076	}
<>	144:ef7eb2e8f9f7	2077
<>	144:ef7eb2e8f9f7	2078	/**
<>	144:ef7eb2e8f9f7	2079	* @brief DMA QSPI transmit process half complete callback
<>	144:ef7eb2e8f9f7	2080	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	2081	* @retval None
<>	144:ef7eb2e8f9f7	2082	*/
<>	144:ef7eb2e8f9f7	2083	static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2084	{
<>	144:ef7eb2e8f9f7	2085	QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	2086
<>	144:ef7eb2e8f9f7	2087	HAL_QSPI_TxHalfCpltCallback(hqspi);
<>	144:ef7eb2e8f9f7	2088	}
<>	144:ef7eb2e8f9f7	2089
<>	144:ef7eb2e8f9f7	2090	/**
<>	144:ef7eb2e8f9f7	2091	* @brief DMA QSPI communication error callback.
<>	144:ef7eb2e8f9f7	2092	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2093	* @retval None
<>	144:ef7eb2e8f9f7	2094	*/
<>	144:ef7eb2e8f9f7	2095	static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2096	{
<>	144:ef7eb2e8f9f7	2097	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2098
<>	144:ef7eb2e8f9f7	2099	/* if DMA error is FIFO error ignore it */
<>	144:ef7eb2e8f9f7	2100	if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
<>	144:ef7eb2e8f9f7	2101	{
<>	144:ef7eb2e8f9f7	2102	hqspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2103	hqspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2104	hqspi->ErrorCode \|= HAL_QSPI_ERROR_DMA;
<>	144:ef7eb2e8f9f7	2105
<>	144:ef7eb2e8f9f7	2106	/* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
<>	144:ef7eb2e8f9f7	2107	CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
<>	144:ef7eb2e8f9f7	2108
<>	144:ef7eb2e8f9f7	2109	/* Abort the QSPI */
<>	144:ef7eb2e8f9f7	2110	HAL_QSPI_Abort_IT(hqspi);
<>	144:ef7eb2e8f9f7	2111	}
<>	144:ef7eb2e8f9f7	2112	}
<>	144:ef7eb2e8f9f7	2113
<>	144:ef7eb2e8f9f7	2114	/**
<>	144:ef7eb2e8f9f7	2115	* @brief DMA QSPI abort complete callback.
<>	144:ef7eb2e8f9f7	2116	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	2117	* @retval None
<>	144:ef7eb2e8f9f7	2118	*/
<>	144:ef7eb2e8f9f7	2119	static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2120	{
<>	144:ef7eb2e8f9f7	2121	QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	hqspi->RxXferCount = 0;
<>	144:ef7eb2e8f9f7	2124	hqspi->TxXferCount = 0;
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126	if(hqspi->State == HAL_QSPI_STATE_ABORT)
<>	144:ef7eb2e8f9f7	2127	{
<>	144:ef7eb2e8f9f7	2128	/* DMA Abort called by QSPI abort */
<>	144:ef7eb2e8f9f7	2129	/* Clear interrupt */
<>	144:ef7eb2e8f9f7	2130	__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
<>	144:ef7eb2e8f9f7	2131
<>	144:ef7eb2e8f9f7	2132	/* Enable the QSPI Transfer Complete Interrupt */
<>	144:ef7eb2e8f9f7	2133	__HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
<>	144:ef7eb2e8f9f7	2134
<>	144:ef7eb2e8f9f7	2135	/* Configure QSPI: CR register with Abort request */
<>	144:ef7eb2e8f9f7	2136	SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
<>	144:ef7eb2e8f9f7	2137	}
<>	144:ef7eb2e8f9f7	2138	else
<>	144:ef7eb2e8f9f7	2139	{
<>	144:ef7eb2e8f9f7	2140	/* DMA Abort called due to a transfer error interrupt */
<>	144:ef7eb2e8f9f7	2141	/* Change state of QSPI */
<>	144:ef7eb2e8f9f7	2142	hqspi->State = HAL_QSPI_STATE_READY;
<>	144:ef7eb2e8f9f7	2143
<>	144:ef7eb2e8f9f7	2144	/* Error callback */
<>	144:ef7eb2e8f9f7	2145	HAL_QSPI_ErrorCallback(hqspi);
<>	144:ef7eb2e8f9f7	2146	}
<>	144:ef7eb2e8f9f7	2147	}
<>	144:ef7eb2e8f9f7	2148
<>	144:ef7eb2e8f9f7	2149	/**
<>	144:ef7eb2e8f9f7	2150	* @brief Wait for a flag state until timeout.
<>	144:ef7eb2e8f9f7	2151	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	2152	* @param Flag: Flag checked
<>	144:ef7eb2e8f9f7	2153	* @param State: Value of the flag expected
<>	144:ef7eb2e8f9f7	2154	* @param tickstart: Start tick value
<>	144:ef7eb2e8f9f7	2155	* @param Timeout: Duration of the time out
<>	144:ef7eb2e8f9f7	2156	* @retval HAL status
<>	144:ef7eb2e8f9f7	2157	*/
<>	144:ef7eb2e8f9f7	2158	static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
<>	144:ef7eb2e8f9f7	2159	FlagStatus State, uint32_t tickstart, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2160	{
<>	144:ef7eb2e8f9f7	2161	/* Wait until flag is in expected state */
<>	144:ef7eb2e8f9f7	2162	while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
<>	144:ef7eb2e8f9f7	2163	{
<>	144:ef7eb2e8f9f7	2164	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	2165	if (Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	2166	{
<>	144:ef7eb2e8f9f7	2167	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	2168	{
<>	144:ef7eb2e8f9f7	2169	hqspi->State = HAL_QSPI_STATE_ERROR;
<>	144:ef7eb2e8f9f7	2170	hqspi->ErrorCode \|= HAL_QSPI_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	2171
<>	144:ef7eb2e8f9f7	2172	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2173	}
<>	144:ef7eb2e8f9f7	2174	}
<>	144:ef7eb2e8f9f7	2175	}
<>	144:ef7eb2e8f9f7	2176	return HAL_OK;
<>	144:ef7eb2e8f9f7	2177	}
<>	144:ef7eb2e8f9f7	2178
<>	144:ef7eb2e8f9f7	2179	/**
<>	144:ef7eb2e8f9f7	2180	* @brief Configure the communication registers.
<>	144:ef7eb2e8f9f7	2181	* @param hqspi: QSPI handle
<>	144:ef7eb2e8f9f7	2182	* @param cmd: structure that contains the command configuration information
<>	144:ef7eb2e8f9f7	2183	* @param FunctionalMode: functional mode to configured
<>	144:ef7eb2e8f9f7	2184	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2185	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
<>	144:ef7eb2e8f9f7	2186	* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
<>	144:ef7eb2e8f9f7	2187	* @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
<>	144:ef7eb2e8f9f7	2188	* @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
<>	144:ef7eb2e8f9f7	2189	* @retval None
<>	144:ef7eb2e8f9f7	2190	*/
<>	144:ef7eb2e8f9f7	2191	static void QSPI_Config(QSPI_HandleTypeDef hqspi, QSPI_CommandTypeDef cmd, uint32_t FunctionalMode)
<>	144:ef7eb2e8f9f7	2192	{
<>	144:ef7eb2e8f9f7	2193	assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
<>	144:ef7eb2e8f9f7	2194
<>	144:ef7eb2e8f9f7	2195	if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
<>	144:ef7eb2e8f9f7	2196	{
<>	144:ef7eb2e8f9f7	2197	/* Configure QSPI: DLR register with the number of data to read or write */
<>	144:ef7eb2e8f9f7	2198	WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
<>	144:ef7eb2e8f9f7	2199	}
<>	144:ef7eb2e8f9f7	2200
<>	144:ef7eb2e8f9f7	2201	if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
<>	144:ef7eb2e8f9f7	2202	{
<>	144:ef7eb2e8f9f7	2203	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	2204	{
<>	144:ef7eb2e8f9f7	2205	/* Configure QSPI: ABR register with alternate bytes value */
<>	144:ef7eb2e8f9f7	2206	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
<>	144:ef7eb2e8f9f7	2207
<>	144:ef7eb2e8f9f7	2208	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2209	{
<>	144:ef7eb2e8f9f7	2210	/---- Command with instruction, address and alternate bytes ----/
<>	144:ef7eb2e8f9f7	2211	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2212	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2213	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
<>	144:ef7eb2e8f9f7	2214	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
<>	144:ef7eb2e8f9f7	2215	cmd->InstructionMode \| cmd->Instruction \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2216
<>	144:ef7eb2e8f9f7	2217	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2218	{
<>	144:ef7eb2e8f9f7	2219	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2220	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2221	}
<>	144:ef7eb2e8f9f7	2222	}
<>	144:ef7eb2e8f9f7	2223	else
<>	144:ef7eb2e8f9f7	2224	{
<>	144:ef7eb2e8f9f7	2225	/---- Command with instruction and alternate bytes ----/
<>	144:ef7eb2e8f9f7	2226	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2227	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2228	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
<>	144:ef7eb2e8f9f7	2229	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
<>	144:ef7eb2e8f9f7	2230	cmd->Instruction \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2231	}
<>	144:ef7eb2e8f9f7	2232	}
<>	144:ef7eb2e8f9f7	2233	else
<>	144:ef7eb2e8f9f7	2234	{
<>	144:ef7eb2e8f9f7	2235	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2236	{
<>	144:ef7eb2e8f9f7	2237	/---- Command with instruction and address ----/
<>	144:ef7eb2e8f9f7	2238	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2239	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2240	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2241	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
<>	144:ef7eb2e8f9f7	2242	cmd->Instruction \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2243
<>	144:ef7eb2e8f9f7	2244	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2245	{
<>	144:ef7eb2e8f9f7	2246	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2247	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2248	}
<>	144:ef7eb2e8f9f7	2249	}
<>	144:ef7eb2e8f9f7	2250	else
<>	144:ef7eb2e8f9f7	2251	{
<>	144:ef7eb2e8f9f7	2252	/---- Command with only instruction ----/
<>	144:ef7eb2e8f9f7	2253	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2254	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2255	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2256	cmd->AddressMode \| cmd->InstructionMode \| cmd->Instruction \|
<>	144:ef7eb2e8f9f7	2257	FunctionalMode));
<>	144:ef7eb2e8f9f7	2258	}
<>	144:ef7eb2e8f9f7	2259	}
<>	144:ef7eb2e8f9f7	2260	}
<>	144:ef7eb2e8f9f7	2261	else
<>	144:ef7eb2e8f9f7	2262	{
<>	144:ef7eb2e8f9f7	2263	if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
<>	144:ef7eb2e8f9f7	2264	{
<>	144:ef7eb2e8f9f7	2265	/* Configure QSPI: ABR register with alternate bytes value */
<>	144:ef7eb2e8f9f7	2266	WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
<>	144:ef7eb2e8f9f7	2267
<>	144:ef7eb2e8f9f7	2268	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2269	{
<>	144:ef7eb2e8f9f7	2270	/---- Command with address and alternate bytes ----/
<>	144:ef7eb2e8f9f7	2271	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2272	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2273	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
<>	144:ef7eb2e8f9f7	2274	cmd->AlternateByteMode \| cmd->AddressSize \| cmd->AddressMode \|
<>	144:ef7eb2e8f9f7	2275	cmd->InstructionMode \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2276
<>	144:ef7eb2e8f9f7	2277	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2278	{
<>	144:ef7eb2e8f9f7	2279	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2280	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2281	}
<>	144:ef7eb2e8f9f7	2282	}
<>	144:ef7eb2e8f9f7	2283	else
<>	144:ef7eb2e8f9f7	2284	{
<>	144:ef7eb2e8f9f7	2285	/---- Command with only alternate bytes ----/
<>	144:ef7eb2e8f9f7	2286	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2287	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2288	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateBytesSize \|
<>	144:ef7eb2e8f9f7	2289	cmd->AlternateByteMode \| cmd->AddressMode \| cmd->InstructionMode \|
<>	144:ef7eb2e8f9f7	2290	FunctionalMode));
<>	144:ef7eb2e8f9f7	2291	}
<>	144:ef7eb2e8f9f7	2292	}
<>	144:ef7eb2e8f9f7	2293	else
<>	144:ef7eb2e8f9f7	2294	{
<>	144:ef7eb2e8f9f7	2295	if (cmd->AddressMode != QSPI_ADDRESS_NONE)
<>	144:ef7eb2e8f9f7	2296	{
<>	144:ef7eb2e8f9f7	2297	/---- Command with only address ----/
<>	144:ef7eb2e8f9f7	2298	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2299	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2300	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2301	cmd->AddressSize \| cmd->AddressMode \| cmd->InstructionMode \|
<>	144:ef7eb2e8f9f7	2302	FunctionalMode));
<>	144:ef7eb2e8f9f7	2303
<>	144:ef7eb2e8f9f7	2304	if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
<>	144:ef7eb2e8f9f7	2305	{
<>	144:ef7eb2e8f9f7	2306	/* Configure QSPI: AR register with address value */
<>	144:ef7eb2e8f9f7	2307	WRITE_REG(hqspi->Instance->AR, cmd->Address);
<>	144:ef7eb2e8f9f7	2308	}
<>	144:ef7eb2e8f9f7	2309	}
<>	144:ef7eb2e8f9f7	2310	else
<>	144:ef7eb2e8f9f7	2311	{
<>	144:ef7eb2e8f9f7	2312	/---- Command with only data phase ----/
<>	144:ef7eb2e8f9f7	2313	if (cmd->DataMode != QSPI_DATA_NONE)
<>	144:ef7eb2e8f9f7	2314	{
<>	144:ef7eb2e8f9f7	2315	/* Configure QSPI: CCR register with all communications parameters */
<>	144:ef7eb2e8f9f7	2316	WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode \| cmd->DdrHoldHalfCycle \| cmd->SIOOMode \|
<>	144:ef7eb2e8f9f7	2317	cmd->DataMode \| (cmd->DummyCycles << 18) \| cmd->AlternateByteMode \|
<>	144:ef7eb2e8f9f7	2318	cmd->AddressMode \| cmd->InstructionMode \| FunctionalMode));
<>	144:ef7eb2e8f9f7	2319	}
<>	144:ef7eb2e8f9f7	2320	}
<>	144:ef7eb2e8f9f7	2321	}
<>	144:ef7eb2e8f9f7	2322	}
<>	144:ef7eb2e8f9f7	2323	}
<>	144:ef7eb2e8f9f7	2324	/**
<>	144:ef7eb2e8f9f7	2325	* @}
<>	144:ef7eb2e8f9f7	2326	*/
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328	#endif /* HAL_QSPI_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2329	/**
<>	144:ef7eb2e8f9f7	2330	* @}
<>	144:ef7eb2e8f9f7	2331	*/
<>	144:ef7eb2e8f9f7	2332
<>	144:ef7eb2e8f9f7	2333	/**
<>	144:ef7eb2e8f9f7	2334	* @}
<>	144:ef7eb2e8f9f7	2335	*/
<>	144:ef7eb2e8f9f7	2336
<>	144:ef7eb2e8f9f7	2337	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/