mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
157:ff67d9f36b67
Child:
168:9672193075cf
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_pwr_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended PWR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of PWR extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Peripheral Extended features functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 ******************************************************************************
<> 144:ef7eb2e8f9f7 13 * @attention
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 18 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 19 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 20 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 23 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 25 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 26 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 ******************************************************************************
<> 144:ef7eb2e8f9f7 40 */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 43 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 46 * @{
<> 144:ef7eb2e8f9f7 47 */
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @defgroup PWREx PWREx
<> 144:ef7eb2e8f9f7 50 * @brief PWR HAL module driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 #ifdef HAL_PWR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 57 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @addtogroup PWREx_Private_Constants
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
<> 144:ef7eb2e8f9f7 62 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
<> 144:ef7eb2e8f9f7 63 #define PWR_BKPREG_TIMEOUT_VALUE 1000
<> 144:ef7eb2e8f9f7 64 #define PWR_VOSRDY_TIMEOUT_VALUE 1000
<> 144:ef7eb2e8f9f7 65 /**
<> 144:ef7eb2e8f9f7 66 * @}
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 70 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 71 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 72 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 73 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
<> 144:ef7eb2e8f9f7 74 * @{
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
<> 144:ef7eb2e8f9f7 78 * @brief Peripheral Extended features functions
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 @verbatim
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 ===============================================================================
<> 144:ef7eb2e8f9f7 83 ##### Peripheral extended features functions #####
<> 144:ef7eb2e8f9f7 84 ===============================================================================
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 *** Main and Backup Regulators configuration ***
<> 144:ef7eb2e8f9f7 87 ================================================
<> 144:ef7eb2e8f9f7 88 [..]
<> 144:ef7eb2e8f9f7 89 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
<> 144:ef7eb2e8f9f7 90 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
<> 144:ef7eb2e8f9f7 91 retained even in Standby or VBAT mode when the low power backup regulator
<> 144:ef7eb2e8f9f7 92 is enabled. It can be considered as an internal EEPROM when VBAT is
<> 144:ef7eb2e8f9f7 93 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
<> 144:ef7eb2e8f9f7 94 enable the low power backup regulator.
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
<> 144:ef7eb2e8f9f7 97 the backup SRAM is powered from VDD which replaces the VBAT power supply to
<> 144:ef7eb2e8f9f7 98 save battery life.
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 (+) The backup SRAM is not mass erased by a tamper event. It is read
<> 144:ef7eb2e8f9f7 101 protected to prevent confidential data, such as cryptographic private
<> 144:ef7eb2e8f9f7 102 key, from being accessed. The backup SRAM can be erased only through
<> 144:ef7eb2e8f9f7 103 the Flash interface when a protection level change from level 1 to
<> 144:ef7eb2e8f9f7 104 level 0 is requested.
<> 144:ef7eb2e8f9f7 105 -@- Refer to the description of Read protection (RDP) in the Flash
<> 144:ef7eb2e8f9f7 106 programming manual.
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 (+) The main internal regulator can be configured to have a tradeoff between
<> 144:ef7eb2e8f9f7 109 performance and power consumption when the device does not operate at
<> 144:ef7eb2e8f9f7 110 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
<> 144:ef7eb2e8f9f7 111 macro which configure VOS bit in PWR_CR register
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 Refer to the product datasheets for more details.
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 *** FLASH Power Down configuration ****
<> 144:ef7eb2e8f9f7 116 =======================================
<> 144:ef7eb2e8f9f7 117 [..]
<> 144:ef7eb2e8f9f7 118 (+) By setting the FPDS bit in the PWR_CR register by using the
<> 144:ef7eb2e8f9f7 119 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
<> 144:ef7eb2e8f9f7 120 down mode when the device enters Stop mode. When the Flash memory
<> 144:ef7eb2e8f9f7 121 is in power down mode, an additional startup delay is incurred when
<> 144:ef7eb2e8f9f7 122 waking up from Stop mode.
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 *** Over-Drive and Under-Drive configuration ****
<> 144:ef7eb2e8f9f7 125 =================================================
<> 144:ef7eb2e8f9f7 126 [..]
<> 144:ef7eb2e8f9f7 127 (+) In Run mode: the main regulator has 2 operating modes available:
<> 144:ef7eb2e8f9f7 128 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
<> 144:ef7eb2e8f9f7 129 voltage scaling (scale 1, scale 2 or scale 3)
<> 144:ef7eb2e8f9f7 130 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
<> 144:ef7eb2e8f9f7 131 higher frequency than the normal mode for a given voltage scaling (scale 1,
<> 144:ef7eb2e8f9f7 132 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
<> 144:ef7eb2e8f9f7 133 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
<> 144:ef7eb2e8f9f7 134 the sequence described in Reference manual.
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 (+) In Stop mode: the main regulator or low power regulator supplies a low power
<> 144:ef7eb2e8f9f7 137 voltage to the 1.2V domain, thus preserving the content of registers
<> 144:ef7eb2e8f9f7 138 and internal SRAM. 2 operating modes are available:
<> 144:ef7eb2e8f9f7 139 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
<> 144:ef7eb2e8f9f7 140 available when the main regulator or the low power regulator is used in Scale 3 or
<> 144:ef7eb2e8f9f7 141 low voltage mode.
<> 144:ef7eb2e8f9f7 142 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
<> 144:ef7eb2e8f9f7 143 available when the main regulator or the low power regulator is in low voltage mode.
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 @endverbatim
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @brief Enables the Backup Regulator.
<> 144:ef7eb2e8f9f7 151 * @retval HAL status
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
<> 144:ef7eb2e8f9f7 154 {
<> 144:ef7eb2e8f9f7 155 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Enable Backup regulator */
<> 144:ef7eb2e8f9f7 158 PWR->CSR1 |= PWR_CSR1_BRE;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Workaround for the following hardware bug: */
<> 144:ef7eb2e8f9f7 161 /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
<> 144:ef7eb2e8f9f7 162 PWR->CSR1 |= PWR_CSR1_EIWUP;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Get tick */
<> 144:ef7eb2e8f9f7 165 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 /* Wait till Backup regulator ready flag is set */
<> 144:ef7eb2e8f9f7 168 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
<> 144:ef7eb2e8f9f7 169 {
<> 144:ef7eb2e8f9f7 170 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175 return HAL_OK;
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @brief Disables the Backup Regulator.
<> 144:ef7eb2e8f9f7 180 * @retval HAL status
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
<> 144:ef7eb2e8f9f7 183 {
<> 144:ef7eb2e8f9f7 184 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Disable Backup regulator */
<> 144:ef7eb2e8f9f7 187 PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Workaround for the following hardware bug: */
<> 144:ef7eb2e8f9f7 190 /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
<> 144:ef7eb2e8f9f7 191 PWR->CSR1 |= PWR_CSR1_EIWUP;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Get tick */
<> 144:ef7eb2e8f9f7 194 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Wait till Backup regulator ready flag is set */
<> 144:ef7eb2e8f9f7 197 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
<> 144:ef7eb2e8f9f7 198 {
<> 144:ef7eb2e8f9f7 199 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 200 {
<> 144:ef7eb2e8f9f7 201 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 return HAL_OK;
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief Enables the Flash Power Down in Stop mode.
<> 144:ef7eb2e8f9f7 209 * @retval None
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211 void HAL_PWREx_EnableFlashPowerDown(void)
<> 144:ef7eb2e8f9f7 212 {
<> 144:ef7eb2e8f9f7 213 /* Enable the Flash Power Down */
<> 144:ef7eb2e8f9f7 214 PWR->CR1 |= PWR_CR1_FPDS;
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief Disables the Flash Power Down in Stop mode.
<> 144:ef7eb2e8f9f7 219 * @retval None
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221 void HAL_PWREx_DisableFlashPowerDown(void)
<> 144:ef7eb2e8f9f7 222 {
<> 144:ef7eb2e8f9f7 223 /* Disable the Flash Power Down */
<> 144:ef7eb2e8f9f7 224 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @brief Enables Main Regulator low voltage mode.
<> 144:ef7eb2e8f9f7 229 * @retval None
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 /* Enable Main regulator low voltage */
<> 144:ef7eb2e8f9f7 234 PWR->CR1 |= PWR_CR1_MRUDS;
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief Disables Main Regulator low voltage mode.
<> 144:ef7eb2e8f9f7 239 * @retval None
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 /* Disable Main regulator low voltage */
<> 144:ef7eb2e8f9f7 244 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @brief Enables Low Power Regulator low voltage mode.
<> 144:ef7eb2e8f9f7 249 * @retval None
<> 144:ef7eb2e8f9f7 250 */
<> 144:ef7eb2e8f9f7 251 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 /* Enable low power regulator */
<> 144:ef7eb2e8f9f7 254 PWR->CR1 |= PWR_CR1_LPUDS;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Disables Low Power Regulator low voltage mode.
<> 144:ef7eb2e8f9f7 259 * @retval None
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 /* Disable low power regulator */
<> 144:ef7eb2e8f9f7 264 PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
<> 144:ef7eb2e8f9f7 265 }
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @brief Activates the Over-Drive mode.
<> 144:ef7eb2e8f9f7 269 * @note This mode allows the CPU and the core logic to operate at a higher frequency
<> 144:ef7eb2e8f9f7 270 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
<> 144:ef7eb2e8f9f7 271 * @note It is recommended to enter or exit Over-drive mode when the application is not running
<> 144:ef7eb2e8f9f7 272 * critical tasks and when the system clock source is either HSI or HSE.
<> 144:ef7eb2e8f9f7 273 * During the Over-drive switch activation, no peripheral clocks should be enabled.
<> 144:ef7eb2e8f9f7 274 * The peripheral clocks must be enabled once the Over-drive mode is activated.
<> 144:ef7eb2e8f9f7 275 * @retval HAL status
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /* Enable the Over-drive to extend the clock frequency to 216 MHz */
<> 144:ef7eb2e8f9f7 284 __HAL_PWR_OVERDRIVE_ENABLE();
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Get tick */
<> 144:ef7eb2e8f9f7 287 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 /* Enable the Over-drive switch */
<> 144:ef7eb2e8f9f7 298 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Get tick */
<> 144:ef7eb2e8f9f7 301 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310 return HAL_OK;
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @brief Deactivates the Over-Drive mode.
<> 144:ef7eb2e8f9f7 315 * @note This mode allows the CPU and the core logic to operate at a higher frequency
<> 144:ef7eb2e8f9f7 316 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
<> 144:ef7eb2e8f9f7 317 * @note It is recommended to enter or exit Over-drive mode when the application is not running
<> 144:ef7eb2e8f9f7 318 * critical tasks and when the system clock source is either HSI or HSE.
<> 144:ef7eb2e8f9f7 319 * During the Over-drive switch activation, no peripheral clocks should be enabled.
<> 144:ef7eb2e8f9f7 320 * The peripheral clocks must be enabled once the Over-drive mode is activated.
<> 144:ef7eb2e8f9f7 321 * @retval HAL status
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Disable the Over-drive switch */
<> 144:ef7eb2e8f9f7 330 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /* Get tick */
<> 144:ef7eb2e8f9f7 333 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Disable the Over-drive */
<> 144:ef7eb2e8f9f7 344 __HAL_PWR_OVERDRIVE_DISABLE();
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Get tick */
<> 144:ef7eb2e8f9f7 347 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
<> 144:ef7eb2e8f9f7 350 {
<> 144:ef7eb2e8f9f7 351 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 return HAL_OK;
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @brief Enters in Under-Drive STOP mode.
<> 144:ef7eb2e8f9f7 362 *
<> 144:ef7eb2e8f9f7 363 * @note This mode can be selected only when the Under-Drive is already active
<> 144:ef7eb2e8f9f7 364 *
<> 144:ef7eb2e8f9f7 365 * @note This mode is enabled only with STOP low power mode.
<> 144:ef7eb2e8f9f7 366 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
<> 144:ef7eb2e8f9f7 367 * mode is only available when the main regulator or the low power regulator
<> 144:ef7eb2e8f9f7 368 * is in low voltage mode
<> 144:ef7eb2e8f9f7 369 *
<> 144:ef7eb2e8f9f7 370 * @note If the Under-drive mode was enabled, it is automatically disabled after
<> 144:ef7eb2e8f9f7 371 * exiting Stop mode.
<> 144:ef7eb2e8f9f7 372 * When the voltage regulator operates in Under-drive mode, an additional
<> 144:ef7eb2e8f9f7 373 * startup delay is induced when waking up from Stop mode.
<> 144:ef7eb2e8f9f7 374 *
<> 144:ef7eb2e8f9f7 375 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 376 *
<> 144:ef7eb2e8f9f7 377 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 378 * the HSI RC oscillator is selected as system clock.
<> 144:ef7eb2e8f9f7 379 *
<> 144:ef7eb2e8f9f7 380 * @note When the voltage regulator operates in low power mode, an additional
<> 144:ef7eb2e8f9f7 381 * startup delay is incurred when waking up from Stop mode.
<> 144:ef7eb2e8f9f7 382 * By keeping the internal regulator ON during Stop mode, the consumption
<> 144:ef7eb2e8f9f7 383 * is higher although the startup time is reduced.
<> 144:ef7eb2e8f9f7 384 *
<> 144:ef7eb2e8f9f7 385 * @param Regulator: specifies the regulator state in STOP mode.
<> 144:ef7eb2e8f9f7 386 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 387 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
<> 144:ef7eb2e8f9f7 388 * and Flash memory in power-down when the device is in Stop under-drive mode
<> 144:ef7eb2e8f9f7 389 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
<> 144:ef7eb2e8f9f7 390 * and Flash memory in power-down when the device is in Stop under-drive mode
<> 144:ef7eb2e8f9f7 391 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 392 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 393 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
<> 144:ef7eb2e8f9f7 394 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
<> 144:ef7eb2e8f9f7 395 * @retval None
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 uint32_t tempreg = 0;
<> 144:ef7eb2e8f9f7 400 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Check the parameters */
<> 144:ef7eb2e8f9f7 403 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
<> 144:ef7eb2e8f9f7 404 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 /* Enable Power ctrl clock */
<> 144:ef7eb2e8f9f7 407 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 408 /* Enable the Under-drive Mode ---------------------------------------------*/
<> 144:ef7eb2e8f9f7 409 /* Clear Under-drive flag */
<> 144:ef7eb2e8f9f7 410 __HAL_PWR_CLEAR_ODRUDR_FLAG();
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Enable the Under-drive */
<> 144:ef7eb2e8f9f7 413 __HAL_PWR_UNDERDRIVE_ENABLE();
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Get tick */
<> 144:ef7eb2e8f9f7 416 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Wait for UnderDrive mode is ready */
<> 144:ef7eb2e8f9f7 419 while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
<> 144:ef7eb2e8f9f7 420 {
<> 144:ef7eb2e8f9f7 421 if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 422 {
<> 144:ef7eb2e8f9f7 423 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Select the regulator state in STOP mode ---------------------------------*/
<> 144:ef7eb2e8f9f7 428 tempreg = PWR->CR1;
<> 144:ef7eb2e8f9f7 429 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
<> 144:ef7eb2e8f9f7 430 tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
<> 144:ef7eb2e8f9f7 433 tempreg |= Regulator;
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Store the new value */
<> 144:ef7eb2e8f9f7 436 PWR->CR1 = tempreg;
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 439 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Select STOP mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 442 if(STOPEntry == PWR_SLEEPENTRY_WFI)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 445 __WFI();
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 else
<> 144:ef7eb2e8f9f7 448 {
<> 144:ef7eb2e8f9f7 449 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 450 __WFE();
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 453 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 return HAL_OK;
<> 144:ef7eb2e8f9f7 456 }
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /**
<> 144:ef7eb2e8f9f7 459 * @brief Returns Voltage Scaling Range.
<> 144:ef7eb2e8f9f7 460 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
<> 144:ef7eb2e8f9f7 461 * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 uint32_t HAL_PWREx_GetVoltageRange(void)
<> 144:ef7eb2e8f9f7 464 {
<> 144:ef7eb2e8f9f7 465 return (PWR->CR1 & PWR_CR1_VOS);
<> 144:ef7eb2e8f9f7 466 }
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /**
<> 144:ef7eb2e8f9f7 469 * @brief Configures the main internal regulator output voltage.
<> 144:ef7eb2e8f9f7 470 * @param VoltageScaling: specifies the regulator output voltage to achieve
<> 144:ef7eb2e8f9f7 471 * a tradeoff between performance and power consumption.
<> 144:ef7eb2e8f9f7 472 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 473 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
<> 144:ef7eb2e8f9f7 474 * typical output voltage at 1.4 V,
<> 144:ef7eb2e8f9f7 475 * system frequency up to 216 MHz.
<> 144:ef7eb2e8f9f7 476 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
<> 144:ef7eb2e8f9f7 477 * typical output voltage at 1.2 V,
<> 144:ef7eb2e8f9f7 478 * system frequency up to 180 MHz.
<> 144:ef7eb2e8f9f7 479 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
<> 144:ef7eb2e8f9f7 480 * typical output voltage at 1.00 V,
<> 144:ef7eb2e8f9f7 481 * system frequency up to 151 MHz.
<> 144:ef7eb2e8f9f7 482 * @note To update the system clock frequency(SYSCLK):
<> 144:ef7eb2e8f9f7 483 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
<> 144:ef7eb2e8f9f7 484 * - Call the HAL_RCC_OscConfig() to configure the PLL.
<> 144:ef7eb2e8f9f7 485 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
<> 144:ef7eb2e8f9f7 486 * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
<> 144:ef7eb2e8f9f7 487 * @note The scale can be modified only when the HSI or HSE clock source is selected
<> 144:ef7eb2e8f9f7 488 * as system clock source, otherwise the API returns HAL_ERROR.
<> 144:ef7eb2e8f9f7 489 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
<> 144:ef7eb2e8f9f7 490 * value in the PWR_CR1 register are not taken in account.
<> 144:ef7eb2e8f9f7 491 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
<> 144:ef7eb2e8f9f7 492 * @note The new voltage scale is active only when the PLL is ON.
<> 144:ef7eb2e8f9f7 493 * @retval HAL Status
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Enable Power ctrl clock */
<> 144:ef7eb2e8f9f7 502 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 505 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 /* Disable the main PLL */
<> 144:ef7eb2e8f9f7 508 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 511 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 512 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 513 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 514 {
<> 144:ef7eb2e8f9f7 515 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Set Range */
<> 144:ef7eb2e8f9f7 522 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Enable the main PLL */
<> 144:ef7eb2e8f9f7 525 __HAL_RCC_PLL_ENABLE();
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 528 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 529 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 530 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 539 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 540 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
<> 144:ef7eb2e8f9f7 541 {
<> 144:ef7eb2e8f9f7 542 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 545 }
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547 }
<> 144:ef7eb2e8f9f7 548 else
<> 144:ef7eb2e8f9f7 549 {
<> 144:ef7eb2e8f9f7 550 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552 return HAL_OK;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /**
<> 144:ef7eb2e8f9f7 556 * @}
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /**
<> 144:ef7eb2e8f9f7 560 * @}
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 #endif /* HAL_PWR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 564 /**
<> 144:ef7eb2e8f9f7 565 * @}
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @}
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/