mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h@144:ef7eb2e8f9f7
Child:
157:ff67d9f36b67
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_ll_fmc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of FMC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_LL_FMC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_LL_FMC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FMC_LL
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup FMC_LL_Private_Macros
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
<> 144:ef7eb2e8f9f7 61 ((BANK) == FMC_NORSRAM_BANK2) || \
<> 144:ef7eb2e8f9f7 62 ((BANK) == FMC_NORSRAM_BANK3) || \
<> 144:ef7eb2e8f9f7 63 ((BANK) == FMC_NORSRAM_BANK4))
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
<> 144:ef7eb2e8f9f7 66 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
<> 144:ef7eb2e8f9f7 69 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
<> 144:ef7eb2e8f9f7 70 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
<> 144:ef7eb2e8f9f7 73 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
<> 144:ef7eb2e8f9f7 74 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
<> 144:ef7eb2e8f9f7 77 ((__MODE__) == FMC_ACCESS_MODE_B) || \
<> 144:ef7eb2e8f9f7 78 ((__MODE__) == FMC_ACCESS_MODE_C) || \
<> 144:ef7eb2e8f9f7 79 ((__MODE__) == FMC_ACCESS_MODE_D))
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
<> 144:ef7eb2e8f9f7 84 ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \
<> 144:ef7eb2e8f9f7 87 ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
<> 144:ef7eb2e8f9f7 90 ((STATE) == FMC_NAND_ECC_ENABLE))
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
<> 144:ef7eb2e8f9f7 93 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
<> 144:ef7eb2e8f9f7 94 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
<> 144:ef7eb2e8f9f7 95 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
<> 144:ef7eb2e8f9f7 96 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
<> 144:ef7eb2e8f9f7 97 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
<> 144:ef7eb2e8f9f7 100 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
<> 144:ef7eb2e8f9f7 101 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
<> 144:ef7eb2e8f9f7 104 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
<> 144:ef7eb2e8f9f7 107 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
<> 144:ef7eb2e8f9f7 108 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
<> 144:ef7eb2e8f9f7 111 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
<> 144:ef7eb2e8f9f7 114 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
<> 144:ef7eb2e8f9f7 115 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
<> 144:ef7eb2e8f9f7 118 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
<> 144:ef7eb2e8f9f7 119 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
<> 144:ef7eb2e8f9f7 120 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
<> 144:ef7eb2e8f9f7 121 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
<> 144:ef7eb2e8f9f7 122 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
<> 144:ef7eb2e8f9f7 123 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
<> 144:ef7eb2e8f9f7 126 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
<> 144:ef7eb2e8f9f7 127 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
<> 144:ef7eb2e8f9f7 133 /**
<> 144:ef7eb2e8f9f7 134 * @}
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
<> 144:ef7eb2e8f9f7 138 * @{
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @defgroup FMC_Setup_Time FMC Setup Time
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
<> 144:ef7eb2e8f9f7 149 /**
<> 144:ef7eb2e8f9f7 150 * @}
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
<> 144:ef7eb2e8f9f7 154 * @{
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
<> 144:ef7eb2e8f9f7 165 /**
<> 144:ef7eb2e8f9f7 166 * @}
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
<> 144:ef7eb2e8f9f7 173 /**
<> 144:ef7eb2e8f9f7 174 * @}
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 178 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 181 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
<> 144:ef7eb2e8f9f7 184 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
<> 144:ef7eb2e8f9f7 187 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
<> 144:ef7eb2e8f9f7 190 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 193 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
<> 144:ef7eb2e8f9f7 196 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @defgroup FMC_Data_Latency FMC Data Latency
<> 144:ef7eb2e8f9f7 199 * @{
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @}
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
<> 144:ef7eb2e8f9f7 207 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
<> 144:ef7eb2e8f9f7 210 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
<> 144:ef7eb2e8f9f7 225 /**
<> 144:ef7eb2e8f9f7 226 * @}
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
<> 144:ef7eb2e8f9f7 230 * @{
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
<> 144:ef7eb2e8f9f7 233 /**
<> 144:ef7eb2e8f9f7 234 * @}
<> 144:ef7eb2e8f9f7 235 */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
<> 144:ef7eb2e8f9f7 238 * @{
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /** @defgroup FMC_CLK_Division FMC CLK Division
<> 144:ef7eb2e8f9f7 246 * @{
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
<> 144:ef7eb2e8f9f7 254 * @{
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @}
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
<> 144:ef7eb2e8f9f7 262 * @{
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @}
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
<> 144:ef7eb2e8f9f7 270 * @{
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @}
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
<> 144:ef7eb2e8f9f7 278 * @{
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
<> 144:ef7eb2e8f9f7 289 /**
<> 144:ef7eb2e8f9f7 290 * @}
<> 144:ef7eb2e8f9f7 291 */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
<> 144:ef7eb2e8f9f7 297 /**
<> 144:ef7eb2e8f9f7 298 * @}
<> 144:ef7eb2e8f9f7 299 */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
<> 144:ef7eb2e8f9f7 302 * @{
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @}
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
<> 144:ef7eb2e8f9f7 310 * @{
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @}
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
<> 144:ef7eb2e8f9f7 318 * @{
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
<> 144:ef7eb2e8f9f7 321 /**
<> 144:ef7eb2e8f9f7 322 * @}
<> 144:ef7eb2e8f9f7 323 */
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
<> 144:ef7eb2e8f9f7 326 * @{
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
<> 144:ef7eb2e8f9f7 329 /**
<> 144:ef7eb2e8f9f7 330 * @}
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
<> 144:ef7eb2e8f9f7 334 * @{
<> 144:ef7eb2e8f9f7 335 */
<> 144:ef7eb2e8f9f7 336 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @}
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
<> 144:ef7eb2e8f9f7 342 * @{
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
<> 144:ef7eb2e8f9f7 350 * @{
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
<> 144:ef7eb2e8f9f7 358 * @{
<> 144:ef7eb2e8f9f7 359 */
<> 144:ef7eb2e8f9f7 360 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
<> 144:ef7eb2e8f9f7 366 ((BANK) == FMC_SDRAM_BANK2))
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
<> 144:ef7eb2e8f9f7 369 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
<> 144:ef7eb2e8f9f7 370 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
<> 144:ef7eb2e8f9f7 371 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
<> 144:ef7eb2e8f9f7 374 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
<> 144:ef7eb2e8f9f7 375 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
<> 144:ef7eb2e8f9f7 378 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
<> 144:ef7eb2e8f9f7 382 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
<> 144:ef7eb2e8f9f7 383 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
<> 144:ef7eb2e8f9f7 386 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
<> 144:ef7eb2e8f9f7 387 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
<> 144:ef7eb2e8f9f7 388 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
<> 144:ef7eb2e8f9f7 389 ((__SIZE__) == FMC_PAGE_SIZE_1024))
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
<> 144:ef7eb2e8f9f7 392 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Exported typedef ----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 398 /** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
<> 144:ef7eb2e8f9f7 399 * @{
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
<> 144:ef7eb2e8f9f7 402 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
<> 144:ef7eb2e8f9f7 403 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
<> 144:ef7eb2e8f9f7 404 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 #define FMC_NORSRAM_DEVICE FMC_Bank1
<> 144:ef7eb2e8f9f7 407 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
<> 144:ef7eb2e8f9f7 408 #define FMC_NAND_DEVICE FMC_Bank3
<> 144:ef7eb2e8f9f7 409 #define FMC_SDRAM_DEVICE FMC_Bank5_6
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief FMC NORSRAM Configuration Structure definition
<> 144:ef7eb2e8f9f7 413 */
<> 144:ef7eb2e8f9f7 414 typedef struct
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
<> 144:ef7eb2e8f9f7 417 This parameter can be a value of @ref FMC_NORSRAM_Bank */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
<> 144:ef7eb2e8f9f7 420 multiplexed on the data bus or not.
<> 144:ef7eb2e8f9f7 421 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
<> 144:ef7eb2e8f9f7 424 the corresponding memory device.
<> 144:ef7eb2e8f9f7 425 This parameter can be a value of @ref FMC_Memory_Type */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
<> 144:ef7eb2e8f9f7 428 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
<> 144:ef7eb2e8f9f7 431 valid only with synchronous burst Flash memories.
<> 144:ef7eb2e8f9f7 432 This parameter can be a value of @ref FMC_Burst_Access_Mode */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
<> 144:ef7eb2e8f9f7 435 the Flash memory in burst mode.
<> 144:ef7eb2e8f9f7 436 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
<> 144:ef7eb2e8f9f7 439 clock cycle before the wait state or during the wait state,
<> 144:ef7eb2e8f9f7 440 valid only when accessing memories in burst mode.
<> 144:ef7eb2e8f9f7 441 This parameter can be a value of @ref FMC_Wait_Timing */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
<> 144:ef7eb2e8f9f7 444 This parameter can be a value of @ref FMC_Write_Operation */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
<> 144:ef7eb2e8f9f7 447 signal, valid for Flash memory access in burst mode.
<> 144:ef7eb2e8f9f7 448 This parameter can be a value of @ref FMC_Wait_Signal */
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
<> 144:ef7eb2e8f9f7 451 This parameter can be a value of @ref FMC_Extended_Mode */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
<> 144:ef7eb2e8f9f7 454 valid only with asynchronous Flash memories.
<> 144:ef7eb2e8f9f7 455 This parameter can be a value of @ref FMC_AsynchronousWait */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
<> 144:ef7eb2e8f9f7 458 This parameter can be a value of @ref FMC_Write_Burst */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
<> 144:ef7eb2e8f9f7 461 This parameter is only enabled through the FMC_BCR1 register, and don't care
<> 144:ef7eb2e8f9f7 462 through FMC_BCR2..4 registers.
<> 144:ef7eb2e8f9f7 463 This parameter can be a value of @ref FMC_Continous_Clock */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
<> 144:ef7eb2e8f9f7 466 This parameter is only enabled through the FMC_BCR1 register, and don't care
<> 144:ef7eb2e8f9f7 467 through FMC_BCR2..4 registers.
<> 144:ef7eb2e8f9f7 468 This parameter can be a value of @ref FMC_Write_FIFO */
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 uint32_t PageSize; /*!< Specifies the memory page size.
<> 144:ef7eb2e8f9f7 471 This parameter can be a value of @ref FMC_Page_Size */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 }FMC_NORSRAM_InitTypeDef;
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /**
<> 144:ef7eb2e8f9f7 476 * @brief FMC NORSRAM Timing parameters structure definition
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 typedef struct
<> 144:ef7eb2e8f9f7 479 {
<> 144:ef7eb2e8f9f7 480 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 481 the duration of the address setup time.
<> 144:ef7eb2e8f9f7 482 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 483 @note This parameter is not used with synchronous NOR Flash memories. */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 486 the duration of the address hold time.
<> 144:ef7eb2e8f9f7 487 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 488 @note This parameter is not used with synchronous NOR Flash memories. */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 491 the duration of the data setup time.
<> 144:ef7eb2e8f9f7 492 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
<> 144:ef7eb2e8f9f7 493 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
<> 144:ef7eb2e8f9f7 494 NOR Flash memories. */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
<> 144:ef7eb2e8f9f7 497 the duration of the bus turnaround.
<> 144:ef7eb2e8f9f7 498 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
<> 144:ef7eb2e8f9f7 499 @note This parameter is only used for multiplexed NOR Flash memories. */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
<> 144:ef7eb2e8f9f7 502 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
<> 144:ef7eb2e8f9f7 503 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
<> 144:ef7eb2e8f9f7 504 accesses. */
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
<> 144:ef7eb2e8f9f7 507 to the memory before getting the first data.
<> 144:ef7eb2e8f9f7 508 The parameter value depends on the memory type as shown below:
<> 144:ef7eb2e8f9f7 509 - It must be set to 0 in case of a CRAM
<> 144:ef7eb2e8f9f7 510 - It is don't care in asynchronous NOR, SRAM or ROM accesses
<> 144:ef7eb2e8f9f7 511 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
<> 144:ef7eb2e8f9f7 512 with synchronous burst mode enable */
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
<> 144:ef7eb2e8f9f7 515 This parameter can be a value of @ref FMC_Access_Mode */
<> 144:ef7eb2e8f9f7 516 }FMC_NORSRAM_TimingTypeDef;
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @brief FMC NAND Configuration Structure definition
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 typedef struct
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
<> 144:ef7eb2e8f9f7 524 This parameter can be a value of @ref FMC_NAND_Bank */
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
<> 144:ef7eb2e8f9f7 527 This parameter can be any value of @ref FMC_Wait_feature */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
<> 144:ef7eb2e8f9f7 530 This parameter can be any value of @ref FMC_NAND_Data_Width */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
<> 144:ef7eb2e8f9f7 533 This parameter can be any value of @ref FMC_ECC */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
<> 144:ef7eb2e8f9f7 536 This parameter can be any value of @ref FMC_ECC_Page_Size */
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 539 delay between CLE low and RE low.
<> 144:ef7eb2e8f9f7 540 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
<> 144:ef7eb2e8f9f7 543 delay between ALE low and RE low.
<> 144:ef7eb2e8f9f7 544 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 545 }FMC_NAND_InitTypeDef;
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @brief FMC NAND Timing parameters structure definition
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 typedef struct
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
<> 144:ef7eb2e8f9f7 553 the command assertion for NAND-Flash read or write access
<> 144:ef7eb2e8f9f7 554 to common/Attribute or I/O memory space (depending on
<> 144:ef7eb2e8f9f7 555 the memory space timing to be configured).
<> 144:ef7eb2e8f9f7 556 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
<> 144:ef7eb2e8f9f7 559 command for NAND-Flash read or write access to
<> 144:ef7eb2e8f9f7 560 common/Attribute or I/O memory space (depending on the
<> 144:ef7eb2e8f9f7 561 memory space timing to be configured).
<> 144:ef7eb2e8f9f7 562 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
<> 144:ef7eb2e8f9f7 565 (and data for write access) after the command de-assertion
<> 144:ef7eb2e8f9f7 566 for NAND-Flash read or write access to common/Attribute
<> 144:ef7eb2e8f9f7 567 or I/O memory space (depending on the memory space timing
<> 144:ef7eb2e8f9f7 568 to be configured).
<> 144:ef7eb2e8f9f7 569 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
<> 144:ef7eb2e8f9f7 572 data bus is kept in HiZ after the start of a NAND-Flash
<> 144:ef7eb2e8f9f7 573 write access to common/Attribute or I/O memory space (depending
<> 144:ef7eb2e8f9f7 574 on the memory space timing to be configured).
<> 144:ef7eb2e8f9f7 575 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
<> 144:ef7eb2e8f9f7 576 }FMC_NAND_PCC_TimingTypeDef;
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /**
<> 144:ef7eb2e8f9f7 579 * @brief FMC SDRAM Configuration Structure definition
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581 typedef struct
<> 144:ef7eb2e8f9f7 582 {
<> 144:ef7eb2e8f9f7 583 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
<> 144:ef7eb2e8f9f7 584 This parameter can be a value of @ref FMC_SDRAM_Bank */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
<> 144:ef7eb2e8f9f7 587 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
<> 144:ef7eb2e8f9f7 590 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
<> 144:ef7eb2e8f9f7 593 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
<> 144:ef7eb2e8f9f7 596 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
<> 144:ef7eb2e8f9f7 599 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
<> 144:ef7eb2e8f9f7 602 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
<> 144:ef7eb2e8f9f7 605 to disable the clock before changing frequency.
<> 144:ef7eb2e8f9f7 606 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
<> 144:ef7eb2e8f9f7 609 commands during the CAS latency and stores data in the Read FIFO.
<> 144:ef7eb2e8f9f7 610 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
<> 144:ef7eb2e8f9f7 613 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
<> 144:ef7eb2e8f9f7 614 }FMC_SDRAM_InitTypeDef;
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /**
<> 144:ef7eb2e8f9f7 617 * @brief FMC SDRAM Timing parameters structure definition
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619 typedef struct
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
<> 144:ef7eb2e8f9f7 622 an active or Refresh command in number of memory clock cycles.
<> 144:ef7eb2e8f9f7 623 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
<> 144:ef7eb2e8f9f7 626 issuing the Activate command in number of memory clock cycles.
<> 144:ef7eb2e8f9f7 627 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
<> 144:ef7eb2e8f9f7 630 cycles.
<> 144:ef7eb2e8f9f7 631 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
<> 144:ef7eb2e8f9f7 634 and the delay between two consecutive Refresh commands in number of
<> 144:ef7eb2e8f9f7 635 memory clock cycles.
<> 144:ef7eb2e8f9f7 636 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
<> 144:ef7eb2e8f9f7 639 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
<> 144:ef7eb2e8f9f7 642 in number of memory clock cycles.
<> 144:ef7eb2e8f9f7 643 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
<> 144:ef7eb2e8f9f7 646 command in number of memory clock cycles.
<> 144:ef7eb2e8f9f7 647 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 648 }FMC_SDRAM_TimingTypeDef;
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /**
<> 144:ef7eb2e8f9f7 651 * @brief SDRAM command parameters structure definition
<> 144:ef7eb2e8f9f7 652 */
<> 144:ef7eb2e8f9f7 653 typedef struct
<> 144:ef7eb2e8f9f7 654 {
<> 144:ef7eb2e8f9f7 655 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
<> 144:ef7eb2e8f9f7 656 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
<> 144:ef7eb2e8f9f7 659 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
<> 144:ef7eb2e8f9f7 662 in auto refresh mode.
<> 144:ef7eb2e8f9f7 663 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
<> 144:ef7eb2e8f9f7 664 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
<> 144:ef7eb2e8f9f7 665 }FMC_SDRAM_CommandTypeDef;
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @}
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 671 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
<> 144:ef7eb2e8f9f7 672 * @{
<> 144:ef7eb2e8f9f7 673 */
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
<> 144:ef7eb2e8f9f7 676 * @{
<> 144:ef7eb2e8f9f7 677 */
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
<> 144:ef7eb2e8f9f7 680 * @{
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 683 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 684 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 685 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
<> 144:ef7eb2e8f9f7 686 /**
<> 144:ef7eb2e8f9f7 687 * @}
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
<> 144:ef7eb2e8f9f7 691 * @{
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 694 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @}
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /** @defgroup FMC_Memory_Type FMC Memory Type
<> 144:ef7eb2e8f9f7 700 * @{
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 703 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 704 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 705 /**
<> 144:ef7eb2e8f9f7 706 * @}
<> 144:ef7eb2e8f9f7 707 */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
<> 144:ef7eb2e8f9f7 710 * @{
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 713 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 714 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 715 /**
<> 144:ef7eb2e8f9f7 716 * @}
<> 144:ef7eb2e8f9f7 717 */
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
<> 144:ef7eb2e8f9f7 720 * @{
<> 144:ef7eb2e8f9f7 721 */
<> 144:ef7eb2e8f9f7 722 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 723 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @}
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
<> 144:ef7eb2e8f9f7 729 * @{
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 732 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 733 /**
<> 144:ef7eb2e8f9f7 734 * @}
<> 144:ef7eb2e8f9f7 735 */
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
<> 144:ef7eb2e8f9f7 738 * @{
<> 144:ef7eb2e8f9f7 739 */
<> 144:ef7eb2e8f9f7 740 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 741 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 742 /**
<> 144:ef7eb2e8f9f7 743 * @}
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /** @defgroup FMC_Wait_Timing FMC Wait Timing
<> 144:ef7eb2e8f9f7 747 * @{
<> 144:ef7eb2e8f9f7 748 */
<> 144:ef7eb2e8f9f7 749 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 750 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 751 /**
<> 144:ef7eb2e8f9f7 752 * @}
<> 144:ef7eb2e8f9f7 753 */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /** @defgroup FMC_Write_Operation FMC Write Operation
<> 144:ef7eb2e8f9f7 756 * @{
<> 144:ef7eb2e8f9f7 757 */
<> 144:ef7eb2e8f9f7 758 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 759 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 760 /**
<> 144:ef7eb2e8f9f7 761 * @}
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /** @defgroup FMC_Wait_Signal FMC Wait Signal
<> 144:ef7eb2e8f9f7 765 * @{
<> 144:ef7eb2e8f9f7 766 */
<> 144:ef7eb2e8f9f7 767 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 768 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @}
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /** @defgroup FMC_Extended_Mode FMC Extended Mode
<> 144:ef7eb2e8f9f7 774 * @{
<> 144:ef7eb2e8f9f7 775 */
<> 144:ef7eb2e8f9f7 776 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 777 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 778 /**
<> 144:ef7eb2e8f9f7 779 * @}
<> 144:ef7eb2e8f9f7 780 */
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
<> 144:ef7eb2e8f9f7 783 * @{
<> 144:ef7eb2e8f9f7 784 */
<> 144:ef7eb2e8f9f7 785 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 786 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @}
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /** @defgroup FMC_Page_Size FMC Page Size
<> 144:ef7eb2e8f9f7 792 * @{
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 795 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
<> 144:ef7eb2e8f9f7 796 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
<> 144:ef7eb2e8f9f7 797 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
<> 144:ef7eb2e8f9f7 798 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
<> 144:ef7eb2e8f9f7 799 /**
<> 144:ef7eb2e8f9f7 800 * @}
<> 144:ef7eb2e8f9f7 801 */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /** @defgroup FMC_Write_Burst FMC Write Burst
<> 144:ef7eb2e8f9f7 804 * @{
<> 144:ef7eb2e8f9f7 805 */
<> 144:ef7eb2e8f9f7 806 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 807 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 808 /**
<> 144:ef7eb2e8f9f7 809 * @}
<> 144:ef7eb2e8f9f7 810 */
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
<> 144:ef7eb2e8f9f7 813 * @{
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 816 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
<> 144:ef7eb2e8f9f7 817 /**
<> 144:ef7eb2e8f9f7 818 * @}
<> 144:ef7eb2e8f9f7 819 */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /** @defgroup FMC_Write_FIFO FMC Write FIFO
<> 144:ef7eb2e8f9f7 822 * @{
<> 144:ef7eb2e8f9f7 823 */
<> 144:ef7eb2e8f9f7 824 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
<> 144:ef7eb2e8f9f7 825 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 826 /**
<> 144:ef7eb2e8f9f7 827 * @}
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 /** @defgroup FMC_Access_Mode FMC Access Mode
<> 144:ef7eb2e8f9f7 831 * @{
<> 144:ef7eb2e8f9f7 832 */
<> 144:ef7eb2e8f9f7 833 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 834 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
<> 144:ef7eb2e8f9f7 835 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
<> 144:ef7eb2e8f9f7 836 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
<> 144:ef7eb2e8f9f7 837 /**
<> 144:ef7eb2e8f9f7 838 * @}
<> 144:ef7eb2e8f9f7 839 */
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /**
<> 144:ef7eb2e8f9f7 842 * @}
<> 144:ef7eb2e8f9f7 843 */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
<> 144:ef7eb2e8f9f7 846 * @{
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 /** @defgroup FMC_NAND_Bank FMC NAND Bank
<> 144:ef7eb2e8f9f7 849 * @{
<> 144:ef7eb2e8f9f7 850 */
<> 144:ef7eb2e8f9f7 851 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 852 /**
<> 144:ef7eb2e8f9f7 853 * @}
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /** @defgroup FMC_Wait_feature FMC Wait feature
<> 144:ef7eb2e8f9f7 857 * @{
<> 144:ef7eb2e8f9f7 858 */
<> 144:ef7eb2e8f9f7 859 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 860 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 861 /**
<> 144:ef7eb2e8f9f7 862 * @}
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
<> 144:ef7eb2e8f9f7 866 * @{
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @}
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
<> 144:ef7eb2e8f9f7 874 * @{
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 877 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @}
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /** @defgroup FMC_ECC FMC ECC
<> 144:ef7eb2e8f9f7 883 * @{
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 886 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 887 /**
<> 144:ef7eb2e8f9f7 888 * @}
<> 144:ef7eb2e8f9f7 889 */
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
<> 144:ef7eb2e8f9f7 892 * @{
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 895 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 896 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
<> 144:ef7eb2e8f9f7 897 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
<> 144:ef7eb2e8f9f7 898 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
<> 144:ef7eb2e8f9f7 899 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
<> 144:ef7eb2e8f9f7 900 /**
<> 144:ef7eb2e8f9f7 901 * @}
<> 144:ef7eb2e8f9f7 902 */
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /**
<> 144:ef7eb2e8f9f7 905 * @}
<> 144:ef7eb2e8f9f7 906 */
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
<> 144:ef7eb2e8f9f7 909 * @{
<> 144:ef7eb2e8f9f7 910 */
<> 144:ef7eb2e8f9f7 911 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
<> 144:ef7eb2e8f9f7 912 * @{
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 915 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 916 /**
<> 144:ef7eb2e8f9f7 917 * @}
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
<> 144:ef7eb2e8f9f7 921 * @{
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 924 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 925 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 926 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @}
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
<> 144:ef7eb2e8f9f7 932 * @{
<> 144:ef7eb2e8f9f7 933 */
<> 144:ef7eb2e8f9f7 934 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 935 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 936 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @}
<> 144:ef7eb2e8f9f7 939 */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
<> 144:ef7eb2e8f9f7 942 * @{
<> 144:ef7eb2e8f9f7 943 */
<> 144:ef7eb2e8f9f7 944 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 945 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 946 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 947 /**
<> 144:ef7eb2e8f9f7 948 * @}
<> 144:ef7eb2e8f9f7 949 */
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
<> 144:ef7eb2e8f9f7 952 * @{
<> 144:ef7eb2e8f9f7 953 */
<> 144:ef7eb2e8f9f7 954 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 955 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 956 /**
<> 144:ef7eb2e8f9f7 957 * @}
<> 144:ef7eb2e8f9f7 958 */
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
<> 144:ef7eb2e8f9f7 961 * @{
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
<> 144:ef7eb2e8f9f7 964 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
<> 144:ef7eb2e8f9f7 965 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
<> 144:ef7eb2e8f9f7 966 /**
<> 144:ef7eb2e8f9f7 967 * @}
<> 144:ef7eb2e8f9f7 968 */
<> 144:ef7eb2e8f9f7 969
<> 144:ef7eb2e8f9f7 970 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
<> 144:ef7eb2e8f9f7 971 * @{
<> 144:ef7eb2e8f9f7 972 */
<> 144:ef7eb2e8f9f7 973 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 974 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
<> 144:ef7eb2e8f9f7 975 /**
<> 144:ef7eb2e8f9f7 976 * @}
<> 144:ef7eb2e8f9f7 977 */
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
<> 144:ef7eb2e8f9f7 980 * @{
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 983 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
<> 144:ef7eb2e8f9f7 984 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
<> 144:ef7eb2e8f9f7 985 /**
<> 144:ef7eb2e8f9f7 986 * @}
<> 144:ef7eb2e8f9f7 987 */
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
<> 144:ef7eb2e8f9f7 990 * @{
<> 144:ef7eb2e8f9f7 991 */
<> 144:ef7eb2e8f9f7 992 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 993 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
<> 144:ef7eb2e8f9f7 994 /**
<> 144:ef7eb2e8f9f7 995 * @}
<> 144:ef7eb2e8f9f7 996 */
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
<> 144:ef7eb2e8f9f7 999 * @{
<> 144:ef7eb2e8f9f7 1000 */
<> 144:ef7eb2e8f9f7 1001 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1002 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
<> 144:ef7eb2e8f9f7 1003 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 1004 /**
<> 144:ef7eb2e8f9f7 1005 * @}
<> 144:ef7eb2e8f9f7 1006 */
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
<> 144:ef7eb2e8f9f7 1009 * @{
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1012 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 1013 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 1014 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
<> 144:ef7eb2e8f9f7 1015 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 1016 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
<> 144:ef7eb2e8f9f7 1017 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
<> 144:ef7eb2e8f9f7 1018 /**
<> 144:ef7eb2e8f9f7 1019 * @}
<> 144:ef7eb2e8f9f7 1020 */
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
<> 144:ef7eb2e8f9f7 1023 * @{
<> 144:ef7eb2e8f9f7 1024 */
<> 144:ef7eb2e8f9f7 1025 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
<> 144:ef7eb2e8f9f7 1026 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
<> 144:ef7eb2e8f9f7 1027 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
<> 144:ef7eb2e8f9f7 1028 /**
<> 144:ef7eb2e8f9f7 1029 * @}
<> 144:ef7eb2e8f9f7 1030 */
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
<> 144:ef7eb2e8f9f7 1033 * @{
<> 144:ef7eb2e8f9f7 1034 */
<> 144:ef7eb2e8f9f7 1035 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
<> 144:ef7eb2e8f9f7 1036 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
<> 144:ef7eb2e8f9f7 1037 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
<> 144:ef7eb2e8f9f7 1038 /**
<> 144:ef7eb2e8f9f7 1039 * @}
<> 144:ef7eb2e8f9f7 1040 */
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 /**
<> 144:ef7eb2e8f9f7 1043 * @}
<> 144:ef7eb2e8f9f7 1044 */
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
<> 144:ef7eb2e8f9f7 1047 * @{
<> 144:ef7eb2e8f9f7 1048 */
<> 144:ef7eb2e8f9f7 1049 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
<> 144:ef7eb2e8f9f7 1050 #define FMC_IT_LEVEL ((uint32_t)0x00000010U)
<> 144:ef7eb2e8f9f7 1051 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
<> 144:ef7eb2e8f9f7 1052 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
<> 144:ef7eb2e8f9f7 1053 /**
<> 144:ef7eb2e8f9f7 1054 * @}
<> 144:ef7eb2e8f9f7 1055 */
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
<> 144:ef7eb2e8f9f7 1058 * @{
<> 144:ef7eb2e8f9f7 1059 */
<> 144:ef7eb2e8f9f7 1060 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 1061 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 1062 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
<> 144:ef7eb2e8f9f7 1063 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
<> 144:ef7eb2e8f9f7 1064 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
<> 144:ef7eb2e8f9f7 1065 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
<> 144:ef7eb2e8f9f7 1066 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
<> 144:ef7eb2e8f9f7 1067 /**
<> 144:ef7eb2e8f9f7 1068 * @}
<> 144:ef7eb2e8f9f7 1069 */
<> 144:ef7eb2e8f9f7 1070 /**
<> 144:ef7eb2e8f9f7 1071 * @}
<> 144:ef7eb2e8f9f7 1072 */
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 /**
<> 144:ef7eb2e8f9f7 1075 * @}
<> 144:ef7eb2e8f9f7 1076 */
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1079 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
<> 144:ef7eb2e8f9f7 1080 * @{
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
<> 144:ef7eb2e8f9f7 1084 * @brief macros to handle NOR device enable/disable and read/write operations
<> 144:ef7eb2e8f9f7 1085 * @{
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /**
<> 144:ef7eb2e8f9f7 1089 * @brief Enable the NORSRAM device access.
<> 144:ef7eb2e8f9f7 1090 * @param __INSTANCE__: FMC_NORSRAM Instance
<> 144:ef7eb2e8f9f7 1091 * @param __BANK__: FMC_NORSRAM Bank
<> 144:ef7eb2e8f9f7 1092 * @retval None
<> 144:ef7eb2e8f9f7 1093 */
<> 144:ef7eb2e8f9f7 1094 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /**
<> 144:ef7eb2e8f9f7 1097 * @brief Disable the NORSRAM device access.
<> 144:ef7eb2e8f9f7 1098 * @param __INSTANCE__: FMC_NORSRAM Instance
<> 144:ef7eb2e8f9f7 1099 * @param __BANK__: FMC_NORSRAM Bank
<> 144:ef7eb2e8f9f7 1100 * @retval None
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /**
<> 144:ef7eb2e8f9f7 1105 * @}
<> 144:ef7eb2e8f9f7 1106 */
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
<> 144:ef7eb2e8f9f7 1109 * @brief macros to handle NAND device enable/disable
<> 144:ef7eb2e8f9f7 1110 * @{
<> 144:ef7eb2e8f9f7 1111 */
<> 144:ef7eb2e8f9f7 1112
<> 144:ef7eb2e8f9f7 1113 /**
<> 144:ef7eb2e8f9f7 1114 * @brief Enable the NAND device access.
<> 144:ef7eb2e8f9f7 1115 * @param __INSTANCE__: FMC_NAND Instance
<> 144:ef7eb2e8f9f7 1116 * @retval None
<> 144:ef7eb2e8f9f7 1117 */
<> 144:ef7eb2e8f9f7 1118 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @brief Disable the NAND device access.
<> 144:ef7eb2e8f9f7 1122 * @param __INSTANCE__: FMC_NAND Instance
<> 144:ef7eb2e8f9f7 1123 * @retval None
<> 144:ef7eb2e8f9f7 1124 */
<> 144:ef7eb2e8f9f7 1125 #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /**
<> 144:ef7eb2e8f9f7 1128 * @}
<> 144:ef7eb2e8f9f7 1129 */
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /** @defgroup FMC_Interrupt FMC Interrupt
<> 144:ef7eb2e8f9f7 1132 * @brief macros to handle FMC interrupts
<> 144:ef7eb2e8f9f7 1133 * @{
<> 144:ef7eb2e8f9f7 1134 */
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /**
<> 144:ef7eb2e8f9f7 1137 * @brief Enable the NAND device interrupt.
<> 144:ef7eb2e8f9f7 1138 * @param __INSTANCE__: FMC_NAND instance
<> 144:ef7eb2e8f9f7 1139 * @param __INTERRUPT__: FMC_NAND interrupt
<> 144:ef7eb2e8f9f7 1140 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1141 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 1142 * @arg FMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 1143 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 1144 * @retval None
<> 144:ef7eb2e8f9f7 1145 */
<> 144:ef7eb2e8f9f7 1146 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1147
<> 144:ef7eb2e8f9f7 1148 /**
<> 144:ef7eb2e8f9f7 1149 * @brief Disable the NAND device interrupt.
<> 144:ef7eb2e8f9f7 1150 * @param __INSTANCE__: FMC_NAND Instance
<> 144:ef7eb2e8f9f7 1151 * @param __INTERRUPT__: FMC_NAND interrupt
<> 144:ef7eb2e8f9f7 1152 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1153 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
<> 144:ef7eb2e8f9f7 1154 * @arg FMC_IT_LEVEL: Interrupt level.
<> 144:ef7eb2e8f9f7 1155 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
<> 144:ef7eb2e8f9f7 1156 * @retval None
<> 144:ef7eb2e8f9f7 1157 */
<> 144:ef7eb2e8f9f7 1158 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 /**
<> 144:ef7eb2e8f9f7 1161 * @brief Get flag status of the NAND device.
<> 144:ef7eb2e8f9f7 1162 * @param __INSTANCE__: FMC_NAND Instance
<> 144:ef7eb2e8f9f7 1163 * @param __BANK__: FMC_NAND Bank
<> 144:ef7eb2e8f9f7 1164 * @param __FLAG__: FMC_NAND flag
<> 144:ef7eb2e8f9f7 1165 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1166 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 1167 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 1168 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 1169 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 1170 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1171 */
<> 144:ef7eb2e8f9f7 1172 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /**
<> 144:ef7eb2e8f9f7 1175 * @brief Clear flag status of the NAND device.
<> 144:ef7eb2e8f9f7 1176 * @param __INSTANCE__: FMC_NAND Instance
<> 144:ef7eb2e8f9f7 1177 * @param __FLAG__: FMC_NAND flag
<> 144:ef7eb2e8f9f7 1178 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1179 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
<> 144:ef7eb2e8f9f7 1180 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
<> 144:ef7eb2e8f9f7 1181 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
<> 144:ef7eb2e8f9f7 1182 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
<> 144:ef7eb2e8f9f7 1183 * @retval None
<> 144:ef7eb2e8f9f7 1184 */
<> 144:ef7eb2e8f9f7 1185 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /**
<> 144:ef7eb2e8f9f7 1188 * @brief Enable the SDRAM device interrupt.
<> 144:ef7eb2e8f9f7 1189 * @param __INSTANCE__: FMC_SDRAM instance
<> 144:ef7eb2e8f9f7 1190 * @param __INTERRUPT__: FMC_SDRAM interrupt
<> 144:ef7eb2e8f9f7 1191 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1192 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
<> 144:ef7eb2e8f9f7 1193 * @retval None
<> 144:ef7eb2e8f9f7 1194 */
<> 144:ef7eb2e8f9f7 1195 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /**
<> 144:ef7eb2e8f9f7 1198 * @brief Disable the SDRAM device interrupt.
<> 144:ef7eb2e8f9f7 1199 * @param __INSTANCE__: FMC_SDRAM instance
<> 144:ef7eb2e8f9f7 1200 * @param __INTERRUPT__: FMC_SDRAM interrupt
<> 144:ef7eb2e8f9f7 1201 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1202 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
<> 144:ef7eb2e8f9f7 1203 * @retval None
<> 144:ef7eb2e8f9f7 1204 */
<> 144:ef7eb2e8f9f7 1205 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /**
<> 144:ef7eb2e8f9f7 1208 * @brief Get flag status of the SDRAM device.
<> 144:ef7eb2e8f9f7 1209 * @param __INSTANCE__: FMC_SDRAM instance
<> 144:ef7eb2e8f9f7 1210 * @param __FLAG__: FMC_SDRAM flag
<> 144:ef7eb2e8f9f7 1211 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1212 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
<> 144:ef7eb2e8f9f7 1213 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
<> 144:ef7eb2e8f9f7 1214 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
<> 144:ef7eb2e8f9f7 1215 * @retval The state of FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1216 */
<> 144:ef7eb2e8f9f7 1217 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /**
<> 144:ef7eb2e8f9f7 1220 * @brief Clear flag status of the SDRAM device.
<> 144:ef7eb2e8f9f7 1221 * @param __INSTANCE__: FMC_SDRAM instance
<> 144:ef7eb2e8f9f7 1222 * @param __FLAG__: FMC_SDRAM flag
<> 144:ef7eb2e8f9f7 1223 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1224 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
<> 144:ef7eb2e8f9f7 1225 * @retval None
<> 144:ef7eb2e8f9f7 1226 */
<> 144:ef7eb2e8f9f7 1227 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
<> 144:ef7eb2e8f9f7 1228 /**
<> 144:ef7eb2e8f9f7 1229 * @}
<> 144:ef7eb2e8f9f7 1230 */
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /**
<> 144:ef7eb2e8f9f7 1233 * @}
<> 144:ef7eb2e8f9f7 1234 */
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1237 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
<> 144:ef7eb2e8f9f7 1238 * @{
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /** @defgroup FMC_LL_NORSRAM NOR SRAM
<> 144:ef7eb2e8f9f7 1242 * @{
<> 144:ef7eb2e8f9f7 1243 */
<> 144:ef7eb2e8f9f7 1244 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 1245 * @{
<> 144:ef7eb2e8f9f7 1246 */
<> 144:ef7eb2e8f9f7 1247 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 1248 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1249 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
<> 144:ef7eb2e8f9f7 1250 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1251 /**
<> 144:ef7eb2e8f9f7 1252 * @}
<> 144:ef7eb2e8f9f7 1253 */
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
<> 144:ef7eb2e8f9f7 1256 * @{
<> 144:ef7eb2e8f9f7 1257 */
<> 144:ef7eb2e8f9f7 1258 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1259 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1260 /**
<> 144:ef7eb2e8f9f7 1261 * @}
<> 144:ef7eb2e8f9f7 1262 */
<> 144:ef7eb2e8f9f7 1263 /**
<> 144:ef7eb2e8f9f7 1264 * @}
<> 144:ef7eb2e8f9f7 1265 */
<> 144:ef7eb2e8f9f7 1266
<> 144:ef7eb2e8f9f7 1267 /** @defgroup FMC_LL_NAND NAND
<> 144:ef7eb2e8f9f7 1268 * @{
<> 144:ef7eb2e8f9f7 1269 */
<> 144:ef7eb2e8f9f7 1270 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 1271 * @{
<> 144:ef7eb2e8f9f7 1272 */
<> 144:ef7eb2e8f9f7 1273 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 1274 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1275 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1276 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1277 /**
<> 144:ef7eb2e8f9f7 1278 * @}
<> 144:ef7eb2e8f9f7 1279 */
<> 144:ef7eb2e8f9f7 1280
<> 144:ef7eb2e8f9f7 1281 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
<> 144:ef7eb2e8f9f7 1282 * @{
<> 144:ef7eb2e8f9f7 1283 */
<> 144:ef7eb2e8f9f7 1284 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1285 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1286 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1287 /**
<> 144:ef7eb2e8f9f7 1288 * @}
<> 144:ef7eb2e8f9f7 1289 */
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /** @defgroup FMC_LL_SDRAM SDRAM
<> 144:ef7eb2e8f9f7 1292 * @{
<> 144:ef7eb2e8f9f7 1293 */
<> 144:ef7eb2e8f9f7 1294 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 1295 * @{
<> 144:ef7eb2e8f9f7 1296 */
<> 144:ef7eb2e8f9f7 1297 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
<> 144:ef7eb2e8f9f7 1298 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1299 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /**
<> 144:ef7eb2e8f9f7 1302 * @}
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
<> 144:ef7eb2e8f9f7 1306 * @{
<> 144:ef7eb2e8f9f7 1307 */
<> 144:ef7eb2e8f9f7 1308 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1309 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1310 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 1311 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
<> 144:ef7eb2e8f9f7 1312 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
<> 144:ef7eb2e8f9f7 1313 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @}
<> 144:ef7eb2e8f9f7 1316 */
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /**
<> 144:ef7eb2e8f9f7 1319 * @}
<> 144:ef7eb2e8f9f7 1320 */
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /**
<> 144:ef7eb2e8f9f7 1323 * @}
<> 144:ef7eb2e8f9f7 1324 */
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /**
<> 144:ef7eb2e8f9f7 1327 * @}
<> 144:ef7eb2e8f9f7 1328 */
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /**
<> 144:ef7eb2e8f9f7 1331 * @}
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1334 }
<> 144:ef7eb2e8f9f7 1335 #endif
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 #endif /* __STM32F7xx_LL_FMC_H */
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/