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mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h@144:ef7eb2e8f9f7
Child:: 157:ff67d9f36b67

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_adc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.0
<>	144:ef7eb2e8f9f7	6	* @date 22-April-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of ADC HAL extension module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F7xx_ADC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F7xx_ADC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f7xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup ADC
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup ADC_Exported_Types ADC Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief Structure definition of ADC and regular group initialization
<>	144:ef7eb2e8f9f7	64	* @note Parameters of this structure are shared within 2 scopes:
<>	144:ef7eb2e8f9f7	65	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
<>	144:ef7eb2e8f9f7	66	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<>	144:ef7eb2e8f9f7	67	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	68	* ADC state can be either:
<>	144:ef7eb2e8f9f7	69	* - For all parameters: ADC disabled
<>	144:ef7eb2e8f9f7	70	* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	71	* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
<>	144:ef7eb2e8f9f7	72	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	73	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	74	*/
<>	144:ef7eb2e8f9f7	75	typedef struct
<>	144:ef7eb2e8f9f7	76	{
<>	144:ef7eb2e8f9f7	77	uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
<>	144:ef7eb2e8f9f7	78	all the ADCs.
<>	144:ef7eb2e8f9f7	79	This parameter can be a value of @ref ADC_ClockPrescaler */
<>	144:ef7eb2e8f9f7	80	uint32_t Resolution; /*!< Configures the ADC resolution.
<>	144:ef7eb2e8f9f7	81	This parameter can be a value of @ref ADC_Resolution */
<>	144:ef7eb2e8f9f7	82	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<>	144:ef7eb2e8f9f7	83	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<>	144:ef7eb2e8f9f7	84	This parameter can be a value of @ref ADC_Data_Align */
<>	144:ef7eb2e8f9f7	85	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<>	144:ef7eb2e8f9f7	86	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<>	144:ef7eb2e8f9f7	87	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<>	144:ef7eb2e8f9f7	88	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<>	144:ef7eb2e8f9f7	89	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<>	144:ef7eb2e8f9f7	90	Scan direction is upward: from rank1 to rank 'n'.
<>	144:ef7eb2e8f9f7	91	This parameter can be set to ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	92	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<>	144:ef7eb2e8f9f7	93	This parameter can be a value of @ref ADC_EOCSelection.
<>	144:ef7eb2e8f9f7	94	Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
<>	144:ef7eb2e8f9f7	95	Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
<>	144:ef7eb2e8f9f7	96	or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
<>	144:ef7eb2e8f9f7	97	Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
<>	144:ef7eb2e8f9f7	98	If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
<>	144:ef7eb2e8f9f7	99	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<>	144:ef7eb2e8f9f7	100	after the selected trigger occurred (software start or external trigger).
<>	144:ef7eb2e8f9f7	101	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	102	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	144:ef7eb2e8f9f7	103	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	144:ef7eb2e8f9f7	104	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
<>	144:ef7eb2e8f9f7	105	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<>	144:ef7eb2e8f9f7	106	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	107	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<>	144:ef7eb2e8f9f7	108	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	109	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<>	144:ef7eb2e8f9f7	110	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	111	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<>	144:ef7eb2e8f9f7	112	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<>	144:ef7eb2e8f9f7	113	If set to ADC_SOFTWARE_START, external triggers are disabled.
<>	144:ef7eb2e8f9f7	114	If set to external trigger source, triggering is on event rising edge by default.
<>	144:ef7eb2e8f9f7	115	This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
<>	144:ef7eb2e8f9f7	116	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<>	144:ef7eb2e8f9f7	117	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<>	144:ef7eb2e8f9f7	118	This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
<>	144:ef7eb2e8f9f7	119	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<>	144:ef7eb2e8f9f7	120	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<>	144:ef7eb2e8f9f7	121	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<>	144:ef7eb2e8f9f7	122	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
<>	144:ef7eb2e8f9f7	123	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	124	}ADC_InitTypeDef;
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	/**
<>	144:ef7eb2e8f9f7	129	* @brief Structure definition of ADC channel for regular group
<>	144:ef7eb2e8f9f7	130	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	131	* ADC can be either disabled or enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	132	*/
<>	144:ef7eb2e8f9f7	133	typedef struct
<>	144:ef7eb2e8f9f7	134	{
<>	144:ef7eb2e8f9f7	135	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<>	144:ef7eb2e8f9f7	136	This parameter can be a value of @ref ADC_channels */
<>	144:ef7eb2e8f9f7	137	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
<>	144:ef7eb2e8f9f7	138	This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
<>	144:ef7eb2e8f9f7	139	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	144:ef7eb2e8f9f7	140	Unit: ADC clock cycles
<>	144:ef7eb2e8f9f7	141	Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
<>	144:ef7eb2e8f9f7	142	This parameter can be a value of @ref ADC_sampling_times
<>	144:ef7eb2e8f9f7	143	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	144:ef7eb2e8f9f7	144	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	144:ef7eb2e8f9f7	145	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	144:ef7eb2e8f9f7	146	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<>	144:ef7eb2e8f9f7	147	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
<>	144:ef7eb2e8f9f7	148	uint32_t Offset; /!< Reserved for future use, can be set to 0 /
<>	144:ef7eb2e8f9f7	149	}ADC_ChannelConfTypeDef;
<>	144:ef7eb2e8f9f7	150
<>	144:ef7eb2e8f9f7	151	/**
<>	144:ef7eb2e8f9f7	152	* @brief ADC Configuration multi-mode structure definition
<>	144:ef7eb2e8f9f7	153	*/
<>	144:ef7eb2e8f9f7	154	typedef struct
<>	144:ef7eb2e8f9f7	155	{
<>	144:ef7eb2e8f9f7	156	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
<>	144:ef7eb2e8f9f7	157	This parameter can be a value of @ref ADC_analog_watchdog_selection */
<>	144:ef7eb2e8f9f7	158	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	159	This parameter must be a 12-bit value. */
<>	144:ef7eb2e8f9f7	160	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	161	This parameter must be a 12-bit value. */
<>	144:ef7eb2e8f9f7	162	uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
<>	144:ef7eb2e8f9f7	163	This parameter has an effect only if watchdog mode is configured on single channel
<>	144:ef7eb2e8f9f7	164	This parameter can be a value of @ref ADC_channels */
<>	144:ef7eb2e8f9f7	165	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
<>	144:ef7eb2e8f9f7	166	is interrupt mode or in polling mode.
<>	144:ef7eb2e8f9f7	167	This parameter can be set to ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	168	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
<>	144:ef7eb2e8f9f7	169	}ADC_AnalogWDGConfTypeDef;
<>	144:ef7eb2e8f9f7	170
<>	144:ef7eb2e8f9f7	171	/**
<>	144:ef7eb2e8f9f7	172	* @brief HAL ADC state machine: ADC states definition (bitfields)
<>	144:ef7eb2e8f9f7	173	*/
<>	144:ef7eb2e8f9f7	174	/* States of ADC global scope */
<>	144:ef7eb2e8f9f7	175	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /!< ADC not yet initialized or disabled /
<>	144:ef7eb2e8f9f7	176	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /!< ADC peripheral ready for use /
<>	144:ef7eb2e8f9f7	177	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /!< ADC is busy to internal process (initialization, calibration) /
<>	144:ef7eb2e8f9f7	178	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /!< TimeOut occurrence /
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	/* States of ADC errors */
<>	144:ef7eb2e8f9f7	181	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /!< Internal error occurrence /
<>	144:ef7eb2e8f9f7	182	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /!< Configuration error occurrence /
<>	144:ef7eb2e8f9f7	183	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /!< DMA error occurrence /
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	/* States of ADC group regular */
<>	144:ef7eb2e8f9f7	186	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<>	144:ef7eb2e8f9f7	187	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<>	144:ef7eb2e8f9f7	188	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /!< Conversion data available on group regular /
<>	144:ef7eb2e8f9f7	189	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /!< Overrun occurrence /
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	/* States of ADC group injected */
<>	144:ef7eb2e8f9f7	192	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<>	144:ef7eb2e8f9f7	193	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<>	144:ef7eb2e8f9f7	194	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /!< Conversion data available on group injected /
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	/* States of ADC analog watchdogs */
<>	144:ef7eb2e8f9f7	197	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /!< Out-of-window occurrence of analog watchdog 1 /
<>	144:ef7eb2e8f9f7	198	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 /
<>	144:ef7eb2e8f9f7	199	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 /
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	/* States of ADC multi-mode */
<>	144:ef7eb2e8f9f7	202	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( /
<>	144:ef7eb2e8f9f7	203
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/**
<>	144:ef7eb2e8f9f7	206	* @brief ADC handle Structure definition
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	typedef struct
<>	144:ef7eb2e8f9f7	209	{
<>	144:ef7eb2e8f9f7	210	ADC_TypeDef Instance; /!< Register base address */
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	ADC_InitTypeDef Init; /!< ADC required parameters /
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	__IO uint32_t NbrOfCurrentConversionRank; /!< ADC number of current conversion rank /
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	HAL_LockTypeDef Lock; /!< ADC locking object /
<>	144:ef7eb2e8f9f7	219
<>	144:ef7eb2e8f9f7	220	__IO uint32_t State; /!< ADC communication state /
<>	144:ef7eb2e8f9f7	221
<>	144:ef7eb2e8f9f7	222	__IO uint32_t ErrorCode; /!< ADC Error code /
<>	144:ef7eb2e8f9f7	223	}ADC_HandleTypeDef;
<>	144:ef7eb2e8f9f7	224	/**
<>	144:ef7eb2e8f9f7	225	* @}
<>	144:ef7eb2e8f9f7	226	*/
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	229	/** @defgroup ADC_Exported_Constants ADC Exported Constants
<>	144:ef7eb2e8f9f7	230	* @{
<>	144:ef7eb2e8f9f7	231	*/
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	/** @defgroup ADC_Error_Code ADC Error Code
<>	144:ef7eb2e8f9f7	234	* @{
<>	144:ef7eb2e8f9f7	235	*/
<>	144:ef7eb2e8f9f7	236	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /!< No error /
<>	144:ef7eb2e8f9f7	237	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
<>	144:ef7eb2e8f9f7	238	enable/disable, erroneous state */
<>	144:ef7eb2e8f9f7	239	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /!< Overrun error /
<>	144:ef7eb2e8f9f7	240	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /!< DMA transfer error /
<>	144:ef7eb2e8f9f7	241	/**
<>	144:ef7eb2e8f9f7	242	* @}
<>	144:ef7eb2e8f9f7	243	*/
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245
<>	144:ef7eb2e8f9f7	246	/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
<>	144:ef7eb2e8f9f7	247	* @{
<>	144:ef7eb2e8f9f7	248	*/
<>	144:ef7eb2e8f9f7	249	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	250	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
<>	144:ef7eb2e8f9f7	251	#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
<>	144:ef7eb2e8f9f7	252	#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
<>	144:ef7eb2e8f9f7	253	/**
<>	144:ef7eb2e8f9f7	254	* @}
<>	144:ef7eb2e8f9f7	255	*/
<>	144:ef7eb2e8f9f7	256
<>	144:ef7eb2e8f9f7	257	/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
<>	144:ef7eb2e8f9f7	258	* @{
<>	144:ef7eb2e8f9f7	259	*/
<>	144:ef7eb2e8f9f7	260	#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	261	#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
<>	144:ef7eb2e8f9f7	262	#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
<>	144:ef7eb2e8f9f7	263	#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	264	#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
<>	144:ef7eb2e8f9f7	265	#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	266	#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
<>	144:ef7eb2e8f9f7	267	#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	268	#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
<>	144:ef7eb2e8f9f7	269	#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	270	#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1))
<>	144:ef7eb2e8f9f7	271	#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	272	#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2))
<>	144:ef7eb2e8f9f7	273	#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	274	#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1))
<>	144:ef7eb2e8f9f7	275	#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
<>	144:ef7eb2e8f9f7	276	/**
<>	144:ef7eb2e8f9f7	277	* @}
<>	144:ef7eb2e8f9f7	278	*/
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/** @defgroup ADC_Resolution ADC Resolution
<>	144:ef7eb2e8f9f7	281	* @{
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	284	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
<>	144:ef7eb2e8f9f7	285	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
<>	144:ef7eb2e8f9f7	286	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
<>	144:ef7eb2e8f9f7	287	/**
<>	144:ef7eb2e8f9f7	288	* @}
<>	144:ef7eb2e8f9f7	289	*/
<>	144:ef7eb2e8f9f7	290
<>	144:ef7eb2e8f9f7	291	/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
<>	144:ef7eb2e8f9f7	292	* @{
<>	144:ef7eb2e8f9f7	293	*/
<>	144:ef7eb2e8f9f7	294	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	295	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
<>	144:ef7eb2e8f9f7	296	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
<>	144:ef7eb2e8f9f7	297	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
<>	144:ef7eb2e8f9f7	298	/**
<>	144:ef7eb2e8f9f7	299	* @}
<>	144:ef7eb2e8f9f7	300	*/
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
<>	144:ef7eb2e8f9f7	303	* @{
<>	144:ef7eb2e8f9f7	304	*/
<>	144:ef7eb2e8f9f7	305	/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
<>	144:ef7eb2e8f9f7	306	/* compatibility with other STM32 devices. */
<>	144:ef7eb2e8f9f7	307
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	310	#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
<>	144:ef7eb2e8f9f7	311	#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
<>	144:ef7eb2e8f9f7	312	#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	313	#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
<>	144:ef7eb2e8f9f7	314	#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	315	#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1))
<>	144:ef7eb2e8f9f7	316	#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	317	#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
<>	144:ef7eb2e8f9f7	318	#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	319	#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1))
<>	144:ef7eb2e8f9f7	320	#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	321	#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2))
<>	144:ef7eb2e8f9f7	322	#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
<>	144:ef7eb2e8f9f7	325	#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
<>	144:ef7eb2e8f9f7	326
<>	144:ef7eb2e8f9f7	327	/**
<>	144:ef7eb2e8f9f7	328	* @}
<>	144:ef7eb2e8f9f7	329	*/
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/** @defgroup ADC_Data_Align ADC Data Align
<>	144:ef7eb2e8f9f7	332	* @{
<>	144:ef7eb2e8f9f7	333	*/
<>	144:ef7eb2e8f9f7	334	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	335	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<>	144:ef7eb2e8f9f7	336	/**
<>	144:ef7eb2e8f9f7	337	* @}
<>	144:ef7eb2e8f9f7	338	*/
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	/** @defgroup ADC_channels ADC Common Channels
<>	144:ef7eb2e8f9f7	341	* @{
<>	144:ef7eb2e8f9f7	342	*/
<>	144:ef7eb2e8f9f7	343	#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	344	#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	345	#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	346	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	347	#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
<>	144:ef7eb2e8f9f7	348	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	349	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
<>	144:ef7eb2e8f9f7	350	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	351	#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
<>	144:ef7eb2e8f9f7	352	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	353	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1))
<>	144:ef7eb2e8f9f7	354	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	355	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2))
<>	144:ef7eb2e8f9f7	356	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	357	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1))
<>	144:ef7eb2e8f9f7	358	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 \| ADC_CR1_AWDCH_2 \| ADC_CR1_AWDCH_1 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	359	#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
<>	144:ef7eb2e8f9f7	360	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_0))
<>	144:ef7eb2e8f9f7	361	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 \| ADC_CR1_AWDCH_1))
<>	144:ef7eb2e8f9f7	362
<>	144:ef7eb2e8f9f7	363	#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
<>	144:ef7eb2e8f9f7	364	#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
<>	144:ef7eb2e8f9f7	365	/**
<>	144:ef7eb2e8f9f7	366	* @}
<>	144:ef7eb2e8f9f7	367	*/
<>	144:ef7eb2e8f9f7	368
<>	144:ef7eb2e8f9f7	369	/** @defgroup ADC_sampling_times ADC Sampling Times
<>	144:ef7eb2e8f9f7	370	* @{
<>	144:ef7eb2e8f9f7	371	*/
<>	144:ef7eb2e8f9f7	372	#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	373	#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
<>	144:ef7eb2e8f9f7	374	#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
<>	144:ef7eb2e8f9f7	375	#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 \| ADC_SMPR1_SMP10_0))
<>	144:ef7eb2e8f9f7	376	#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
<>	144:ef7eb2e8f9f7	377	#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_0))
<>	144:ef7eb2e8f9f7	378	#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 \| ADC_SMPR1_SMP10_1))
<>	144:ef7eb2e8f9f7	379	#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
<>	144:ef7eb2e8f9f7	380	/**
<>	144:ef7eb2e8f9f7	381	* @}
<>	144:ef7eb2e8f9f7	382	*/
<>	144:ef7eb2e8f9f7	383
<>	144:ef7eb2e8f9f7	384	/** @defgroup ADC_EOCSelection ADC EOC Selection
<>	144:ef7eb2e8f9f7	385	* @{
<>	144:ef7eb2e8f9f7	386	*/
<>	144:ef7eb2e8f9f7	387	#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	388	#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	389	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /!< reserved for future use /
<>	144:ef7eb2e8f9f7	390	/**
<>	144:ef7eb2e8f9f7	391	* @}
<>	144:ef7eb2e8f9f7	392	*/
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/** @defgroup ADC_Event_type ADC Event Type
<>	144:ef7eb2e8f9f7	395	* @{
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
<>	144:ef7eb2e8f9f7	398	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
<>	144:ef7eb2e8f9f7	399	/**
<>	144:ef7eb2e8f9f7	400	* @}
<>	144:ef7eb2e8f9f7	401	*/
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
<>	144:ef7eb2e8f9f7	404	* @{
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
<>	144:ef7eb2e8f9f7	407	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
<>	144:ef7eb2e8f9f7	408	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	144:ef7eb2e8f9f7	409	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
<>	144:ef7eb2e8f9f7	410	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
<>	144:ef7eb2e8f9f7	411	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	144:ef7eb2e8f9f7	412	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	413	/**
<>	144:ef7eb2e8f9f7	414	* @}
<>	144:ef7eb2e8f9f7	415	*/
<>	144:ef7eb2e8f9f7	416
<>	144:ef7eb2e8f9f7	417	/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
<>	144:ef7eb2e8f9f7	418	* @{
<>	144:ef7eb2e8f9f7	419	*/
<>	144:ef7eb2e8f9f7	420	#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
<>	144:ef7eb2e8f9f7	421	#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
<>	144:ef7eb2e8f9f7	422	#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
<>	144:ef7eb2e8f9f7	423	#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
<>	144:ef7eb2e8f9f7	424	/**
<>	144:ef7eb2e8f9f7	425	* @}
<>	144:ef7eb2e8f9f7	426	*/
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/** @defgroup ADC_flags_definition ADC Flags Definition
<>	144:ef7eb2e8f9f7	429	* @{
<>	144:ef7eb2e8f9f7	430	*/
<>	144:ef7eb2e8f9f7	431	#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
<>	144:ef7eb2e8f9f7	432	#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
<>	144:ef7eb2e8f9f7	433	#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
<>	144:ef7eb2e8f9f7	434	#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
<>	144:ef7eb2e8f9f7	435	#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
<>	144:ef7eb2e8f9f7	436	#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
<>	144:ef7eb2e8f9f7	437	/**
<>	144:ef7eb2e8f9f7	438	* @}
<>	144:ef7eb2e8f9f7	439	*/
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	/** @defgroup ADC_channels_type ADC Channels Type
<>	144:ef7eb2e8f9f7	442	* @{
<>	144:ef7eb2e8f9f7	443	*/
<>	144:ef7eb2e8f9f7	444	#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	445	#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /!< reserved for future use /
<>	144:ef7eb2e8f9f7	446	#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /!< reserved for future use /
<>	144:ef7eb2e8f9f7	447	/**
<>	144:ef7eb2e8f9f7	448	* @}
<>	144:ef7eb2e8f9f7	449	*/
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/**
<>	144:ef7eb2e8f9f7	452	* @}
<>	144:ef7eb2e8f9f7	453	*/
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	456	/** @defgroup ADC_Exported_Macros ADC Exported Macros
<>	144:ef7eb2e8f9f7	457	* @{
<>	144:ef7eb2e8f9f7	458	*/
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	/** @brief Reset ADC handle state
<>	144:ef7eb2e8f9f7	461	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	462	* @retval None
<>	144:ef7eb2e8f9f7	463	*/
<>	144:ef7eb2e8f9f7	464	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/**
<>	144:ef7eb2e8f9f7	467	* @brief Enable the ADC peripheral.
<>	144:ef7eb2e8f9f7	468	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	469	* @retval None
<>	144:ef7eb2e8f9f7	470	*/
<>	144:ef7eb2e8f9f7	471	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 \|= ADC_CR2_ADON)
<>	144:ef7eb2e8f9f7	472
<>	144:ef7eb2e8f9f7	473	/**
<>	144:ef7eb2e8f9f7	474	* @brief Disable the ADC peripheral.
<>	144:ef7eb2e8f9f7	475	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	476	* @retval None
<>	144:ef7eb2e8f9f7	477	*/
<>	144:ef7eb2e8f9f7	478	#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/**
<>	144:ef7eb2e8f9f7	481	* @brief Enable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	482	* @param __HANDLE__: specifies the ADC Handle.
<>	144:ef7eb2e8f9f7	483	* @param __INTERRUPT__: ADC Interrupt.
<>	144:ef7eb2e8f9f7	484	* @retval None
<>	144:ef7eb2e8f9f7	485	*/
<>	144:ef7eb2e8f9f7	486	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	/**
<>	144:ef7eb2e8f9f7	489	* @brief Disable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	490	* @param __HANDLE__: specifies the ADC Handle.
<>	144:ef7eb2e8f9f7	491	* @param __INTERRUPT__: ADC interrupt.
<>	144:ef7eb2e8f9f7	492	* @retval None
<>	144:ef7eb2e8f9f7	493	*/
<>	144:ef7eb2e8f9f7	494	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	495
<>	144:ef7eb2e8f9f7	496	/** @brief Check if the specified ADC interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	497	* @param __HANDLE__: specifies the ADC Handle.
<>	144:ef7eb2e8f9f7	498	* @param __INTERRUPT__: specifies the ADC interrupt source to check.
<>	144:ef7eb2e8f9f7	499	* @retval The new state of __IT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	500	*/
<>	144:ef7eb2e8f9f7	501	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/**
<>	144:ef7eb2e8f9f7	504	* @brief Clear the ADC's pending flags.
<>	144:ef7eb2e8f9f7	505	* @param __HANDLE__: specifies the ADC Handle.
<>	144:ef7eb2e8f9f7	506	* @param __FLAG__: ADC flag.
<>	144:ef7eb2e8f9f7	507	* @retval None
<>	144:ef7eb2e8f9f7	508	*/
<>	144:ef7eb2e8f9f7	509	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/**
<>	144:ef7eb2e8f9f7	512	* @brief Get the selected ADC's flag status.
<>	144:ef7eb2e8f9f7	513	* @param __HANDLE__: specifies the ADC Handle.
<>	144:ef7eb2e8f9f7	514	* @param __FLAG__: ADC flag.
<>	144:ef7eb2e8f9f7	515	* @retval None
<>	144:ef7eb2e8f9f7	516	*/
<>	144:ef7eb2e8f9f7	517	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	/**
<>	144:ef7eb2e8f9f7	520	* @}
<>	144:ef7eb2e8f9f7	521	*/
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/* Include ADC HAL Extension module */
<>	144:ef7eb2e8f9f7	524	#include "stm32f7xx_hal_adc_ex.h"
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	527	/** @addtogroup ADC_Exported_Functions
<>	144:ef7eb2e8f9f7	528	* @{
<>	144:ef7eb2e8f9f7	529	*/
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	/** @addtogroup ADC_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	532	* @{
<>	144:ef7eb2e8f9f7	533	*/
<>	144:ef7eb2e8f9f7	534	/* Initialization/de-initialization functions ***********************************/
<>	144:ef7eb2e8f9f7	535	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	536	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	537	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	538	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	539	/**
<>	144:ef7eb2e8f9f7	540	* @}
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/** @addtogroup ADC_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	544	* @{
<>	144:ef7eb2e8f9f7	545	*/
<>	144:ef7eb2e8f9f7	546	/* I/O operation functions ******************************************************/
<>	144:ef7eb2e8f9f7	547	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	548	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	549	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	554	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	555
<>	144:ef7eb2e8f9f7	556	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	559	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	564	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	565	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	566	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	567	/**
<>	144:ef7eb2e8f9f7	568	* @}
<>	144:ef7eb2e8f9f7	569	*/
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	/** @addtogroup ADC_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	572	* @{
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574	/* Peripheral Control functions *************************************************/
<>	144:ef7eb2e8f9f7	575	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<>	144:ef7eb2e8f9f7	576	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<>	144:ef7eb2e8f9f7	577	/**
<>	144:ef7eb2e8f9f7	578	* @}
<>	144:ef7eb2e8f9f7	579	*/
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/** @addtogroup ADC_Exported_Functions_Group4
<>	144:ef7eb2e8f9f7	582	* @{
<>	144:ef7eb2e8f9f7	583	*/
<>	144:ef7eb2e8f9f7	584	/* Peripheral State functions ***************************************************/
<>	144:ef7eb2e8f9f7	585	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	586	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	587	/**
<>	144:ef7eb2e8f9f7	588	* @}
<>	144:ef7eb2e8f9f7	589	*/
<>	144:ef7eb2e8f9f7	590
<>	144:ef7eb2e8f9f7	591	/**
<>	144:ef7eb2e8f9f7	592	* @}
<>	144:ef7eb2e8f9f7	593	*/
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	/* Private types -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	596	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	597	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	598	/** @defgroup ADC_Private_Constants ADC Private Constants
<>	144:ef7eb2e8f9f7	599	* @{
<>	144:ef7eb2e8f9f7	600	*/
<>	144:ef7eb2e8f9f7	601	/* Delay for ADC stabilization time. */
<>	144:ef7eb2e8f9f7	602	/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
<>	144:ef7eb2e8f9f7	603	/* Unit: us */
<>	144:ef7eb2e8f9f7	604	#define ADC_STAB_DELAY_US ((uint32_t) 3U)
<>	144:ef7eb2e8f9f7	605	/* Delay for temperature sensor stabilization time. */
<>	144:ef7eb2e8f9f7	606	/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<>	144:ef7eb2e8f9f7	607	/* Unit: us */
<>	144:ef7eb2e8f9f7	608	#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
<>	144:ef7eb2e8f9f7	609	/**
<>	144:ef7eb2e8f9f7	610	* @}
<>	144:ef7eb2e8f9f7	611	*/
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	614	/** @defgroup ADC_Private_Macros ADC Private Macros
<>	144:ef7eb2e8f9f7	615	* @{
<>	144:ef7eb2e8f9f7	616	*/
<>	144:ef7eb2e8f9f7	617	/* Macro reserved for internal HAL driver usage, not intended to be used in
<>	144:ef7eb2e8f9f7	618	code of final user */
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/**
<>	144:ef7eb2e8f9f7	621	* @brief Verification of ADC state: enabled or disabled
<>	144:ef7eb2e8f9f7	622	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	623	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	144:ef7eb2e8f9f7	624	*/
<>	144:ef7eb2e8f9f7	625	#define ADC_IS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	626	((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
<>	144:ef7eb2e8f9f7	627	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	628
<>	144:ef7eb2e8f9f7	629	/**
<>	144:ef7eb2e8f9f7	630	* @brief Test if conversion trigger of regular group is software start
<>	144:ef7eb2e8f9f7	631	* or external trigger.
<>	144:ef7eb2e8f9f7	632	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	633	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	634	*/
<>	144:ef7eb2e8f9f7	635	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	636	(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
<>	144:ef7eb2e8f9f7	637
<>	144:ef7eb2e8f9f7	638	/**
<>	144:ef7eb2e8f9f7	639	* @brief Test if conversion trigger of injected group is software start
<>	144:ef7eb2e8f9f7	640	* or external trigger.
<>	144:ef7eb2e8f9f7	641	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	642	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	643	*/
<>	144:ef7eb2e8f9f7	644	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	645	(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	/**
<>	144:ef7eb2e8f9f7	648	* @brief Simultaneously clears and sets specific bits of the handle State
<>	144:ef7eb2e8f9f7	649	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<>	144:ef7eb2e8f9f7	650	* the first parameter is the ADC handle State, the second parameter is the
<>	144:ef7eb2e8f9f7	651	* bit field to clear, the third and last parameter is the bit field to set.
<>	144:ef7eb2e8f9f7	652	* @retval None
<>	144:ef7eb2e8f9f7	653	*/
<>	144:ef7eb2e8f9f7	654	#define ADC_STATE_CLR_SET MODIFY_REG
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/**
<>	144:ef7eb2e8f9f7	657	* @brief Clear ADC error code (set it to error code: "no error")
<>	144:ef7eb2e8f9f7	658	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	659	* @retval None
<>	144:ef7eb2e8f9f7	660	*/
<>	144:ef7eb2e8f9f7	661	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	662	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<>	144:ef7eb2e8f9f7	663	#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	664	((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	665	((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) \|\| \
<>	144:ef7eb2e8f9f7	666	((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
<>	144:ef7eb2e8f9f7	667	#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	668	((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	669	((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	670	((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	671	((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	672	((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	673	((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	674	((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	675	((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	676	((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	677	((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	678	((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	679	((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	680	((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	681	((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	682	((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
<>	144:ef7eb2e8f9f7	683	#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) \|\| \
<>	144:ef7eb2e8f9f7	684	((__RESOLUTION__) == ADC_RESOLUTION_10B) \|\| \
<>	144:ef7eb2e8f9f7	685	((__RESOLUTION__) == ADC_RESOLUTION_8B) \|\| \
<>	144:ef7eb2e8f9f7	686	((__RESOLUTION__) == ADC_RESOLUTION_6B))
<>	144:ef7eb2e8f9f7	687	#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	688	((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
<>	144:ef7eb2e8f9f7	689	((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	690	((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
<>	144:ef7eb2e8f9f7	691	#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	692	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	693	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	694	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	695	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	696	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	697	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	698	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	699	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	700	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	701	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	702	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	703	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	704	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	705	((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	706	((__REGTRIG__) == ADC_SOFTWARE_START))
<>	144:ef7eb2e8f9f7	707	#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) \|\| \
<>	144:ef7eb2e8f9f7	708	((__ALIGN__) == ADC_DATAALIGN_LEFT))
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	711	((__TIME__) == ADC_SAMPLETIME_15CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	712	((__TIME__) == ADC_SAMPLETIME_28CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	713	((__TIME__) == ADC_SAMPLETIME_56CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	714	((__TIME__) == ADC_SAMPLETIME_84CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	715	((__TIME__) == ADC_SAMPLETIME_112CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	716	((__TIME__) == ADC_SAMPLETIME_144CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	717	((__TIME__) == ADC_SAMPLETIME_480CYCLES))
<>	144:ef7eb2e8f9f7	718	#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) \|\| \
<>	144:ef7eb2e8f9f7	719	((__EOCSelection__) == ADC_EOC_SEQ_CONV) \|\| \
<>	144:ef7eb2e8f9f7	720	((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
<>	144:ef7eb2e8f9f7	721	#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	722	((__EVENT__) == ADC_OVR_EVENT))
<>	144:ef7eb2e8f9f7	723	#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	144:ef7eb2e8f9f7	724	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	725	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
<>	144:ef7eb2e8f9f7	726	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
<>	144:ef7eb2e8f9f7	727	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	728	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) \|\| \
<>	144:ef7eb2e8f9f7	729	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
<>	144:ef7eb2e8f9f7	730	#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) \|\| \
<>	144:ef7eb2e8f9f7	731	((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) \|\| \
<>	144:ef7eb2e8f9f7	732	((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
<>	144:ef7eb2e8f9f7	733	#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
<>	144:ef7eb2e8f9f7	734	#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
<>	144:ef7eb2e8f9f7	735	#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) >= ((uint32_t)1)) && ((__RANK__) <= ((uint32_t)16)))
<>	144:ef7eb2e8f9f7	736	#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
<>	144:ef7eb2e8f9f7	737	#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
<>	144:ef7eb2e8f9f7	738	((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) \|\| \
<>	144:ef7eb2e8f9f7	739	(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) \|\| \
<>	144:ef7eb2e8f9f7	740	(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) \|\| \
<>	144:ef7eb2e8f9f7	741	(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	/**
<>	144:ef7eb2e8f9f7	744	* @brief Set ADC Regular channel sequence length.
<>	144:ef7eb2e8f9f7	745	* @param _NbrOfConversion_: Regular channel sequence length.
<>	144:ef7eb2e8f9f7	746	* @retval None
<>	144:ef7eb2e8f9f7	747	*/
<>	144:ef7eb2e8f9f7	748	#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/**
<>	144:ef7eb2e8f9f7	751	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
<>	144:ef7eb2e8f9f7	752	* @param _SAMPLETIME_: Sample time parameter.
<>	144:ef7eb2e8f9f7	753	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	754	* @retval None
<>	144:ef7eb2e8f9f7	755	*/
<>	144:ef7eb2e8f9f7	756	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
<>	144:ef7eb2e8f9f7	757
<>	144:ef7eb2e8f9f7	758	/**
<>	144:ef7eb2e8f9f7	759	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
<>	144:ef7eb2e8f9f7	760	* @param _SAMPLETIME_: Sample time parameter.
<>	144:ef7eb2e8f9f7	761	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	762	* @retval None
<>	144:ef7eb2e8f9f7	763	*/
<>	144:ef7eb2e8f9f7	764	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/**
<>	144:ef7eb2e8f9f7	767	* @brief Set the selected regular channel rank for rank between 1 and 6.
<>	144:ef7eb2e8f9f7	768	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	769	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	770	* @retval None
<>	144:ef7eb2e8f9f7	771	*/
<>	144:ef7eb2e8f9f7	772	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
<>	144:ef7eb2e8f9f7	773
<>	144:ef7eb2e8f9f7	774	/**
<>	144:ef7eb2e8f9f7	775	* @brief Set the selected regular channel rank for rank between 7 and 12.
<>	144:ef7eb2e8f9f7	776	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	777	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	778	* @retval None
<>	144:ef7eb2e8f9f7	779	*/
<>	144:ef7eb2e8f9f7	780	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
<>	144:ef7eb2e8f9f7	781
<>	144:ef7eb2e8f9f7	782	/**
<>	144:ef7eb2e8f9f7	783	* @brief Set the selected regular channel rank for rank between 13 and 16.
<>	144:ef7eb2e8f9f7	784	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	785	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	786	* @retval None
<>	144:ef7eb2e8f9f7	787	*/
<>	144:ef7eb2e8f9f7	788	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
<>	144:ef7eb2e8f9f7	789
<>	144:ef7eb2e8f9f7	790	/**
<>	144:ef7eb2e8f9f7	791	* @brief Enable ADC continuous conversion mode.
<>	144:ef7eb2e8f9f7	792	* @param _CONTINUOUS_MODE_: Continuous mode.
<>	144:ef7eb2e8f9f7	793	* @retval None
<>	144:ef7eb2e8f9f7	794	*/
<>	144:ef7eb2e8f9f7	795	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797	/**
<>	144:ef7eb2e8f9f7	798	* @brief Configures the number of discontinuous conversions for the regular group channels.
<>	144:ef7eb2e8f9f7	799	* @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
<>	144:ef7eb2e8f9f7	800	* @retval None
<>	144:ef7eb2e8f9f7	801	*/
<>	144:ef7eb2e8f9f7	802	#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
<>	144:ef7eb2e8f9f7	803
<>	144:ef7eb2e8f9f7	804	/**
<>	144:ef7eb2e8f9f7	805	* @brief Enable ADC scan mode.
<>	144:ef7eb2e8f9f7	806	* @param _SCANCONV_MODE_: Scan conversion mode.
<>	144:ef7eb2e8f9f7	807	* @retval None
<>	144:ef7eb2e8f9f7	808	*/
<>	144:ef7eb2e8f9f7	809	#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	/**
<>	144:ef7eb2e8f9f7	812	* @brief Enable the ADC end of conversion selection.
<>	144:ef7eb2e8f9f7	813	* @param _EOCSelection_MODE_: End of conversion selection mode.
<>	144:ef7eb2e8f9f7	814	* @retval None
<>	144:ef7eb2e8f9f7	815	*/
<>	144:ef7eb2e8f9f7	816	#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
<>	144:ef7eb2e8f9f7	817
<>	144:ef7eb2e8f9f7	818	/**
<>	144:ef7eb2e8f9f7	819	* @brief Enable the ADC DMA continuous request.
<>	144:ef7eb2e8f9f7	820	* @param _DMAContReq_MODE_: DMA continuous request mode.
<>	144:ef7eb2e8f9f7	821	* @retval None
<>	144:ef7eb2e8f9f7	822	*/
<>	144:ef7eb2e8f9f7	823	#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/**
<>	144:ef7eb2e8f9f7	826	* @brief Return resolution bits in CR1 register.
<>	144:ef7eb2e8f9f7	827	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	828	* @retval None
<>	144:ef7eb2e8f9f7	829	*/
<>	144:ef7eb2e8f9f7	830	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
<>	144:ef7eb2e8f9f7	831
<>	144:ef7eb2e8f9f7	832	/**
<>	144:ef7eb2e8f9f7	833	* @}
<>	144:ef7eb2e8f9f7	834	*/
<>	144:ef7eb2e8f9f7	835
<>	144:ef7eb2e8f9f7	836	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	837	/** @defgroup ADC_Private_Functions ADC Private Functions
<>	144:ef7eb2e8f9f7	838	* @{
<>	144:ef7eb2e8f9f7	839	*/
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/**
<>	144:ef7eb2e8f9f7	842	* @}
<>	144:ef7eb2e8f9f7	843	*/
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/**
<>	144:ef7eb2e8f9f7	846	* @}
<>	144:ef7eb2e8f9f7	847	*/
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	/**
<>	144:ef7eb2e8f9f7	850	* @}
<>	144:ef7eb2e8f9f7	851	*/
<>	144:ef7eb2e8f9f7	852
<>	144:ef7eb2e8f9f7	853	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	854	}
<>	144:ef7eb2e8f9f7	855	#endif
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	#endif /__STM32F7xx_ADC_H /
<>	144:ef7eb2e8f9f7	858
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/