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mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
159:612c381a210f
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file us_ticker_api.h
<> 149:156823d33999 4 * @brief Implementation of a Timer driver
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: $
<> 149:156823d33999 8 * $Date: 2015-11-15 $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup timer
<> 149:156823d33999 28 */
<> 149:156823d33999 29
<> 149:156823d33999 30 #include <stddef.h>
<> 149:156823d33999 31 #include "timer.h"
<> 149:156823d33999 32
<> 149:156823d33999 33 #define US_TIMER TIMER0
<> 149:156823d33999 34 #define US_TICKER TIMER1
<> 149:156823d33999 35
<> 149:156823d33999 36 static int us_ticker_inited = 0;
<> 149:156823d33999 37
<> 149:156823d33999 38 static void us_timer_init(void);
<> 149:156823d33999 39
<> 149:156823d33999 40 static uint32_t us_ticker_int_counter = 0;
<> 149:156823d33999 41 static volatile uint32_t msb_counter = 0;
<> 149:156823d33999 42
<> 149:156823d33999 43 void us_ticker_init(void)
<> 149:156823d33999 44 {
<> 149:156823d33999 45 if (!us_ticker_inited) {
<> 149:156823d33999 46 us_timer_init();
<> 149:156823d33999 47 }
<> 149:156823d33999 48 }
<> 149:156823d33999 49
<> 149:156823d33999 50 /*******************************************************************************
<> 149:156823d33999 51 * Timer for us timing reference
<> 149:156823d33999 52 *
<> 149:156823d33999 53 * Uptime counter for scheduling reference. It uses TIMER0.
<> 149:156823d33999 54 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
<> 149:156823d33999 55 * which is why a software timer is required to get 32-bit word length.
<> 149:156823d33999 56 ******************************************************************************/
<> 149:156823d33999 57 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
<> 149:156823d33999 58 /* TODO - Add msb_counter rollover protection at 16 bits count? */
<> 149:156823d33999 59 /* TODO - How is overflow handled? */
<> 149:156823d33999 60
<> 149:156823d33999 61 /* Timer 0 for free running time */
<> 149:156823d33999 62 extern void us_timer_isr(void)
<> 149:156823d33999 63 {
<> 149:156823d33999 64 TIM0REG->CLEAR = 0;
<> 149:156823d33999 65 msb_counter++;
<> 149:156823d33999 66 }
<> 149:156823d33999 67
<> 149:156823d33999 68 /* Initializing TIMER 0(TImer) and TIMER 1(Ticker) */
<> 149:156823d33999 69 static void us_timer_init(void)
<> 149:156823d33999 70 {
<> 149:156823d33999 71 /* Enable the timer0 periphery clock */
<> 149:156823d33999 72 CLOCK_ENABLE(CLOCK_TIMER0);
<> 149:156823d33999 73 /* Enable the timer0 periphery clock */
<> 149:156823d33999 74 CLOCK_ENABLE(CLOCK_TIMER1);
<> 149:156823d33999 75
<> 149:156823d33999 76 /* Timer init */
<> 149:156823d33999 77 /* load timer value */
<> 149:156823d33999 78 TIM0REG->LOAD = 0xFFFF;
<> 149:156823d33999 79
<> 149:156823d33999 80 /* set timer prescale 32 (1 us), mode & enable */
<> 149:156823d33999 81 TIM0REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
<> 149:156823d33999 82 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS) |
<> 149:156823d33999 83 (TIMER_ENABLE_BIT << TIMER_ENABLE_BIT_POS));
<> 149:156823d33999 84
<> 149:156823d33999 85 /* Ticker init */
<> 149:156823d33999 86 /* load timer value */
<> 149:156823d33999 87 TIM1REG->LOAD = 0xFFFF;
<> 149:156823d33999 88
<> 149:156823d33999 89 /* set timer prescale 32 (1 us), mode & enable */
<> 149:156823d33999 90 TIM1REG->CONTROL.WORD = ((CLK_DIVIDER_32 << TIMER_PRESCALE_BIT_POS) |
<> 149:156823d33999 91 (TIME_MODE_PERIODIC << TIMER_MODE_BIT_POS));
<> 149:156823d33999 92
<> 149:156823d33999 93 /* Register & enable interrupt associated with the timer */
<> 149:156823d33999 94 NVIC_SetVector(Tim0_IRQn,(uint32_t)us_timer_isr);
<> 149:156823d33999 95 NVIC_SetVector(Tim1_IRQn,(uint32_t)us_ticker_isr);
<> 149:156823d33999 96
<> 149:156823d33999 97 /* Clear pending irqs */
<> 149:156823d33999 98 NVIC_ClearPendingIRQ(Tim0_IRQn);
<> 149:156823d33999 99 NVIC_ClearPendingIRQ(Tim1_IRQn);
<> 149:156823d33999 100
<> 149:156823d33999 101 /* Setup NVIC for timer */
<> 149:156823d33999 102 NVIC_EnableIRQ(Tim0_IRQn);
<> 149:156823d33999 103 NVIC_EnableIRQ(Tim1_IRQn);
<> 149:156823d33999 104
<> 149:156823d33999 105 us_ticker_inited = 1;
<> 149:156823d33999 106 }
<> 149:156823d33999 107
<> 149:156823d33999 108 /* Reads 32 bit timer's current value (16 bit s/w timer | 16 bit h/w timer) */
<> 149:156823d33999 109 uint32_t us_ticker_read()
<> 149:156823d33999 110 {
<> 149:156823d33999 111 uint32_t retval, tim0cval;
<> 149:156823d33999 112
<> 149:156823d33999 113 if (!us_ticker_inited) {
<> 149:156823d33999 114 us_timer_init();
<> 149:156823d33999 115 }
<> 149:156823d33999 116
<> 149:156823d33999 117 /* Get the current tick from the hw and sw timers */
<> 149:156823d33999 118 tim0cval = TIM0REG->VALUE; /* read current time */
<> 149:156823d33999 119 retval = (0xFFFF - tim0cval); /* subtract down count */
<> 149:156823d33999 120
<> 149:156823d33999 121 NVIC_DisableIRQ(Tim0_IRQn);
<> 149:156823d33999 122 if (TIM0REG->CONTROL.BITS.INT) {
<> 149:156823d33999 123 TIM0REG->CLEAR = 0;
<> 149:156823d33999 124 msb_counter++;
<> 149:156823d33999 125 tim0cval = TIM0REG->VALUE; /* read current time again after interrupt */
<> 149:156823d33999 126 retval = (0xFFFF - tim0cval);
<> 149:156823d33999 127 }
<> 149:156823d33999 128 retval |= msb_counter << 16; /* add software bits */
<> 149:156823d33999 129 NVIC_EnableIRQ(Tim0_IRQn);
<> 149:156823d33999 130 return retval;
<> 149:156823d33999 131 }
<> 149:156823d33999 132
<> 149:156823d33999 133 /*******************************************************************************
<> 149:156823d33999 134 * Event Timer
<> 149:156823d33999 135 *
<> 149:156823d33999 136 * Schedules interrupts at given (32bit)us interval of time. It uses TIMER1.
<> 149:156823d33999 137 * The NCS36510 does not have a 32 bit timer nor the option to chain timers,
<> 149:156823d33999 138 * which is why a software timer is required to get 32-bit word length.
<> 149:156823d33999 139 *******************************************************************************/
<> 149:156823d33999 140 /* TODO - Need some sort of load value/prescale calculation for non-32MHz clock */
<> 149:156823d33999 141
<> 149:156823d33999 142 /* TImer 1 disbale interrupt */
<> 149:156823d33999 143 void us_ticker_disable_interrupt(void)
<> 149:156823d33999 144 {
<> 149:156823d33999 145 /* Disable the TIMER1 interrupt */
<> 149:156823d33999 146 TIM1REG->CONTROL.BITS.ENABLE = 0x0;
<> 149:156823d33999 147 }
<> 149:156823d33999 148
<> 149:156823d33999 149 /* TImer 1 clear interrupt */
<> 149:156823d33999 150 void us_ticker_clear_interrupt(void)
<> 149:156823d33999 151 {
<> 149:156823d33999 152 /* Clear the Ticker (TIMER1) interrupt */
<> 149:156823d33999 153 TIM1REG->CLEAR = 0;
<> 149:156823d33999 154 }
<> 149:156823d33999 155
<> 149:156823d33999 156 /* Setting TImer 1 (ticker) */
<> 149:156823d33999 157 inline static void ticker_set(uint32_t count)
<> 149:156823d33999 158 {
<> 149:156823d33999 159 /* Disable TIMER1, load the new value, and re-enable */
<> 149:156823d33999 160 TIM1REG->CONTROL.BITS.ENABLE = 0;
<> 149:156823d33999 161 TIM1REG->LOAD = count;
<> 149:156823d33999 162 TIM1REG->CONTROL.BITS.ENABLE = 1;
<> 149:156823d33999 163 }
<> 149:156823d33999 164
<> 149:156823d33999 165 /* TImer 1 - ticker ISR */
<> 149:156823d33999 166 extern void us_ticker_isr(void)
<> 149:156823d33999 167 {
<> 149:156823d33999 168 /* Clear IRQ flag */
<> 149:156823d33999 169 TIM1REG->CLEAR = 0;
<> 149:156823d33999 170
<> 149:156823d33999 171 /* If this is a longer timer it will take multiple full hw counter cycles */
<> 149:156823d33999 172 if (us_ticker_int_counter > 0) {
<> 149:156823d33999 173 ticker_set(0xFFFF);
<> 149:156823d33999 174 us_ticker_int_counter--;
<> 149:156823d33999 175 } else {
<> 149:156823d33999 176 TIM1REG->CONTROL.BITS.ENABLE = False;
<> 149:156823d33999 177 us_ticker_irq_handler();
<> 149:156823d33999 178 }
<> 149:156823d33999 179 }
<> 149:156823d33999 180
<> 149:156823d33999 181 /* Set timer 1 ticker interrupt */
<> 149:156823d33999 182 void us_ticker_set_interrupt(timestamp_t timestamp)
<> 149:156823d33999 183 {
<> 149:156823d33999 184 int32_t delta = (uint32_t)timestamp - us_ticker_read();
<> 149:156823d33999 185
<> 149:156823d33999 186 if (delta <= 0) {
<> 149:156823d33999 187 /* This event was in the past */
<> 149:156823d33999 188 //us_ticker_irq_handler();
<> 149:156823d33999 189 // This event was in the past.
<> 149:156823d33999 190 // Set the interrupt as pending, but don't process it here.
<> 149:156823d33999 191 // This prevents a recurive loop under heavy load
<> 149:156823d33999 192 // which can lead to a stack overflow.
<> 149:156823d33999 193 NVIC_SetPendingIRQ(Tim1_IRQn);
<> 149:156823d33999 194
<> 149:156823d33999 195 return;
<> 149:156823d33999 196 }
<> 149:156823d33999 197
<> 149:156823d33999 198 /* Calculate how much delta falls outside the 16-bit counter range. */
<> 149:156823d33999 199 /* You will have to perform a full timer overflow for each bit above */
<> 149:156823d33999 200 /* that range. */
<> 149:156823d33999 201 us_ticker_int_counter = (uint32_t)(delta >> 16);
<> 149:156823d33999 202
<> 149:156823d33999 203 ticker_set(delta);
<> 149:156823d33999 204 }