The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Parent:
86:04dd9b1680ae
Release 92 of the mbed libray

Main changes:

- nRF51822: fixed pin assignment issues
- ST targets moving to the STM32Cube driver
- LPC1439: fixed serial interrupt issue
- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 12-Sept-2014
bogdanm 86:04dd9b1680ae 7 * @brief This file contains all the functions prototypes for the HAL
bogdanm 86:04dd9b1680ae 8 * module driver.
bogdanm 86:04dd9b1680ae 9 ******************************************************************************
bogdanm 86:04dd9b1680ae 10 * @attention
bogdanm 86:04dd9b1680ae 11 *
bogdanm 86:04dd9b1680ae 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 13 *
bogdanm 86:04dd9b1680ae 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 15 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 17 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 20 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 22 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 23 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 24 *
bogdanm 86:04dd9b1680ae 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 35 *
bogdanm 86:04dd9b1680ae 36 ******************************************************************************
bogdanm 86:04dd9b1680ae 37 */
bogdanm 86:04dd9b1680ae 38
bogdanm 86:04dd9b1680ae 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 40 #ifndef __STM32F3xx_HAL_H
bogdanm 86:04dd9b1680ae 41 #define __STM32F3xx_HAL_H
bogdanm 86:04dd9b1680ae 42
bogdanm 86:04dd9b1680ae 43 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 44 extern "C" {
bogdanm 86:04dd9b1680ae 45 #endif
bogdanm 86:04dd9b1680ae 46
bogdanm 86:04dd9b1680ae 47 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 48 #include "stm32f3xx_hal_conf.h"
bogdanm 86:04dd9b1680ae 49
bogdanm 86:04dd9b1680ae 50 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 51 * @{
bogdanm 86:04dd9b1680ae 52 */
bogdanm 86:04dd9b1680ae 53
bogdanm 86:04dd9b1680ae 54 /** @addtogroup HAL
bogdanm 86:04dd9b1680ae 55 * @{
bogdanm 86:04dd9b1680ae 56 */
bogdanm 86:04dd9b1680ae 57
bogdanm 86:04dd9b1680ae 58 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 59 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 60 /** @defgroup HAL_Exported_Constants HAL Exported Constants
bogdanm 92:4fc01daae5a5 61 * @{
bogdanm 92:4fc01daae5a5 62 */
bogdanm 92:4fc01daae5a5 63 /** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
bogdanm 86:04dd9b1680ae 64 * @brief SYSCFG registers bit address in the alias region
bogdanm 86:04dd9b1680ae 65 * @{
bogdanm 86:04dd9b1680ae 66 */
bogdanm 86:04dd9b1680ae 67 /* ------------ SYSCFG registers bit address in the alias region -------------*/
bogdanm 86:04dd9b1680ae 68 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
bogdanm 86:04dd9b1680ae 69 /* --- CFGR2 Register ---*/
bogdanm 86:04dd9b1680ae 70 /* Alias word address of BYP_ADDR_PAR bit */
bogdanm 86:04dd9b1680ae 71 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
bogdanm 86:04dd9b1680ae 72 #define BYPADDRPAR_BitNumber 0x04
bogdanm 86:04dd9b1680ae 73 #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
bogdanm 86:04dd9b1680ae 74 /**
bogdanm 86:04dd9b1680ae 75 * @}
bogdanm 86:04dd9b1680ae 76 */
bogdanm 86:04dd9b1680ae 77
bogdanm 86:04dd9b1680ae 78 #if defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 92:4fc01daae5a5 79 /** @defgroup HAL_DMA_Remapping DMA Remapping
bogdanm 86:04dd9b1680ae 80 * Elements values convention: 0xXXYYYYYY
bogdanm 86:04dd9b1680ae 81 * - YYYYYY : Position in the register
bogdanm 86:04dd9b1680ae 82 * - XX : Register index
bogdanm 86:04dd9b1680ae 83 * - 00: CFGR1 register in SYSCFG
bogdanm 86:04dd9b1680ae 84 * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
bogdanm 86:04dd9b1680ae 85 * @{
bogdanm 86:04dd9b1680ae 86 */
bogdanm 92:4fc01daae5a5 87 #define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
bogdanm 86:04dd9b1680ae 88 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
bogdanm 86:04dd9b1680ae 89 #define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap
bogdanm 86:04dd9b1680ae 90 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
bogdanm 86:04dd9b1680ae 91 #define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap
bogdanm 86:04dd9b1680ae 92 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
bogdanm 92:4fc01daae5a5 93 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
bogdanm 86:04dd9b1680ae 94 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
bogdanm 92:4fc01daae5a5 95 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
bogdanm 86:04dd9b1680ae 96 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
bogdanm 86:04dd9b1680ae 97 #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 98 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
bogdanm 86:04dd9b1680ae 99 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 100 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
bogdanm 86:04dd9b1680ae 101 #if defined(SYSCFG_CFGR3_DMA_RMP)
bogdanm 86:04dd9b1680ae 102 #if !defined(HAL_REMAP_CFGR3_MASK)
bogdanm 86:04dd9b1680ae 103 #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 104 #endif
bogdanm 86:04dd9b1680ae 105
bogdanm 86:04dd9b1680ae 106 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 107 11: Map on DMA1 channel 2 */
bogdanm 86:04dd9b1680ae 108 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 109 01: Map on DMA1 channel 4 */
bogdanm 86:04dd9b1680ae 110 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 111 10: Map on DMA1 channel 6 */
bogdanm 86:04dd9b1680ae 112 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 113 11: Map on DMA1 channel 3 */
bogdanm 86:04dd9b1680ae 114 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 115 01: Map on DMA1 channel 5 */
bogdanm 86:04dd9b1680ae 116 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 117 10: Map on DMA1 channel 7 */
bogdanm 86:04dd9b1680ae 118 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 119 11: Map on DMA1 channel 7 */
bogdanm 86:04dd9b1680ae 120 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 121 01: Map on DMA1 channel 3 */
bogdanm 86:04dd9b1680ae 122 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 123 10: Map on DMA1 channel 5 */
bogdanm 86:04dd9b1680ae 124 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 125 11: Map on DMA1 channel 6 */
bogdanm 86:04dd9b1680ae 126 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 127 01: Map on DMA1 channel 2 */
bogdanm 86:04dd9b1680ae 128 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 129 10: Map on DMA1 channel 4 */
bogdanm 86:04dd9b1680ae 130 #define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap
bogdanm 86:04dd9b1680ae 131 x0: No remap (ADC2 on DMA2)
bogdanm 86:04dd9b1680ae 132 10: Map on DMA1 channel 2 */
bogdanm 86:04dd9b1680ae 133 #define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap
bogdanm 86:04dd9b1680ae 134 11: Map on DMA1 channel 4 */
bogdanm 86:04dd9b1680ae 135 #endif /* SYSCFG_CFGR3_DMA_RMP */
bogdanm 86:04dd9b1680ae 136
bogdanm 92:4fc01daae5a5 137 #if defined(SYSCFG_CFGR3_DMA_RMP)
bogdanm 86:04dd9b1680ae 138 #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
bogdanm 86:04dd9b1680ae 139 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 140 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 141 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 142 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 143 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 144 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 145 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
bogdanm 86:04dd9b1680ae 146 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 147 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 148 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 149 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 150 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 151 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 152 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 153 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 154 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 155 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
bogdanm 86:04dd9b1680ae 156 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 157 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
bogdanm 86:04dd9b1680ae 158 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
bogdanm 92:4fc01daae5a5 159 #else
bogdanm 86:04dd9b1680ae 160 #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
bogdanm 86:04dd9b1680ae 161 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 162 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 163 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 164 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 165 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 166 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
bogdanm 86:04dd9b1680ae 167 #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
bogdanm 86:04dd9b1680ae 168 /**
bogdanm 86:04dd9b1680ae 169 * @}
bogdanm 86:04dd9b1680ae 170 */
bogdanm 86:04dd9b1680ae 171 #endif /* SYSCFG_CFGR1_DMA_RMP */
bogdanm 86:04dd9b1680ae 172
bogdanm 92:4fc01daae5a5 173 /** @defgroup HAL_Trigger_Remapping Trigger Remapping
bogdanm 86:04dd9b1680ae 174 * Elements values convention: 0xXXYYYYYY
bogdanm 86:04dd9b1680ae 175 * - YYYYYY : Position in the register
bogdanm 86:04dd9b1680ae 176 * - XX : Register index
bogdanm 86:04dd9b1680ae 177 * - 00: CFGR1 register in SYSCFG
bogdanm 86:04dd9b1680ae 178 * - 01: CFGR3 register in SYSCFG
bogdanm 86:04dd9b1680ae 179 * @{
bogdanm 86:04dd9b1680ae 180 */
bogdanm 86:04dd9b1680ae 181 #define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
bogdanm 86:04dd9b1680ae 182 0: No remap (DAC trigger is TIM8_TRGO)
bogdanm 86:04dd9b1680ae 183 1: Remap (DAC trigger is TIM3_TRGO) */
bogdanm 86:04dd9b1680ae 184 #define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap
bogdanm 86:04dd9b1680ae 185 0: No remap
bogdanm 86:04dd9b1680ae 186 1: Remap (TIM1_TRG3 = TIM17_OC) */
bogdanm 86:04dd9b1680ae 187 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
bogdanm 86:04dd9b1680ae 188 #if !defined(HAL_REMAP_CFGR3_MASK)
bogdanm 86:04dd9b1680ae 189 #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 190 #endif
bogdanm 86:04dd9b1680ae 191 #define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
bogdanm 86:04dd9b1680ae 192 0: Remap (DAC trigger is TIM15_TRGO)
bogdanm 86:04dd9b1680ae 193 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
bogdanm 86:04dd9b1680ae 194 #define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
bogdanm 86:04dd9b1680ae 195 0: No remap
bogdanm 86:04dd9b1680ae 196 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
bogdanm 86:04dd9b1680ae 197 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
bogdanm 86:04dd9b1680ae 198 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
bogdanm 86:04dd9b1680ae 199 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
bogdanm 86:04dd9b1680ae 200 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
bogdanm 86:04dd9b1680ae 201 #else
bogdanm 86:04dd9b1680ae 202 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
bogdanm 86:04dd9b1680ae 203 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
bogdanm 86:04dd9b1680ae 204 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
bogdanm 86:04dd9b1680ae 205 /**
bogdanm 86:04dd9b1680ae 206 * @}
bogdanm 86:04dd9b1680ae 207 */
bogdanm 86:04dd9b1680ae 208
bogdanm 92:4fc01daae5a5 209 #if defined (STM32F303xE) || defined (STM32F398xx)
bogdanm 92:4fc01daae5a5 210 /** @defgroup HAL_ADC_Trigger_Remapping ADC Trigger Remapping
bogdanm 92:4fc01daae5a5 211 * @{
bogdanm 92:4fc01daae5a5 212 */
bogdanm 92:4fc01daae5a5 213 #define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
bogdanm 92:4fc01daae5a5 214 0: No remap (TIM1_CC3)
bogdanm 92:4fc01daae5a5 215 1: Remap (TIM20_TRGO) */
bogdanm 92:4fc01daae5a5 216 #define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
bogdanm 92:4fc01daae5a5 217 0: No remap (TIM2_CC2)
bogdanm 92:4fc01daae5a5 218 1: Remap (TIM20_TRGO2) */
bogdanm 92:4fc01daae5a5 219 #define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
bogdanm 92:4fc01daae5a5 220 0: No remap (TIM4_CC4)
bogdanm 92:4fc01daae5a5 221 1: Remap (TIM20_CC1) */
bogdanm 92:4fc01daae5a5 222 #define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
bogdanm 92:4fc01daae5a5 223 0: No remap (TIM6_TRGO)
bogdanm 92:4fc01daae5a5 224 1: Remap (TIM20_CC2) */
bogdanm 92:4fc01daae5a5 225 #define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
bogdanm 92:4fc01daae5a5 226 0: No remap (TIM3_CC4)
bogdanm 92:4fc01daae5a5 227 1: Remap (TIM20_CC3) */
bogdanm 92:4fc01daae5a5 228 #define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
bogdanm 92:4fc01daae5a5 229 0: No remap (TIM2_CC1)
bogdanm 92:4fc01daae5a5 230 1: Remap (TIM20_TRGO) */
bogdanm 92:4fc01daae5a5 231 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
bogdanm 92:4fc01daae5a5 232 0: No remap (EXTI line 15)
bogdanm 92:4fc01daae5a5 233 1: Remap (TIM20_TRGO2) */
bogdanm 92:4fc01daae5a5 234 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
bogdanm 92:4fc01daae5a5 235 0: No remap (TIM3_CC1)
bogdanm 92:4fc01daae5a5 236 1: Remap (TIM20_CC4) */
bogdanm 92:4fc01daae5a5 237 #define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
bogdanm 92:4fc01daae5a5 238 0: No remap (EXTI line 2)
bogdanm 92:4fc01daae5a5 239 1: Remap (TIM20_TRGO) */
bogdanm 92:4fc01daae5a5 240 #define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
bogdanm 92:4fc01daae5a5 241 0: No remap (TIM4_CC1)
bogdanm 92:4fc01daae5a5 242 1: Remap (TIM20_TRGO2) */
bogdanm 92:4fc01daae5a5 243 #define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
bogdanm 92:4fc01daae5a5 244 0: No remap (TIM2_CC1)
bogdanm 92:4fc01daae5a5 245 1: Remap (TIM20_CC1) */
bogdanm 92:4fc01daae5a5 246 #define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
bogdanm 92:4fc01daae5a5 247 0: No remap (TIM4_CC3)
bogdanm 92:4fc01daae5a5 248 1: Remap (TIM20_TRGO) */
bogdanm 92:4fc01daae5a5 249 #define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
bogdanm 92:4fc01daae5a5 250 0: No remap (TIM1_CC3)
bogdanm 92:4fc01daae5a5 251 1: Remap (TIM20_TRGO2) */
bogdanm 92:4fc01daae5a5 252 #define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
bogdanm 92:4fc01daae5a5 253 0: No remap (TIM7_TRGO)
bogdanm 92:4fc01daae5a5 254 1: Remap (TIM20_CC2) */
bogdanm 92:4fc01daae5a5 255
bogdanm 92:4fc01daae5a5 256 #define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
bogdanm 92:4fc01daae5a5 257 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
bogdanm 92:4fc01daae5a5 258 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
bogdanm 92:4fc01daae5a5 259 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
bogdanm 92:4fc01daae5a5 260 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
bogdanm 92:4fc01daae5a5 261 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
bogdanm 92:4fc01daae5a5 262 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
bogdanm 92:4fc01daae5a5 263 (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
bogdanm 92:4fc01daae5a5 264 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
bogdanm 92:4fc01daae5a5 265 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
bogdanm 92:4fc01daae5a5 266 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
bogdanm 92:4fc01daae5a5 267 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
bogdanm 92:4fc01daae5a5 268 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
bogdanm 92:4fc01daae5a5 269 (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
bogdanm 92:4fc01daae5a5 270 /**
bogdanm 92:4fc01daae5a5 271 * @}
bogdanm 92:4fc01daae5a5 272 */
bogdanm 92:4fc01daae5a5 273 #endif /* STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 /** @defgroup HAL_FastModePlus_I2C I2C Fast Mode Plus
bogdanm 86:04dd9b1680ae 276 * @{
bogdanm 86:04dd9b1680ae 277 */
bogdanm 86:04dd9b1680ae 278 #if defined(SYSCFG_CFGR1_I2C1_FMP)
bogdanm 86:04dd9b1680ae 279 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< I2C1 fast mode Plus driving capability activation
bogdanm 86:04dd9b1680ae 280 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
bogdanm 86:04dd9b1680ae 281 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
bogdanm 86:04dd9b1680ae 282 #endif /* SYSCFG_CFGR1_I2C1_FMP */
bogdanm 86:04dd9b1680ae 283
bogdanm 86:04dd9b1680ae 284 #if defined(SYSCFG_CFGR1_I2C2_FMP)
bogdanm 86:04dd9b1680ae 285 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< I2C2 fast mode Plus driving capability activation
bogdanm 86:04dd9b1680ae 286 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
bogdanm 86:04dd9b1680ae 287 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
bogdanm 86:04dd9b1680ae 288 #endif /* SYSCFG_CFGR1_I2C2_FMP */
bogdanm 86:04dd9b1680ae 289
bogdanm 86:04dd9b1680ae 290 #if defined(SYSCFG_CFGR1_I2C3_FMP)
bogdanm 86:04dd9b1680ae 291 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< I2C3 fast mode Plus driving capability activation
bogdanm 86:04dd9b1680ae 292 0: FM+ mode is not enabled on I2C3 pins selected through AF selection bits
bogdanm 86:04dd9b1680ae 293 1: FM+ mode is enabled on I2C3 pins selected through AF selection bits */
bogdanm 86:04dd9b1680ae 294 #endif /* SYSCFG_CFGR1_I2C3_FMP */
bogdanm 86:04dd9b1680ae 295
bogdanm 86:04dd9b1680ae 296 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
bogdanm 86:04dd9b1680ae 297 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 298 0: PB6 pin operates in standard mode
bogdanm 86:04dd9b1680ae 299 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 300 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
bogdanm 86:04dd9b1680ae 301
bogdanm 86:04dd9b1680ae 302 #if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
bogdanm 86:04dd9b1680ae 303 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 304 0: PB7 pin operates in standard mode
bogdanm 86:04dd9b1680ae 305 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 306 #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
bogdanm 86:04dd9b1680ae 307
bogdanm 86:04dd9b1680ae 308 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
bogdanm 86:04dd9b1680ae 309 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 310 0: PB8 pin operates in standard mode
bogdanm 86:04dd9b1680ae 311 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 312 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
bogdanm 86:04dd9b1680ae 313
bogdanm 86:04dd9b1680ae 314 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
bogdanm 86:04dd9b1680ae 315 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 316 0: PB9 pin operates in standard mode
bogdanm 86:04dd9b1680ae 317 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 318 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
bogdanm 86:04dd9b1680ae 319
bogdanm 86:04dd9b1680ae 320 #if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP)
bogdanm 86:04dd9b1680ae 321 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
bogdanm 86:04dd9b1680ae 322 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
bogdanm 86:04dd9b1680ae 323 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C3) == HAL_SYSCFG_FASTMODEPLUS_I2C3) || \
bogdanm 86:04dd9b1680ae 324 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
bogdanm 86:04dd9b1680ae 325 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
bogdanm 86:04dd9b1680ae 326 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
bogdanm 86:04dd9b1680ae 327 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
bogdanm 86:04dd9b1680ae 328 #elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP)
bogdanm 86:04dd9b1680ae 329 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
bogdanm 86:04dd9b1680ae 330 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
bogdanm 86:04dd9b1680ae 331 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
bogdanm 86:04dd9b1680ae 332 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
bogdanm 86:04dd9b1680ae 333 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
bogdanm 86:04dd9b1680ae 334 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
bogdanm 86:04dd9b1680ae 335 #elif defined(SYSCFG_CFGR1_I2C1_FMP)
bogdanm 86:04dd9b1680ae 336 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
bogdanm 86:04dd9b1680ae 337 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
bogdanm 86:04dd9b1680ae 338 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
bogdanm 86:04dd9b1680ae 339 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
bogdanm 86:04dd9b1680ae 340 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
bogdanm 86:04dd9b1680ae 341 #endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */
bogdanm 86:04dd9b1680ae 342 /**
bogdanm 86:04dd9b1680ae 343 * @}
bogdanm 86:04dd9b1680ae 344 */
bogdanm 86:04dd9b1680ae 345
bogdanm 86:04dd9b1680ae 346 #if defined(SYSCFG_RCR_PAGE0)
bogdanm 86:04dd9b1680ae 347 /* CCM-SRAM defined */
bogdanm 92:4fc01daae5a5 348 /** @defgroup HAL_Page_Write_Protection CCM RAM page write protection
bogdanm 86:04dd9b1680ae 349 * @{
bogdanm 86:04dd9b1680ae 350 */
bogdanm 86:04dd9b1680ae 351 #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
bogdanm 86:04dd9b1680ae 352 #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
bogdanm 86:04dd9b1680ae 353 #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
bogdanm 86:04dd9b1680ae 354 #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
bogdanm 86:04dd9b1680ae 355 #if defined(SYSCFG_RCR_PAGE4)
bogdanm 86:04dd9b1680ae 356 /* More than 4KB CCM-SRAM defined */
bogdanm 86:04dd9b1680ae 357 #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
bogdanm 86:04dd9b1680ae 358 #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
bogdanm 86:04dd9b1680ae 359 #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
bogdanm 86:04dd9b1680ae 360 #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
bogdanm 86:04dd9b1680ae 361 #endif /* SYSCFG_RCR_PAGE4 */
bogdanm 92:4fc01daae5a5 362 #if defined(SYSCFG_RCR_PAGE8)
bogdanm 92:4fc01daae5a5 363 #define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
bogdanm 92:4fc01daae5a5 364 #define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
bogdanm 92:4fc01daae5a5 365 #define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
bogdanm 92:4fc01daae5a5 366 #define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
bogdanm 92:4fc01daae5a5 367 #define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
bogdanm 92:4fc01daae5a5 368 #define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
bogdanm 92:4fc01daae5a5 369 #define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
bogdanm 92:4fc01daae5a5 370 #define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
bogdanm 92:4fc01daae5a5 371 #endif /* SYSCFG_RCR_PAGE8 */
bogdanm 86:04dd9b1680ae 372
bogdanm 92:4fc01daae5a5 373 #if defined(SYSCFG_RCR_PAGE8)
bogdanm 92:4fc01daae5a5 374 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0xFFFF))
bogdanm 92:4fc01daae5a5 375 #elif defined(SYSCFG_RCR_PAGE4)
bogdanm 92:4fc01daae5a5 376 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x00FF))
bogdanm 86:04dd9b1680ae 377 #else
bogdanm 92:4fc01daae5a5 378 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= (uint32_t)0x000F))
bogdanm 92:4fc01daae5a5 379 #endif /* SYSCFG_RCR_PAGE8 */
bogdanm 86:04dd9b1680ae 380 /**
bogdanm 86:04dd9b1680ae 381 * @}
bogdanm 86:04dd9b1680ae 382 */
bogdanm 86:04dd9b1680ae 383 #endif /* SYSCFG_RCR_PAGE0 */
bogdanm 86:04dd9b1680ae 384
bogdanm 92:4fc01daae5a5 385 /** @defgroup HAL_SYSCFG_Interrupts SYSCFG Interrupts
bogdanm 86:04dd9b1680ae 386 * @{
bogdanm 86:04dd9b1680ae 387 */
bogdanm 86:04dd9b1680ae 388 #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
bogdanm 86:04dd9b1680ae 389 #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
bogdanm 86:04dd9b1680ae 390 #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
bogdanm 86:04dd9b1680ae 391 #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
bogdanm 86:04dd9b1680ae 392 #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
bogdanm 86:04dd9b1680ae 393 #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
bogdanm 86:04dd9b1680ae 394
bogdanm 86:04dd9b1680ae 395 #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
bogdanm 86:04dd9b1680ae 396 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
bogdanm 86:04dd9b1680ae 397 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
bogdanm 86:04dd9b1680ae 398 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
bogdanm 86:04dd9b1680ae 399 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
bogdanm 86:04dd9b1680ae 400 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
bogdanm 86:04dd9b1680ae 401
bogdanm 86:04dd9b1680ae 402 /**
bogdanm 86:04dd9b1680ae 403 * @}
bogdanm 86:04dd9b1680ae 404 */
bogdanm 92:4fc01daae5a5 405
bogdanm 92:4fc01daae5a5 406 /**
bogdanm 92:4fc01daae5a5 407 * @}
bogdanm 92:4fc01daae5a5 408 */
bogdanm 86:04dd9b1680ae 409
bogdanm 86:04dd9b1680ae 410 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 411 /** @defgroup HAL_Exported_Macros HAL Exported Macros
bogdanm 92:4fc01daae5a5 412 * @{
bogdanm 86:04dd9b1680ae 413 */
bogdanm 86:04dd9b1680ae 414
bogdanm 92:4fc01daae5a5 415 /** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
bogdanm 92:4fc01daae5a5 416 * @{
bogdanm 92:4fc01daae5a5 417 */
bogdanm 86:04dd9b1680ae 418 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
bogdanm 86:04dd9b1680ae 419 #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
bogdanm 86:04dd9b1680ae 420 #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
bogdanm 86:04dd9b1680ae 421 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
bogdanm 86:04dd9b1680ae 422
bogdanm 86:04dd9b1680ae 423 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
bogdanm 86:04dd9b1680ae 424 #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
bogdanm 86:04dd9b1680ae 425 #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
bogdanm 86:04dd9b1680ae 426 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
bogdanm 86:04dd9b1680ae 427
bogdanm 86:04dd9b1680ae 428 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
bogdanm 86:04dd9b1680ae 429 #define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
bogdanm 86:04dd9b1680ae 430 #define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
bogdanm 86:04dd9b1680ae 431 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
bogdanm 86:04dd9b1680ae 432
bogdanm 86:04dd9b1680ae 433 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
bogdanm 86:04dd9b1680ae 434 #define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
bogdanm 86:04dd9b1680ae 435 #define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
bogdanm 86:04dd9b1680ae 436 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
bogdanm 86:04dd9b1680ae 437
bogdanm 86:04dd9b1680ae 438 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
bogdanm 86:04dd9b1680ae 439 #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
bogdanm 86:04dd9b1680ae 440 #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
bogdanm 86:04dd9b1680ae 441 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
bogdanm 86:04dd9b1680ae 442
bogdanm 86:04dd9b1680ae 443 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
bogdanm 86:04dd9b1680ae 444 #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
bogdanm 86:04dd9b1680ae 445 #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
bogdanm 86:04dd9b1680ae 446 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
bogdanm 86:04dd9b1680ae 447
bogdanm 86:04dd9b1680ae 448 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
bogdanm 86:04dd9b1680ae 449 #define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
bogdanm 86:04dd9b1680ae 450 #define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
bogdanm 86:04dd9b1680ae 451 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
bogdanm 86:04dd9b1680ae 452
bogdanm 86:04dd9b1680ae 453 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
bogdanm 86:04dd9b1680ae 454 #define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
bogdanm 86:04dd9b1680ae 455 #define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
bogdanm 86:04dd9b1680ae 456 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
bogdanm 86:04dd9b1680ae 457
bogdanm 86:04dd9b1680ae 458 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
bogdanm 86:04dd9b1680ae 459 #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
bogdanm 86:04dd9b1680ae 460 #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
bogdanm 86:04dd9b1680ae 461 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
bogdanm 86:04dd9b1680ae 462
bogdanm 92:4fc01daae5a5 463 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
bogdanm 92:4fc01daae5a5 464 #define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
bogdanm 92:4fc01daae5a5 465 #define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
bogdanm 92:4fc01daae5a5 466 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
bogdanm 86:04dd9b1680ae 467
bogdanm 92:4fc01daae5a5 468 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
bogdanm 92:4fc01daae5a5 469 #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
bogdanm 92:4fc01daae5a5 470 #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
bogdanm 92:4fc01daae5a5 471 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
bogdanm 86:04dd9b1680ae 472
bogdanm 92:4fc01daae5a5 473 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
bogdanm 92:4fc01daae5a5 474 #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
bogdanm 92:4fc01daae5a5 475 #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
bogdanm 92:4fc01daae5a5 476 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
bogdanm 86:04dd9b1680ae 477
bogdanm 92:4fc01daae5a5 478 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
bogdanm 92:4fc01daae5a5 479 #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
bogdanm 92:4fc01daae5a5 480 #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
bogdanm 92:4fc01daae5a5 481 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
bogdanm 86:04dd9b1680ae 482
bogdanm 86:04dd9b1680ae 483 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
bogdanm 86:04dd9b1680ae 484 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 485 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 486 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
bogdanm 86:04dd9b1680ae 487
bogdanm 86:04dd9b1680ae 488 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
bogdanm 86:04dd9b1680ae 489 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 490 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 491 #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
bogdanm 86:04dd9b1680ae 492
bogdanm 86:04dd9b1680ae 493 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
bogdanm 86:04dd9b1680ae 494 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 495 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 496 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
bogdanm 86:04dd9b1680ae 497
bogdanm 86:04dd9b1680ae 498 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
bogdanm 86:04dd9b1680ae 499 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
bogdanm 86:04dd9b1680ae 500 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
bogdanm 86:04dd9b1680ae 501 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
bogdanm 92:4fc01daae5a5 502 /**
bogdanm 92:4fc01daae5a5 503 * @}
bogdanm 92:4fc01daae5a5 504 */
bogdanm 92:4fc01daae5a5 505
bogdanm 92:4fc01daae5a5 506 /** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
bogdanm 92:4fc01daae5a5 507 * @{
bogdanm 92:4fc01daae5a5 508 */
bogdanm 92:4fc01daae5a5 509 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
bogdanm 92:4fc01daae5a5 510 #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
bogdanm 92:4fc01daae5a5 511 #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
bogdanm 92:4fc01daae5a5 512 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
bogdanm 86:04dd9b1680ae 513
bogdanm 92:4fc01daae5a5 514 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
bogdanm 92:4fc01daae5a5 515 #define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
bogdanm 92:4fc01daae5a5 516 #define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
bogdanm 92:4fc01daae5a5 517 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
bogdanm 86:04dd9b1680ae 518
bogdanm 92:4fc01daae5a5 519 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
bogdanm 92:4fc01daae5a5 520 #define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
bogdanm 92:4fc01daae5a5 521 #define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
bogdanm 92:4fc01daae5a5 522 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
bogdanm 92:4fc01daae5a5 523
bogdanm 92:4fc01daae5a5 524 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
bogdanm 92:4fc01daae5a5 525 #define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
bogdanm 92:4fc01daae5a5 526 #define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
bogdanm 92:4fc01daae5a5 527 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
bogdanm 92:4fc01daae5a5 528
bogdanm 92:4fc01daae5a5 529 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
bogdanm 92:4fc01daae5a5 530 #define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
bogdanm 92:4fc01daae5a5 531 #define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
bogdanm 92:4fc01daae5a5 532 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
bogdanm 92:4fc01daae5a5 535 #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
bogdanm 92:4fc01daae5a5 536 #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
bogdanm 92:4fc01daae5a5 537 #endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
bogdanm 92:4fc01daae5a5 538
bogdanm 92:4fc01daae5a5 539 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
bogdanm 92:4fc01daae5a5 540 #define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
bogdanm 92:4fc01daae5a5 541 #define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
bogdanm 92:4fc01daae5a5 542 #endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
bogdanm 92:4fc01daae5a5 543 /**
bogdanm 92:4fc01daae5a5 544 * @}
bogdanm 92:4fc01daae5a5 545 */
bogdanm 92:4fc01daae5a5 546
bogdanm 92:4fc01daae5a5 547 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
bogdanm 92:4fc01daae5a5 548 * @{
bogdanm 92:4fc01daae5a5 549 */
bogdanm 86:04dd9b1680ae 550 #if defined(SYSCFG_CFGR1_MEM_MODE)
bogdanm 86:04dd9b1680ae 551 /** @brief Main Flash memory mapped at 0x00000000
bogdanm 86:04dd9b1680ae 552 */
bogdanm 86:04dd9b1680ae 553 #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
bogdanm 86:04dd9b1680ae 554 #endif /* SYSCFG_CFGR1_MEM_MODE */
bogdanm 86:04dd9b1680ae 555
bogdanm 86:04dd9b1680ae 556 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
bogdanm 86:04dd9b1680ae 557 /** @brief System Flash memory mapped at 0x00000000
bogdanm 86:04dd9b1680ae 558 */
bogdanm 86:04dd9b1680ae 559 #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
bogdanm 86:04dd9b1680ae 560 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
bogdanm 86:04dd9b1680ae 561 }while(0)
bogdanm 86:04dd9b1680ae 562 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
bogdanm 86:04dd9b1680ae 563
bogdanm 86:04dd9b1680ae 564 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
bogdanm 86:04dd9b1680ae 565 /** @brief Embedded SRAM mapped at 0x00000000
bogdanm 86:04dd9b1680ae 566 */
bogdanm 86:04dd9b1680ae 567 #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
bogdanm 86:04dd9b1680ae 568 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
bogdanm 86:04dd9b1680ae 569 }while(0)
bogdanm 86:04dd9b1680ae 570 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
bogdanm 86:04dd9b1680ae 571
bogdanm 92:4fc01daae5a5 572 #if defined(SYSCFG_CFGR1_MEM_MODE_2)
bogdanm 92:4fc01daae5a5 573 #define __HAL_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
bogdanm 92:4fc01daae5a5 574 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
bogdanm 92:4fc01daae5a5 575 }while(0)
bogdanm 92:4fc01daae5a5 576 #endif /* SYSCFG_CFGR1_MEM_MODE_2 */
bogdanm 92:4fc01daae5a5 577 /**
bogdanm 92:4fc01daae5a5 578 * @}
bogdanm 92:4fc01daae5a5 579 */
bogdanm 92:4fc01daae5a5 580
bogdanm 92:4fc01daae5a5 581 /** @defgroup Encoder_Mode Encoder Mode
bogdanm 92:4fc01daae5a5 582 * @{
bogdanm 92:4fc01daae5a5 583 */
bogdanm 86:04dd9b1680ae 584 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
bogdanm 86:04dd9b1680ae 585 /** @brief No Encoder mode
bogdanm 86:04dd9b1680ae 586 */
bogdanm 86:04dd9b1680ae 587 #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
bogdanm 86:04dd9b1680ae 588 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
bogdanm 86:04dd9b1680ae 589
bogdanm 86:04dd9b1680ae 590 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
bogdanm 86:04dd9b1680ae 591 /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
bogdanm 86:04dd9b1680ae 592 */
bogdanm 86:04dd9b1680ae 593 #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
bogdanm 86:04dd9b1680ae 594 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
bogdanm 86:04dd9b1680ae 595 }while(0)
bogdanm 86:04dd9b1680ae 596 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
bogdanm 86:04dd9b1680ae 597
bogdanm 86:04dd9b1680ae 598 #if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
bogdanm 86:04dd9b1680ae 599 /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
bogdanm 86:04dd9b1680ae 600 */
bogdanm 86:04dd9b1680ae 601 #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
bogdanm 86:04dd9b1680ae 602 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
bogdanm 86:04dd9b1680ae 603 }while(0)
bogdanm 86:04dd9b1680ae 604 #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
bogdanm 86:04dd9b1680ae 605
bogdanm 86:04dd9b1680ae 606 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
bogdanm 86:04dd9b1680ae 607 /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
bogdanm 86:04dd9b1680ae 608 */
bogdanm 86:04dd9b1680ae 609 #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
bogdanm 86:04dd9b1680ae 610 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
bogdanm 86:04dd9b1680ae 611 }while(0)
bogdanm 86:04dd9b1680ae 612 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
bogdanm 92:4fc01daae5a5 613 /**
bogdanm 92:4fc01daae5a5 614 * @}
bogdanm 92:4fc01daae5a5 615 */
bogdanm 92:4fc01daae5a5 616
bogdanm 92:4fc01daae5a5 617 /** @defgroup DMA_Remap_Enable DMA Remap Enable
bogdanm 92:4fc01daae5a5 618 * @{
bogdanm 92:4fc01daae5a5 619 */
bogdanm 86:04dd9b1680ae 620 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 86:04dd9b1680ae 621 /** @brief DMA remapping enable/disable macros
bogdanm 86:04dd9b1680ae 622 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
bogdanm 86:04dd9b1680ae 623 */
bogdanm 86:04dd9b1680ae 624 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 625 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 626 (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 627 (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 628 }while(0)
bogdanm 86:04dd9b1680ae 629 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 630 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 631 (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 632 (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 633 }while(0)
bogdanm 86:04dd9b1680ae 634 #elif defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 86:04dd9b1680ae 635 /** @brief DMA remapping enable/disable macros
bogdanm 86:04dd9b1680ae 636 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
bogdanm 86:04dd9b1680ae 637 */
bogdanm 86:04dd9b1680ae 638 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 639 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
bogdanm 86:04dd9b1680ae 640 }while(0)
bogdanm 86:04dd9b1680ae 641 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 642 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
bogdanm 86:04dd9b1680ae 643 }while(0)
bogdanm 86:04dd9b1680ae 644 #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
bogdanm 92:4fc01daae5a5 645 /**
bogdanm 92:4fc01daae5a5 646 * @}
bogdanm 92:4fc01daae5a5 647 */
bogdanm 92:4fc01daae5a5 648
bogdanm 92:4fc01daae5a5 649 /** @defgroup I2C2_Fast_Mode_Plus_Enable I2C2 Fast Mode Plus Enable
bogdanm 92:4fc01daae5a5 650 * @{
bogdanm 92:4fc01daae5a5 651 */
bogdanm 86:04dd9b1680ae 652 /** @brief Fast mode Plus driving capability enable/disable macros
bogdanm 86:04dd9b1680ae 653 * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
bogdanm 86:04dd9b1680ae 654 */
bogdanm 86:04dd9b1680ae 655 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
bogdanm 86:04dd9b1680ae 656 SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
bogdanm 86:04dd9b1680ae 657 }while(0)
bogdanm 86:04dd9b1680ae 658
bogdanm 86:04dd9b1680ae 659 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
bogdanm 86:04dd9b1680ae 660 SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
bogdanm 86:04dd9b1680ae 661 }while(0)
bogdanm 92:4fc01daae5a5 662 /**
bogdanm 92:4fc01daae5a5 663 * @}
bogdanm 92:4fc01daae5a5 664 */
bogdanm 86:04dd9b1680ae 665
bogdanm 92:4fc01daae5a5 666 /** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
bogdanm 92:4fc01daae5a5 667 * @{
bogdanm 92:4fc01daae5a5 668 */
bogdanm 86:04dd9b1680ae 669 /** @brief SYSCFG interrupt enable/disable macros
bogdanm 86:04dd9b1680ae 670 * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
bogdanm 86:04dd9b1680ae 671 */
bogdanm 86:04dd9b1680ae 672 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
bogdanm 86:04dd9b1680ae 673 SYSCFG->CFGR1 |= (__INTERRUPT__); \
bogdanm 86:04dd9b1680ae 674 }while(0)
bogdanm 86:04dd9b1680ae 675
bogdanm 86:04dd9b1680ae 676 #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
bogdanm 86:04dd9b1680ae 677 SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
bogdanm 86:04dd9b1680ae 678 }while(0)
bogdanm 92:4fc01daae5a5 679 /**
bogdanm 92:4fc01daae5a5 680 * @}
bogdanm 92:4fc01daae5a5 681 */
bogdanm 92:4fc01daae5a5 682
bogdanm 86:04dd9b1680ae 683 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
bogdanm 92:4fc01daae5a5 684 /** @defgroup USB_Interrupt_Remap USB Interrupt Remap
bogdanm 92:4fc01daae5a5 685 * @{
bogdanm 92:4fc01daae5a5 686 */
bogdanm 86:04dd9b1680ae 687 /** @brief USB interrupt remapping enable/disable macros
bogdanm 86:04dd9b1680ae 688 */
bogdanm 86:04dd9b1680ae 689 #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
bogdanm 86:04dd9b1680ae 690 #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
bogdanm 92:4fc01daae5a5 691 /**
bogdanm 92:4fc01daae5a5 692 * @}
bogdanm 92:4fc01daae5a5 693 */
bogdanm 86:04dd9b1680ae 694 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
bogdanm 92:4fc01daae5a5 695
bogdanm 86:04dd9b1680ae 696 #if defined(SYSCFG_CFGR1_VBAT)
bogdanm 92:4fc01daae5a5 697 /** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
bogdanm 92:4fc01daae5a5 698 * @{
bogdanm 92:4fc01daae5a5 699 */
bogdanm 86:04dd9b1680ae 700 /** @brief SYSCFG interrupt enable/disable macros
bogdanm 86:04dd9b1680ae 701 */
bogdanm 86:04dd9b1680ae 702 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
bogdanm 86:04dd9b1680ae 703 #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
bogdanm 92:4fc01daae5a5 704 /**
bogdanm 92:4fc01daae5a5 705 * @}
bogdanm 92:4fc01daae5a5 706 */
bogdanm 86:04dd9b1680ae 707 #endif /* SYSCFG_CFGR1_VBAT */
bogdanm 92:4fc01daae5a5 708
bogdanm 86:04dd9b1680ae 709 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
bogdanm 92:4fc01daae5a5 710 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
bogdanm 92:4fc01daae5a5 711 * @{
bogdanm 92:4fc01daae5a5 712 */
bogdanm 86:04dd9b1680ae 713 /** @brief SYSCFG Break Lockup lock
bogdanm 86:04dd9b1680ae 714 * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
bogdanm 86:04dd9b1680ae 715 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 86:04dd9b1680ae 716 */
bogdanm 86:04dd9b1680ae 717 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
bogdanm 86:04dd9b1680ae 718 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
bogdanm 86:04dd9b1680ae 719 }while(0)
bogdanm 92:4fc01daae5a5 720 /**
bogdanm 92:4fc01daae5a5 721 * @}
bogdanm 92:4fc01daae5a5 722 */
bogdanm 86:04dd9b1680ae 723 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
bogdanm 92:4fc01daae5a5 724
bogdanm 86:04dd9b1680ae 725 #if defined(SYSCFG_CFGR2_PVD_LOCK)
bogdanm 92:4fc01daae5a5 726 /** @defgroup PVD_Lock_Enable PVD Lock
bogdanm 92:4fc01daae5a5 727 * @{
bogdanm 92:4fc01daae5a5 728 */
bogdanm 86:04dd9b1680ae 729 /** @brief SYSCFG Break PVD lock
bogdanm 86:04dd9b1680ae 730 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
bogdanm 86:04dd9b1680ae 731 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 86:04dd9b1680ae 732 */
bogdanm 86:04dd9b1680ae 733 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
bogdanm 86:04dd9b1680ae 734 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
bogdanm 86:04dd9b1680ae 735 }while(0)
bogdanm 92:4fc01daae5a5 736 /**
bogdanm 92:4fc01daae5a5 737 * @}
bogdanm 92:4fc01daae5a5 738 */
bogdanm 86:04dd9b1680ae 739 #endif /* SYSCFG_CFGR2_PVD_LOCK */
bogdanm 86:04dd9b1680ae 740
bogdanm 86:04dd9b1680ae 741 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
bogdanm 92:4fc01daae5a5 742 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
bogdanm 92:4fc01daae5a5 743 * @{
bogdanm 92:4fc01daae5a5 744 */
bogdanm 86:04dd9b1680ae 745 /** @brief SYSCFG Break SRAM PARITY lock
bogdanm 86:04dd9b1680ae 746 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
bogdanm 86:04dd9b1680ae 747 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 86:04dd9b1680ae 748 */
bogdanm 86:04dd9b1680ae 749 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
bogdanm 86:04dd9b1680ae 750 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
bogdanm 86:04dd9b1680ae 751 }while(0)
bogdanm 92:4fc01daae5a5 752 /**
bogdanm 92:4fc01daae5a5 753 * @}
bogdanm 92:4fc01daae5a5 754 */
bogdanm 86:04dd9b1680ae 755 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
bogdanm 92:4fc01daae5a5 756
bogdanm 92:4fc01daae5a5 757 /** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
bogdanm 92:4fc01daae5a5 758 * @{
bogdanm 92:4fc01daae5a5 759 */
bogdanm 86:04dd9b1680ae 760 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
bogdanm 86:04dd9b1680ae 761 /** @brief Trigger remapping enable/disable macros
bogdanm 86:04dd9b1680ae 762 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
bogdanm 86:04dd9b1680ae 763 */
bogdanm 86:04dd9b1680ae 764 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 765 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 766 (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 767 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 768 }while(0)
bogdanm 86:04dd9b1680ae 769 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 770 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 771 (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 772 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 773 }while(0)
bogdanm 86:04dd9b1680ae 774 #else
bogdanm 86:04dd9b1680ae 775 /** @brief Trigger remapping enable/disable macros
bogdanm 86:04dd9b1680ae 776 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
bogdanm 86:04dd9b1680ae 777 */
bogdanm 86:04dd9b1680ae 778 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 779 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
bogdanm 86:04dd9b1680ae 780 }while(0)
bogdanm 86:04dd9b1680ae 781 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 782 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
bogdanm 86:04dd9b1680ae 783 }while(0)
bogdanm 86:04dd9b1680ae 784 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
bogdanm 92:4fc01daae5a5 785 /**
bogdanm 92:4fc01daae5a5 786 * @}
bogdanm 92:4fc01daae5a5 787 */
bogdanm 92:4fc01daae5a5 788
bogdanm 92:4fc01daae5a5 789 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
bogdanm 92:4fc01daae5a5 790 /** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
bogdanm 92:4fc01daae5a5 791 * @{
bogdanm 92:4fc01daae5a5 792 */
bogdanm 92:4fc01daae5a5 793 /** @brief ADC trigger remapping enable/disable macros
bogdanm 92:4fc01daae5a5 794 * @param __ADCTRIGGER_REMAP__: This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
bogdanm 92:4fc01daae5a5 795 */
bogdanm 92:4fc01daae5a5 796 #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
bogdanm 92:4fc01daae5a5 797 (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
bogdanm 92:4fc01daae5a5 798 }while(0)
bogdanm 92:4fc01daae5a5 799 #define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
bogdanm 92:4fc01daae5a5 800 (SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
bogdanm 92:4fc01daae5a5 801 }while(0)
bogdanm 92:4fc01daae5a5 802 /**
bogdanm 92:4fc01daae5a5 803 * @}
bogdanm 92:4fc01daae5a5 804 */
bogdanm 92:4fc01daae5a5 805 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 86:04dd9b1680ae 806
bogdanm 86:04dd9b1680ae 807 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
bogdanm 92:4fc01daae5a5 808 /** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
bogdanm 92:4fc01daae5a5 809 * @{
bogdanm 92:4fc01daae5a5 810 */
bogdanm 86:04dd9b1680ae 811 /**
bogdanm 86:04dd9b1680ae 812 * @brief Parity check on RAM disable macro
bogdanm 86:04dd9b1680ae 813 * @note Disabling the parity check on RAM locks the configuration bit.
bogdanm 86:04dd9b1680ae 814 * To re-enable the parity check on RAM perform a system reset.
bogdanm 86:04dd9b1680ae 815 */
bogdanm 86:04dd9b1680ae 816 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 817 /**
bogdanm 92:4fc01daae5a5 818 * @}
bogdanm 92:4fc01daae5a5 819 */
bogdanm 86:04dd9b1680ae 820 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
bogdanm 92:4fc01daae5a5 821
bogdanm 86:04dd9b1680ae 822 #if defined(SYSCFG_RCR_PAGE0)
bogdanm 92:4fc01daae5a5 823 /** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
bogdanm 92:4fc01daae5a5 824 * @{
bogdanm 92:4fc01daae5a5 825 */
bogdanm 86:04dd9b1680ae 826 /** @brief CCM RAM page write protection enable macro
bogdanm 86:04dd9b1680ae 827 * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
bogdanm 86:04dd9b1680ae 828 * @note write protection can only be disabled by a system reset
bogdanm 86:04dd9b1680ae 829 */
bogdanm 86:04dd9b1680ae 830 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
bogdanm 86:04dd9b1680ae 831 SYSCFG->RCR |= (__PAGE_WP__); \
bogdanm 86:04dd9b1680ae 832 }while(0)
bogdanm 92:4fc01daae5a5 833 /**
bogdanm 92:4fc01daae5a5 834 * @}
bogdanm 92:4fc01daae5a5 835 */
bogdanm 86:04dd9b1680ae 836 #endif /* SYSCFG_RCR_PAGE0 */
bogdanm 92:4fc01daae5a5 837
bogdanm 92:4fc01daae5a5 838 /**
bogdanm 92:4fc01daae5a5 839 * @}
bogdanm 92:4fc01daae5a5 840 */
bogdanm 92:4fc01daae5a5 841 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 842 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
bogdanm 92:4fc01daae5a5 843 * @{
bogdanm 92:4fc01daae5a5 844 */
bogdanm 86:04dd9b1680ae 845
bogdanm 92:4fc01daae5a5 846 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
bogdanm 92:4fc01daae5a5 847 * @brief Initialization and de-initialization functions
bogdanm 92:4fc01daae5a5 848 * @{
bogdanm 92:4fc01daae5a5 849 */
bogdanm 86:04dd9b1680ae 850 /* Initialization and de-initialization functions ******************************/
bogdanm 86:04dd9b1680ae 851 HAL_StatusTypeDef HAL_Init(void);
bogdanm 86:04dd9b1680ae 852 HAL_StatusTypeDef HAL_DeInit(void);
bogdanm 86:04dd9b1680ae 853 void HAL_MspInit(void);
bogdanm 86:04dd9b1680ae 854 void HAL_MspDeInit(void);
bogdanm 86:04dd9b1680ae 855 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
bogdanm 92:4fc01daae5a5 856 /**
bogdanm 92:4fc01daae5a5 857 * @}
bogdanm 92:4fc01daae5a5 858 */
bogdanm 92:4fc01daae5a5 859
bogdanm 92:4fc01daae5a5 860 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
bogdanm 92:4fc01daae5a5 861 * @brief HAL Control functions
bogdanm 92:4fc01daae5a5 862 * @{
bogdanm 92:4fc01daae5a5 863 */
bogdanm 86:04dd9b1680ae 864 /* Peripheral Control functions ************************************************/
bogdanm 86:04dd9b1680ae 865 void HAL_IncTick(void);
bogdanm 86:04dd9b1680ae 866 void HAL_Delay(__IO uint32_t Delay);
bogdanm 86:04dd9b1680ae 867 void HAL_SuspendTick(void);
bogdanm 86:04dd9b1680ae 868 void HAL_ResumeTick(void);
bogdanm 86:04dd9b1680ae 869 uint32_t HAL_GetTick(void);
bogdanm 86:04dd9b1680ae 870 uint32_t HAL_GetHalVersion(void);
bogdanm 86:04dd9b1680ae 871 uint32_t HAL_GetREVID(void);
bogdanm 86:04dd9b1680ae 872 uint32_t HAL_GetDEVID(void);
bogdanm 86:04dd9b1680ae 873 void HAL_EnableDBGSleepMode(void);
bogdanm 86:04dd9b1680ae 874 void HAL_DisableDBGSleepMode(void);
bogdanm 86:04dd9b1680ae 875 void HAL_EnableDBGStopMode(void);
bogdanm 86:04dd9b1680ae 876 void HAL_DisableDBGStopMode(void);
bogdanm 86:04dd9b1680ae 877 void HAL_EnableDBGStandbyMode(void);
bogdanm 86:04dd9b1680ae 878 void HAL_DisableDBGStandbyMode(void);
bogdanm 92:4fc01daae5a5 879 /**
bogdanm 92:4fc01daae5a5 880 * @}
bogdanm 92:4fc01daae5a5 881 */
bogdanm 86:04dd9b1680ae 882
bogdanm 92:4fc01daae5a5 883 /**
bogdanm 92:4fc01daae5a5 884 * @}
bogdanm 92:4fc01daae5a5 885 */
bogdanm 86:04dd9b1680ae 886
bogdanm 86:04dd9b1680ae 887 /**
bogdanm 86:04dd9b1680ae 888 * @}
bogdanm 86:04dd9b1680ae 889 */
bogdanm 86:04dd9b1680ae 890
bogdanm 86:04dd9b1680ae 891 /**
bogdanm 86:04dd9b1680ae 892 * @}
bogdanm 86:04dd9b1680ae 893 */
bogdanm 86:04dd9b1680ae 894
bogdanm 86:04dd9b1680ae 895 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 896 }
bogdanm 86:04dd9b1680ae 897 #endif
bogdanm 86:04dd9b1680ae 898
bogdanm 86:04dd9b1680ae 899 #endif /* __STM32F3xx_HAL_H */
bogdanm 86:04dd9b1680ae 900
bogdanm 86:04dd9b1680ae 901 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/