The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

Committer:
bogdanm
Date:
Wed Jul 02 13:22:23 2014 +0100
Revision:
86:04dd9b1680ae
Child:
92:4fc01daae5a5
Release 86 of the mbed library

Main changes:


- bug fixes in various backends
- mbed "error" replaced by assert logic (mbed_assert)
- new ST Nucleo targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.0.1
bogdanm 86:04dd9b1680ae 6 * @date 18-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief This file contains all the functions prototypes for the HAL
bogdanm 86:04dd9b1680ae 8 * module driver.
bogdanm 86:04dd9b1680ae 9 ******************************************************************************
bogdanm 86:04dd9b1680ae 10 * @attention
bogdanm 86:04dd9b1680ae 11 *
bogdanm 86:04dd9b1680ae 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 13 *
bogdanm 86:04dd9b1680ae 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 15 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 17 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 20 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 22 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 23 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 24 *
bogdanm 86:04dd9b1680ae 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 35 *
bogdanm 86:04dd9b1680ae 36 ******************************************************************************
bogdanm 86:04dd9b1680ae 37 */
bogdanm 86:04dd9b1680ae 38
bogdanm 86:04dd9b1680ae 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 40 #ifndef __STM32F3xx_HAL_H
bogdanm 86:04dd9b1680ae 41 #define __STM32F3xx_HAL_H
bogdanm 86:04dd9b1680ae 42
bogdanm 86:04dd9b1680ae 43 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 44 extern "C" {
bogdanm 86:04dd9b1680ae 45 #endif
bogdanm 86:04dd9b1680ae 46
bogdanm 86:04dd9b1680ae 47 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 48 #include "stm32f3xx_hal_conf.h"
bogdanm 86:04dd9b1680ae 49
bogdanm 86:04dd9b1680ae 50 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 51 * @{
bogdanm 86:04dd9b1680ae 52 */
bogdanm 86:04dd9b1680ae 53
bogdanm 86:04dd9b1680ae 54 /** @addtogroup HAL
bogdanm 86:04dd9b1680ae 55 * @{
bogdanm 86:04dd9b1680ae 56 */
bogdanm 86:04dd9b1680ae 57
bogdanm 86:04dd9b1680ae 58 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 59 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 60
bogdanm 86:04dd9b1680ae 61 /** @defgroup SYSCFG_BitAddress_AliasRegion
bogdanm 86:04dd9b1680ae 62 * @brief SYSCFG registers bit address in the alias region
bogdanm 86:04dd9b1680ae 63 * @{
bogdanm 86:04dd9b1680ae 64 */
bogdanm 86:04dd9b1680ae 65 /* ------------ SYSCFG registers bit address in the alias region -------------*/
bogdanm 86:04dd9b1680ae 66 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
bogdanm 86:04dd9b1680ae 67 /* --- CFGR2 Register ---*/
bogdanm 86:04dd9b1680ae 68 /* Alias word address of BYP_ADDR_PAR bit */
bogdanm 86:04dd9b1680ae 69 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
bogdanm 86:04dd9b1680ae 70 #define BYPADDRPAR_BitNumber 0x04
bogdanm 86:04dd9b1680ae 71 #define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
bogdanm 86:04dd9b1680ae 72 /**
bogdanm 86:04dd9b1680ae 73 * @}
bogdanm 86:04dd9b1680ae 74 */
bogdanm 86:04dd9b1680ae 75
bogdanm 86:04dd9b1680ae 76 #if defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 86:04dd9b1680ae 77 /** @defgroup HAL_DMA_Remapping
bogdanm 86:04dd9b1680ae 78 * Elements values convention: 0xXXYYYYYY
bogdanm 86:04dd9b1680ae 79 * - YYYYYY : Position in the register
bogdanm 86:04dd9b1680ae 80 * - XX : Register index
bogdanm 86:04dd9b1680ae 81 * - 00: CFGR1 register in SYSCFG
bogdanm 86:04dd9b1680ae 82 * - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
bogdanm 86:04dd9b1680ae 83 * @{
bogdanm 86:04dd9b1680ae 84 */
bogdanm 86:04dd9b1680ae 85 #define HAL_REMAPDMA_ADC24_DMA2_CH34 ((uint32_t)0x00000100) /*!< ADC24 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
bogdanm 86:04dd9b1680ae 86 1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
bogdanm 86:04dd9b1680ae 87 #define HAL_REMAPDMA_TIM16_DMA1_CH6 ((uint32_t)0x00000800) /*!< TIM16 DMA request remap
bogdanm 86:04dd9b1680ae 88 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
bogdanm 86:04dd9b1680ae 89 #define HAL_REMAPDMA_TIM17_DMA1_CH7 ((uint32_t)0x00001000) /*!< TIM17 DMA request remap
bogdanm 86:04dd9b1680ae 90 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
bogdanm 86:04dd9b1680ae 91 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 ((uint32_t)0x00002000) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
bogdanm 86:04dd9b1680ae 92 1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
bogdanm 86:04dd9b1680ae 93 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 ((uint32_t)0x00004000) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E and STM32F358xx devices)
bogdanm 86:04dd9b1680ae 94 1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
bogdanm 86:04dd9b1680ae 95 #define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 96 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
bogdanm 86:04dd9b1680ae 97 #define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 ((uint32_t)0x00008000) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 98 1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
bogdanm 86:04dd9b1680ae 99 #if defined(SYSCFG_CFGR3_DMA_RMP)
bogdanm 86:04dd9b1680ae 100 #if !defined(HAL_REMAP_CFGR3_MASK)
bogdanm 86:04dd9b1680ae 101 #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 102 #endif
bogdanm 86:04dd9b1680ae 103
bogdanm 86:04dd9b1680ae 104 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 ((uint32_t)0x01000003) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 105 11: Map on DMA1 channel 2 */
bogdanm 86:04dd9b1680ae 106 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 ((uint32_t)0x01000001) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 107 01: Map on DMA1 channel 4 */
bogdanm 86:04dd9b1680ae 108 #define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 ((uint32_t)0x01000002) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 109 10: Map on DMA1 channel 6 */
bogdanm 86:04dd9b1680ae 110 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 ((uint32_t)0x0100000C) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 111 11: Map on DMA1 channel 3 */
bogdanm 86:04dd9b1680ae 112 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 ((uint32_t)0x01000004) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 113 01: Map on DMA1 channel 5 */
bogdanm 86:04dd9b1680ae 114 #define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 ((uint32_t)0x01000008) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 115 10: Map on DMA1 channel 7 */
bogdanm 86:04dd9b1680ae 116 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 ((uint32_t)0x01000030) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 117 11: Map on DMA1 channel 7 */
bogdanm 86:04dd9b1680ae 118 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 ((uint32_t)0x01000010) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 119 01: Map on DMA1 channel 3 */
bogdanm 86:04dd9b1680ae 120 #define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 ((uint32_t)0x01000020) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 121 10: Map on DMA1 channel 5 */
bogdanm 86:04dd9b1680ae 122 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 ((uint32_t)0x010000C0) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 123 11: Map on DMA1 channel 6 */
bogdanm 86:04dd9b1680ae 124 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 ((uint32_t)0x01000040) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 125 01: Map on DMA1 channel 2 */
bogdanm 86:04dd9b1680ae 126 #define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 ((uint32_t)0x01000080) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
bogdanm 86:04dd9b1680ae 127 10: Map on DMA1 channel 4 */
bogdanm 86:04dd9b1680ae 128 #define HAL_REMAPDMA_ADC2_DMA1_CH2 ((uint32_t)0x01000100) /*!< ADC2 DMA remap
bogdanm 86:04dd9b1680ae 129 x0: No remap (ADC2 on DMA2)
bogdanm 86:04dd9b1680ae 130 10: Map on DMA1 channel 2 */
bogdanm 86:04dd9b1680ae 131 #define HAL_REMAPDMA_ADC2_DMA1_CH4 ((uint32_t)0x01000300) /*!< ADC2 DMA remap
bogdanm 86:04dd9b1680ae 132 11: Map on DMA1 channel 4 */
bogdanm 86:04dd9b1680ae 133 #endif /* SYSCFG_CFGR3_DMA_RMP */
bogdanm 86:04dd9b1680ae 134
bogdanm 86:04dd9b1680ae 135 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 86:04dd9b1680ae 136 #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
bogdanm 86:04dd9b1680ae 137 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 138 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 139 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 140 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 141 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 142 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 143 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
bogdanm 86:04dd9b1680ae 144 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 145 (((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 146 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 147 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 148 (((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 149 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 150 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 151 (((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 152 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 153 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
bogdanm 86:04dd9b1680ae 154 (((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 155 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
bogdanm 86:04dd9b1680ae 156 (((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
bogdanm 86:04dd9b1680ae 157 #elif defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 86:04dd9b1680ae 158 #define IS_HAL_REMAPDMA(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
bogdanm 86:04dd9b1680ae 159 (((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
bogdanm 86:04dd9b1680ae 160 (((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
bogdanm 86:04dd9b1680ae 161 (((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
bogdanm 86:04dd9b1680ae 162 (((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
bogdanm 86:04dd9b1680ae 163 (((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
bogdanm 86:04dd9b1680ae 164 (((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
bogdanm 86:04dd9b1680ae 165 #endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
bogdanm 86:04dd9b1680ae 166 /**
bogdanm 86:04dd9b1680ae 167 * @}
bogdanm 86:04dd9b1680ae 168 */
bogdanm 86:04dd9b1680ae 169 #endif /* SYSCFG_CFGR1_DMA_RMP */
bogdanm 86:04dd9b1680ae 170
bogdanm 86:04dd9b1680ae 171 /** @defgroup HAL_Trigger_Remapping
bogdanm 86:04dd9b1680ae 172 * Elements values convention: 0xXXYYYYYY
bogdanm 86:04dd9b1680ae 173 * - YYYYYY : Position in the register
bogdanm 86:04dd9b1680ae 174 * - XX : Register index
bogdanm 86:04dd9b1680ae 175 * - 00: CFGR1 register in SYSCFG
bogdanm 86:04dd9b1680ae 176 * - 01: CFGR3 register in SYSCFG
bogdanm 86:04dd9b1680ae 177 * @{
bogdanm 86:04dd9b1680ae 178 */
bogdanm 86:04dd9b1680ae 179 #define HAL_REMAPTRIGGER_DAC1_TRIG ((uint32_t)0x00000080) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
bogdanm 86:04dd9b1680ae 180 0: No remap (DAC trigger is TIM8_TRGO)
bogdanm 86:04dd9b1680ae 181 1: Remap (DAC trigger is TIM3_TRGO) */
bogdanm 86:04dd9b1680ae 182 #define HAL_REMAPTRIGGER_TIM1_ITR3 ((uint32_t)0x00000040) /*!< TIM1 ITR3 trigger remap
bogdanm 86:04dd9b1680ae 183 0: No remap
bogdanm 86:04dd9b1680ae 184 1: Remap (TIM1_TRG3 = TIM17_OC) */
bogdanm 86:04dd9b1680ae 185 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
bogdanm 86:04dd9b1680ae 186 #if !defined(HAL_REMAP_CFGR3_MASK)
bogdanm 86:04dd9b1680ae 187 #define HAL_REMAP_CFGR3_MASK ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 188 #endif
bogdanm 86:04dd9b1680ae 189 #define HAL_REMAPTRIGGER_DAC1_TRIG3 ((uint32_t)0x01010000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
bogdanm 86:04dd9b1680ae 190 0: Remap (DAC trigger is TIM15_TRGO)
bogdanm 86:04dd9b1680ae 191 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
bogdanm 86:04dd9b1680ae 192 #define HAL_REMAPTRIGGER_DAC1_TRIG5 ((uint32_t)0x01020000) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
bogdanm 86:04dd9b1680ae 193 0: No remap
bogdanm 86:04dd9b1680ae 194 1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
bogdanm 86:04dd9b1680ae 195 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
bogdanm 86:04dd9b1680ae 196
bogdanm 86:04dd9b1680ae 197 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
bogdanm 86:04dd9b1680ae 198 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
bogdanm 86:04dd9b1680ae 199 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
bogdanm 86:04dd9b1680ae 200 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
bogdanm 86:04dd9b1680ae 201 (((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
bogdanm 86:04dd9b1680ae 202 #else
bogdanm 86:04dd9b1680ae 203 #define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
bogdanm 86:04dd9b1680ae 204 (((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
bogdanm 86:04dd9b1680ae 205 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
bogdanm 86:04dd9b1680ae 206 /**
bogdanm 86:04dd9b1680ae 207 * @}
bogdanm 86:04dd9b1680ae 208 */
bogdanm 86:04dd9b1680ae 209
bogdanm 86:04dd9b1680ae 210 /** @defgroup HAL_FastModePlus_I2C
bogdanm 86:04dd9b1680ae 211 * @{
bogdanm 86:04dd9b1680ae 212 */
bogdanm 86:04dd9b1680ae 213 #if defined(SYSCFG_CFGR1_I2C1_FMP)
bogdanm 86:04dd9b1680ae 214 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 ((uint32_t)SYSCFG_CFGR1_I2C1_FMP) /*!< I2C1 fast mode Plus driving capability activation
bogdanm 86:04dd9b1680ae 215 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
bogdanm 86:04dd9b1680ae 216 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
bogdanm 86:04dd9b1680ae 217 #endif /* SYSCFG_CFGR1_I2C1_FMP */
bogdanm 86:04dd9b1680ae 218
bogdanm 86:04dd9b1680ae 219 #if defined(SYSCFG_CFGR1_I2C2_FMP)
bogdanm 86:04dd9b1680ae 220 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 ((uint32_t)SYSCFG_CFGR1_I2C2_FMP) /*!< I2C2 fast mode Plus driving capability activation
bogdanm 86:04dd9b1680ae 221 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
bogdanm 86:04dd9b1680ae 222 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
bogdanm 86:04dd9b1680ae 223 #endif /* SYSCFG_CFGR1_I2C2_FMP */
bogdanm 86:04dd9b1680ae 224
bogdanm 86:04dd9b1680ae 225 #if defined(SYSCFG_CFGR1_I2C3_FMP)
bogdanm 86:04dd9b1680ae 226 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 ((uint32_t)SYSCFG_CFGR1_I2C3_FMP) /*!< I2C3 fast mode Plus driving capability activation
bogdanm 86:04dd9b1680ae 227 0: FM+ mode is not enabled on I2C3 pins selected through AF selection bits
bogdanm 86:04dd9b1680ae 228 1: FM+ mode is enabled on I2C3 pins selected through AF selection bits */
bogdanm 86:04dd9b1680ae 229 #endif /* SYSCFG_CFGR1_I2C3_FMP */
bogdanm 86:04dd9b1680ae 230
bogdanm 86:04dd9b1680ae 231 #if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
bogdanm 86:04dd9b1680ae 232 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 233 0: PB6 pin operates in standard mode
bogdanm 86:04dd9b1680ae 234 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 235 #endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
bogdanm 86:04dd9b1680ae 236
bogdanm 86:04dd9b1680ae 237 #if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
bogdanm 86:04dd9b1680ae 238 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 239 0: PB7 pin operates in standard mode
bogdanm 86:04dd9b1680ae 240 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 241 #endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
bogdanm 86:04dd9b1680ae 242
bogdanm 86:04dd9b1680ae 243 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
bogdanm 86:04dd9b1680ae 244 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 245 0: PB8 pin operates in standard mode
bogdanm 86:04dd9b1680ae 246 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 247 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
bogdanm 86:04dd9b1680ae 248
bogdanm 86:04dd9b1680ae 249 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
bogdanm 86:04dd9b1680ae 250 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
bogdanm 86:04dd9b1680ae 251 0: PB9 pin operates in standard mode
bogdanm 86:04dd9b1680ae 252 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
bogdanm 86:04dd9b1680ae 253 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
bogdanm 86:04dd9b1680ae 254
bogdanm 86:04dd9b1680ae 255 #if defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP) && defined(SYSCFG_CFGR1_I2C3_FMP)
bogdanm 86:04dd9b1680ae 256 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
bogdanm 86:04dd9b1680ae 257 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
bogdanm 86:04dd9b1680ae 258 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C3) == HAL_SYSCFG_FASTMODEPLUS_I2C3) || \
bogdanm 86:04dd9b1680ae 259 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
bogdanm 86:04dd9b1680ae 260 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
bogdanm 86:04dd9b1680ae 261 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
bogdanm 86:04dd9b1680ae 262 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
bogdanm 86:04dd9b1680ae 263 #elif defined(SYSCFG_CFGR1_I2C1_FMP) && defined(SYSCFG_CFGR1_I2C2_FMP)
bogdanm 86:04dd9b1680ae 264 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
bogdanm 86:04dd9b1680ae 265 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C2) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
bogdanm 86:04dd9b1680ae 266 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
bogdanm 86:04dd9b1680ae 267 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
bogdanm 86:04dd9b1680ae 268 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
bogdanm 86:04dd9b1680ae 269 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
bogdanm 86:04dd9b1680ae 270 #elif defined(SYSCFG_CFGR1_I2C1_FMP)
bogdanm 86:04dd9b1680ae 271 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) ((((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C1) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
bogdanm 86:04dd9b1680ae 272 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
bogdanm 86:04dd9b1680ae 273 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
bogdanm 86:04dd9b1680ae 274 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
bogdanm 86:04dd9b1680ae 275 (((CONFIG) & HAL_SYSCFG_FASTMODEPLUS_I2C_PB9) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
bogdanm 86:04dd9b1680ae 276 #endif /* SYSCFG_CFGR1_I2C1_FMP && SYSCFG_CFGR1_I2C2_FMP && SYSCFG_CFGR3_I2C1_FMP */
bogdanm 86:04dd9b1680ae 277 /**
bogdanm 86:04dd9b1680ae 278 * @}
bogdanm 86:04dd9b1680ae 279 */
bogdanm 86:04dd9b1680ae 280
bogdanm 86:04dd9b1680ae 281 #if defined(SYSCFG_RCR_PAGE0)
bogdanm 86:04dd9b1680ae 282 /* CCM-SRAM defined */
bogdanm 86:04dd9b1680ae 283 /** @defgroup HAL_Page_Write_Protection
bogdanm 86:04dd9b1680ae 284 * @{
bogdanm 86:04dd9b1680ae 285 */
bogdanm 86:04dd9b1680ae 286 #define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
bogdanm 86:04dd9b1680ae 287 #define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
bogdanm 86:04dd9b1680ae 288 #define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
bogdanm 86:04dd9b1680ae 289 #define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
bogdanm 86:04dd9b1680ae 290 #if defined(SYSCFG_RCR_PAGE4)
bogdanm 86:04dd9b1680ae 291 /* More than 4KB CCM-SRAM defined */
bogdanm 86:04dd9b1680ae 292 #define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
bogdanm 86:04dd9b1680ae 293 #define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
bogdanm 86:04dd9b1680ae 294 #define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
bogdanm 86:04dd9b1680ae 295 #define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
bogdanm 86:04dd9b1680ae 296 #endif /* SYSCFG_RCR_PAGE4 */
bogdanm 86:04dd9b1680ae 297
bogdanm 86:04dd9b1680ae 298 #if defined(SYSCFG_RCR_PAGE4)
bogdanm 86:04dd9b1680ae 299 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= SYSCFG_RCR_PAGE7))
bogdanm 86:04dd9b1680ae 300 #else
bogdanm 86:04dd9b1680ae 301 #define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= SYSCFG_RCR_PAGE3))
bogdanm 86:04dd9b1680ae 302 #endif
bogdanm 86:04dd9b1680ae 303 /**
bogdanm 86:04dd9b1680ae 304 * @}
bogdanm 86:04dd9b1680ae 305 */
bogdanm 86:04dd9b1680ae 306 #endif /* SYSCFG_RCR_PAGE0 */
bogdanm 86:04dd9b1680ae 307
bogdanm 86:04dd9b1680ae 308 /** @defgroup HAL_SYSCFG_Interrupts
bogdanm 86:04dd9b1680ae 309 * @{
bogdanm 86:04dd9b1680ae 310 */
bogdanm 86:04dd9b1680ae 311 #define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
bogdanm 86:04dd9b1680ae 312 #define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
bogdanm 86:04dd9b1680ae 313 #define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
bogdanm 86:04dd9b1680ae 314 #define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
bogdanm 86:04dd9b1680ae 315 #define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
bogdanm 86:04dd9b1680ae 316 #define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
bogdanm 86:04dd9b1680ae 317
bogdanm 86:04dd9b1680ae 318 #define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
bogdanm 86:04dd9b1680ae 319 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
bogdanm 86:04dd9b1680ae 320 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
bogdanm 86:04dd9b1680ae 321 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
bogdanm 86:04dd9b1680ae 322 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
bogdanm 86:04dd9b1680ae 323 (((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
bogdanm 86:04dd9b1680ae 324
bogdanm 86:04dd9b1680ae 325 /**
bogdanm 86:04dd9b1680ae 326 * @}
bogdanm 86:04dd9b1680ae 327 */
bogdanm 86:04dd9b1680ae 328
bogdanm 86:04dd9b1680ae 329
bogdanm 86:04dd9b1680ae 330 /* Exported macro ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 331
bogdanm 86:04dd9b1680ae 332 /** @brief Freeze/Unfreeze Peripherals in Debug mode
bogdanm 86:04dd9b1680ae 333 */
bogdanm 86:04dd9b1680ae 334 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
bogdanm 86:04dd9b1680ae 335 #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
bogdanm 86:04dd9b1680ae 336 #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
bogdanm 86:04dd9b1680ae 337 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
bogdanm 86:04dd9b1680ae 338
bogdanm 86:04dd9b1680ae 339 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
bogdanm 86:04dd9b1680ae 340 #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
bogdanm 86:04dd9b1680ae 341 #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
bogdanm 86:04dd9b1680ae 342 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
bogdanm 86:04dd9b1680ae 343
bogdanm 86:04dd9b1680ae 344 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
bogdanm 86:04dd9b1680ae 345 #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
bogdanm 86:04dd9b1680ae 346 #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
bogdanm 86:04dd9b1680ae 347 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
bogdanm 86:04dd9b1680ae 348
bogdanm 86:04dd9b1680ae 349 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
bogdanm 86:04dd9b1680ae 350 #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
bogdanm 86:04dd9b1680ae 351 #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
bogdanm 86:04dd9b1680ae 352 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
bogdanm 86:04dd9b1680ae 353
bogdanm 86:04dd9b1680ae 354 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
bogdanm 86:04dd9b1680ae 355 #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
bogdanm 86:04dd9b1680ae 356 #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
bogdanm 86:04dd9b1680ae 357 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
bogdanm 86:04dd9b1680ae 358
bogdanm 86:04dd9b1680ae 359 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
bogdanm 86:04dd9b1680ae 360 #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
bogdanm 86:04dd9b1680ae 361 #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
bogdanm 86:04dd9b1680ae 362 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
bogdanm 86:04dd9b1680ae 363
bogdanm 86:04dd9b1680ae 364 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
bogdanm 86:04dd9b1680ae 365 #define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
bogdanm 86:04dd9b1680ae 366 #define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
bogdanm 86:04dd9b1680ae 367 #endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
bogdanm 86:04dd9b1680ae 368
bogdanm 86:04dd9b1680ae 369 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
bogdanm 86:04dd9b1680ae 370 #define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
bogdanm 86:04dd9b1680ae 371 #define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
bogdanm 86:04dd9b1680ae 372 #endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
bogdanm 86:04dd9b1680ae 373
bogdanm 86:04dd9b1680ae 374 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
bogdanm 86:04dd9b1680ae 375 #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
bogdanm 86:04dd9b1680ae 376 #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
bogdanm 86:04dd9b1680ae 377 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
bogdanm 86:04dd9b1680ae 378
bogdanm 86:04dd9b1680ae 379 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
bogdanm 86:04dd9b1680ae 380 #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
bogdanm 86:04dd9b1680ae 381 #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
bogdanm 86:04dd9b1680ae 382 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
bogdanm 86:04dd9b1680ae 383
bogdanm 86:04dd9b1680ae 384 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
bogdanm 86:04dd9b1680ae 385 #define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
bogdanm 86:04dd9b1680ae 386 #define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
bogdanm 86:04dd9b1680ae 387 #endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
bogdanm 86:04dd9b1680ae 388
bogdanm 86:04dd9b1680ae 389 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
bogdanm 86:04dd9b1680ae 390 #define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
bogdanm 86:04dd9b1680ae 391 #define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
bogdanm 86:04dd9b1680ae 392 #endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
bogdanm 86:04dd9b1680ae 393
bogdanm 86:04dd9b1680ae 394 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
bogdanm 86:04dd9b1680ae 395 #define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
bogdanm 86:04dd9b1680ae 396 #define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
bogdanm 86:04dd9b1680ae 397 #endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
bogdanm 86:04dd9b1680ae 398
bogdanm 86:04dd9b1680ae 399 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
bogdanm 86:04dd9b1680ae 400 #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
bogdanm 86:04dd9b1680ae 401 #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
bogdanm 86:04dd9b1680ae 402 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
bogdanm 86:04dd9b1680ae 403
bogdanm 86:04dd9b1680ae 404 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
bogdanm 86:04dd9b1680ae 405 #define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
bogdanm 86:04dd9b1680ae 406 #define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
bogdanm 86:04dd9b1680ae 407 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
bogdanm 86:04dd9b1680ae 408
bogdanm 86:04dd9b1680ae 409 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
bogdanm 86:04dd9b1680ae 410 #define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
bogdanm 86:04dd9b1680ae 411 #define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
bogdanm 86:04dd9b1680ae 412 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
bogdanm 86:04dd9b1680ae 413
bogdanm 86:04dd9b1680ae 414 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
bogdanm 86:04dd9b1680ae 415 #define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
bogdanm 86:04dd9b1680ae 416 #define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
bogdanm 86:04dd9b1680ae 417 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
bogdanm 86:04dd9b1680ae 418
bogdanm 86:04dd9b1680ae 419 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
bogdanm 86:04dd9b1680ae 420 #define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
bogdanm 86:04dd9b1680ae 421 #define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
bogdanm 86:04dd9b1680ae 422 #endif /* */
bogdanm 86:04dd9b1680ae 423
bogdanm 86:04dd9b1680ae 424 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
bogdanm 86:04dd9b1680ae 425 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 426 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 427 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
bogdanm 86:04dd9b1680ae 428
bogdanm 86:04dd9b1680ae 429 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
bogdanm 86:04dd9b1680ae 430 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 431 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 432 #endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
bogdanm 86:04dd9b1680ae 433
bogdanm 86:04dd9b1680ae 434 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
bogdanm 86:04dd9b1680ae 435 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 436 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
bogdanm 86:04dd9b1680ae 437 #endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
bogdanm 86:04dd9b1680ae 438
bogdanm 86:04dd9b1680ae 439 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
bogdanm 86:04dd9b1680ae 440 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
bogdanm 86:04dd9b1680ae 441 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
bogdanm 86:04dd9b1680ae 442 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
bogdanm 86:04dd9b1680ae 443
bogdanm 86:04dd9b1680ae 444
bogdanm 86:04dd9b1680ae 445 #if defined(SYSCFG_CFGR1_MEM_MODE)
bogdanm 86:04dd9b1680ae 446 /** @brief Main Flash memory mapped at 0x00000000
bogdanm 86:04dd9b1680ae 447 */
bogdanm 86:04dd9b1680ae 448 #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
bogdanm 86:04dd9b1680ae 449 #endif /* SYSCFG_CFGR1_MEM_MODE */
bogdanm 86:04dd9b1680ae 450
bogdanm 86:04dd9b1680ae 451 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
bogdanm 86:04dd9b1680ae 452 /** @brief System Flash memory mapped at 0x00000000
bogdanm 86:04dd9b1680ae 453 */
bogdanm 86:04dd9b1680ae 454 #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
bogdanm 86:04dd9b1680ae 455 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
bogdanm 86:04dd9b1680ae 456 }while(0)
bogdanm 86:04dd9b1680ae 457 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
bogdanm 86:04dd9b1680ae 458
bogdanm 86:04dd9b1680ae 459 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
bogdanm 86:04dd9b1680ae 460 /** @brief Embedded SRAM mapped at 0x00000000
bogdanm 86:04dd9b1680ae 461 */
bogdanm 86:04dd9b1680ae 462 #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
bogdanm 86:04dd9b1680ae 463 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
bogdanm 86:04dd9b1680ae 464 }while(0)
bogdanm 86:04dd9b1680ae 465 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
bogdanm 86:04dd9b1680ae 466
bogdanm 86:04dd9b1680ae 467 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
bogdanm 86:04dd9b1680ae 468 /** @brief No Encoder mode
bogdanm 86:04dd9b1680ae 469 */
bogdanm 86:04dd9b1680ae 470 #define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
bogdanm 86:04dd9b1680ae 471 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
bogdanm 86:04dd9b1680ae 472
bogdanm 86:04dd9b1680ae 473 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
bogdanm 86:04dd9b1680ae 474 /** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
bogdanm 86:04dd9b1680ae 475 */
bogdanm 86:04dd9b1680ae 476 #define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
bogdanm 86:04dd9b1680ae 477 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
bogdanm 86:04dd9b1680ae 478 }while(0)
bogdanm 86:04dd9b1680ae 479 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
bogdanm 86:04dd9b1680ae 480
bogdanm 86:04dd9b1680ae 481 #if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
bogdanm 86:04dd9b1680ae 482 /** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
bogdanm 86:04dd9b1680ae 483 */
bogdanm 86:04dd9b1680ae 484 #define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
bogdanm 86:04dd9b1680ae 485 SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
bogdanm 86:04dd9b1680ae 486 }while(0)
bogdanm 86:04dd9b1680ae 487 #endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
bogdanm 86:04dd9b1680ae 488
bogdanm 86:04dd9b1680ae 489 #if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
bogdanm 86:04dd9b1680ae 490 /** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
bogdanm 86:04dd9b1680ae 491 */
bogdanm 86:04dd9b1680ae 492 #define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
bogdanm 86:04dd9b1680ae 493 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
bogdanm 86:04dd9b1680ae 494 }while(0)
bogdanm 86:04dd9b1680ae 495 #endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
bogdanm 86:04dd9b1680ae 496
bogdanm 86:04dd9b1680ae 497 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 86:04dd9b1680ae 498 /** @brief DMA remapping enable/disable macros
bogdanm 86:04dd9b1680ae 499 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
bogdanm 86:04dd9b1680ae 500 */
bogdanm 86:04dd9b1680ae 501 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 502 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 503 (SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 504 (SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 505 }while(0)
bogdanm 86:04dd9b1680ae 506 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 507 (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 508 (SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 509 (SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 510 }while(0)
bogdanm 86:04dd9b1680ae 511 #elif defined(SYSCFG_CFGR1_DMA_RMP)
bogdanm 86:04dd9b1680ae 512 /** @brief DMA remapping enable/disable macros
bogdanm 86:04dd9b1680ae 513 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
bogdanm 86:04dd9b1680ae 514 */
bogdanm 86:04dd9b1680ae 515 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 516 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
bogdanm 86:04dd9b1680ae 517 }while(0)
bogdanm 86:04dd9b1680ae 518 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
bogdanm 86:04dd9b1680ae 519 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
bogdanm 86:04dd9b1680ae 520 }while(0)
bogdanm 86:04dd9b1680ae 521 #endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
bogdanm 86:04dd9b1680ae 522
bogdanm 86:04dd9b1680ae 523 /** @brief Fast mode Plus driving capability enable/disable macros
bogdanm 86:04dd9b1680ae 524 * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
bogdanm 86:04dd9b1680ae 525 */
bogdanm 86:04dd9b1680ae 526 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
bogdanm 86:04dd9b1680ae 527 SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
bogdanm 86:04dd9b1680ae 528 }while(0)
bogdanm 86:04dd9b1680ae 529
bogdanm 86:04dd9b1680ae 530 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
bogdanm 86:04dd9b1680ae 531 SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
bogdanm 86:04dd9b1680ae 532 }while(0)
bogdanm 86:04dd9b1680ae 533
bogdanm 86:04dd9b1680ae 534 /** @brief SYSCFG interrupt enable/disable macros
bogdanm 86:04dd9b1680ae 535 * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
bogdanm 86:04dd9b1680ae 536 */
bogdanm 86:04dd9b1680ae 537 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
bogdanm 86:04dd9b1680ae 538 SYSCFG->CFGR1 |= (__INTERRUPT__); \
bogdanm 86:04dd9b1680ae 539 }while(0)
bogdanm 86:04dd9b1680ae 540
bogdanm 86:04dd9b1680ae 541 #define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
bogdanm 86:04dd9b1680ae 542 SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
bogdanm 86:04dd9b1680ae 543 }while(0)
bogdanm 86:04dd9b1680ae 544
bogdanm 86:04dd9b1680ae 545 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
bogdanm 86:04dd9b1680ae 546 /** @brief USB interrupt remapping enable/disable macros
bogdanm 86:04dd9b1680ae 547 */
bogdanm 86:04dd9b1680ae 548 #define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
bogdanm 86:04dd9b1680ae 549 #define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
bogdanm 86:04dd9b1680ae 550 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
bogdanm 86:04dd9b1680ae 551
bogdanm 86:04dd9b1680ae 552 #if defined(SYSCFG_CFGR1_VBAT)
bogdanm 86:04dd9b1680ae 553 /** @brief SYSCFG interrupt enable/disable macros
bogdanm 86:04dd9b1680ae 554 */
bogdanm 86:04dd9b1680ae 555 #define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
bogdanm 86:04dd9b1680ae 556 #define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
bogdanm 86:04dd9b1680ae 557 #endif /* SYSCFG_CFGR1_VBAT */
bogdanm 86:04dd9b1680ae 558
bogdanm 86:04dd9b1680ae 559 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
bogdanm 86:04dd9b1680ae 560 /** @brief SYSCFG Break Lockup lock
bogdanm 86:04dd9b1680ae 561 * Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
bogdanm 86:04dd9b1680ae 562 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 86:04dd9b1680ae 563 */
bogdanm 86:04dd9b1680ae 564 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
bogdanm 86:04dd9b1680ae 565 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
bogdanm 86:04dd9b1680ae 566 }while(0)
bogdanm 86:04dd9b1680ae 567 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
bogdanm 86:04dd9b1680ae 568
bogdanm 86:04dd9b1680ae 569 #if defined(SYSCFG_CFGR2_PVD_LOCK)
bogdanm 86:04dd9b1680ae 570 /** @brief SYSCFG Break PVD lock
bogdanm 86:04dd9b1680ae 571 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
bogdanm 86:04dd9b1680ae 572 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 86:04dd9b1680ae 573 */
bogdanm 86:04dd9b1680ae 574 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
bogdanm 86:04dd9b1680ae 575 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
bogdanm 86:04dd9b1680ae 576 }while(0)
bogdanm 86:04dd9b1680ae 577 #endif /* SYSCFG_CFGR2_PVD_LOCK */
bogdanm 86:04dd9b1680ae 578
bogdanm 86:04dd9b1680ae 579 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
bogdanm 86:04dd9b1680ae 580 /** @brief SYSCFG Break SRAM PARITY lock
bogdanm 86:04dd9b1680ae 581 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
bogdanm 86:04dd9b1680ae 582 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 86:04dd9b1680ae 583 */
bogdanm 86:04dd9b1680ae 584 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
bogdanm 86:04dd9b1680ae 585 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
bogdanm 86:04dd9b1680ae 586 }while(0)
bogdanm 86:04dd9b1680ae 587 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
bogdanm 86:04dd9b1680ae 588
bogdanm 86:04dd9b1680ae 589 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
bogdanm 86:04dd9b1680ae 590 /** @brief Trigger remapping enable/disable macros
bogdanm 86:04dd9b1680ae 591 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
bogdanm 86:04dd9b1680ae 592 */
bogdanm 86:04dd9b1680ae 593 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 594 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 595 (SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 596 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 597 }while(0)
bogdanm 86:04dd9b1680ae 598 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 599 (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
bogdanm 86:04dd9b1680ae 600 (SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
bogdanm 86:04dd9b1680ae 601 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 602 }while(0)
bogdanm 86:04dd9b1680ae 603 #else
bogdanm 86:04dd9b1680ae 604 /** @brief Trigger remapping enable/disable macros
bogdanm 86:04dd9b1680ae 605 * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
bogdanm 86:04dd9b1680ae 606 */
bogdanm 86:04dd9b1680ae 607 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 608 (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
bogdanm 86:04dd9b1680ae 609 }while(0)
bogdanm 86:04dd9b1680ae 610 #define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
bogdanm 86:04dd9b1680ae 611 (SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
bogdanm 86:04dd9b1680ae 612 }while(0)
bogdanm 86:04dd9b1680ae 613 #endif /* SYSCFG_CFGR3_TRIGGER_RMP */
bogdanm 86:04dd9b1680ae 614
bogdanm 86:04dd9b1680ae 615 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
bogdanm 86:04dd9b1680ae 616 /**
bogdanm 86:04dd9b1680ae 617 * @brief Parity check on RAM disable macro
bogdanm 86:04dd9b1680ae 618 * @note Disabling the parity check on RAM locks the configuration bit.
bogdanm 86:04dd9b1680ae 619 * To re-enable the parity check on RAM perform a system reset.
bogdanm 86:04dd9b1680ae 620 */
bogdanm 86:04dd9b1680ae 621 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = (uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 622 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
bogdanm 86:04dd9b1680ae 623
bogdanm 86:04dd9b1680ae 624 #if defined(SYSCFG_RCR_PAGE0)
bogdanm 86:04dd9b1680ae 625 /** @brief CCM RAM page write protection enable macro
bogdanm 86:04dd9b1680ae 626 * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
bogdanm 86:04dd9b1680ae 627 * @note write protection can only be disabled by a system reset
bogdanm 86:04dd9b1680ae 628 */
bogdanm 86:04dd9b1680ae 629 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
bogdanm 86:04dd9b1680ae 630 SYSCFG->RCR |= (__PAGE_WP__); \
bogdanm 86:04dd9b1680ae 631 }while(0)
bogdanm 86:04dd9b1680ae 632 #endif /* SYSCFG_RCR_PAGE0 */
bogdanm 86:04dd9b1680ae 633
bogdanm 86:04dd9b1680ae 634
bogdanm 86:04dd9b1680ae 635 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 636
bogdanm 86:04dd9b1680ae 637 /* Initialization and de-initialization functions ******************************/
bogdanm 86:04dd9b1680ae 638 HAL_StatusTypeDef HAL_Init(void);
bogdanm 86:04dd9b1680ae 639 HAL_StatusTypeDef HAL_DeInit(void);
bogdanm 86:04dd9b1680ae 640 void HAL_MspInit(void);
bogdanm 86:04dd9b1680ae 641 void HAL_MspDeInit(void);
bogdanm 86:04dd9b1680ae 642 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
bogdanm 86:04dd9b1680ae 643
bogdanm 86:04dd9b1680ae 644 /* Peripheral Control functions ************************************************/
bogdanm 86:04dd9b1680ae 645 void HAL_IncTick(void);
bogdanm 86:04dd9b1680ae 646 void HAL_Delay(__IO uint32_t Delay);
bogdanm 86:04dd9b1680ae 647 void HAL_SuspendTick(void);
bogdanm 86:04dd9b1680ae 648 void HAL_ResumeTick(void);
bogdanm 86:04dd9b1680ae 649 uint32_t HAL_GetTick(void);
bogdanm 86:04dd9b1680ae 650 uint32_t HAL_GetHalVersion(void);
bogdanm 86:04dd9b1680ae 651 uint32_t HAL_GetREVID(void);
bogdanm 86:04dd9b1680ae 652 uint32_t HAL_GetDEVID(void);
bogdanm 86:04dd9b1680ae 653 void HAL_EnableDBGSleepMode(void);
bogdanm 86:04dd9b1680ae 654 void HAL_DisableDBGSleepMode(void);
bogdanm 86:04dd9b1680ae 655 void HAL_EnableDBGStopMode(void);
bogdanm 86:04dd9b1680ae 656 void HAL_DisableDBGStopMode(void);
bogdanm 86:04dd9b1680ae 657 void HAL_EnableDBGStandbyMode(void);
bogdanm 86:04dd9b1680ae 658 void HAL_DisableDBGStandbyMode(void);
bogdanm 86:04dd9b1680ae 659
bogdanm 86:04dd9b1680ae 660
bogdanm 86:04dd9b1680ae 661 /**
bogdanm 86:04dd9b1680ae 662 * @}
bogdanm 86:04dd9b1680ae 663 */
bogdanm 86:04dd9b1680ae 664
bogdanm 86:04dd9b1680ae 665 /**
bogdanm 86:04dd9b1680ae 666 * @}
bogdanm 86:04dd9b1680ae 667 */
bogdanm 86:04dd9b1680ae 668
bogdanm 86:04dd9b1680ae 669 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 670 }
bogdanm 86:04dd9b1680ae 671 #endif
bogdanm 86:04dd9b1680ae 672
bogdanm 86:04dd9b1680ae 673 #endif /* __STM32F3xx_HAL_H */
bogdanm 86:04dd9b1680ae 674
bogdanm 86:04dd9b1680ae 675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/