NXP / fsl_phy_mcr20a

A library implementing IEEE 802.15.4 PHY functionality for the MCR20A transceiver. The PHY sublayer provides two services: the PHY data service and the PHY management service interfacing to the PHY sublayer management entity (PLME) service access point (SAP) (known as PLME-SAP). The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) over the media (radio).

Fork of fsl_phy_mcr20a by Freescale

The Freescale PHY Layer deals with the physical burst which is to be sent and/or received. It performs modulation and demodulation, transmitter and receiver switching, fragmentation, scrambling, interleaving, and error correction coding. The communication to the upper protocol layers is carried out through the Layer 1 Interface.

The PHY Layer is capable of executing the following sequences:

  • I (Idle)
  • R (Receive Sequence conditionally followed by a TxAck)
  • T (Transmit Sequence)
  • C (Standalone CCA)
  • CCCA (Continuous CCA)
  • TR (Transmit/Receive Sequence - transmit unconditionally followed by either an R or RxAck)

In addition to these sequences the PHY Layer also integrates a packet processor which determines whether the packet is MAC-compliant, and if it is, whether it is addressed to the end device. Another feature of the packet processor is Source Address Matching which can be viewed as an extension of packet filtering; however its function is very specific to its intended application (data-polling and indirect queue management by a PAN Coordinator).

Documentation

MCR20A PHY Reference Manual

PHY/MCR20Drv/XcvrSpi.cpp@0:764779eedf2d, 2015-08-18 (annotated)

Committer:
andreikovacs
Date:
Tue Aug 18 12:41:42 2015 +0000
Revision:
0:764779eedf2d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreikovacs 0:764779eedf2d 1 /*!
andreikovacs 0:764779eedf2d 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
andreikovacs 0:764779eedf2d 3 * All rights reserved.
andreikovacs 0:764779eedf2d 4 *
andreikovacs 0:764779eedf2d 5 * \file XcvrSpi.c
andreikovacs 0:764779eedf2d 6 *
andreikovacs 0:764779eedf2d 7 * Redistribution and use in source and binary forms, with or without modification,
andreikovacs 0:764779eedf2d 8 * are permitted provided that the following conditions are met:
andreikovacs 0:764779eedf2d 9 *
andreikovacs 0:764779eedf2d 10 * o Redistributions of source code must retain the above copyright notice, this list
andreikovacs 0:764779eedf2d 11 * of conditions and the following disclaimer.
andreikovacs 0:764779eedf2d 12 *
andreikovacs 0:764779eedf2d 13 * o Redistributions in binary form must reproduce the above copyright notice, this
andreikovacs 0:764779eedf2d 14 * list of conditions and the following disclaimer in the documentation and/or
andreikovacs 0:764779eedf2d 15 * other materials provided with the distribution.
andreikovacs 0:764779eedf2d 16 *
andreikovacs 0:764779eedf2d 17 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
andreikovacs 0:764779eedf2d 18 * contributors may be used to endorse or promote products derived from this
andreikovacs 0:764779eedf2d 19 * software without specific prior written permission.
andreikovacs 0:764779eedf2d 20 *
andreikovacs 0:764779eedf2d 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
andreikovacs 0:764779eedf2d 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
andreikovacs 0:764779eedf2d 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
andreikovacs 0:764779eedf2d 24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
andreikovacs 0:764779eedf2d 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
andreikovacs 0:764779eedf2d 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
andreikovacs 0:764779eedf2d 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
andreikovacs 0:764779eedf2d 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
andreikovacs 0:764779eedf2d 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
andreikovacs 0:764779eedf2d 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
andreikovacs 0:764779eedf2d 31 */
andreikovacs 0:764779eedf2d 32
andreikovacs 0:764779eedf2d 33
andreikovacs 0:764779eedf2d 34 /*****************************************************************************
andreikovacs 0:764779eedf2d 35 * INCLUDED HEADERS *
andreikovacs 0:764779eedf2d 36 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 37 * Add to this section all the headers that this module needs to include. *
andreikovacs 0:764779eedf2d 38 * Note that it is not a good practice to include header files into header *
andreikovacs 0:764779eedf2d 39 * files, so use this section only if there is no other better solution. *
andreikovacs 0:764779eedf2d 40 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 41 *****************************************************************************/
andreikovacs 0:764779eedf2d 42
andreikovacs 0:764779eedf2d 43 #include "mbed.h"
andreikovacs 0:764779eedf2d 44 #include "EmbeddedTypes.h"
andreikovacs 0:764779eedf2d 45
andreikovacs 0:764779eedf2d 46 #if defined(TARGET_K64F)
andreikovacs 0:764779eedf2d 47 SPI spi(PTD2, PTD3, PTD1);
andreikovacs 0:764779eedf2d 48 #elif defined(TARGET_NUCLEO_F401RE)
andreikovacs 0:764779eedf2d 49 SPI spi(SPI_MOSI, SPI_MISO, SPI_SCK);
andreikovacs 0:764779eedf2d 50 #else
andreikovacs 0:764779eedf2d 51 "SPI not defined for this platform"
andreikovacs 0:764779eedf2d 52 #endif
andreikovacs 0:764779eedf2d 53
andreikovacs 0:764779eedf2d 54 DigitalOut RF_CS(D10);
andreikovacs 0:764779eedf2d 55 DigitalOut RF_RST(D5);
andreikovacs 0:764779eedf2d 56 DigitalOut RF_SLP_TR(D7); // Not used in FSL
andreikovacs 0:764779eedf2d 57 InterruptIn RF_IRQ (D2); // FSL //(D9); // Atmel Radio
andreikovacs 0:764779eedf2d 58 DigitalIn RF_IRQ_PIN (D2);
andreikovacs 0:764779eedf2d 59
andreikovacs 0:764779eedf2d 60 extern "C" void PHY_InterruptHandler(void);
andreikovacs 0:764779eedf2d 61
andreikovacs 0:764779eedf2d 62 extern "C" void RF_IRQ_Init(void) {
andreikovacs 0:764779eedf2d 63 RF_IRQ.mode(PullUp);
andreikovacs 0:764779eedf2d 64 RF_IRQ.fall(&PHY_InterruptHandler);
andreikovacs 0:764779eedf2d 65 }
andreikovacs 0:764779eedf2d 66
andreikovacs 0:764779eedf2d 67 extern "C" void RF_IRQ_Enable(void) {
andreikovacs 0:764779eedf2d 68 RF_IRQ.enable_irq();
andreikovacs 0:764779eedf2d 69 }
andreikovacs 0:764779eedf2d 70 extern "C" void RF_IRQ_Disable(void) {
andreikovacs 0:764779eedf2d 71 RF_IRQ.disable_irq();
andreikovacs 0:764779eedf2d 72 }
andreikovacs 0:764779eedf2d 73
andreikovacs 0:764779eedf2d 74 extern "C" bool_t RF_isIRQ_Pending(void) {
andreikovacs 0:764779eedf2d 75 return !RF_IRQ_PIN.read();
andreikovacs 0:764779eedf2d 76 }
andreikovacs 0:764779eedf2d 77
andreikovacs 0:764779eedf2d 78 extern "C" void RF_RST_Set(int state) {
andreikovacs 0:764779eedf2d 79 RF_RST = state;
andreikovacs 0:764779eedf2d 80 }
andreikovacs 0:764779eedf2d 81
andreikovacs 0:764779eedf2d 82 extern "C" void RF_SLP_TR_Set(int state) {
andreikovacs 0:764779eedf2d 83 RF_SLP_TR = state;
andreikovacs 0:764779eedf2d 84 }
andreikovacs 0:764779eedf2d 85
andreikovacs 0:764779eedf2d 86 extern "C" void RF_CS_while_active(void) {
andreikovacs 0:764779eedf2d 87
andreikovacs 0:764779eedf2d 88 while(!RF_CS);
andreikovacs 0:764779eedf2d 89 }
andreikovacs 0:764779eedf2d 90
andreikovacs 0:764779eedf2d 91 /*****************************************************************************
andreikovacs 0:764779eedf2d 92 * PRIVATE MACROS *
andreikovacs 0:764779eedf2d 93 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 94 * Add to this section all the access macros, registers mappings, bit access *
andreikovacs 0:764779eedf2d 95 * macros, masks, flags etc ...
andreikovacs 0:764779eedf2d 96 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 97 *****************************************************************************/
andreikovacs 0:764779eedf2d 98
andreikovacs 0:764779eedf2d 99 /*****************************************************************************/
andreikovacs 0:764779eedf2d 100 /*****************************************************************************/
andreikovacs 0:764779eedf2d 101 extern "C" void spi_master_init(uint32_t instance)
andreikovacs 0:764779eedf2d 102 {
andreikovacs 0:764779eedf2d 103
andreikovacs 0:764779eedf2d 104 }
andreikovacs 0:764779eedf2d 105
andreikovacs 0:764779eedf2d 106 /*****************************************************************************/
andreikovacs 0:764779eedf2d 107 /*****************************************************************************/
andreikovacs 0:764779eedf2d 108 extern "C" void spi_master_configure_speed(uint32_t instance, uint32_t freq)
andreikovacs 0:764779eedf2d 109 {
andreikovacs 0:764779eedf2d 110 //spi.frequency(8000000);
andreikovacs 0:764779eedf2d 111 spi.frequency(freq);
andreikovacs 0:764779eedf2d 112 }
andreikovacs 0:764779eedf2d 113
andreikovacs 0:764779eedf2d 114 /*****************************************************************************/
andreikovacs 0:764779eedf2d 115 /*****************************************************************************/
andreikovacs 0:764779eedf2d 116 extern "C" void spi_master_transfer(uint32_t instance,
andreikovacs 0:764779eedf2d 117 uint8_t * sendBuffer,
andreikovacs 0:764779eedf2d 118 uint8_t * receiveBuffer,
andreikovacs 0:764779eedf2d 119 size_t transferByteCount)
andreikovacs 0:764779eedf2d 120 {
andreikovacs 0:764779eedf2d 121 volatile uint8_t dummy;
andreikovacs 0:764779eedf2d 122
andreikovacs 0:764779eedf2d 123 if( !transferByteCount )
andreikovacs 0:764779eedf2d 124 return;
andreikovacs 0:764779eedf2d 125
andreikovacs 0:764779eedf2d 126 if( !sendBuffer && !receiveBuffer )
andreikovacs 0:764779eedf2d 127 return;
andreikovacs 0:764779eedf2d 128
andreikovacs 0:764779eedf2d 129 while( transferByteCount-- )
andreikovacs 0:764779eedf2d 130 {
andreikovacs 0:764779eedf2d 131 if( sendBuffer )
andreikovacs 0:764779eedf2d 132 {
andreikovacs 0:764779eedf2d 133 dummy = *sendBuffer;
andreikovacs 0:764779eedf2d 134 sendBuffer++;
andreikovacs 0:764779eedf2d 135 }
andreikovacs 0:764779eedf2d 136 else
andreikovacs 0:764779eedf2d 137 {
andreikovacs 0:764779eedf2d 138 dummy = 0xFF;
andreikovacs 0:764779eedf2d 139 }
andreikovacs 0:764779eedf2d 140
andreikovacs 0:764779eedf2d 141 dummy = spi.write(dummy);
andreikovacs 0:764779eedf2d 142
andreikovacs 0:764779eedf2d 143 if( receiveBuffer )
andreikovacs 0:764779eedf2d 144 {
andreikovacs 0:764779eedf2d 145 *receiveBuffer = dummy;
andreikovacs 0:764779eedf2d 146 receiveBuffer++;
andreikovacs 0:764779eedf2d 147 }
andreikovacs 0:764779eedf2d 148 }
andreikovacs 0:764779eedf2d 149 }
andreikovacs 0:764779eedf2d 150
andreikovacs 0:764779eedf2d 151 extern "C" void gXcvrAssertCS_d(void)
andreikovacs 0:764779eedf2d 152 {
andreikovacs 0:764779eedf2d 153 RF_CS = 0;
andreikovacs 0:764779eedf2d 154 }
andreikovacs 0:764779eedf2d 155
andreikovacs 0:764779eedf2d 156 extern "C" void gXcvrDeassertCS_d(void)
andreikovacs 0:764779eedf2d 157 {
andreikovacs 0:764779eedf2d 158 RF_CS = 1;
andreikovacs 0:764779eedf2d 159 }