A library implementing IEEE 802.15.4 PHY functionality for the MCR20A transceiver. The PHY sublayer provides two services: the PHY data service and the PHY management service interfacing to the PHY sublayer management entity (PLME) service access point (SAP) (known as PLME-SAP). The PHY data service enables the transmission and reception of PHY protocol data units (PSDUs) over the media (radio).

Fork of fsl_phy_mcr20a by Freescale

The Freescale PHY Layer deals with the physical burst which is to be sent and/or received. It performs modulation and demodulation, transmitter and receiver switching, fragmentation, scrambling, interleaving, and error correction coding. The communication to the upper protocol layers is carried out through the Layer 1 Interface.

The PHY Layer is capable of executing the following sequences:

  • I (Idle)
  • R (Receive Sequence conditionally followed by a TxAck)
  • T (Transmit Sequence)
  • C (Standalone CCA)
  • CCCA (Continuous CCA)
  • TR (Transmit/Receive Sequence - transmit unconditionally followed by either an R or RxAck)

In addition to these sequences the PHY Layer also integrates a packet processor which determines whether the packet is MAC-compliant, and if it is, whether it is addressed to the end device. Another feature of the packet processor is Source Address Matching which can be viewed as an extension of packet filtering; however its function is very specific to its intended application (data-polling and indirect queue management by a PAN Coordinator).

Documentation

MCR20A PHY Reference Manual

Committer:
andreikovacs
Date:
Tue Aug 18 12:41:42 2015 +0000
Revision:
0:764779eedf2d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andreikovacs 0:764779eedf2d 1 /*!
andreikovacs 0:764779eedf2d 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
andreikovacs 0:764779eedf2d 3 * All rights reserved.
andreikovacs 0:764779eedf2d 4 *
andreikovacs 0:764779eedf2d 5 * \file MCR20reg.h
andreikovacs 0:764779eedf2d 6 * MCR20 Registers
andreikovacs 0:764779eedf2d 7 *
andreikovacs 0:764779eedf2d 8 * Redistribution and use in source and binary forms, with or without modification,
andreikovacs 0:764779eedf2d 9 * are permitted provided that the following conditions are met:
andreikovacs 0:764779eedf2d 10 *
andreikovacs 0:764779eedf2d 11 * o Redistributions of source code must retain the above copyright notice, this list
andreikovacs 0:764779eedf2d 12 * of conditions and the following disclaimer.
andreikovacs 0:764779eedf2d 13 *
andreikovacs 0:764779eedf2d 14 * o Redistributions in binary form must reproduce the above copyright notice, this
andreikovacs 0:764779eedf2d 15 * list of conditions and the following disclaimer in the documentation and/or
andreikovacs 0:764779eedf2d 16 * other materials provided with the distribution.
andreikovacs 0:764779eedf2d 17 *
andreikovacs 0:764779eedf2d 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
andreikovacs 0:764779eedf2d 19 * contributors may be used to endorse or promote products derived from this
andreikovacs 0:764779eedf2d 20 * software without specific prior written permission.
andreikovacs 0:764779eedf2d 21 *
andreikovacs 0:764779eedf2d 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
andreikovacs 0:764779eedf2d 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
andreikovacs 0:764779eedf2d 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
andreikovacs 0:764779eedf2d 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
andreikovacs 0:764779eedf2d 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
andreikovacs 0:764779eedf2d 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
andreikovacs 0:764779eedf2d 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
andreikovacs 0:764779eedf2d 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
andreikovacs 0:764779eedf2d 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
andreikovacs 0:764779eedf2d 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
andreikovacs 0:764779eedf2d 32 */
andreikovacs 0:764779eedf2d 33
andreikovacs 0:764779eedf2d 34 #ifndef __MCR20_REG_H__
andreikovacs 0:764779eedf2d 35 #define __MCR20_REG_H__
andreikovacs 0:764779eedf2d 36 /*****************************************************************************
andreikovacs 0:764779eedf2d 37 * INCLUDED HEADERS *
andreikovacs 0:764779eedf2d 38 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 39 * Add to this section all the headers that this module needs to include. *
andreikovacs 0:764779eedf2d 40 * Note that it is not a good practice to include header files into header *
andreikovacs 0:764779eedf2d 41 * files, so use this section only if there is no other better solution. *
andreikovacs 0:764779eedf2d 42 *---------------------------------------------------------------------------*
andreikovacs 0:764779eedf2d 43 *****************************************************************************/
andreikovacs 0:764779eedf2d 44
andreikovacs 0:764779eedf2d 45 /****************************************************************************/
andreikovacs 0:764779eedf2d 46 /* Transceiver SPI Registers */
andreikovacs 0:764779eedf2d 47 /****************************************************************************/
andreikovacs 0:764779eedf2d 48
andreikovacs 0:764779eedf2d 49 #define TransceiverSPI_IARIndexReg (0x3E)
andreikovacs 0:764779eedf2d 50
andreikovacs 0:764779eedf2d 51 #define TransceiverSPI_ReadSelect (1<<7)
andreikovacs 0:764779eedf2d 52 #define TransceiverSPI_WriteSelect (0<<7)
andreikovacs 0:764779eedf2d 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
andreikovacs 0:764779eedf2d 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
andreikovacs 0:764779eedf2d 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
andreikovacs 0:764779eedf2d 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
andreikovacs 0:764779eedf2d 57
andreikovacs 0:764779eedf2d 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
andreikovacs 0:764779eedf2d 59
andreikovacs 0:764779eedf2d 60 #define IRQSTS1 0x00
andreikovacs 0:764779eedf2d 61 #define IRQSTS2 0x01
andreikovacs 0:764779eedf2d 62 #define IRQSTS3 0x02
andreikovacs 0:764779eedf2d 63 #define PHY_CTRL1 0x03
andreikovacs 0:764779eedf2d 64 #define PHY_CTRL2 0x04
andreikovacs 0:764779eedf2d 65 #define PHY_CTRL3 0x05
andreikovacs 0:764779eedf2d 66 #define RX_FRM_LEN 0x06
andreikovacs 0:764779eedf2d 67 #define PHY_CTRL4 0x07
andreikovacs 0:764779eedf2d 68 #define SRC_CTRL 0x08
andreikovacs 0:764779eedf2d 69 #define SRC_ADDRS_SUM_LSB 0x09
andreikovacs 0:764779eedf2d 70 #define SRC_ADDRS_SUM_MSB 0x0A
andreikovacs 0:764779eedf2d 71 #define CCA1_ED_FNL 0x0B
andreikovacs 0:764779eedf2d 72 #define EVENT_TMR_LSB 0x0C
andreikovacs 0:764779eedf2d 73 #define EVENT_TMR_MSB 0x0D
andreikovacs 0:764779eedf2d 74 #define EVENT_TMR_USB 0x0E
andreikovacs 0:764779eedf2d 75 #define TIMESTAMP_LSB 0x0F
andreikovacs 0:764779eedf2d 76 #define TIMESTAMP_MSB 0x10
andreikovacs 0:764779eedf2d 77 #define TIMESTAMP_USB 0x11
andreikovacs 0:764779eedf2d 78 #define T3CMP_LSB 0x12
andreikovacs 0:764779eedf2d 79 #define T3CMP_MSB 0x13
andreikovacs 0:764779eedf2d 80 #define T3CMP_USB 0x14
andreikovacs 0:764779eedf2d 81 #define T2PRIMECMP_LSB 0x15
andreikovacs 0:764779eedf2d 82 #define T2PRIMECMP_MSB 0x16
andreikovacs 0:764779eedf2d 83 #define T1CMP_LSB 0x17
andreikovacs 0:764779eedf2d 84 #define T1CMP_MSB 0x18
andreikovacs 0:764779eedf2d 85 #define T1CMP_USB 0x19
andreikovacs 0:764779eedf2d 86 #define T2CMP_LSB 0x1A
andreikovacs 0:764779eedf2d 87 #define T2CMP_MSB 0x1B
andreikovacs 0:764779eedf2d 88 #define T2CMP_USB 0x1C
andreikovacs 0:764779eedf2d 89 #define T4CMP_LSB 0x1D
andreikovacs 0:764779eedf2d 90 #define T4CMP_MSB 0x1E
andreikovacs 0:764779eedf2d 91 #define T4CMP_USB 0x1F
andreikovacs 0:764779eedf2d 92 #define PLL_INT0 0x20
andreikovacs 0:764779eedf2d 93 #define PLL_FRAC0_LSB 0x21
andreikovacs 0:764779eedf2d 94 #define PLL_FRAC0_MSB 0x22
andreikovacs 0:764779eedf2d 95 #define PA_PWR 0x23
andreikovacs 0:764779eedf2d 96 #define SEQ_STATE 0x24
andreikovacs 0:764779eedf2d 97 #define LQI_VALUE 0x25
andreikovacs 0:764779eedf2d 98 #define RSSI_CCA_CONT 0x26
andreikovacs 0:764779eedf2d 99 //-------------- 0x27
andreikovacs 0:764779eedf2d 100 #define ASM_CTRL1 0x28
andreikovacs 0:764779eedf2d 101 #define ASM_CTRL2 0x29
andreikovacs 0:764779eedf2d 102 #define ASM_DATA_0 0x2A
andreikovacs 0:764779eedf2d 103 #define ASM_DATA_1 0x2B
andreikovacs 0:764779eedf2d 104 #define ASM_DATA_2 0x2C
andreikovacs 0:764779eedf2d 105 #define ASM_DATA_3 0x2D
andreikovacs 0:764779eedf2d 106 #define ASM_DATA_4 0x2E
andreikovacs 0:764779eedf2d 107 #define ASM_DATA_5 0x2F
andreikovacs 0:764779eedf2d 108 #define ASM_DATA_6 0x30
andreikovacs 0:764779eedf2d 109 #define ASM_DATA_7 0x31
andreikovacs 0:764779eedf2d 110 #define ASM_DATA_8 0x32
andreikovacs 0:764779eedf2d 111 #define ASM_DATA_9 0x33
andreikovacs 0:764779eedf2d 112 #define ASM_DATA_A 0x34
andreikovacs 0:764779eedf2d 113 #define ASM_DATA_B 0x35
andreikovacs 0:764779eedf2d 114 #define ASM_DATA_C 0x36
andreikovacs 0:764779eedf2d 115 #define ASM_DATA_D 0x37
andreikovacs 0:764779eedf2d 116 #define ASM_DATA_E 0x38
andreikovacs 0:764779eedf2d 117 #define ASM_DATA_F 0x39
andreikovacs 0:764779eedf2d 118 //------------------- 0x3A
andreikovacs 0:764779eedf2d 119 #define OVERWRITE_VER 0x3B
andreikovacs 0:764779eedf2d 120 #define CLK_OUT_CTRL 0x3C
andreikovacs 0:764779eedf2d 121 #define PWR_MODES 0x3D
andreikovacs 0:764779eedf2d 122 #define IAR_INDEX 0x3E
andreikovacs 0:764779eedf2d 123 #define IAR_DATA 0x3F
andreikovacs 0:764779eedf2d 124
andreikovacs 0:764779eedf2d 125
andreikovacs 0:764779eedf2d 126 #define PART_ID 0x00
andreikovacs 0:764779eedf2d 127 #define XTAL_TRIM 0x01
andreikovacs 0:764779eedf2d 128 #define PMC_LP_TRIM 0x02
andreikovacs 0:764779eedf2d 129 #define MACPANID0_LSB 0x03
andreikovacs 0:764779eedf2d 130 #define MACPANID0_MSB 0x04
andreikovacs 0:764779eedf2d 131 #define MACSHORTADDRS0_LSB 0x05
andreikovacs 0:764779eedf2d 132 #define MACSHORTADDRS0_MSB 0x06
andreikovacs 0:764779eedf2d 133 #define MACLONGADDRS0_0 0x07
andreikovacs 0:764779eedf2d 134 #define MACLONGADDRS0_8 0x08
andreikovacs 0:764779eedf2d 135 #define MACLONGADDRS0_16 0x09
andreikovacs 0:764779eedf2d 136 #define MACLONGADDRS0_24 0x0A
andreikovacs 0:764779eedf2d 137 #define MACLONGADDRS0_32 0x0B
andreikovacs 0:764779eedf2d 138 #define MACLONGADDRS0_40 0x0C
andreikovacs 0:764779eedf2d 139 #define MACLONGADDRS0_48 0x0D
andreikovacs 0:764779eedf2d 140 #define MACLONGADDRS0_56 0x0E
andreikovacs 0:764779eedf2d 141 #define RX_FRAME_FILTER 0x0F
andreikovacs 0:764779eedf2d 142 #define PLL_INT1 0x10
andreikovacs 0:764779eedf2d 143 #define PLL_FRAC1_LSB 0x11
andreikovacs 0:764779eedf2d 144 #define PLL_FRAC1_MSB 0x12
andreikovacs 0:764779eedf2d 145 #define MACPANID1_LSB 0x13
andreikovacs 0:764779eedf2d 146 #define MACPANID1_MSB 0x14
andreikovacs 0:764779eedf2d 147 #define MACSHORTADDRS1_LSB 0x15
andreikovacs 0:764779eedf2d 148 #define MACSHORTADDRS1_MSB 0x16
andreikovacs 0:764779eedf2d 149 #define MACLONGADDRS1_0 0x17
andreikovacs 0:764779eedf2d 150 #define MACLONGADDRS1_8 0x18
andreikovacs 0:764779eedf2d 151 #define MACLONGADDRS1_16 0x19
andreikovacs 0:764779eedf2d 152 #define MACLONGADDRS1_24 0x1A
andreikovacs 0:764779eedf2d 153 #define MACLONGADDRS1_32 0x1B
andreikovacs 0:764779eedf2d 154 #define MACLONGADDRS1_40 0x1C
andreikovacs 0:764779eedf2d 155 #define MACLONGADDRS1_48 0x1D
andreikovacs 0:764779eedf2d 156 #define MACLONGADDRS1_56 0x1E
andreikovacs 0:764779eedf2d 157 #define DUAL_PAN_CTRL 0x1F
andreikovacs 0:764779eedf2d 158 #define DUAL_PAN_DWELL 0x20
andreikovacs 0:764779eedf2d 159 #define DUAL_PAN_STS 0x21
andreikovacs 0:764779eedf2d 160 #define CCA1_THRESH 0x22
andreikovacs 0:764779eedf2d 161 #define CCA1_ED_OFFSET_COMP 0x23
andreikovacs 0:764779eedf2d 162 #define LQI_OFFSET_COMP 0x24
andreikovacs 0:764779eedf2d 163 #define CCA_CTRL 0x25
andreikovacs 0:764779eedf2d 164 #define CCA2_CORR_PEAKS 0x26
andreikovacs 0:764779eedf2d 165 #define CCA2_CORR_THRESH 0x27
andreikovacs 0:764779eedf2d 166 #define TMR_PRESCALE 0x28
andreikovacs 0:764779eedf2d 167 //---------------- 0x29
andreikovacs 0:764779eedf2d 168 #define GPIO_DATA 0x2A
andreikovacs 0:764779eedf2d 169 #define GPIO_DIR 0x2B
andreikovacs 0:764779eedf2d 170 #define GPIO_PUL_EN 0x2C
andreikovacs 0:764779eedf2d 171 #define GPIO_PUL_SEL 0x2D
andreikovacs 0:764779eedf2d 172 #define GPIO_DS 0x2E
andreikovacs 0:764779eedf2d 173 //-------------- 0x2F
andreikovacs 0:764779eedf2d 174 #define ANT_PAD_CTRL 0x30
andreikovacs 0:764779eedf2d 175 #define MISC_PAD_CTRL 0x31
andreikovacs 0:764779eedf2d 176 #define BSM_CTRL 0x32
andreikovacs 0:764779eedf2d 177 //--------------- 0x33
andreikovacs 0:764779eedf2d 178 #define _RNG 0x34
andreikovacs 0:764779eedf2d 179 #define RX_BYTE_COUNT 0x35
andreikovacs 0:764779eedf2d 180 #define RX_WTR_MARK 0x36
andreikovacs 0:764779eedf2d 181 #define SOFT_RESET 0x37
andreikovacs 0:764779eedf2d 182 #define TXDELAY 0x38
andreikovacs 0:764779eedf2d 183 #define ACKDELAY 0x39
andreikovacs 0:764779eedf2d 184 #define SEQ_MGR_CTRL 0x3A
andreikovacs 0:764779eedf2d 185 #define SEQ_MGR_STS 0x3B
andreikovacs 0:764779eedf2d 186 #define SEQ_T_STS 0x3C
andreikovacs 0:764779eedf2d 187 #define ABORT_STS 0x3D
andreikovacs 0:764779eedf2d 188 #define CCCA_BUSY_CNT 0x3E
andreikovacs 0:764779eedf2d 189 #define SRC_ADDR_CHECKSUM1 0x3F
andreikovacs 0:764779eedf2d 190 #define SRC_ADDR_CHECKSUM2 0x40
andreikovacs 0:764779eedf2d 191 #define SRC_TBL_VALID1 0x41
andreikovacs 0:764779eedf2d 192 #define SRC_TBL_VALID2 0x42
andreikovacs 0:764779eedf2d 193 #define FILTERFAIL_CODE1 0x43
andreikovacs 0:764779eedf2d 194 #define FILTERFAIL_CODE2 0x44
andreikovacs 0:764779eedf2d 195 #define SLOT_PRELOAD 0x45
andreikovacs 0:764779eedf2d 196 //---------------- 0x46
andreikovacs 0:764779eedf2d 197 #define CORR_VT 0x47
andreikovacs 0:764779eedf2d 198 #define SYNC_CTRL 0x48
andreikovacs 0:764779eedf2d 199 #define PN_LSB_0 0x49
andreikovacs 0:764779eedf2d 200 #define PN_LSB_1 0x4A
andreikovacs 0:764779eedf2d 201 #define PN_MSB_0 0x4B
andreikovacs 0:764779eedf2d 202 #define PN_MSB_1 0x4C
andreikovacs 0:764779eedf2d 203 #define CORR_NVAL 0x4D
andreikovacs 0:764779eedf2d 204 #define TX_MODE_CTRL 0x4E
andreikovacs 0:764779eedf2d 205 #define SNF_THR 0x4F
andreikovacs 0:764779eedf2d 206 #define FAD_THR 0x50
andreikovacs 0:764779eedf2d 207 #define ANT_AGC_CTRL 0x51
andreikovacs 0:764779eedf2d 208 #define AGC_THR1 0x52
andreikovacs 0:764779eedf2d 209 #define AGC_THR2 0x53
andreikovacs 0:764779eedf2d 210 #define AGC_HYS 0x54
andreikovacs 0:764779eedf2d 211 #define AFC 0x55
andreikovacs 0:764779eedf2d 212 //--------------- 0x56
andreikovacs 0:764779eedf2d 213 //--------------- 0x57
andreikovacs 0:764779eedf2d 214 #define PHY_STS 0x58
andreikovacs 0:764779eedf2d 215 #define RX_MAX_CORR 0x59
andreikovacs 0:764779eedf2d 216 #define RX_MAX_PREAMBLE 0x5A
andreikovacs 0:764779eedf2d 217 #define RSSI 0x5B
andreikovacs 0:764779eedf2d 218 //--------------- 0x5C
andreikovacs 0:764779eedf2d 219 //--------------- 0x5D
andreikovacs 0:764779eedf2d 220 #define PLL_DIG_CTRL 0x5E
andreikovacs 0:764779eedf2d 221 #define VCO_CAL 0x5F
andreikovacs 0:764779eedf2d 222 #define VCO_BEST_DIFF 0x60
andreikovacs 0:764779eedf2d 223 #define VCO_BIAS 0x61
andreikovacs 0:764779eedf2d 224 #define KMOD_CTRL 0x62
andreikovacs 0:764779eedf2d 225 #define KMOD_CAL 0x63
andreikovacs 0:764779eedf2d 226 #define PA_CAL 0x64
andreikovacs 0:764779eedf2d 227 #define PA_PWRCAL 0x65
andreikovacs 0:764779eedf2d 228 #define ATT_RSSI1 0x66
andreikovacs 0:764779eedf2d 229 #define ATT_RSSI2 0x67
andreikovacs 0:764779eedf2d 230 #define RSSI_OFFSET 0x68
andreikovacs 0:764779eedf2d 231 #define RSSI_SLOPE 0x69
andreikovacs 0:764779eedf2d 232 #define RSSI_CAL1 0x6A
andreikovacs 0:764779eedf2d 233 #define RSSI_CAL2 0x6B
andreikovacs 0:764779eedf2d 234 //--------------- 0x6C
andreikovacs 0:764779eedf2d 235 //--------------- 0x6D
andreikovacs 0:764779eedf2d 236 #define XTAL_CTRL 0x6E
andreikovacs 0:764779eedf2d 237 #define XTAL_COMP_MIN 0x6F
andreikovacs 0:764779eedf2d 238 #define XTAL_COMP_MAX 0x70
andreikovacs 0:764779eedf2d 239 #define XTAL_GM 0x71
andreikovacs 0:764779eedf2d 240 //--------------- 0x72
andreikovacs 0:764779eedf2d 241 //--------------- 0x73
andreikovacs 0:764779eedf2d 242 #define LNA_TUNE 0x74
andreikovacs 0:764779eedf2d 243 #define LNA_AGCGAIN 0x75
andreikovacs 0:764779eedf2d 244 //--------------- 0x76
andreikovacs 0:764779eedf2d 245 //--------------- 0x77
andreikovacs 0:764779eedf2d 246 #define CHF_PMA_GAIN 0x78
andreikovacs 0:764779eedf2d 247 #define CHF_IBUF 0x79
andreikovacs 0:764779eedf2d 248 #define CHF_QBUF 0x7A
andreikovacs 0:764779eedf2d 249 #define CHF_IRIN 0x7B
andreikovacs 0:764779eedf2d 250 #define CHF_QRIN 0x7C
andreikovacs 0:764779eedf2d 251 #define CHF_IL 0x7D
andreikovacs 0:764779eedf2d 252 #define CHF_QL 0x7E
andreikovacs 0:764779eedf2d 253 #define CHF_CC1 0x7F
andreikovacs 0:764779eedf2d 254 #define CHF_CCL 0x80
andreikovacs 0:764779eedf2d 255 #define CHF_CC2 0x81
andreikovacs 0:764779eedf2d 256 #define CHF_IROUT 0x82
andreikovacs 0:764779eedf2d 257 #define CHF_QROUT 0x83
andreikovacs 0:764779eedf2d 258 //--------------- 0x84
andreikovacs 0:764779eedf2d 259 //--------------- 0x85
andreikovacs 0:764779eedf2d 260 #define RSSI_CTRL 0x86
andreikovacs 0:764779eedf2d 261 //--------------- 0x87
andreikovacs 0:764779eedf2d 262 //--------------- 0x88
andreikovacs 0:764779eedf2d 263 #define PA_BIAS 0x89
andreikovacs 0:764779eedf2d 264 #define PA_TUNING 0x8A
andreikovacs 0:764779eedf2d 265 //--------------- 0x8B
andreikovacs 0:764779eedf2d 266 //--------------- 0x8C
andreikovacs 0:764779eedf2d 267 #define PMC_HP_TRIM 0x8D
andreikovacs 0:764779eedf2d 268 #define VREGA_TRIM 0x8E
andreikovacs 0:764779eedf2d 269 //--------------- 0x8F
andreikovacs 0:764779eedf2d 270 //--------------- 0x90
andreikovacs 0:764779eedf2d 271 #define VCO_CTRL1 0x91
andreikovacs 0:764779eedf2d 272 #define VCO_CTRL2 0x92
andreikovacs 0:764779eedf2d 273 //--------------- 0x93
andreikovacs 0:764779eedf2d 274 //--------------- 0x94
andreikovacs 0:764779eedf2d 275 #define ANA_SPARE_OUT1 0x95
andreikovacs 0:764779eedf2d 276 #define ANA_SPARE_OUT2 0x96
andreikovacs 0:764779eedf2d 277 #define ANA_SPARE_IN 0x97
andreikovacs 0:764779eedf2d 278 #define MISCELLANEOUS 0x98
andreikovacs 0:764779eedf2d 279 //--------------- 0x99
andreikovacs 0:764779eedf2d 280 #define SEQ_MGR_OVRD0 0x9A
andreikovacs 0:764779eedf2d 281 #define SEQ_MGR_OVRD1 0x9B
andreikovacs 0:764779eedf2d 282 #define SEQ_MGR_OVRD2 0x9C
andreikovacs 0:764779eedf2d 283 #define SEQ_MGR_OVRD3 0x9D
andreikovacs 0:764779eedf2d 284 #define SEQ_MGR_OVRD4 0x9E
andreikovacs 0:764779eedf2d 285 #define SEQ_MGR_OVRD5 0x9F
andreikovacs 0:764779eedf2d 286 #define SEQ_MGR_OVRD6 0xA0
andreikovacs 0:764779eedf2d 287 #define SEQ_MGR_OVRD7 0xA1
andreikovacs 0:764779eedf2d 288 //--------------- 0xA2
andreikovacs 0:764779eedf2d 289 #define TESTMODE_CTRL 0xA3
andreikovacs 0:764779eedf2d 290 #define DTM_CTRL1 0xA4
andreikovacs 0:764779eedf2d 291 #define DTM_CTRL2 0xA5
andreikovacs 0:764779eedf2d 292 #define ATM_CTRL1 0xA6
andreikovacs 0:764779eedf2d 293 #define ATM_CTRL2 0xA7
andreikovacs 0:764779eedf2d 294 #define ATM_CTRL3 0xA8
andreikovacs 0:764779eedf2d 295 //--------------- 0xA9
andreikovacs 0:764779eedf2d 296 #define LIM_FE_TEST_CTRL 0xAA
andreikovacs 0:764779eedf2d 297 #define CHF_TEST_CTRL 0xAB
andreikovacs 0:764779eedf2d 298 #define VCO_TEST_CTRL 0xAC
andreikovacs 0:764779eedf2d 299 #define PLL_TEST_CTRL 0xAD
andreikovacs 0:764779eedf2d 300 #define PA_TEST_CTRL 0xAE
andreikovacs 0:764779eedf2d 301 #define PMC_TEST_CTRL 0xAF
andreikovacs 0:764779eedf2d 302 #define SCAN_DTM_PROTECT_1 0xFE
andreikovacs 0:764779eedf2d 303 #define SCAN_DTM_PROTECT_0 0xFF
andreikovacs 0:764779eedf2d 304
andreikovacs 0:764779eedf2d 305 // IRQSTS1 bits
andreikovacs 0:764779eedf2d 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
andreikovacs 0:764779eedf2d 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
andreikovacs 0:764779eedf2d 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
andreikovacs 0:764779eedf2d 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
andreikovacs 0:764779eedf2d 310 #define cIRQSTS1_CCAIRQ (1<<3)
andreikovacs 0:764779eedf2d 311 #define cIRQSTS1_RXIRQ (1<<2)
andreikovacs 0:764779eedf2d 312 #define cIRQSTS1_TXIRQ (1<<1)
andreikovacs 0:764779eedf2d 313 #define cIRQSTS1_SEQIRQ (1<<0)
andreikovacs 0:764779eedf2d 314
andreikovacs 0:764779eedf2d 315 typedef union regIRQSTS1_tag{
andreikovacs 0:764779eedf2d 316 uint8_t byte;
andreikovacs 0:764779eedf2d 317 struct{
andreikovacs 0:764779eedf2d 318 uint8_t SEQIRQ:1;
andreikovacs 0:764779eedf2d 319 uint8_t TXIRQ:1;
andreikovacs 0:764779eedf2d 320 uint8_t RXIRQ:1;
andreikovacs 0:764779eedf2d 321 uint8_t CCAIRQ:1;
andreikovacs 0:764779eedf2d 322 uint8_t RXWTRMRKIRQ:1;
andreikovacs 0:764779eedf2d 323 uint8_t FILTERFAIL_IRQ:1;
andreikovacs 0:764779eedf2d 324 uint8_t PLL_UNLOCK_IRQ:1;
andreikovacs 0:764779eedf2d 325 uint8_t RX_FRM_PEND:1;
andreikovacs 0:764779eedf2d 326 }bit;
andreikovacs 0:764779eedf2d 327 } regIRQSTS1_t;
andreikovacs 0:764779eedf2d 328
andreikovacs 0:764779eedf2d 329 // IRQSTS2 bits
andreikovacs 0:764779eedf2d 330 #define cIRQSTS2_CRCVALID (1<<7)
andreikovacs 0:764779eedf2d 331 #define cIRQSTS2_CCA (1<<6)
andreikovacs 0:764779eedf2d 332 #define cIRQSTS2_SRCADDR (1<<5)
andreikovacs 0:764779eedf2d 333 #define cIRQSTS2_PI (1<<4)
andreikovacs 0:764779eedf2d 334 #define cIRQSTS2_TMRSTATUS (1<<3)
andreikovacs 0:764779eedf2d 335 #define cIRQSTS2_ASM_IRQ (1<<2)
andreikovacs 0:764779eedf2d 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
andreikovacs 0:764779eedf2d 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
andreikovacs 0:764779eedf2d 338
andreikovacs 0:764779eedf2d 339 typedef union regIRQSTS2_tag{
andreikovacs 0:764779eedf2d 340 uint8_t byte;
andreikovacs 0:764779eedf2d 341 struct{
andreikovacs 0:764779eedf2d 342 uint8_t WAKE_IRQ:1;
andreikovacs 0:764779eedf2d 343 uint8_t PB_ERR_IRQ:1;
andreikovacs 0:764779eedf2d 344 uint8_t ASM_IRQ:1;
andreikovacs 0:764779eedf2d 345 uint8_t TMRSTATUS:1;
andreikovacs 0:764779eedf2d 346 uint8_t PI:1;
andreikovacs 0:764779eedf2d 347 uint8_t SRCADDR:1;
andreikovacs 0:764779eedf2d 348 uint8_t CCA:1;
andreikovacs 0:764779eedf2d 349 uint8_t CRCVALID:1;
andreikovacs 0:764779eedf2d 350 }bit;
andreikovacs 0:764779eedf2d 351 } regIRQSTS2_t;
andreikovacs 0:764779eedf2d 352
andreikovacs 0:764779eedf2d 353 // IRQSTS3 bits
andreikovacs 0:764779eedf2d 354 #define cIRQSTS3_TMR4MSK (1<<7)
andreikovacs 0:764779eedf2d 355 #define cIRQSTS3_TMR3MSK (1<<6)
andreikovacs 0:764779eedf2d 356 #define cIRQSTS3_TMR2MSK (1<<5)
andreikovacs 0:764779eedf2d 357 #define cIRQSTS3_TMR1MSK (1<<4)
andreikovacs 0:764779eedf2d 358 #define cIRQSTS3_TMR4IRQ (1<<3)
andreikovacs 0:764779eedf2d 359 #define cIRQSTS3_TMR3IRQ (1<<2)
andreikovacs 0:764779eedf2d 360 #define cIRQSTS3_TMR2IRQ (1<<1)
andreikovacs 0:764779eedf2d 361 #define cIRQSTS3_TMR1IRQ (1<<0)
andreikovacs 0:764779eedf2d 362
andreikovacs 0:764779eedf2d 363 typedef union regIRQSTS3_tag{
andreikovacs 0:764779eedf2d 364 uint8_t byte;
andreikovacs 0:764779eedf2d 365 struct{
andreikovacs 0:764779eedf2d 366 uint8_t TMR1IRQ:1;
andreikovacs 0:764779eedf2d 367 uint8_t TMR2IRQ:1;
andreikovacs 0:764779eedf2d 368 uint8_t TMR3IRQ:1;
andreikovacs 0:764779eedf2d 369 uint8_t TMR4IRQ:1;
andreikovacs 0:764779eedf2d 370 uint8_t TMR1MSK:1;
andreikovacs 0:764779eedf2d 371 uint8_t TMR2MSK:1;
andreikovacs 0:764779eedf2d 372 uint8_t TMR3MSK:1;
andreikovacs 0:764779eedf2d 373 uint8_t TMR4MSK:1;
andreikovacs 0:764779eedf2d 374 }bit;
andreikovacs 0:764779eedf2d 375 } regIRQSTS3_t;
andreikovacs 0:764779eedf2d 376
andreikovacs 0:764779eedf2d 377 // PHY_CTRL1 bits
andreikovacs 0:764779eedf2d 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
andreikovacs 0:764779eedf2d 379 #define cPHY_CTRL1_SLOTTED (1<<6)
andreikovacs 0:764779eedf2d 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
andreikovacs 0:764779eedf2d 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
andreikovacs 0:764779eedf2d 382 #define cPHY_CTRL1_AUTOACK (1<<3)
andreikovacs 0:764779eedf2d 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
andreikovacs 0:764779eedf2d 384
andreikovacs 0:764779eedf2d 385 typedef union regPHY_CTRL1_tag{
andreikovacs 0:764779eedf2d 386 uint8_t byte;
andreikovacs 0:764779eedf2d 387 struct{
andreikovacs 0:764779eedf2d 388 uint8_t XCVSEQ:3;
andreikovacs 0:764779eedf2d 389 uint8_t AUTOACK:1;
andreikovacs 0:764779eedf2d 390 uint8_t RXACKRQD:1;
andreikovacs 0:764779eedf2d 391 uint8_t CCABFRTX:1;
andreikovacs 0:764779eedf2d 392 uint8_t SLOTTED:1;
andreikovacs 0:764779eedf2d 393 uint8_t TMRTRIGEN:1;
andreikovacs 0:764779eedf2d 394 }bit;
andreikovacs 0:764779eedf2d 395 } regPHY_CTRL1_t;
andreikovacs 0:764779eedf2d 396
andreikovacs 0:764779eedf2d 397 // PHY_CTRL2 bits
andreikovacs 0:764779eedf2d 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
andreikovacs 0:764779eedf2d 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
andreikovacs 0:764779eedf2d 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
andreikovacs 0:764779eedf2d 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
andreikovacs 0:764779eedf2d 402 #define cPHY_CTRL2_CCAMSK (1<<3)
andreikovacs 0:764779eedf2d 403 #define cPHY_CTRL2_RXMSK (1<<2)
andreikovacs 0:764779eedf2d 404 #define cPHY_CTRL2_TXMSK (1<<1)
andreikovacs 0:764779eedf2d 405 #define cPHY_CTRL2_SEQMSK (1<<0)
andreikovacs 0:764779eedf2d 406
andreikovacs 0:764779eedf2d 407 typedef union regPHY_CTRL2_tag{
andreikovacs 0:764779eedf2d 408 uint8_t byte;
andreikovacs 0:764779eedf2d 409 struct{
andreikovacs 0:764779eedf2d 410 uint8_t SEQMSK:1;
andreikovacs 0:764779eedf2d 411 uint8_t TXMSK:1;
andreikovacs 0:764779eedf2d 412 uint8_t RXMSK:1;
andreikovacs 0:764779eedf2d 413 uint8_t CCAMSK:1;
andreikovacs 0:764779eedf2d 414 uint8_t RX_WMRK_MSK:1;
andreikovacs 0:764779eedf2d 415 uint8_t FILTERFAIL_MSK:1;
andreikovacs 0:764779eedf2d 416 uint8_t PLL_UNLOCK_MSK:1;
andreikovacs 0:764779eedf2d 417 uint8_t CRC_MSK:1;
andreikovacs 0:764779eedf2d 418 }bit;
andreikovacs 0:764779eedf2d 419 } regPHY_CTRL2_t;
andreikovacs 0:764779eedf2d 420
andreikovacs 0:764779eedf2d 421 // PHY_CTRL3 bits
andreikovacs 0:764779eedf2d 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
andreikovacs 0:764779eedf2d 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
andreikovacs 0:764779eedf2d 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
andreikovacs 0:764779eedf2d 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
andreikovacs 0:764779eedf2d 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
andreikovacs 0:764779eedf2d 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
andreikovacs 0:764779eedf2d 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
andreikovacs 0:764779eedf2d 429
andreikovacs 0:764779eedf2d 430 typedef union regPHY_CTRL3_tag{
andreikovacs 0:764779eedf2d 431 uint8_t byte;
andreikovacs 0:764779eedf2d 432 struct{
andreikovacs 0:764779eedf2d 433 uint8_t WAKE_MSK:1;
andreikovacs 0:764779eedf2d 434 uint8_t PB_ERR_MSK:1;
andreikovacs 0:764779eedf2d 435 uint8_t ASM_MSK:1;
andreikovacs 0:764779eedf2d 436 uint8_t RESERVED:1;
andreikovacs 0:764779eedf2d 437 uint8_t TMR1CMP_EN:1;
andreikovacs 0:764779eedf2d 438 uint8_t TMR2CMP_EN:1;
andreikovacs 0:764779eedf2d 439 uint8_t TMR3CMP_EN:1;
andreikovacs 0:764779eedf2d 440 uint8_t TMR4CMP_EN:1;
andreikovacs 0:764779eedf2d 441 }bit;
andreikovacs 0:764779eedf2d 442 } regPHY_CTRL3_t;
andreikovacs 0:764779eedf2d 443
andreikovacs 0:764779eedf2d 444 // RX_FRM_LEN bits
andreikovacs 0:764779eedf2d 445 #define cRX_FRAME_LENGTH (0x7F)
andreikovacs 0:764779eedf2d 446
andreikovacs 0:764779eedf2d 447 // PHY_CTRL4 bits
andreikovacs 0:764779eedf2d 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
andreikovacs 0:764779eedf2d 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
andreikovacs 0:764779eedf2d 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
andreikovacs 0:764779eedf2d 451 #define cPHY_CTRL4_CCATYPE (3<<0)
andreikovacs 0:764779eedf2d 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
andreikovacs 0:764779eedf2d 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
andreikovacs 0:764779eedf2d 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
andreikovacs 0:764779eedf2d 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
andreikovacs 0:764779eedf2d 456
andreikovacs 0:764779eedf2d 457 typedef union regPHY_CTRL4_tag{
andreikovacs 0:764779eedf2d 458 uint8_t byte;
andreikovacs 0:764779eedf2d 459 struct{
andreikovacs 0:764779eedf2d 460 uint8_t TC2PRIME_EN:1;
andreikovacs 0:764779eedf2d 461 uint8_t PROMISCUOUS:1;
andreikovacs 0:764779eedf2d 462 uint8_t TMRLOAD:1;
andreikovacs 0:764779eedf2d 463 uint8_t CCATYPE:2;
andreikovacs 0:764779eedf2d 464 uint8_t PANCORDNTR0:1;
andreikovacs 0:764779eedf2d 465 uint8_t TC3TMOUT:1;
andreikovacs 0:764779eedf2d 466 uint8_t TRCV_MSK:1;
andreikovacs 0:764779eedf2d 467 }bit;
andreikovacs 0:764779eedf2d 468 } regPHY_CTRL4_t;
andreikovacs 0:764779eedf2d 469
andreikovacs 0:764779eedf2d 470 // SRC_CTRL bits
andreikovacs 0:764779eedf2d 471 #define cSRC_CTRL_INDEX (0x0F)
andreikovacs 0:764779eedf2d 472 #define cSRC_CTRL_INDEX_Shift_c (4)
andreikovacs 0:764779eedf2d 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
andreikovacs 0:764779eedf2d 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
andreikovacs 0:764779eedf2d 475 #define cSRC_CTRL_INDEX_EN (1<<1)
andreikovacs 0:764779eedf2d 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
andreikovacs 0:764779eedf2d 477
andreikovacs 0:764779eedf2d 478 typedef union regSRC_CTRL_tag{
andreikovacs 0:764779eedf2d 479 uint8_t byte;
andreikovacs 0:764779eedf2d 480 struct{
andreikovacs 0:764779eedf2d 481 uint8_t INDEX_DISABLE:1;
andreikovacs 0:764779eedf2d 482 uint8_t INDEX_EN:1;
andreikovacs 0:764779eedf2d 483 uint8_t SRCADDR_EN:1;
andreikovacs 0:764779eedf2d 484 uint8_t ACK_FRM_PND:1;
andreikovacs 0:764779eedf2d 485 uint8_t INDEX:4;
andreikovacs 0:764779eedf2d 486 }bit;
andreikovacs 0:764779eedf2d 487 } regSRC_CTRL_t;
andreikovacs 0:764779eedf2d 488
andreikovacs 0:764779eedf2d 489 // ASM_CTRL1 bits
andreikovacs 0:764779eedf2d 490 #define cASM_CTRL1_CLEAR (1<<7)
andreikovacs 0:764779eedf2d 491 #define cASM_CTRL1_START (1<<6)
andreikovacs 0:764779eedf2d 492 #define cASM_CTRL1_SELFTST (1<<5)
andreikovacs 0:764779eedf2d 493 #define cASM_CTRL1_CTR (1<<4)
andreikovacs 0:764779eedf2d 494 #define cASM_CTRL1_CBC (1<<3)
andreikovacs 0:764779eedf2d 495 #define cASM_CTRL1_AES (1<<2)
andreikovacs 0:764779eedf2d 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
andreikovacs 0:764779eedf2d 497
andreikovacs 0:764779eedf2d 498 // ASM_CTRL2 bits
andreikovacs 0:764779eedf2d 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
andreikovacs 0:764779eedf2d 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
andreikovacs 0:764779eedf2d 501 #define cASM_CTRL2_TSTPAS (1<<1)
andreikovacs 0:764779eedf2d 502
andreikovacs 0:764779eedf2d 503 // CLK_OUT_CTRL bits
andreikovacs 0:764779eedf2d 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
andreikovacs 0:764779eedf2d 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
andreikovacs 0:764779eedf2d 506 #define cCLK_OUT_CTRL_SR (1<<5)
andreikovacs 0:764779eedf2d 507 #define cCLK_OUT_CTRL_DS (1<<4)
andreikovacs 0:764779eedf2d 508 #define cCLK_OUT_CTRL_EN (1<<3)
andreikovacs 0:764779eedf2d 509 #define cCLK_OUT_CTRL_DIV (7)
andreikovacs 0:764779eedf2d 510
andreikovacs 0:764779eedf2d 511 // PWR_MODES bits
andreikovacs 0:764779eedf2d 512 #define cPWR_MODES_XTAL_READY (1<<5)
andreikovacs 0:764779eedf2d 513 #define cPWR_MODES_XTALEN (1<<4)
andreikovacs 0:764779eedf2d 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
andreikovacs 0:764779eedf2d 515 #define cPWR_MODES_AUTODOZE (1<<1)
andreikovacs 0:764779eedf2d 516 #define cPWR_MODES_PMC_MODE (1<<0)
andreikovacs 0:764779eedf2d 517
andreikovacs 0:764779eedf2d 518 // RX_FRAME_FILTER bits
andreikovacs 0:764779eedf2d 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
andreikovacs 0:764779eedf2d 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
andreikovacs 0:764779eedf2d 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
andreikovacs 0:764779eedf2d 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
andreikovacs 0:764779eedf2d 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
andreikovacs 0:764779eedf2d 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
andreikovacs 0:764779eedf2d 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
andreikovacs 0:764779eedf2d 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
andreikovacs 0:764779eedf2d 527
andreikovacs 0:764779eedf2d 528 typedef union regRX_FRAME_FILTER_tag{
andreikovacs 0:764779eedf2d 529 uint8_t byte;
andreikovacs 0:764779eedf2d 530 struct{
andreikovacs 0:764779eedf2d 531 uint8_t FRAME_FLT_BEACON_FT:1;
andreikovacs 0:764779eedf2d 532 uint8_t FRAME_FLT_DATA_FT:1;
andreikovacs 0:764779eedf2d 533 uint8_t FRAME_FLT_ACK_FT:1;
andreikovacs 0:764779eedf2d 534 uint8_t FRAME_FLT_CMD_FT:1;
andreikovacs 0:764779eedf2d 535 uint8_t FRAME_FLT_NS_FT:1;
andreikovacs 0:764779eedf2d 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
andreikovacs 0:764779eedf2d 537 uint8_t FRAME_FLT_FRM_VER:2;
andreikovacs 0:764779eedf2d 538 }bit;
andreikovacs 0:764779eedf2d 539 } regRX_FRAME_FILTER_t;
andreikovacs 0:764779eedf2d 540
andreikovacs 0:764779eedf2d 541 // DUAL_PAN_CTRL bits
andreikovacs 0:764779eedf2d 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
andreikovacs 0:764779eedf2d 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
andreikovacs 0:764779eedf2d 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
andreikovacs 0:764779eedf2d 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
andreikovacs 0:764779eedf2d 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
andreikovacs 0:764779eedf2d 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
andreikovacs 0:764779eedf2d 548
andreikovacs 0:764779eedf2d 549 // DUAL_PAN_STS bits
andreikovacs 0:764779eedf2d 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
andreikovacs 0:764779eedf2d 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
andreikovacs 0:764779eedf2d 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
andreikovacs 0:764779eedf2d 553
andreikovacs 0:764779eedf2d 554 // CCA_CTRL bits
andreikovacs 0:764779eedf2d 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
andreikovacs 0:764779eedf2d 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
andreikovacs 0:764779eedf2d 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
andreikovacs 0:764779eedf2d 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
andreikovacs 0:764779eedf2d 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
andreikovacs 0:764779eedf2d 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
andreikovacs 0:764779eedf2d 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
andreikovacs 0:764779eedf2d 562
andreikovacs 0:764779eedf2d 563 // GPIO_DATA bits
andreikovacs 0:764779eedf2d 564 #define cGPIO_DATA_7 (1<<7)
andreikovacs 0:764779eedf2d 565 #define cGPIO_DATA_6 (1<<6)
andreikovacs 0:764779eedf2d 566 #define cGPIO_DATA_5 (1<<5)
andreikovacs 0:764779eedf2d 567 #define cGPIO_DATA_4 (1<<4)
andreikovacs 0:764779eedf2d 568 #define cGPIO_DATA_3 (1<<3)
andreikovacs 0:764779eedf2d 569 #define cGPIO_DATA_2 (1<<2)
andreikovacs 0:764779eedf2d 570 #define cGPIO_DATA_1 (1<<1)
andreikovacs 0:764779eedf2d 571 #define cGPIO_DATA_0 (1<<0)
andreikovacs 0:764779eedf2d 572
andreikovacs 0:764779eedf2d 573 // GPIO_DIR bits
andreikovacs 0:764779eedf2d 574 #define cGPIO_DIR_7 (1<<7)
andreikovacs 0:764779eedf2d 575 #define cGPIO_DIR_6 (1<<6)
andreikovacs 0:764779eedf2d 576 #define cGPIO_DIR_5 (1<<5)
andreikovacs 0:764779eedf2d 577 #define cGPIO_DIR_4 (1<<4)
andreikovacs 0:764779eedf2d 578 #define cGPIO_DIR_3 (1<<3)
andreikovacs 0:764779eedf2d 579 #define cGPIO_DIR_2 (1<<2)
andreikovacs 0:764779eedf2d 580 #define cGPIO_DIR_1 (1<<1)
andreikovacs 0:764779eedf2d 581 #define cGPIO_DIR_0 (1<<0)
andreikovacs 0:764779eedf2d 582
andreikovacs 0:764779eedf2d 583 // GPIO_PUL_EN bits
andreikovacs 0:764779eedf2d 584 #define cGPIO_PUL_EN_7 (1<<7)
andreikovacs 0:764779eedf2d 585 #define cGPIO_PUL_EN_6 (1<<6)
andreikovacs 0:764779eedf2d 586 #define cGPIO_PUL_EN_5 (1<<5)
andreikovacs 0:764779eedf2d 587 #define cGPIO_PUL_EN_4 (1<<4)
andreikovacs 0:764779eedf2d 588 #define cGPIO_PUL_EN_3 (1<<3)
andreikovacs 0:764779eedf2d 589 #define cGPIO_PUL_EN_2 (1<<2)
andreikovacs 0:764779eedf2d 590 #define cGPIO_PUL_EN_1 (1<<1)
andreikovacs 0:764779eedf2d 591 #define cGPIO_PUL_EN_0 (1<<0)
andreikovacs 0:764779eedf2d 592
andreikovacs 0:764779eedf2d 593 // GPIO_PUL_SEL bits
andreikovacs 0:764779eedf2d 594 #define cGPIO_PUL_SEL_7 (1<<7)
andreikovacs 0:764779eedf2d 595 #define cGPIO_PUL_SEL_6 (1<<6)
andreikovacs 0:764779eedf2d 596 #define cGPIO_PUL_SEL_5 (1<<5)
andreikovacs 0:764779eedf2d 597 #define cGPIO_PUL_SEL_4 (1<<4)
andreikovacs 0:764779eedf2d 598 #define cGPIO_PUL_SEL_3 (1<<3)
andreikovacs 0:764779eedf2d 599 #define cGPIO_PUL_SEL_2 (1<<2)
andreikovacs 0:764779eedf2d 600 #define cGPIO_PUL_SEL_1 (1<<1)
andreikovacs 0:764779eedf2d 601 #define cGPIO_PUL_SEL_0 (1<<0)
andreikovacs 0:764779eedf2d 602
andreikovacs 0:764779eedf2d 603 // GPIO_DS bits
andreikovacs 0:764779eedf2d 604 #define cGPIO_DS_7 (1<<7)
andreikovacs 0:764779eedf2d 605 #define cGPIO_DS_6 (1<<6)
andreikovacs 0:764779eedf2d 606 #define cGPIO_DS_5 (1<<5)
andreikovacs 0:764779eedf2d 607 #define cGPIO_DS_4 (1<<4)
andreikovacs 0:764779eedf2d 608 #define cGPIO_DS_3 (1<<3)
andreikovacs 0:764779eedf2d 609 #define cGPIO_DS_2 (1<<2)
andreikovacs 0:764779eedf2d 610 #define cGPIO_DS_1 (1<<1)
andreikovacs 0:764779eedf2d 611 #define cGPIO_DS_0 (1<<0)
andreikovacs 0:764779eedf2d 612
andreikovacs 0:764779eedf2d 613 // SPI_CTRL bits
andreikovacs 0:764779eedf2d 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
andreikovacs 0:764779eedf2d 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
andreikovacs 0:764779eedf2d 616
andreikovacs 0:764779eedf2d 617 // ANT_PAD_CTRL bits
andreikovacs 0:764779eedf2d 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
andreikovacs 0:764779eedf2d 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
andreikovacs 0:764779eedf2d 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
andreikovacs 0:764779eedf2d 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
andreikovacs 0:764779eedf2d 622 #define cANT_PAD_CTRL_ANTX_EN (3)
andreikovacs 0:764779eedf2d 623
andreikovacs 0:764779eedf2d 624 // MISC_PAD_CTRL bits
andreikovacs 0:764779eedf2d 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
andreikovacs 0:764779eedf2d 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
andreikovacs 0:764779eedf2d 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
andreikovacs 0:764779eedf2d 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
andreikovacs 0:764779eedf2d 629
andreikovacs 0:764779eedf2d 630 // ANT_AGC_CTRL bits
andreikovacs 0:764779eedf2d 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
andreikovacs 0:764779eedf2d 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
andreikovacs 0:764779eedf2d 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
andreikovacs 0:764779eedf2d 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
andreikovacs 0:764779eedf2d 635
andreikovacs 0:764779eedf2d 636 // BSM_CTRL bits
andreikovacs 0:764779eedf2d 637 #define cBSM_CTRL_BSM_EN (1<<0)
andreikovacs 0:764779eedf2d 638
andreikovacs 0:764779eedf2d 639 // SOFT_RESET bits
andreikovacs 0:764779eedf2d 640 #define cSOFT_RESET_SOG_RST (1<<7)
andreikovacs 0:764779eedf2d 641 #define cSOFT_RESET_REGS_RST (1<<4)
andreikovacs 0:764779eedf2d 642 #define cSOFT_RESET_PLL_RST (1<<3)
andreikovacs 0:764779eedf2d 643 #define cSOFT_RESET_TX_RST (1<<2)
andreikovacs 0:764779eedf2d 644 #define cSOFT_RESET_RX_RST (1<<1)
andreikovacs 0:764779eedf2d 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
andreikovacs 0:764779eedf2d 646
andreikovacs 0:764779eedf2d 647 // SEQ_MGR_CTRL bits
andreikovacs 0:764779eedf2d 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
andreikovacs 0:764779eedf2d 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
andreikovacs 0:764779eedf2d 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
andreikovacs 0:764779eedf2d 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
andreikovacs 0:764779eedf2d 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
andreikovacs 0:764779eedf2d 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
andreikovacs 0:764779eedf2d 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
andreikovacs 0:764779eedf2d 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
andreikovacs 0:764779eedf2d 656
andreikovacs 0:764779eedf2d 657 // SEQ_MGR_STS bits
andreikovacs 0:764779eedf2d 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
andreikovacs 0:764779eedf2d 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
andreikovacs 0:764779eedf2d 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
andreikovacs 0:764779eedf2d 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
andreikovacs 0:764779eedf2d 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
andreikovacs 0:764779eedf2d 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
andreikovacs 0:764779eedf2d 664
andreikovacs 0:764779eedf2d 665 // ABORT_STS bits
andreikovacs 0:764779eedf2d 666 #define cABORT_STS_PLL_ABORTED (1<<2)
andreikovacs 0:764779eedf2d 667 #define cABORT_STS_TC3_ABORTED (1<<1)
andreikovacs 0:764779eedf2d 668 #define cABORT_STS_SW_ABORTED (1<<0)
andreikovacs 0:764779eedf2d 669
andreikovacs 0:764779eedf2d 670 // FILTERFAIL_CODE2 bits
andreikovacs 0:764779eedf2d 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
andreikovacs 0:764779eedf2d 672 #define cFILTERFAIL_CODE2_9_8 (3)
andreikovacs 0:764779eedf2d 673
andreikovacs 0:764779eedf2d 674 // PHY_STS bits
andreikovacs 0:764779eedf2d 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
andreikovacs 0:764779eedf2d 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
andreikovacs 0:764779eedf2d 677 #define cPHY_STS_PLL_LOCK (1<<5)
andreikovacs 0:764779eedf2d 678 #define cPHY_STS_CRCVALID (1<<3)
andreikovacs 0:764779eedf2d 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
andreikovacs 0:764779eedf2d 680 #define cPHY_STS_SFD_DET (1<<1)
andreikovacs 0:764779eedf2d 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
andreikovacs 0:764779eedf2d 682
andreikovacs 0:764779eedf2d 683 // TESTMODE_CTRL bits
andreikovacs 0:764779eedf2d 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
andreikovacs 0:764779eedf2d 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
andreikovacs 0:764779eedf2d 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
andreikovacs 0:764779eedf2d 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
andreikovacs 0:764779eedf2d 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
andreikovacs 0:764779eedf2d 689
andreikovacs 0:764779eedf2d 690 // DTM_CTRL1 bits
andreikovacs 0:764779eedf2d 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
andreikovacs 0:764779eedf2d 692 #define cDTM_CTRL1_DTM_EN (1<<6)
andreikovacs 0:764779eedf2d 693 #define cDTM_CTRL1_PAGE5 (1<<5)
andreikovacs 0:764779eedf2d 694 #define cDTM_CTRL1_PAGE4 (1<<4)
andreikovacs 0:764779eedf2d 695 #define cDTM_CTRL1_PAGE3 (1<<3)
andreikovacs 0:764779eedf2d 696 #define cDTM_CTRL1_PAGE2 (1<<2)
andreikovacs 0:764779eedf2d 697 #define cDTM_CTRL1_PAGE1 (1<<1)
andreikovacs 0:764779eedf2d 698 #define cDTM_CTRL1_PAGE0 (1<<0)
andreikovacs 0:764779eedf2d 699
andreikovacs 0:764779eedf2d 700 // TX_MODE_CTRL
andreikovacs 0:764779eedf2d 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
andreikovacs 0:764779eedf2d 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
andreikovacs 0:764779eedf2d 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
andreikovacs 0:764779eedf2d 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
andreikovacs 0:764779eedf2d 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
andreikovacs 0:764779eedf2d 706
andreikovacs 0:764779eedf2d 707 #define cTX_MODE_CTRL_DTS_MASK (7)
andreikovacs 0:764779eedf2d 708
andreikovacs 0:764779eedf2d 709 // CLK_OUT_CTRL bits
andreikovacs 0:764779eedf2d 710 #define cCLK_OUT_EXTEND (1<<7)
andreikovacs 0:764779eedf2d 711 #define cCLK_OUT_HIZ (1<<6)
andreikovacs 0:764779eedf2d 712 #define cCLK_OUT_SR (1<<5)
andreikovacs 0:764779eedf2d 713 #define cCLK_OUT_DS (1<<4)
andreikovacs 0:764779eedf2d 714 #define cCLK_OUT_EN (1<<3)
andreikovacs 0:764779eedf2d 715 #define cCLK_OUT_DIV_Mask (7<<0)
andreikovacs 0:764779eedf2d 716
andreikovacs 0:764779eedf2d 717 #define gCLK_OUT_FREQ_32_MHz (0)
andreikovacs 0:764779eedf2d 718 #define gCLK_OUT_FREQ_16_MHz (1)
andreikovacs 0:764779eedf2d 719 #define gCLK_OUT_FREQ_8_MHz (2)
andreikovacs 0:764779eedf2d 720 #define gCLK_OUT_FREQ_4_MHz (3)
andreikovacs 0:764779eedf2d 721 #define gCLK_OUT_FREQ_1_MHz (4)
andreikovacs 0:764779eedf2d 722 #define gCLK_OUT_FREQ_250_KHz (5)
andreikovacs 0:764779eedf2d 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
andreikovacs 0:764779eedf2d 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
andreikovacs 0:764779eedf2d 725 #define gCLK_OUT_FREQ_DISABLE (8)
andreikovacs 0:764779eedf2d 726
andreikovacs 0:764779eedf2d 727
andreikovacs 0:764779eedf2d 728
andreikovacs 0:764779eedf2d 729
andreikovacs 0:764779eedf2d 730 #endif /* __MCR20_REG_H__ */