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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/cmsis_nvic.c@270:e2babe29baf8, 2014-08-01 (annotated)

Committer:
mbed_official
Date:
Fri Aug 01 14:45:06 2014 +0100
Revision:
270:e2babe29baf8
Parent:
targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/cmsis_nvic.c@104:a6a92e2e5a92
Child:
358:9d7ef901f004
Synchronized with git revision 988c22d5984ba5565d9e83305cc1eb6431a683ee



Full URL: https://github.com/mbedmicro/mbed/commit/988c22d5984ba5565d9e83305cc1eb6431a683ee/



Fixed L6235E link error for NRF51822 variants

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 85:e1a8e879a6a9 1 /* mbed Microcontroller Library - cmsis_nvic for LCP407x_8x
mbed_official 85:e1a8e879a6a9 2 * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
mbed_official 85:e1a8e879a6a9 3 *
mbed_official 85:e1a8e879a6a9 4 * CMSIS-style functionality to support dynamic vectors
mbed_official 85:e1a8e879a6a9 5 */
mbed_official 85:e1a8e879a6a9 6 #include "cmsis_nvic.h"
mbed_official 85:e1a8e879a6a9 7
mbed_official 85:e1a8e879a6a9 8 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
mbed_official 85:e1a8e879a6a9 9 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
mbed_official 85:e1a8e879a6a9 10 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
mbed_official 85:e1a8e879a6a9 11 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
mbed_official 85:e1a8e879a6a9 12 *
mbed_official 85:e1a8e879a6a9 13 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
mbed_official 85:e1a8e879a6a9 14 * above the vector table before 0x200 will actually go to RAM. So we need to provide
mbed_official 85:e1a8e879a6a9 15 * a solution where the compiler gets the right results based on the memory map
mbed_official 85:e1a8e879a6a9 16 *
mbed_official 85:e1a8e879a6a9 17 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
mbed_official 85:e1a8e879a6a9 18 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
mbed_official 85:e1a8e879a6a9 19 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
mbed_official 85:e1a8e879a6a9 20 *
mbed_official 85:e1a8e879a6a9 21 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
mbed_official 85:e1a8e879a6a9 22 * - No flash accesses will go to ram, as there will be nothing there
mbed_official 85:e1a8e879a6a9 23 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
mbed_official 85:e1a8e879a6a9 24 * - RAM overhead: 0, FLASH overhead: 320 bytes
mbed_official 85:e1a8e879a6a9 25 *
mbed_official 85:e1a8e879a6a9 26 * Option 2 is the one to go for, as RAM is the most valuable resource
mbed_official 85:e1a8e879a6a9 27 */
mbed_official 85:e1a8e879a6a9 28
mbed_official 85:e1a8e879a6a9 29
mbed_official 85:e1a8e879a6a9 30 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
mbed_official 85:e1a8e879a6a9 31 #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
mbed_official 85:e1a8e879a6a9 32 /*
mbed_official 85:e1a8e879a6a9 33 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
mbed_official 85:e1a8e879a6a9 34 uint32_t *vectors = (uint32_t*)SCB->VTOR;
mbed_official 85:e1a8e879a6a9 35 uint32_t i;
mbed_official 85:e1a8e879a6a9 36
mbed_official 85:e1a8e879a6a9 37 // Copy and switch to dynamic vectors if the first time called
mbed_official 85:e1a8e879a6a9 38 if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
mbed_official 85:e1a8e879a6a9 39 uint32_t *old_vectors = vectors;
mbed_official 85:e1a8e879a6a9 40 vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
mbed_official 85:e1a8e879a6a9 41 for (i=0; i<NVIC_NUM_VECTORS; i++) {
mbed_official 85:e1a8e879a6a9 42 vectors[i] = old_vectors[i];
mbed_official 85:e1a8e879a6a9 43 }
mbed_official 85:e1a8e879a6a9 44 SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
mbed_official 85:e1a8e879a6a9 45 }
mbed_official 85:e1a8e879a6a9 46 vectors[IRQn + 16] = vector;
mbed_official 85:e1a8e879a6a9 47 }
mbed_official 85:e1a8e879a6a9 48
mbed_official 85:e1a8e879a6a9 49 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
mbed_official 85:e1a8e879a6a9 50 uint32_t *vectors = (uint32_t*)SCB->VTOR;
mbed_official 85:e1a8e879a6a9 51 return vectors[IRQn + 16];
mbed_official 85:e1a8e879a6a9 52 }*/
mbed_official 85:e1a8e879a6a9 53
mbed_official 85:e1a8e879a6a9 54 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
mbed_official 104:a6a92e2e5a92 55 // int i;
mbed_official 85:e1a8e879a6a9 56 // Space for dynamic vectors, initialised to allocate in R/W
mbed_official 85:e1a8e879a6a9 57 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
mbed_official 85:e1a8e879a6a9 58 /*
mbed_official 85:e1a8e879a6a9 59 // Copy and switch to dynamic vectors if first time called
mbed_official 85:e1a8e879a6a9 60 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
mbed_official 85:e1a8e879a6a9 61 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
mbed_official 85:e1a8e879a6a9 62 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
mbed_official 85:e1a8e879a6a9 63 vectors[i] = old_vectors[i];
mbed_official 85:e1a8e879a6a9 64 }
mbed_official 85:e1a8e879a6a9 65 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
mbed_official 85:e1a8e879a6a9 66 }*/
mbed_official 85:e1a8e879a6a9 67
mbed_official 85:e1a8e879a6a9 68 // Set the vector
mbed_official 85:e1a8e879a6a9 69 vectors[IRQn + 16] = vector;
mbed_official 85:e1a8e879a6a9 70 }
mbed_official 85:e1a8e879a6a9 71
mbed_official 85:e1a8e879a6a9 72 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
mbed_official 85:e1a8e879a6a9 73 // We can always read vectors at 0x0, as the addresses are remapped
mbed_official 85:e1a8e879a6a9 74 uint32_t *vectors = (uint32_t*)0;
mbed_official 85:e1a8e879a6a9 75
mbed_official 85:e1a8e879a6a9 76 // Return the vector
mbed_official 85:e1a8e879a6a9 77 return vectors[IRQn + 16];
mbed_official 85:e1a8e879a6a9 78 }