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TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_rcc.h@93:e188a91d3eaa, 2015-02-03 (annotated)

Committer:
Kojto
Date:
Tue Feb 03 15:31:20 2015 +0000
Revision:
93:e188a91d3eaa
Release 93 of the mbed library



Main changes:



- Renesas RZ_A1H bugfixes - i2c, ticker

- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,

                Dragonfly 411RE,

- BusXXX - is connected method, plus operators addition

- LPC8xx - I2c fixes

- timestamp_t reverted to uint32_t

- RTX - fixes regarding stack (alignment, magic word)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f4xx_hal_rcc.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.1.0
Kojto 93:e188a91d3eaa 6 * @date 19-June-2014
Kojto 93:e188a91d3eaa 7 * @brief Header file of RCC HAL module.
Kojto 93:e188a91d3eaa 8 ******************************************************************************
Kojto 93:e188a91d3eaa 9 * @attention
Kojto 93:e188a91d3eaa 10 *
Kojto 93:e188a91d3eaa 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 12 *
Kojto 93:e188a91d3eaa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 14 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 16 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 19 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 21 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 22 * without specific prior written permission.
Kojto 93:e188a91d3eaa 23 *
Kojto 93:e188a91d3eaa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 34 *
Kojto 93:e188a91d3eaa 35 ******************************************************************************
Kojto 93:e188a91d3eaa 36 */
Kojto 93:e188a91d3eaa 37
Kojto 93:e188a91d3eaa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 93:e188a91d3eaa 39 #ifndef __STM32F4xx_HAL_RCC_H
Kojto 93:e188a91d3eaa 40 #define __STM32F4xx_HAL_RCC_H
Kojto 93:e188a91d3eaa 41
Kojto 93:e188a91d3eaa 42 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 43 extern "C" {
Kojto 93:e188a91d3eaa 44 #endif
Kojto 93:e188a91d3eaa 45
Kojto 93:e188a91d3eaa 46 /* Includes ------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 47 #include "stm32f4xx_hal_def.h"
Kojto 93:e188a91d3eaa 48
Kojto 93:e188a91d3eaa 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 93:e188a91d3eaa 50 * @{
Kojto 93:e188a91d3eaa 51 */
Kojto 93:e188a91d3eaa 52
Kojto 93:e188a91d3eaa 53 /** @addtogroup RCC
Kojto 93:e188a91d3eaa 54 * @{
Kojto 93:e188a91d3eaa 55 */
Kojto 93:e188a91d3eaa 56
Kojto 93:e188a91d3eaa 57 /* Exported types ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 58
Kojto 93:e188a91d3eaa 59 /**
Kojto 93:e188a91d3eaa 60 * @brief RCC PLL configuration structure definition
Kojto 93:e188a91d3eaa 61 */
Kojto 93:e188a91d3eaa 62 typedef struct
Kojto 93:e188a91d3eaa 63 {
Kojto 93:e188a91d3eaa 64 uint32_t PLLState; /*!< The new state of the PLL.
Kojto 93:e188a91d3eaa 65 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 93:e188a91d3eaa 66
Kojto 93:e188a91d3eaa 67 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto 93:e188a91d3eaa 68 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 93:e188a91d3eaa 69
Kojto 93:e188a91d3eaa 70 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto 93:e188a91d3eaa 71 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto 93:e188a91d3eaa 72
Kojto 93:e188a91d3eaa 73 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto 93:e188a91d3eaa 74 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto 93:e188a91d3eaa 75
Kojto 93:e188a91d3eaa 76 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto 93:e188a91d3eaa 77 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 93:e188a91d3eaa 78
Kojto 93:e188a91d3eaa 79 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
Kojto 93:e188a91d3eaa 80 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto 93:e188a91d3eaa 81
Kojto 93:e188a91d3eaa 82 }RCC_PLLInitTypeDef;
Kojto 93:e188a91d3eaa 83
Kojto 93:e188a91d3eaa 84 /**
Kojto 93:e188a91d3eaa 85 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 93:e188a91d3eaa 86 */
Kojto 93:e188a91d3eaa 87 typedef struct
Kojto 93:e188a91d3eaa 88 {
Kojto 93:e188a91d3eaa 89 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 93:e188a91d3eaa 90 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 93:e188a91d3eaa 91
Kojto 93:e188a91d3eaa 92 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 93:e188a91d3eaa 93 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 93:e188a91d3eaa 94
Kojto 93:e188a91d3eaa 95 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 93:e188a91d3eaa 96 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 93:e188a91d3eaa 97
Kojto 93:e188a91d3eaa 98 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 93:e188a91d3eaa 99 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 93:e188a91d3eaa 100
Kojto 93:e188a91d3eaa 101 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto 93:e188a91d3eaa 102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 93:e188a91d3eaa 103
Kojto 93:e188a91d3eaa 104 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 93:e188a91d3eaa 105 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 93:e188a91d3eaa 106
Kojto 93:e188a91d3eaa 107 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 93:e188a91d3eaa 108
Kojto 93:e188a91d3eaa 109 }RCC_OscInitTypeDef;
Kojto 93:e188a91d3eaa 110
Kojto 93:e188a91d3eaa 111 /**
Kojto 93:e188a91d3eaa 112 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 93:e188a91d3eaa 113 */
Kojto 93:e188a91d3eaa 114 typedef struct
Kojto 93:e188a91d3eaa 115 {
Kojto 93:e188a91d3eaa 116 uint32_t ClockType; /*!< The clock to be configured.
Kojto 93:e188a91d3eaa 117 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 93:e188a91d3eaa 118
Kojto 93:e188a91d3eaa 119 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 93:e188a91d3eaa 120 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 93:e188a91d3eaa 121
Kojto 93:e188a91d3eaa 122 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 93:e188a91d3eaa 123 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 93:e188a91d3eaa 124
Kojto 93:e188a91d3eaa 125 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 93:e188a91d3eaa 126 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 93:e188a91d3eaa 127
Kojto 93:e188a91d3eaa 128 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 93:e188a91d3eaa 129 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 93:e188a91d3eaa 130
Kojto 93:e188a91d3eaa 131 }RCC_ClkInitTypeDef;
Kojto 93:e188a91d3eaa 132
Kojto 93:e188a91d3eaa 133 /* Exported constants --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 134 /** @defgroup RCC_Exported_Constants
Kojto 93:e188a91d3eaa 135 * @{
Kojto 93:e188a91d3eaa 136 */
Kojto 93:e188a91d3eaa 137
Kojto 93:e188a91d3eaa 138 /** @defgroup RCC_BitAddress_AliasRegion
Kojto 93:e188a91d3eaa 139 * @brief RCC registers bit address in the alias region
Kojto 93:e188a91d3eaa 140 * @{
Kojto 93:e188a91d3eaa 141 */
Kojto 93:e188a91d3eaa 142 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 93:e188a91d3eaa 143 /* --- CR Register ---*/
Kojto 93:e188a91d3eaa 144 /* Alias word address of HSION bit */
Kojto 93:e188a91d3eaa 145 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto 93:e188a91d3eaa 146 #define HSION_BitNumber 0x00
Kojto 93:e188a91d3eaa 147 #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
Kojto 93:e188a91d3eaa 148 /* Alias word address of CSSON bit */
Kojto 93:e188a91d3eaa 149 #define CSSON_BitNumber 0x13
Kojto 93:e188a91d3eaa 150 #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
Kojto 93:e188a91d3eaa 151 /* Alias word address of PLLON bit */
Kojto 93:e188a91d3eaa 152 #define PLLON_BitNumber 0x18
Kojto 93:e188a91d3eaa 153 #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
Kojto 93:e188a91d3eaa 154 /* Alias word address of PLLI2SON bit */
Kojto 93:e188a91d3eaa 155 #define PLLI2SON_BitNumber 0x1A
Kojto 93:e188a91d3eaa 156 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
Kojto 93:e188a91d3eaa 157
Kojto 93:e188a91d3eaa 158 /* --- CFGR Register ---*/
Kojto 93:e188a91d3eaa 159 /* Alias word address of I2SSRC bit */
Kojto 93:e188a91d3eaa 160 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
Kojto 93:e188a91d3eaa 161 #define I2SSRC_BitNumber 0x17
Kojto 93:e188a91d3eaa 162 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
Kojto 93:e188a91d3eaa 163
Kojto 93:e188a91d3eaa 164 /* --- BDCR Register ---*/
Kojto 93:e188a91d3eaa 165 /* Alias word address of RTCEN bit */
Kojto 93:e188a91d3eaa 166 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
Kojto 93:e188a91d3eaa 167 #define RTCEN_BitNumber 0x0F
Kojto 93:e188a91d3eaa 168 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
Kojto 93:e188a91d3eaa 169 /* Alias word address of BDRST bit */
Kojto 93:e188a91d3eaa 170 #define BDRST_BitNumber 0x10
Kojto 93:e188a91d3eaa 171 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
Kojto 93:e188a91d3eaa 172
Kojto 93:e188a91d3eaa 173 /* --- CSR Register ---*/
Kojto 93:e188a91d3eaa 174 /* Alias word address of LSION bit */
Kojto 93:e188a91d3eaa 175 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto 93:e188a91d3eaa 176 #define LSION_BitNumber 0x00
Kojto 93:e188a91d3eaa 177 #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
Kojto 93:e188a91d3eaa 178
Kojto 93:e188a91d3eaa 179 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 93:e188a91d3eaa 180 #define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto 93:e188a91d3eaa 181
Kojto 93:e188a91d3eaa 182 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 93:e188a91d3eaa 183 #define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto 93:e188a91d3eaa 184
Kojto 93:e188a91d3eaa 185 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 93:e188a91d3eaa 186 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto 93:e188a91d3eaa 187
Kojto 93:e188a91d3eaa 188 /* BDCR register base address */
Kojto 93:e188a91d3eaa 189 #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 93:e188a91d3eaa 190
Kojto 93:e188a91d3eaa 191
Kojto 93:e188a91d3eaa 192 #define DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto 93:e188a91d3eaa 193 #define LSE_TIMEOUT_VALUE ((uint32_t)600)
Kojto 93:e188a91d3eaa 194 /**
Kojto 93:e188a91d3eaa 195 * @}
Kojto 93:e188a91d3eaa 196 */
Kojto 93:e188a91d3eaa 197
Kojto 93:e188a91d3eaa 198 /** @defgroup RCC_Oscillator_Type
Kojto 93:e188a91d3eaa 199 * @{
Kojto 93:e188a91d3eaa 200 */
Kojto 93:e188a91d3eaa 201 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 202 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 203 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 204 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 205 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 206
Kojto 93:e188a91d3eaa 207 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto 93:e188a91d3eaa 208 /**
Kojto 93:e188a91d3eaa 209 * @}
Kojto 93:e188a91d3eaa 210 */
Kojto 93:e188a91d3eaa 211
Kojto 93:e188a91d3eaa 212 /** @defgroup RCC_HSE_Config
Kojto 93:e188a91d3eaa 213 * @{
Kojto 93:e188a91d3eaa 214 */
Kojto 93:e188a91d3eaa 215 #define RCC_HSE_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 216 #define RCC_HSE_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 217 #define RCC_HSE_BYPASS ((uint8_t)0x05)
Kojto 93:e188a91d3eaa 218
Kojto 93:e188a91d3eaa 219 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 93:e188a91d3eaa 220 ((HSE) == RCC_HSE_BYPASS))
Kojto 93:e188a91d3eaa 221 /**
Kojto 93:e188a91d3eaa 222 * @}
Kojto 93:e188a91d3eaa 223 */
Kojto 93:e188a91d3eaa 224
Kojto 93:e188a91d3eaa 225 /** @defgroup RCC_LSE_Config
Kojto 93:e188a91d3eaa 226 * @{
Kojto 93:e188a91d3eaa 227 */
Kojto 93:e188a91d3eaa 228 #define RCC_LSE_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 229 #define RCC_LSE_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 230 #define RCC_LSE_BYPASS ((uint8_t)0x05)
Kojto 93:e188a91d3eaa 231
Kojto 93:e188a91d3eaa 232 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 93:e188a91d3eaa 233 ((LSE) == RCC_LSE_BYPASS))
Kojto 93:e188a91d3eaa 234 /**
Kojto 93:e188a91d3eaa 235 * @}
Kojto 93:e188a91d3eaa 236 */
Kojto 93:e188a91d3eaa 237
Kojto 93:e188a91d3eaa 238 /** @defgroup RCC_HSI_Config
Kojto 93:e188a91d3eaa 239 * @{
Kojto 93:e188a91d3eaa 240 */
Kojto 93:e188a91d3eaa 241 #define RCC_HSI_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 242 #define RCC_HSI_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 243
Kojto 93:e188a91d3eaa 244 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 93:e188a91d3eaa 245 /**
Kojto 93:e188a91d3eaa 246 * @}
Kojto 93:e188a91d3eaa 247 */
Kojto 93:e188a91d3eaa 248
Kojto 93:e188a91d3eaa 249 /** @defgroup RCC_LSI_Config
Kojto 93:e188a91d3eaa 250 * @{
Kojto 93:e188a91d3eaa 251 */
Kojto 93:e188a91d3eaa 252 #define RCC_LSI_OFF ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 253 #define RCC_LSI_ON ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 254
Kojto 93:e188a91d3eaa 255 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 93:e188a91d3eaa 256 /**
Kojto 93:e188a91d3eaa 257 * @}
Kojto 93:e188a91d3eaa 258 */
Kojto 93:e188a91d3eaa 259
Kojto 93:e188a91d3eaa 260 /** @defgroup RCC_PLL_Config
Kojto 93:e188a91d3eaa 261 * @{
Kojto 93:e188a91d3eaa 262 */
Kojto 93:e188a91d3eaa 263 #define RCC_PLL_NONE ((uint8_t)0x00)
Kojto 93:e188a91d3eaa 264 #define RCC_PLL_OFF ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 265 #define RCC_PLL_ON ((uint8_t)0x02)
Kojto 93:e188a91d3eaa 266
Kojto 93:e188a91d3eaa 267 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 93:e188a91d3eaa 268 /**
Kojto 93:e188a91d3eaa 269 * @}
Kojto 93:e188a91d3eaa 270 */
Kojto 93:e188a91d3eaa 271
Kojto 93:e188a91d3eaa 272 /** @defgroup RCC_PLLP_Clock_Divider
Kojto 93:e188a91d3eaa 273 * @{
Kojto 93:e188a91d3eaa 274 */
Kojto 93:e188a91d3eaa 275 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 276 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 277 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
Kojto 93:e188a91d3eaa 278 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 279 /**
Kojto 93:e188a91d3eaa 280 * @}
Kojto 93:e188a91d3eaa 281 */
Kojto 93:e188a91d3eaa 282
Kojto 93:e188a91d3eaa 283 /** @defgroup RCC_PLL_Clock_Source
Kojto 93:e188a91d3eaa 284 * @{
Kojto 93:e188a91d3eaa 285 */
Kojto 93:e188a91d3eaa 286 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto 93:e188a91d3eaa 287 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto 93:e188a91d3eaa 288
Kojto 93:e188a91d3eaa 289 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 290 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 93:e188a91d3eaa 291 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 93:e188a91d3eaa 292 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 93:e188a91d3eaa 293 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
Kojto 93:e188a91d3eaa 294 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
Kojto 93:e188a91d3eaa 295
Kojto 93:e188a91d3eaa 296 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 93:e188a91d3eaa 297 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 93:e188a91d3eaa 298
Kojto 93:e188a91d3eaa 299 /**
Kojto 93:e188a91d3eaa 300 * @}
Kojto 93:e188a91d3eaa 301 */
Kojto 93:e188a91d3eaa 302
Kojto 93:e188a91d3eaa 303 /** @defgroup RCC_System_Clock_Type
Kojto 93:e188a91d3eaa 304 * @{
Kojto 93:e188a91d3eaa 305 */
Kojto 93:e188a91d3eaa 306 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 307 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 308 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 309 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 310
Kojto 93:e188a91d3eaa 311 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto 93:e188a91d3eaa 312 /**
Kojto 93:e188a91d3eaa 313 * @}
Kojto 93:e188a91d3eaa 314 */
Kojto 93:e188a91d3eaa 315
Kojto 93:e188a91d3eaa 316 /** @defgroup RCC_System_Clock_Source
Kojto 93:e188a91d3eaa 317 * @{
Kojto 93:e188a91d3eaa 318 */
Kojto 93:e188a91d3eaa 319 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto 93:e188a91d3eaa 320 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto 93:e188a91d3eaa 321 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 93:e188a91d3eaa 322
Kojto 93:e188a91d3eaa 323 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 93:e188a91d3eaa 324 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 93:e188a91d3eaa 325 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 93:e188a91d3eaa 326 /**
Kojto 93:e188a91d3eaa 327 * @}
Kojto 93:e188a91d3eaa 328 */
Kojto 93:e188a91d3eaa 329
Kojto 93:e188a91d3eaa 330 /** @defgroup RCC_AHB_Clock_Source
Kojto 93:e188a91d3eaa 331 * @{
Kojto 93:e188a91d3eaa 332 */
Kojto 93:e188a91d3eaa 333 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto 93:e188a91d3eaa 334 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto 93:e188a91d3eaa 335 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto 93:e188a91d3eaa 336 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto 93:e188a91d3eaa 337 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto 93:e188a91d3eaa 338 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto 93:e188a91d3eaa 339 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto 93:e188a91d3eaa 340 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto 93:e188a91d3eaa 341 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto 93:e188a91d3eaa 342
Kojto 93:e188a91d3eaa 343 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 93:e188a91d3eaa 344 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 93:e188a91d3eaa 345 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 93:e188a91d3eaa 346 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 93:e188a91d3eaa 347 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 93:e188a91d3eaa 348 /**
Kojto 93:e188a91d3eaa 349 * @}
Kojto 93:e188a91d3eaa 350 */
Kojto 93:e188a91d3eaa 351
Kojto 93:e188a91d3eaa 352 /** @defgroup RCC_APB1_APB2_Clock_Source
Kojto 93:e188a91d3eaa 353 * @{
Kojto 93:e188a91d3eaa 354 */
Kojto 93:e188a91d3eaa 355 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto 93:e188a91d3eaa 356 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto 93:e188a91d3eaa 357 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto 93:e188a91d3eaa 358 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto 93:e188a91d3eaa 359 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto 93:e188a91d3eaa 360
Kojto 93:e188a91d3eaa 361 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 93:e188a91d3eaa 362 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 93:e188a91d3eaa 363 ((PCLK) == RCC_HCLK_DIV16))
Kojto 93:e188a91d3eaa 364 /**
Kojto 93:e188a91d3eaa 365 * @}
Kojto 93:e188a91d3eaa 366 */
Kojto 93:e188a91d3eaa 367
Kojto 93:e188a91d3eaa 368 /** @defgroup RCC_RTC_Clock_Source
Kojto 93:e188a91d3eaa 369 * @{
Kojto 93:e188a91d3eaa 370 */
Kojto 93:e188a91d3eaa 371 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 372 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 373 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
Kojto 93:e188a91d3eaa 374 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
Kojto 93:e188a91d3eaa 375 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
Kojto 93:e188a91d3eaa 376 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
Kojto 93:e188a91d3eaa 377 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
Kojto 93:e188a91d3eaa 378 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
Kojto 93:e188a91d3eaa 379 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
Kojto 93:e188a91d3eaa 380 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
Kojto 93:e188a91d3eaa 381 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
Kojto 93:e188a91d3eaa 382 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
Kojto 93:e188a91d3eaa 383 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
Kojto 93:e188a91d3eaa 384 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
Kojto 93:e188a91d3eaa 385 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
Kojto 93:e188a91d3eaa 386 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
Kojto 93:e188a91d3eaa 387 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
Kojto 93:e188a91d3eaa 388 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
Kojto 93:e188a91d3eaa 389 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
Kojto 93:e188a91d3eaa 390 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
Kojto 93:e188a91d3eaa 391 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
Kojto 93:e188a91d3eaa 392 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
Kojto 93:e188a91d3eaa 393 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
Kojto 93:e188a91d3eaa 394 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
Kojto 93:e188a91d3eaa 395 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
Kojto 93:e188a91d3eaa 396 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
Kojto 93:e188a91d3eaa 397 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
Kojto 93:e188a91d3eaa 398 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
Kojto 93:e188a91d3eaa 399 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
Kojto 93:e188a91d3eaa 400 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
Kojto 93:e188a91d3eaa 401 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
Kojto 93:e188a91d3eaa 402 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
Kojto 93:e188a91d3eaa 403 /**
Kojto 93:e188a91d3eaa 404 * @}
Kojto 93:e188a91d3eaa 405 */
Kojto 93:e188a91d3eaa 406
Kojto 93:e188a91d3eaa 407 /** @defgroup RCC_I2S_Clock_Source
Kojto 93:e188a91d3eaa 408 * @{
Kojto 93:e188a91d3eaa 409 */
Kojto 93:e188a91d3eaa 410 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 411 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 412 /**
Kojto 93:e188a91d3eaa 413 * @}
Kojto 93:e188a91d3eaa 414 */
Kojto 93:e188a91d3eaa 415
Kojto 93:e188a91d3eaa 416 /** @defgroup RCC_MCO_Index
Kojto 93:e188a91d3eaa 417 * @{
Kojto 93:e188a91d3eaa 418 */
Kojto 93:e188a91d3eaa 419 #define RCC_MCO1 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 420 #define RCC_MCO2 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 421
Kojto 93:e188a91d3eaa 422 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 93:e188a91d3eaa 423 /**
Kojto 93:e188a91d3eaa 424 * @}
Kojto 93:e188a91d3eaa 425 */
Kojto 93:e188a91d3eaa 426
Kojto 93:e188a91d3eaa 427 /** @defgroup RCC_MCO1_Clock_Source
Kojto 93:e188a91d3eaa 428 * @{
Kojto 93:e188a91d3eaa 429 */
Kojto 93:e188a91d3eaa 430 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 431 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto 93:e188a91d3eaa 432 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto 93:e188a91d3eaa 433 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto 93:e188a91d3eaa 434
Kojto 93:e188a91d3eaa 435 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 93:e188a91d3eaa 436 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 93:e188a91d3eaa 437 /**
Kojto 93:e188a91d3eaa 438 * @}
Kojto 93:e188a91d3eaa 439 */
Kojto 93:e188a91d3eaa 440
Kojto 93:e188a91d3eaa 441 /** @defgroup RCC_MCO2_Clock_Source
Kojto 93:e188a91d3eaa 442 * @{
Kojto 93:e188a91d3eaa 443 */
Kojto 93:e188a91d3eaa 444 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 445 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto 93:e188a91d3eaa 446 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto 93:e188a91d3eaa 447 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto 93:e188a91d3eaa 448
Kojto 93:e188a91d3eaa 449 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
Kojto 93:e188a91d3eaa 450 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto 93:e188a91d3eaa 451 /**
Kojto 93:e188a91d3eaa 452 * @}
Kojto 93:e188a91d3eaa 453 */
Kojto 93:e188a91d3eaa 454
Kojto 93:e188a91d3eaa 455 /** @defgroup RCC_MCOx_Clock_Prescaler
Kojto 93:e188a91d3eaa 456 * @{
Kojto 93:e188a91d3eaa 457 */
Kojto 93:e188a91d3eaa 458 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 459 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto 93:e188a91d3eaa 460 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
Kojto 93:e188a91d3eaa 461 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
Kojto 93:e188a91d3eaa 462 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto 93:e188a91d3eaa 463
Kojto 93:e188a91d3eaa 464 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 93:e188a91d3eaa 465 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 93:e188a91d3eaa 466 ((DIV) == RCC_MCODIV_5))
Kojto 93:e188a91d3eaa 467 /**
Kojto 93:e188a91d3eaa 468 * @}
Kojto 93:e188a91d3eaa 469 */
Kojto 93:e188a91d3eaa 470
Kojto 93:e188a91d3eaa 471 /** @defgroup RCC_Interrupt
Kojto 93:e188a91d3eaa 472 * @{
Kojto 93:e188a91d3eaa 473 */
Kojto 93:e188a91d3eaa 474 #define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto 93:e188a91d3eaa 475 #define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto 93:e188a91d3eaa 476 #define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto 93:e188a91d3eaa 477 #define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto 93:e188a91d3eaa 478 #define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto 93:e188a91d3eaa 479 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Kojto 93:e188a91d3eaa 480 #define RCC_IT_CSS ((uint8_t)0x80)
Kojto 93:e188a91d3eaa 481 /**
Kojto 93:e188a91d3eaa 482 * @}
Kojto 93:e188a91d3eaa 483 */
Kojto 93:e188a91d3eaa 484
Kojto 93:e188a91d3eaa 485 /** @defgroup RCC_Flag
Kojto 93:e188a91d3eaa 486 * Elements values convention: 0XXYYYYYb
Kojto 93:e188a91d3eaa 487 * - YYYYY : Flag position in the register
Kojto 93:e188a91d3eaa 488 * - 0XX : Register index
Kojto 93:e188a91d3eaa 489 * - 01: CR register
Kojto 93:e188a91d3eaa 490 * - 10: BDCR register
Kojto 93:e188a91d3eaa 491 * - 11: CSR register
Kojto 93:e188a91d3eaa 492 * @{
Kojto 93:e188a91d3eaa 493 */
Kojto 93:e188a91d3eaa 494 /* Flags in the CR register */
Kojto 93:e188a91d3eaa 495 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Kojto 93:e188a91d3eaa 496 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto 93:e188a91d3eaa 497 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto 93:e188a91d3eaa 498 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Kojto 93:e188a91d3eaa 499
Kojto 93:e188a91d3eaa 500 /* Flags in the BDCR register */
Kojto 93:e188a91d3eaa 501 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
Kojto 93:e188a91d3eaa 502
Kojto 93:e188a91d3eaa 503 /* Flags in the CSR register */
Kojto 93:e188a91d3eaa 504 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Kojto 93:e188a91d3eaa 505 #define RCC_FLAG_BORRST ((uint8_t)0x79)
Kojto 93:e188a91d3eaa 506 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
Kojto 93:e188a91d3eaa 507 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
Kojto 93:e188a91d3eaa 508 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Kojto 93:e188a91d3eaa 509 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Kojto 93:e188a91d3eaa 510 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Kojto 93:e188a91d3eaa 511 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Kojto 93:e188a91d3eaa 512
Kojto 93:e188a91d3eaa 513 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto 93:e188a91d3eaa 514 /**
Kojto 93:e188a91d3eaa 515 * @}
Kojto 93:e188a91d3eaa 516 */
Kojto 93:e188a91d3eaa 517
Kojto 93:e188a91d3eaa 518 /**
Kojto 93:e188a91d3eaa 519 * @}
Kojto 93:e188a91d3eaa 520 */
Kojto 93:e188a91d3eaa 521 /* Exported macro ------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 522
Kojto 93:e188a91d3eaa 523 /** @brief Enable or disable the AHB1 peripheral clock.
Kojto 93:e188a91d3eaa 524 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 525 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 526 * using it.
Kojto 93:e188a91d3eaa 527 */
Kojto 93:e188a91d3eaa 528 #define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
Kojto 93:e188a91d3eaa 529 #define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
Kojto 93:e188a91d3eaa 530 #define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
Kojto 93:e188a91d3eaa 531 #define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
Kojto 93:e188a91d3eaa 532 #define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
Kojto 93:e188a91d3eaa 533 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 534 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
Kojto 93:e188a91d3eaa 535 #define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
Kojto 93:e188a91d3eaa 536 #define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
Kojto 93:e188a91d3eaa 537 #define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
Kojto 93:e188a91d3eaa 538 #define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
Kojto 93:e188a91d3eaa 539 #define __DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
Kojto 93:e188a91d3eaa 540 #define __DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
Kojto 93:e188a91d3eaa 541
Kojto 93:e188a91d3eaa 542 #define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 93:e188a91d3eaa 543 #define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 93:e188a91d3eaa 544 #define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 93:e188a91d3eaa 545 #define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto 93:e188a91d3eaa 546 #define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto 93:e188a91d3eaa 547 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 548 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 93:e188a91d3eaa 549 #define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 93:e188a91d3eaa 550 #define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto 93:e188a91d3eaa 551 #define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto 93:e188a91d3eaa 552 #define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto 93:e188a91d3eaa 553 #define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 93:e188a91d3eaa 554 #define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 93:e188a91d3eaa 555
Kojto 93:e188a91d3eaa 556 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 93:e188a91d3eaa 557 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 558 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 559 * using it.
Kojto 93:e188a91d3eaa 560 */
Kojto 93:e188a91d3eaa 561 #define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
Kojto 93:e188a91d3eaa 562 __SYSCFG_CLK_ENABLE();\
Kojto 93:e188a91d3eaa 563 }while(0)
Kojto 93:e188a91d3eaa 564
Kojto 93:e188a91d3eaa 565
Kojto 93:e188a91d3eaa 566 #define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto 93:e188a91d3eaa 567 __SYSCFG_CLK_DISABLE();\
Kojto 93:e188a91d3eaa 568 }while(0)
Kojto 93:e188a91d3eaa 569
Kojto 93:e188a91d3eaa 570 #define __RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
Kojto 93:e188a91d3eaa 571 #define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto 93:e188a91d3eaa 572 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 93:e188a91d3eaa 573 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 574 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 575 * using it.
Kojto 93:e188a91d3eaa 576 */
Kojto 93:e188a91d3eaa 577 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
Kojto 93:e188a91d3eaa 578 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
Kojto 93:e188a91d3eaa 579 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
Kojto 93:e188a91d3eaa 580 #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
Kojto 93:e188a91d3eaa 581 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 582 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 93:e188a91d3eaa 583 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
Kojto 93:e188a91d3eaa 584 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
Kojto 93:e188a91d3eaa 585 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
Kojto 93:e188a91d3eaa 586 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 93:e188a91d3eaa 587 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
Kojto 93:e188a91d3eaa 588 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
Kojto 93:e188a91d3eaa 589
Kojto 93:e188a91d3eaa 590 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 93:e188a91d3eaa 591 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 93:e188a91d3eaa 592 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 93:e188a91d3eaa 593 #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 93:e188a91d3eaa 594 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 93:e188a91d3eaa 595 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 93:e188a91d3eaa 596 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 93:e188a91d3eaa 597 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 93:e188a91d3eaa 598 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 93:e188a91d3eaa 599 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 93:e188a91d3eaa 600 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto 93:e188a91d3eaa 601 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 93:e188a91d3eaa 602
Kojto 93:e188a91d3eaa 603 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 93:e188a91d3eaa 604 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 93:e188a91d3eaa 605 * is disabled and the application software has to enable this clock before
Kojto 93:e188a91d3eaa 606 * using it.
Kojto 93:e188a91d3eaa 607 */
Kojto 93:e188a91d3eaa 608 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
Kojto 93:e188a91d3eaa 609 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
Kojto 93:e188a91d3eaa 610 #define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
Kojto 93:e188a91d3eaa 611 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
Kojto 93:e188a91d3eaa 612 #define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
Kojto 93:e188a91d3eaa 613 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
Kojto 93:e188a91d3eaa 614 #define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
Kojto 93:e188a91d3eaa 615 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
Kojto 93:e188a91d3eaa 616 #define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
Kojto 93:e188a91d3eaa 617 #define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
Kojto 93:e188a91d3eaa 618 #define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
Kojto 93:e188a91d3eaa 619
Kojto 93:e188a91d3eaa 620 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 93:e188a91d3eaa 621 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 93:e188a91d3eaa 622 #define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 93:e188a91d3eaa 623 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 93:e188a91d3eaa 624 #define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto 93:e188a91d3eaa 625 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 93:e188a91d3eaa 626 #define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto 93:e188a91d3eaa 627 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 93:e188a91d3eaa 628 #define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 93:e188a91d3eaa 629 #define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto 93:e188a91d3eaa 630 #define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 93:e188a91d3eaa 631
Kojto 93:e188a91d3eaa 632 /** @brief Force or release AHB1 peripheral reset.
Kojto 93:e188a91d3eaa 633 */
Kojto 93:e188a91d3eaa 634 #define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 635 #define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 93:e188a91d3eaa 636 #define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 93:e188a91d3eaa 637 #define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 93:e188a91d3eaa 638 #define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
Kojto 93:e188a91d3eaa 639 #define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
Kojto 93:e188a91d3eaa 640 #define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 93:e188a91d3eaa 641 #define __CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
Kojto 93:e188a91d3eaa 642 #define __DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 93:e188a91d3eaa 643 #define __DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Kojto 93:e188a91d3eaa 644
Kojto 93:e188a91d3eaa 645 #define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto 93:e188a91d3eaa 646 #define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 93:e188a91d3eaa 647 #define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 93:e188a91d3eaa 648 #define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 93:e188a91d3eaa 649 #define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto 93:e188a91d3eaa 650 #define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto 93:e188a91d3eaa 651 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 93:e188a91d3eaa 652 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 93:e188a91d3eaa 653 #define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 93:e188a91d3eaa 654 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 93:e188a91d3eaa 655 #define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto 93:e188a91d3eaa 656 #define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 93:e188a91d3eaa 657 #define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 93:e188a91d3eaa 658
Kojto 93:e188a91d3eaa 659 /** @brief Force or release AHB2 peripheral reset.
Kojto 93:e188a91d3eaa 660 */
Kojto 93:e188a91d3eaa 661 #define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 662 #define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
Kojto 93:e188a91d3eaa 663
Kojto 93:e188a91d3eaa 664 #define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto 93:e188a91d3eaa 665 #define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto 93:e188a91d3eaa 666
Kojto 93:e188a91d3eaa 667 /* alias define maintained for legacy */
Kojto 93:e188a91d3eaa 668 #define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET
Kojto 93:e188a91d3eaa 669 #define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET
Kojto 93:e188a91d3eaa 670
Kojto 93:e188a91d3eaa 671 #define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
Kojto 93:e188a91d3eaa 672 #define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto 93:e188a91d3eaa 673
Kojto 93:e188a91d3eaa 674 /** @brief Force or release APB1 peripheral reset.
Kojto 93:e188a91d3eaa 675 */
Kojto 93:e188a91d3eaa 676 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 677 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 93:e188a91d3eaa 678 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 93:e188a91d3eaa 679 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 93:e188a91d3eaa 680 #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 93:e188a91d3eaa 681 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 93:e188a91d3eaa 682 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 93:e188a91d3eaa 683 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 93:e188a91d3eaa 684 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 93:e188a91d3eaa 685 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 93:e188a91d3eaa 686 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 93:e188a91d3eaa 687 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 93:e188a91d3eaa 688 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 93:e188a91d3eaa 689
Kojto 93:e188a91d3eaa 690 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 93:e188a91d3eaa 691 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 93:e188a91d3eaa 692 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 93:e188a91d3eaa 693 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 93:e188a91d3eaa 694 #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 93:e188a91d3eaa 695 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 93:e188a91d3eaa 696 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 93:e188a91d3eaa 697 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 93:e188a91d3eaa 698 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 93:e188a91d3eaa 699 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 93:e188a91d3eaa 700 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 93:e188a91d3eaa 701 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto 93:e188a91d3eaa 702 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 93:e188a91d3eaa 703
Kojto 93:e188a91d3eaa 704 /** @brief Force or release APB2 peripheral reset.
Kojto 93:e188a91d3eaa 705 */
Kojto 93:e188a91d3eaa 706 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 707 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 93:e188a91d3eaa 708 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 93:e188a91d3eaa 709 #define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 93:e188a91d3eaa 710 #define __ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 93:e188a91d3eaa 711 #define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
Kojto 93:e188a91d3eaa 712 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 93:e188a91d3eaa 713 #define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
Kojto 93:e188a91d3eaa 714 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 93:e188a91d3eaa 715 #define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 93:e188a91d3eaa 716 #define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
Kojto 93:e188a91d3eaa 717 #define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Kojto 93:e188a91d3eaa 718
Kojto 93:e188a91d3eaa 719 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 93:e188a91d3eaa 720 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 93:e188a91d3eaa 721 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 93:e188a91d3eaa 722 #define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 93:e188a91d3eaa 723 #define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 93:e188a91d3eaa 724 #define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto 93:e188a91d3eaa 725 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 93:e188a91d3eaa 726 #define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto 93:e188a91d3eaa 727 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 93:e188a91d3eaa 728 #define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 93:e188a91d3eaa 729 #define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto 93:e188a91d3eaa 730 #define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 93:e188a91d3eaa 731
Kojto 93:e188a91d3eaa 732 /** @brief Force or release AHB3 peripheral reset.
Kojto 93:e188a91d3eaa 733 */
Kojto 93:e188a91d3eaa 734 #define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto 93:e188a91d3eaa 735 #define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto 93:e188a91d3eaa 736
Kojto 93:e188a91d3eaa 737 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 738 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 739 * power consumption.
Kojto 93:e188a91d3eaa 740 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 741 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 742 */
Kojto 93:e188a91d3eaa 743 #define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 93:e188a91d3eaa 744 #define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 93:e188a91d3eaa 745 #define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 93:e188a91d3eaa 746 #define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
Kojto 93:e188a91d3eaa 747 #define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
Kojto 93:e188a91d3eaa 748 #define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 93:e188a91d3eaa 749 #define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
Kojto 93:e188a91d3eaa 750 #define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
Kojto 93:e188a91d3eaa 751 #define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto 93:e188a91d3eaa 752 #define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 93:e188a91d3eaa 753 #define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 93:e188a91d3eaa 754 #define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
Kojto 93:e188a91d3eaa 755
Kojto 93:e188a91d3eaa 756 #define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 93:e188a91d3eaa 757 #define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 93:e188a91d3eaa 758 #define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 93:e188a91d3eaa 759 #define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto 93:e188a91d3eaa 760 #define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto 93:e188a91d3eaa 761 #define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 93:e188a91d3eaa 762 #define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto 93:e188a91d3eaa 763 #define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto 93:e188a91d3eaa 764 #define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto 93:e188a91d3eaa 765 #define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 93:e188a91d3eaa 766 #define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 93:e188a91d3eaa 767 #define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 93:e188a91d3eaa 768
Kojto 93:e188a91d3eaa 769 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 770 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 771 * power consumption.
Kojto 93:e188a91d3eaa 772 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 773 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 774 */
Kojto 93:e188a91d3eaa 775 #define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto 93:e188a91d3eaa 776
Kojto 93:e188a91d3eaa 777 #define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto 93:e188a91d3eaa 778
Kojto 93:e188a91d3eaa 779 /* alias define maintained for legacy */
Kojto 93:e188a91d3eaa 780 #define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto 93:e188a91d3eaa 781 #define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto 93:e188a91d3eaa 782
Kojto 93:e188a91d3eaa 783 #define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
Kojto 93:e188a91d3eaa 784 #define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto 93:e188a91d3eaa 785
Kojto 93:e188a91d3eaa 786 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 787 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 788 * power consumption.
Kojto 93:e188a91d3eaa 789 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 790 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 791 */
Kojto 93:e188a91d3eaa 792 #define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
Kojto 93:e188a91d3eaa 793 #define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
Kojto 93:e188a91d3eaa 794 #define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
Kojto 93:e188a91d3eaa 795 #define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 93:e188a91d3eaa 796 #define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 93:e188a91d3eaa 797 #define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 93:e188a91d3eaa 798 #define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
Kojto 93:e188a91d3eaa 799 #define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 93:e188a91d3eaa 800 #define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 93:e188a91d3eaa 801 #define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 93:e188a91d3eaa 802 #define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
Kojto 93:e188a91d3eaa 803 #define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
Kojto 93:e188a91d3eaa 804
Kojto 93:e188a91d3eaa 805 #define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto 93:e188a91d3eaa 806 #define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto 93:e188a91d3eaa 807 #define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto 93:e188a91d3eaa 808 #define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 93:e188a91d3eaa 809 #define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 93:e188a91d3eaa 810 #define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 93:e188a91d3eaa 811 #define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto 93:e188a91d3eaa 812 #define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 93:e188a91d3eaa 813 #define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 93:e188a91d3eaa 814 #define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 93:e188a91d3eaa 815 #define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto 93:e188a91d3eaa 816 #define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 93:e188a91d3eaa 817
Kojto 93:e188a91d3eaa 818 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 93:e188a91d3eaa 819 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 93:e188a91d3eaa 820 * power consumption.
Kojto 93:e188a91d3eaa 821 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 93:e188a91d3eaa 822 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 93:e188a91d3eaa 823 */
Kojto 93:e188a91d3eaa 824 #define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 93:e188a91d3eaa 825 #define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 93:e188a91d3eaa 826 #define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 93:e188a91d3eaa 827 #define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 93:e188a91d3eaa 828 #define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
Kojto 93:e188a91d3eaa 829 #define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 93:e188a91d3eaa 830 #define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
Kojto 93:e188a91d3eaa 831 #define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 93:e188a91d3eaa 832 #define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 93:e188a91d3eaa 833 #define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
Kojto 93:e188a91d3eaa 834 #define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
Kojto 93:e188a91d3eaa 835
Kojto 93:e188a91d3eaa 836 #define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 93:e188a91d3eaa 837 #define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 93:e188a91d3eaa 838 #define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 93:e188a91d3eaa 839 #define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 93:e188a91d3eaa 840 #define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto 93:e188a91d3eaa 841 #define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 93:e188a91d3eaa 842 #define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto 93:e188a91d3eaa 843 #define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 93:e188a91d3eaa 844 #define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 93:e188a91d3eaa 845 #define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto 93:e188a91d3eaa 846 #define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 93:e188a91d3eaa 847
Kojto 93:e188a91d3eaa 848 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 93:e188a91d3eaa 849 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 850 * It is used (enabled by hardware) as system clock source after startup
Kojto 93:e188a91d3eaa 851 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto 93:e188a91d3eaa 852 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 93:e188a91d3eaa 853 * Security System CSS is enabled).
Kojto 93:e188a91d3eaa 854 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 93:e188a91d3eaa 855 * you have to select another source of the system clock then stop the HSI.
Kojto 93:e188a91d3eaa 856 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 93:e188a91d3eaa 857 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 93:e188a91d3eaa 858 * system clock source.
Kojto 93:e188a91d3eaa 859 * This parameter can be: ENABLE or DISABLE.
Kojto 93:e188a91d3eaa 860 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 93:e188a91d3eaa 861 * clock cycles.
Kojto 93:e188a91d3eaa 862 */
Kojto 93:e188a91d3eaa 863 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
Kojto 93:e188a91d3eaa 864 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
Kojto 93:e188a91d3eaa 865
Kojto 93:e188a91d3eaa 866 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 93:e188a91d3eaa 867 * @note The calibration is used to compensate for the variations in voltage
Kojto 93:e188a91d3eaa 868 * and temperature that influence the frequency of the internal HSI RC.
Kojto 93:e188a91d3eaa 869 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 93:e188a91d3eaa 870 * This parameter must be a number between 0 and 0x1F.
Kojto 93:e188a91d3eaa 871 */
Kojto 93:e188a91d3eaa 872 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
Kojto 93:e188a91d3eaa 873 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 93:e188a91d3eaa 874
Kojto 93:e188a91d3eaa 875 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 93:e188a91d3eaa 876 * @note After enabling the LSI, the application software should wait on
Kojto 93:e188a91d3eaa 877 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 93:e188a91d3eaa 878 * be used to clock the IWDG and/or the RTC.
Kojto 93:e188a91d3eaa 879 * @note LSI can not be disabled if the IWDG is running.
Kojto 93:e188a91d3eaa 880 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 93:e188a91d3eaa 881 * clock cycles.
Kojto 93:e188a91d3eaa 882 */
Kojto 93:e188a91d3eaa 883 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
Kojto 93:e188a91d3eaa 884 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
Kojto 93:e188a91d3eaa 885
Kojto 93:e188a91d3eaa 886 /**
Kojto 93:e188a91d3eaa 887 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 93:e188a91d3eaa 888 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 93:e188a91d3eaa 889 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 93:e188a91d3eaa 890 * is stable and can be used to clock the PLL and/or system clock.
Kojto 93:e188a91d3eaa 891 * @note HSE state can not be changed if it is used directly or through the
Kojto 93:e188a91d3eaa 892 * PLL as system clock. In this case, you have to select another source
Kojto 93:e188a91d3eaa 893 * of the system clock then change the HSE state (ex. disable it).
Kojto 93:e188a91d3eaa 894 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 895 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto 93:e188a91d3eaa 896 * was previously enabled you have to enable it again after calling this
Kojto 93:e188a91d3eaa 897 * function.
Kojto 93:e188a91d3eaa 898 * @param __STATE__: specifies the new state of the HSE.
Kojto 93:e188a91d3eaa 899 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 900 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 93:e188a91d3eaa 901 * 6 HSE oscillator clock cycles.
Kojto 93:e188a91d3eaa 902 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto 93:e188a91d3eaa 903 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto 93:e188a91d3eaa 904 */
Kojto 93:e188a91d3eaa 905 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
Kojto 93:e188a91d3eaa 906
Kojto 93:e188a91d3eaa 907 /**
Kojto 93:e188a91d3eaa 908 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 93:e188a91d3eaa 909 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 93:e188a91d3eaa 910 * this domain after reset, you have to enable write access using
Kojto 93:e188a91d3eaa 911 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 93:e188a91d3eaa 912 * (to be done once after reset).
Kojto 93:e188a91d3eaa 913 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 93:e188a91d3eaa 914 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 93:e188a91d3eaa 915 * is stable and can be used to clock the RTC.
Kojto 93:e188a91d3eaa 916 * @param __STATE__: specifies the new state of the LSE.
Kojto 93:e188a91d3eaa 917 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 918 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 93:e188a91d3eaa 919 * 6 LSE oscillator clock cycles.
Kojto 93:e188a91d3eaa 920 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto 93:e188a91d3eaa 921 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto 93:e188a91d3eaa 922 */
Kojto 93:e188a91d3eaa 923 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto 93:e188a91d3eaa 924
Kojto 93:e188a91d3eaa 925 /** @brief Macros to enable or disable the the RTC clock.
Kojto 93:e188a91d3eaa 926 * @note These macros must be used only after the RTC clock source was selected.
Kojto 93:e188a91d3eaa 927 */
Kojto 93:e188a91d3eaa 928 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
Kojto 93:e188a91d3eaa 929 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
Kojto 93:e188a91d3eaa 930
Kojto 93:e188a91d3eaa 931 /** @brief Macros to configure the RTC clock (RTCCLK).
Kojto 93:e188a91d3eaa 932 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 93:e188a91d3eaa 933 * access is denied to this domain after reset, you have to enable write
Kojto 93:e188a91d3eaa 934 * access using the Power Backup Access macro before to configure
Kojto 93:e188a91d3eaa 935 * the RTC clock source (to be done once after reset).
Kojto 93:e188a91d3eaa 936 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 93:e188a91d3eaa 937 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto 93:e188a91d3eaa 938 * a Power On Reset (POR).
Kojto 93:e188a91d3eaa 939 * @param __RTCCLKSource__: specifies the RTC clock source.
Kojto 93:e188a91d3eaa 940 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 941 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto 93:e188a91d3eaa 942 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto 93:e188a91d3eaa 943 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto 93:e188a91d3eaa 944 * as RTC clock, where x:[2,31]
Kojto 93:e188a91d3eaa 945 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 93:e188a91d3eaa 946 * work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto 93:e188a91d3eaa 947 * However, when the HSE clock is used as RTC clock source, the RTC
Kojto 93:e188a91d3eaa 948 * cannot be used in STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 949 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto 93:e188a91d3eaa 950 * RTC clock source).
Kojto 93:e188a91d3eaa 951 */
Kojto 93:e188a91d3eaa 952 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto 93:e188a91d3eaa 953 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto 93:e188a91d3eaa 954
Kojto 93:e188a91d3eaa 955 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto 93:e188a91d3eaa 956 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
Kojto 93:e188a91d3eaa 957 } while (0)
Kojto 93:e188a91d3eaa 958
Kojto 93:e188a91d3eaa 959 /** @brief Macros to force or release the Backup domain reset.
Kojto 93:e188a91d3eaa 960 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 93:e188a91d3eaa 961 * and the RTC clock source selection in RCC_CSR register.
Kojto 93:e188a91d3eaa 962 * @note The BKPSRAM is not affected by this reset.
Kojto 93:e188a91d3eaa 963 */
Kojto 93:e188a91d3eaa 964 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
Kojto 93:e188a91d3eaa 965 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
Kojto 93:e188a91d3eaa 966
Kojto 93:e188a91d3eaa 967 /** @brief Macros to enable or disable the main PLL.
Kojto 93:e188a91d3eaa 968 * @note After enabling the main PLL, the application software should wait on
Kojto 93:e188a91d3eaa 969 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 93:e188a91d3eaa 970 * be used as system clock source.
Kojto 93:e188a91d3eaa 971 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 93:e188a91d3eaa 972 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 973 */
Kojto 93:e188a91d3eaa 974 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
Kojto 93:e188a91d3eaa 975 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
Kojto 93:e188a91d3eaa 976
Kojto 93:e188a91d3eaa 977 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 93:e188a91d3eaa 978 * @note This function must be used only when the main PLL is disabled.
Kojto 93:e188a91d3eaa 979 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 93:e188a91d3eaa 980 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 981 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 93:e188a91d3eaa 982 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 93:e188a91d3eaa 983 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto 93:e188a91d3eaa 984 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 93:e188a91d3eaa 985 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 93:e188a91d3eaa 986 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 93:e188a91d3eaa 987 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 93:e188a91d3eaa 988 * of 2 MHz to limit PLL jitter.
Kojto 93:e188a91d3eaa 989 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto 93:e188a91d3eaa 990 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 93:e188a91d3eaa 991 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 93:e188a91d3eaa 992 * output frequency is between 192 and 432 MHz.
Kojto 93:e188a91d3eaa 993 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto 93:e188a91d3eaa 994 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 93:e188a91d3eaa 995 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
Kojto 93:e188a91d3eaa 996 * the System clock frequency.
Kojto 93:e188a91d3eaa 997 * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto 93:e188a91d3eaa 998 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 93:e188a91d3eaa 999 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 93:e188a91d3eaa 1000 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 93:e188a91d3eaa 1001 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 93:e188a91d3eaa 1002 * correctly.
Kojto 93:e188a91d3eaa 1003 */
Kojto 93:e188a91d3eaa 1004 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
Kojto 93:e188a91d3eaa 1005 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
Kojto 93:e188a91d3eaa 1006 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
Kojto 93:e188a91d3eaa 1007 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto 93:e188a91d3eaa 1008
Kojto 93:e188a91d3eaa 1009 /** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto 93:e188a91d3eaa 1010 * @note This function must be called before enabling the I2S APB clock.
Kojto 93:e188a91d3eaa 1011 * @param __SOURCE__: specifies the I2S clock source.
Kojto 93:e188a91d3eaa 1012 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1013 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto 93:e188a91d3eaa 1014 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto 93:e188a91d3eaa 1015 * used as I2S clock source.
Kojto 93:e188a91d3eaa 1016 */
Kojto 93:e188a91d3eaa 1017 #define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
Kojto 93:e188a91d3eaa 1018
Kojto 93:e188a91d3eaa 1019 /** @brief Macros to enable or disable the PLLI2S.
Kojto 93:e188a91d3eaa 1020 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto 93:e188a91d3eaa 1021 */
Kojto 93:e188a91d3eaa 1022 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
Kojto 93:e188a91d3eaa 1023 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
Kojto 93:e188a91d3eaa 1024
Kojto 93:e188a91d3eaa 1025 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto 93:e188a91d3eaa 1026 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 93:e188a91d3eaa 1027 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 93:e188a91d3eaa 1028 * HAL_RCC_ClockConfig() API).
Kojto 93:e188a91d3eaa 1029 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto 93:e188a91d3eaa 1030 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 93:e188a91d3eaa 1031 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 93:e188a91d3eaa 1032 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 93:e188a91d3eaa 1033 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 93:e188a91d3eaa 1034 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 93:e188a91d3eaa 1035 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 93:e188a91d3eaa 1036 * on the I2S clock frequency.
Kojto 93:e188a91d3eaa 1037 */
Kojto 93:e188a91d3eaa 1038 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
Kojto 93:e188a91d3eaa 1039
Kojto 93:e188a91d3eaa 1040 /** @brief Macro to get the clock source used as system clock.
Kojto 93:e188a91d3eaa 1041 * @retval The clock source used as system clock. The returned value can be one
Kojto 93:e188a91d3eaa 1042 * of the following:
Kojto 93:e188a91d3eaa 1043 * - RCC_CFGR_SWS_HSI: HSI used as system clock.
Kojto 93:e188a91d3eaa 1044 * - RCC_CFGR_SWS_HSE: HSE used as system clock.
Kojto 93:e188a91d3eaa 1045 * - RCC_CFGR_SWS_PLL: PLL used as system clock.
Kojto 93:e188a91d3eaa 1046 */
Kojto 93:e188a91d3eaa 1047 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 93:e188a91d3eaa 1048
Kojto 93:e188a91d3eaa 1049 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 93:e188a91d3eaa 1050 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 93:e188a91d3eaa 1051 * of the following:
Kojto 93:e188a91d3eaa 1052 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 93:e188a91d3eaa 1053 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 93:e188a91d3eaa 1054 */
Kojto 93:e188a91d3eaa 1055 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 93:e188a91d3eaa 1056
Kojto 93:e188a91d3eaa 1057 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto 93:e188a91d3eaa 1058 * the selected interrupts).
Kojto 93:e188a91d3eaa 1059 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 93:e188a91d3eaa 1060 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1061 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 93:e188a91d3eaa 1062 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 93:e188a91d3eaa 1063 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 93:e188a91d3eaa 1064 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 93:e188a91d3eaa 1065 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 93:e188a91d3eaa 1066 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 93:e188a91d3eaa 1067 */
Kojto 93:e188a91d3eaa 1068 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 93:e188a91d3eaa 1069
Kojto 93:e188a91d3eaa 1070 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto 93:e188a91d3eaa 1071 * the selected interrupts).
Kojto 93:e188a91d3eaa 1072 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 93:e188a91d3eaa 1073 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1074 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 93:e188a91d3eaa 1075 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 93:e188a91d3eaa 1076 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 93:e188a91d3eaa 1077 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 93:e188a91d3eaa 1078 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 93:e188a91d3eaa 1079 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 93:e188a91d3eaa 1080 */
Kojto 93:e188a91d3eaa 1081 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto 93:e188a91d3eaa 1082
Kojto 93:e188a91d3eaa 1083 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto 93:e188a91d3eaa 1084 * bits to clear the selected interrupt pending bits.
Kojto 93:e188a91d3eaa 1085 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 93:e188a91d3eaa 1086 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1087 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 93:e188a91d3eaa 1088 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 93:e188a91d3eaa 1089 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 93:e188a91d3eaa 1090 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 93:e188a91d3eaa 1091 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 93:e188a91d3eaa 1092 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 93:e188a91d3eaa 1093 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 93:e188a91d3eaa 1094 */
Kojto 93:e188a91d3eaa 1095 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto 93:e188a91d3eaa 1096
Kojto 93:e188a91d3eaa 1097 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 93:e188a91d3eaa 1098 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 93:e188a91d3eaa 1099 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1100 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 93:e188a91d3eaa 1101 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 93:e188a91d3eaa 1102 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 93:e188a91d3eaa 1103 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 93:e188a91d3eaa 1104 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 93:e188a91d3eaa 1105 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 93:e188a91d3eaa 1106 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 93:e188a91d3eaa 1107 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 93:e188a91d3eaa 1108 */
Kojto 93:e188a91d3eaa 1109 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 93:e188a91d3eaa 1110
Kojto 93:e188a91d3eaa 1111 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto 93:e188a91d3eaa 1112 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto 93:e188a91d3eaa 1113 */
Kojto 93:e188a91d3eaa 1114 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 93:e188a91d3eaa 1115
Kojto 93:e188a91d3eaa 1116 /** @brief Check RCC flag is set or not.
Kojto 93:e188a91d3eaa 1117 * @param __FLAG__: specifies the flag to check.
Kojto 93:e188a91d3eaa 1118 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1119 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto 93:e188a91d3eaa 1120 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto 93:e188a91d3eaa 1121 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto 93:e188a91d3eaa 1122 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto 93:e188a91d3eaa 1123 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto 93:e188a91d3eaa 1124 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto 93:e188a91d3eaa 1125 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto 93:e188a91d3eaa 1126 * @arg RCC_FLAG_PINRST: Pin reset.
Kojto 93:e188a91d3eaa 1127 * @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto 93:e188a91d3eaa 1128 * @arg RCC_FLAG_SFTRST: Software reset.
Kojto 93:e188a91d3eaa 1129 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto 93:e188a91d3eaa 1130 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto 93:e188a91d3eaa 1131 * @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto 93:e188a91d3eaa 1132 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 93:e188a91d3eaa 1133 */
Kojto 93:e188a91d3eaa 1134 #define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto 93:e188a91d3eaa 1135 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
Kojto 93:e188a91d3eaa 1136
Kojto 93:e188a91d3eaa 1137 #define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
Kojto 93:e188a91d3eaa 1138
Kojto 93:e188a91d3eaa 1139
Kojto 93:e188a91d3eaa 1140 /* Include RCC HAL Extension module */
Kojto 93:e188a91d3eaa 1141 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 93:e188a91d3eaa 1142
Kojto 93:e188a91d3eaa 1143 /* Exported functions --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 1144
Kojto 93:e188a91d3eaa 1145 /* Initialization and de-initialization functions ******************************/
Kojto 93:e188a91d3eaa 1146 void HAL_RCC_DeInit(void);
Kojto 93:e188a91d3eaa 1147 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 93:e188a91d3eaa 1148 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 93:e188a91d3eaa 1149
Kojto 93:e188a91d3eaa 1150 /* Peripheral Control functions ************************************************/
Kojto 93:e188a91d3eaa 1151 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 93:e188a91d3eaa 1152 void HAL_RCC_EnableCSS(void);
Kojto 93:e188a91d3eaa 1153 void HAL_RCC_DisableCSS(void);
Kojto 93:e188a91d3eaa 1154 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 93:e188a91d3eaa 1155 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 93:e188a91d3eaa 1156 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 93:e188a91d3eaa 1157 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 93:e188a91d3eaa 1158 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 93:e188a91d3eaa 1159 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 93:e188a91d3eaa 1160
Kojto 93:e188a91d3eaa 1161 /* CSS NMI IRQ handler */
Kojto 93:e188a91d3eaa 1162 void HAL_RCC_NMI_IRQHandler(void);
Kojto 93:e188a91d3eaa 1163
Kojto 93:e188a91d3eaa 1164 /* User Callbacks in non blocking mode (IT mode) */
Kojto 93:e188a91d3eaa 1165 void HAL_RCC_CCSCallback(void);
Kojto 93:e188a91d3eaa 1166
Kojto 93:e188a91d3eaa 1167 /**
Kojto 93:e188a91d3eaa 1168 * @}
Kojto 93:e188a91d3eaa 1169 */
Kojto 93:e188a91d3eaa 1170
Kojto 93:e188a91d3eaa 1171 /**
Kojto 93:e188a91d3eaa 1172 * @}
Kojto 93:e188a91d3eaa 1173 */
Kojto 93:e188a91d3eaa 1174
Kojto 93:e188a91d3eaa 1175 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 1176 }
Kojto 93:e188a91d3eaa 1177 #endif
Kojto 93:e188a91d3eaa 1178
Kojto 93:e188a91d3eaa 1179 #endif /* __STM32F4xx_HAL_RCC_H */
Kojto 93:e188a91d3eaa 1180
Kojto 93:e188a91d3eaa 1181 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/