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mbed(SerialHalfDuplex入り)

TARGET_NUCLEO_F091RC/stm32f0xx_hal_rcc_ex.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:: Kojto
Date:: Tue Oct 28 16:40:41 2014 +0000
Revision:: 90:cb3d968589d8
Child:: 93:e188a91d3eaa

Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/**
Kojto	90:cb3d968589d8	2	******************************************************************************
Kojto	90:cb3d968589d8	3	* @file stm32f0xx_hal_rcc_ex.h
Kojto	90:cb3d968589d8	4	* @author MCD Application Team
Kojto	90:cb3d968589d8	5	* @version V1.1.0
Kojto	90:cb3d968589d8	6	* @date 03-Oct-2014
Kojto	90:cb3d968589d8	7	* @brief Header file of RCC HAL Extension module.
Kojto	90:cb3d968589d8	8	******************************************************************************
Kojto	90:cb3d968589d8	9	* @attention
Kojto	90:cb3d968589d8	10	*
Kojto	90:cb3d968589d8	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	90:cb3d968589d8	12	*
Kojto	90:cb3d968589d8	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	14	* are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	90:cb3d968589d8	16	* this list of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	90:cb3d968589d8	18	* this list of conditions and the following disclaimer in the documentation
Kojto	90:cb3d968589d8	19	* and/or other materials provided with the distribution.
Kojto	90:cb3d968589d8	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	90:cb3d968589d8	21	* may be used to endorse or promote products derived from this software
Kojto	90:cb3d968589d8	22	* without specific prior written permission.
Kojto	90:cb3d968589d8	23	*
Kojto	90:cb3d968589d8	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	90:cb3d968589d8	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	90:cb3d968589d8	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	90:cb3d968589d8	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	90:cb3d968589d8	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	90:cb3d968589d8	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	90:cb3d968589d8	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	90:cb3d968589d8	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	90:cb3d968589d8	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	34	*
Kojto	90:cb3d968589d8	35	******************************************************************************
Kojto	90:cb3d968589d8	36	*/
Kojto	90:cb3d968589d8	37
Kojto	90:cb3d968589d8	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	90:cb3d968589d8	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
Kojto	90:cb3d968589d8	40	#define __STM32F0xx_HAL_RCC_EX_H
Kojto	90:cb3d968589d8	41
Kojto	90:cb3d968589d8	42	#ifdef __cplusplus
Kojto	90:cb3d968589d8	43	extern "C" {
Kojto	90:cb3d968589d8	44	#endif
Kojto	90:cb3d968589d8	45
Kojto	90:cb3d968589d8	46	/* Includes ------------------------------------------------------------------*/
Kojto	90:cb3d968589d8	47	#include "stm32f0xx_hal_def.h"
Kojto	90:cb3d968589d8	48
Kojto	90:cb3d968589d8	49	/** @addtogroup STM32F0xx_HAL_Driver
Kojto	90:cb3d968589d8	50	* @{
Kojto	90:cb3d968589d8	51	*/
Kojto	90:cb3d968589d8	52
Kojto	90:cb3d968589d8	53	/** @addtogroup RCCEx
Kojto	90:cb3d968589d8	54	* @{
Kojto	90:cb3d968589d8	55	*/
Kojto	90:cb3d968589d8	56
Kojto	90:cb3d968589d8	57	/* Exported types ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	58
Kojto	90:cb3d968589d8	59	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	90:cb3d968589d8	60	* @{
Kojto	90:cb3d968589d8	61	*/
Kojto	90:cb3d968589d8	62
Kojto	90:cb3d968589d8	63	/**
Kojto	90:cb3d968589d8	64	* @brief RCC extended clocks structure definition
Kojto	90:cb3d968589d8	65	*/
Kojto	90:cb3d968589d8	66	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
Kojto	90:cb3d968589d8	67	typedef struct
Kojto	90:cb3d968589d8	68	{
Kojto	90:cb3d968589d8	69	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	70	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	71
Kojto	90:cb3d968589d8	72	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	73	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	74
Kojto	90:cb3d968589d8	75	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	76	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	90:cb3d968589d8	77
Kojto	90:cb3d968589d8	78	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	79	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	80
Kojto	90:cb3d968589d8	81	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	82	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx */
Kojto	90:cb3d968589d8	83
Kojto	90:cb3d968589d8	84	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
Kojto	90:cb3d968589d8	85	typedef struct
Kojto	90:cb3d968589d8	86	{
Kojto	90:cb3d968589d8	87	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	88	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	89
Kojto	90:cb3d968589d8	90	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	91	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	92
Kojto	90:cb3d968589d8	93	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	94	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	90:cb3d968589d8	95
Kojto	90:cb3d968589d8	96	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	97	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	98
Kojto	90:cb3d968589d8	99	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	90:cb3d968589d8	100	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	90:cb3d968589d8	101
Kojto	90:cb3d968589d8	102	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	103	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	104
Kojto	90:cb3d968589d8	105	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	106	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	90:cb3d968589d8	107
Kojto	90:cb3d968589d8	108	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	90:cb3d968589d8	109	typedef struct
Kojto	90:cb3d968589d8	110	{
Kojto	90:cb3d968589d8	111	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	112	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	113
Kojto	90:cb3d968589d8	114	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	115	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	116
Kojto	90:cb3d968589d8	117	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	118	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	90:cb3d968589d8	119
Kojto	90:cb3d968589d8	120	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	121	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	122
Kojto	90:cb3d968589d8	123	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	90:cb3d968589d8	124	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	90:cb3d968589d8	125
Kojto	90:cb3d968589d8	126	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	127	#endif /* STM32F051x8 \|\| STM32F058xx */
Kojto	90:cb3d968589d8	128
Kojto	90:cb3d968589d8	129	#if defined(STM32F071xB)
Kojto	90:cb3d968589d8	130	typedef struct
Kojto	90:cb3d968589d8	131	{
Kojto	90:cb3d968589d8	132	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	133	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	134
Kojto	90:cb3d968589d8	135	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	136	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	137
Kojto	90:cb3d968589d8	138	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	139	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	90:cb3d968589d8	140
Kojto	90:cb3d968589d8	141	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	142	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto	90:cb3d968589d8	143
Kojto	90:cb3d968589d8	144	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	145	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	146
Kojto	90:cb3d968589d8	147	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	90:cb3d968589d8	148	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	90:cb3d968589d8	149
Kojto	90:cb3d968589d8	150	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	151	#endif /* STM32F071xB */
Kojto	90:cb3d968589d8	152
Kojto	90:cb3d968589d8	153	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	90:cb3d968589d8	154	typedef struct
Kojto	90:cb3d968589d8	155	{
Kojto	90:cb3d968589d8	156	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	157	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	158
Kojto	90:cb3d968589d8	159	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	160	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	161
Kojto	90:cb3d968589d8	162	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	163	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	90:cb3d968589d8	164
Kojto	90:cb3d968589d8	165	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	166	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto	90:cb3d968589d8	167
Kojto	90:cb3d968589d8	168	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	169	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	170
Kojto	90:cb3d968589d8	171	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	90:cb3d968589d8	172	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	90:cb3d968589d8	173
Kojto	90:cb3d968589d8	174	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	175	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	176
Kojto	90:cb3d968589d8	177	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	178	#endif /* STM32F072xB \|\| STM32F078xx */
Kojto	90:cb3d968589d8	179
Kojto	90:cb3d968589d8	180
Kojto	90:cb3d968589d8	181	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	182	typedef struct
Kojto	90:cb3d968589d8	183	{
Kojto	90:cb3d968589d8	184	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	185	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	186
Kojto	90:cb3d968589d8	187	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	188	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	189
Kojto	90:cb3d968589d8	190	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	191	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	90:cb3d968589d8	192
Kojto	90:cb3d968589d8	193	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	194	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto	90:cb3d968589d8	195
Kojto	90:cb3d968589d8	196	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	197	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto	90:cb3d968589d8	198
Kojto	90:cb3d968589d8	199	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	200	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	201
Kojto	90:cb3d968589d8	202	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	90:cb3d968589d8	203	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	90:cb3d968589d8	204
Kojto	90:cb3d968589d8	205	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	206	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	207
Kojto	90:cb3d968589d8	208
Kojto	90:cb3d968589d8	209	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	210	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	211	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	212	/**
Kojto	90:cb3d968589d8	213	* @brief RCC CRS Status structures definition
Kojto	90:cb3d968589d8	214	*/
Kojto	90:cb3d968589d8	215	typedef enum
Kojto	90:cb3d968589d8	216	{
Kojto	90:cb3d968589d8	217	RCC_CRS_NONE = 0x00,
Kojto	90:cb3d968589d8	218	RCC_CRS_TIMEOUT = 0x01,
Kojto	90:cb3d968589d8	219	RCC_CRS_SYNCOK = 0x02,
Kojto	90:cb3d968589d8	220	RCC_CRS_SYNCWARM = 0x04,
Kojto	90:cb3d968589d8	221	RCC_CRS_SYNCERR = 0x08,
Kojto	90:cb3d968589d8	222	RCC_CRS_SYNCMISS = 0x10,
Kojto	90:cb3d968589d8	223	RCC_CRS_TRIMOV = 0x20
Kojto	90:cb3d968589d8	224	} RCC_CRSStatusTypeDef;
Kojto	90:cb3d968589d8	225
Kojto	90:cb3d968589d8	226	/**
Kojto	90:cb3d968589d8	227	* @brief RCC_CRS Init structure definition
Kojto	90:cb3d968589d8	228	*/
Kojto	90:cb3d968589d8	229	typedef struct
Kojto	90:cb3d968589d8	230	{
Kojto	90:cb3d968589d8	231	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
Kojto	90:cb3d968589d8	232	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
Kojto	90:cb3d968589d8	233
Kojto	90:cb3d968589d8	234	uint32_t Source; /*!< Specifies the SYNC signal source.
Kojto	90:cb3d968589d8	235	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
Kojto	90:cb3d968589d8	236
Kojto	90:cb3d968589d8	237	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
Kojto	90:cb3d968589d8	238	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
Kojto	90:cb3d968589d8	239
Kojto	90:cb3d968589d8	240	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto	90:cb3d968589d8	241	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
Kojto	90:cb3d968589d8	242	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
Kojto	90:cb3d968589d8	243
Kojto	90:cb3d968589d8	244	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
Kojto	90:cb3d968589d8	245	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
Kojto	90:cb3d968589d8	246
Kojto	90:cb3d968589d8	247	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
Kojto	90:cb3d968589d8	248	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto	90:cb3d968589d8	249
Kojto	90:cb3d968589d8	250	}RCC_CRSInitTypeDef;
Kojto	90:cb3d968589d8	251
Kojto	90:cb3d968589d8	252	/**
Kojto	90:cb3d968589d8	253	* @brief RCC_CRS Synchronization structure definition
Kojto	90:cb3d968589d8	254	*/
Kojto	90:cb3d968589d8	255	typedef struct
Kojto	90:cb3d968589d8	256	{
Kojto	90:cb3d968589d8	257	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto	90:cb3d968589d8	258	This parameter must be a number between 0 and 0xFFFF*/
Kojto	90:cb3d968589d8	259
Kojto	90:cb3d968589d8	260	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Kojto	90:cb3d968589d8	261	This parameter must be a number between 0 and 0x3F */
Kojto	90:cb3d968589d8	262
Kojto	90:cb3d968589d8	263	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Kojto	90:cb3d968589d8	264	value latched in the time of the last SYNC event.
Kojto	90:cb3d968589d8	265	This parameter must be a number between 0 and 0xFFFF */
Kojto	90:cb3d968589d8	266
Kojto	90:cb3d968589d8	267	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
Kojto	90:cb3d968589d8	268	frequency error counter latched in the time of the last SYNC event.
Kojto	90:cb3d968589d8	269	It shows whether the actual frequency is below or above the target.
Kojto	90:cb3d968589d8	270	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
Kojto	90:cb3d968589d8	271
Kojto	90:cb3d968589d8	272	}RCC_CRSSynchroInfoTypeDef;
Kojto	90:cb3d968589d8	273
Kojto	90:cb3d968589d8	274	#endif /* STM32F042x6 \|\| */
Kojto	90:cb3d968589d8	275	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	276	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	277
Kojto	90:cb3d968589d8	278	/**
Kojto	90:cb3d968589d8	279	* @}
Kojto	90:cb3d968589d8	280	*/
Kojto	90:cb3d968589d8	281
Kojto	90:cb3d968589d8	282	/* Exported constants --------------------------------------------------------*/
Kojto	90:cb3d968589d8	283
Kojto	90:cb3d968589d8	284	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto	90:cb3d968589d8	285	* @{
Kojto	90:cb3d968589d8	286	*/
Kojto	90:cb3d968589d8	287
Kojto	90:cb3d968589d8	288	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
Kojto	90:cb3d968589d8	289	* @{
Kojto	90:cb3d968589d8	290	*/
Kojto	90:cb3d968589d8	291	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
Kojto	90:cb3d968589d8	292	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	293	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	294	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	295
Kojto	90:cb3d968589d8	296	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	90:cb3d968589d8	297	RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	298	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx */
Kojto	90:cb3d968589d8	299
Kojto	90:cb3d968589d8	300	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
Kojto	90:cb3d968589d8	301	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	302	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	303	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	304	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	305	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	306
Kojto	90:cb3d968589d8	307	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	90:cb3d968589d8	308	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
Kojto	90:cb3d968589d8	309	RCC_PERIPHCLK_USB))
Kojto	90:cb3d968589d8	310	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	90:cb3d968589d8	311
Kojto	90:cb3d968589d8	312	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	90:cb3d968589d8	313	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	314	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	315	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	316	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	317
Kojto	90:cb3d968589d8	318	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	90:cb3d968589d8	319	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	320	#endif /* STM32F051x8 \|\| STM32F058xx */
Kojto	90:cb3d968589d8	321
Kojto	90:cb3d968589d8	322	#if defined(STM32F071xB)
Kojto	90:cb3d968589d8	323	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	324	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	325	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	326	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	327	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	328
Kojto	90:cb3d968589d8	329	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	90:cb3d968589d8	330	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	90:cb3d968589d8	331	RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	332	#endif /* STM32F071xB */
Kojto	90:cb3d968589d8	333
Kojto	90:cb3d968589d8	334	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	90:cb3d968589d8	335	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	336	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	337	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	338	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	339	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	340	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	341
Kojto	90:cb3d968589d8	342	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	90:cb3d968589d8	343	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	90:cb3d968589d8	344	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	90:cb3d968589d8	345	#endif /* STM32F072xB \|\| STM32F078xx */
Kojto	90:cb3d968589d8	346
Kojto	90:cb3d968589d8	347	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	348	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	349	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	350	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	351	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	352	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	353	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	354
Kojto	90:cb3d968589d8	355	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	90:cb3d968589d8	356	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	90:cb3d968589d8	357	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
Kojto	90:cb3d968589d8	358	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	359
Kojto	90:cb3d968589d8	360	/**
Kojto	90:cb3d968589d8	361	* @}
Kojto	90:cb3d968589d8	362	*/
Kojto	90:cb3d968589d8	363
Kojto	90:cb3d968589d8	364	/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
Kojto	90:cb3d968589d8	365	* @{
Kojto	90:cb3d968589d8	366	*/
Kojto	90:cb3d968589d8	367
Kojto	90:cb3d968589d8	368	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
Kojto	90:cb3d968589d8	369
Kojto	90:cb3d968589d8	370	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
Kojto	90:cb3d968589d8	371
Kojto	90:cb3d968589d8	372	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	90:cb3d968589d8	373	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	90:cb3d968589d8	374	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	375	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	376	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	377	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	378	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
Kojto	90:cb3d968589d8	379	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	380	((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto	90:cb3d968589d8	381
Kojto	90:cb3d968589d8	382	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx */
Kojto	90:cb3d968589d8	383
Kojto	90:cb3d968589d8	384	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	90:cb3d968589d8	385
Kojto	90:cb3d968589d8	386	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	90:cb3d968589d8	387	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	90:cb3d968589d8	388	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	389	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	390	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	391	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	392	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	393	((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto	90:cb3d968589d8	394
Kojto	90:cb3d968589d8	395	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
Kojto	90:cb3d968589d8	396
Kojto	90:cb3d968589d8	397	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	398	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	399	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	400
Kojto	90:cb3d968589d8	401	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto	90:cb3d968589d8	402	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
Kojto	90:cb3d968589d8	403
Kojto	90:cb3d968589d8	404	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	90:cb3d968589d8	405	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	90:cb3d968589d8	406	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	407	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	408	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	409	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	410	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
Kojto	90:cb3d968589d8	411	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	412	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
Kojto	90:cb3d968589d8	413	((SOURCE) == RCC_MCOSOURCE_HSI48))
Kojto	90:cb3d968589d8	414
Kojto	90:cb3d968589d8	415	#define RCC_IT_HSI48 ((uint8_t)0x40)
Kojto	90:cb3d968589d8	416
Kojto	90:cb3d968589d8	417	/* Flags in the CR2 register */
Kojto	90:cb3d968589d8	418	#define RCC_CR2_HSI48RDY_BitNumber 16
Kojto	90:cb3d968589d8	419
Kojto	90:cb3d968589d8	420	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
Kojto	90:cb3d968589d8	421
Kojto	90:cb3d968589d8	422	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	423	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	424	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	425	/**
Kojto	90:cb3d968589d8	426	* @}
Kojto	90:cb3d968589d8	427	*/
Kojto	90:cb3d968589d8	428
Kojto	90:cb3d968589d8	429	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	90:cb3d968589d8	430
Kojto	90:cb3d968589d8	431	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto	90:cb3d968589d8	432	* @{
Kojto	90:cb3d968589d8	433	*/
Kojto	90:cb3d968589d8	434	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
Kojto	90:cb3d968589d8	435	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto	90:cb3d968589d8	436
Kojto	90:cb3d968589d8	437	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
Kojto	90:cb3d968589d8	438	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto	90:cb3d968589d8	439	/**
Kojto	90:cb3d968589d8	440	* @}
Kojto	90:cb3d968589d8	441	*/
Kojto	90:cb3d968589d8	442
Kojto	90:cb3d968589d8	443	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
Kojto	90:cb3d968589d8	444
Kojto	90:cb3d968589d8	445	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	446	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	447
Kojto	90:cb3d968589d8	448	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
Kojto	90:cb3d968589d8	449	* @{
Kojto	90:cb3d968589d8	450	*/
Kojto	90:cb3d968589d8	451	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
Kojto	90:cb3d968589d8	452	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
Kojto	90:cb3d968589d8	453	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
Kojto	90:cb3d968589d8	454	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
Kojto	90:cb3d968589d8	455
Kojto	90:cb3d968589d8	456	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	457	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	458	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	459	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	460	/**
Kojto	90:cb3d968589d8	461	* @}
Kojto	90:cb3d968589d8	462	*/
Kojto	90:cb3d968589d8	463
Kojto	90:cb3d968589d8	464	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	465	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	466
Kojto	90:cb3d968589d8	467	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	468
Kojto	90:cb3d968589d8	469	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
Kojto	90:cb3d968589d8	470	* @{
Kojto	90:cb3d968589d8	471	*/
Kojto	90:cb3d968589d8	472	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
Kojto	90:cb3d968589d8	473	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
Kojto	90:cb3d968589d8	474	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
Kojto	90:cb3d968589d8	475	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
Kojto	90:cb3d968589d8	476
Kojto	90:cb3d968589d8	477	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	478	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	479	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	480	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	481	/**
Kojto	90:cb3d968589d8	482	* @}
Kojto	90:cb3d968589d8	483	*/
Kojto	90:cb3d968589d8	484
Kojto	90:cb3d968589d8	485	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	486
Kojto	90:cb3d968589d8	487
Kojto	90:cb3d968589d8	488	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	489	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	490	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	491	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	492
Kojto	90:cb3d968589d8	493	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
Kojto	90:cb3d968589d8	494	* @{
Kojto	90:cb3d968589d8	495	*/
Kojto	90:cb3d968589d8	496	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
Kojto	90:cb3d968589d8	497	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
Kojto	90:cb3d968589d8	498
Kojto	90:cb3d968589d8	499	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	500	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	90:cb3d968589d8	501	/**
Kojto	90:cb3d968589d8	502	* @}
Kojto	90:cb3d968589d8	503	*/
Kojto	90:cb3d968589d8	504
Kojto	90:cb3d968589d8	505	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	506	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	507	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	508	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	509
Kojto	90:cb3d968589d8	510	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	511	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	512	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	513
Kojto	90:cb3d968589d8	514	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
Kojto	90:cb3d968589d8	515	* @{
Kojto	90:cb3d968589d8	516	*/
Kojto	90:cb3d968589d8	517	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	90:cb3d968589d8	518	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
Kojto	90:cb3d968589d8	519
Kojto	90:cb3d968589d8	520	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	521	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
Kojto	90:cb3d968589d8	522	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	90:cb3d968589d8	523	/**
Kojto	90:cb3d968589d8	524	* @}
Kojto	90:cb3d968589d8	525	*/
Kojto	90:cb3d968589d8	526
Kojto	90:cb3d968589d8	527	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
Kojto	90:cb3d968589d8	528	* @{
Kojto	90:cb3d968589d8	529	*/
Kojto	90:cb3d968589d8	530	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
Kojto	90:cb3d968589d8	531
Kojto	90:cb3d968589d8	532	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	533	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	534	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
Kojto	90:cb3d968589d8	535	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
Kojto	90:cb3d968589d8	536
Kojto	90:cb3d968589d8	537	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
Kojto	90:cb3d968589d8	538
Kojto	90:cb3d968589d8	539	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	90:cb3d968589d8	540	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	90:cb3d968589d8	541	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
Kojto	90:cb3d968589d8	542	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
Kojto	90:cb3d968589d8	543	/**
Kojto	90:cb3d968589d8	544	* @}
Kojto	90:cb3d968589d8	545	*/
Kojto	90:cb3d968589d8	546
Kojto	90:cb3d968589d8	547	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto	90:cb3d968589d8	548	* @{
Kojto	90:cb3d968589d8	549	*/
Kojto	90:cb3d968589d8	550	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	90:cb3d968589d8	551	#define RCC_HSI48_ON ((uint8_t)0x01)
Kojto	90:cb3d968589d8	552
Kojto	90:cb3d968589d8	553	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
Kojto	90:cb3d968589d8	554	/**
Kojto	90:cb3d968589d8	555	* @}
Kojto	90:cb3d968589d8	556	*/
Kojto	90:cb3d968589d8	557
Kojto	90:cb3d968589d8	558	#else
Kojto	90:cb3d968589d8	559	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
Kojto	90:cb3d968589d8	560	* @{
Kojto	90:cb3d968589d8	561	*/
Kojto	90:cb3d968589d8	562	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto	90:cb3d968589d8	563
Kojto	90:cb3d968589d8	564	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	565	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	90:cb3d968589d8	566	/**
Kojto	90:cb3d968589d8	567	* @}
Kojto	90:cb3d968589d8	568	*/
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
Kojto	90:cb3d968589d8	571	* @{
Kojto	90:cb3d968589d8	572	*/
Kojto	90:cb3d968589d8	573	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	574	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	575	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	90:cb3d968589d8	576
Kojto	90:cb3d968589d8	577	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	90:cb3d968589d8	578	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	90:cb3d968589d8	579	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Kojto	90:cb3d968589d8	580	/**
Kojto	90:cb3d968589d8	581	* @}
Kojto	90:cb3d968589d8	582	*/
Kojto	90:cb3d968589d8	583
Kojto	90:cb3d968589d8	584	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto	90:cb3d968589d8	585	* @{
Kojto	90:cb3d968589d8	586	*/
Kojto	90:cb3d968589d8	587	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	90:cb3d968589d8	588
Kojto	90:cb3d968589d8	589	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
Kojto	90:cb3d968589d8	590	/**
Kojto	90:cb3d968589d8	591	* @}
Kojto	90:cb3d968589d8	592	*/
Kojto	90:cb3d968589d8	593
Kojto	90:cb3d968589d8	594	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	595	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	596	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	597
Kojto	90:cb3d968589d8	598
Kojto	90:cb3d968589d8	599	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
Kojto	90:cb3d968589d8	600	* @{
Kojto	90:cb3d968589d8	601	*/
Kojto	90:cb3d968589d8	602
Kojto	90:cb3d968589d8	603	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	90:cb3d968589d8	604
Kojto	90:cb3d968589d8	605	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	606
Kojto	90:cb3d968589d8	607	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
Kojto	90:cb3d968589d8	608
Kojto	90:cb3d968589d8	609	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
Kojto	90:cb3d968589d8	610
Kojto	90:cb3d968589d8	611	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
Kojto	90:cb3d968589d8	612	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| \
Kojto	90:cb3d968589d8	613	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	614	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	615
Kojto	90:cb3d968589d8	616	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	617	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
Kojto	90:cb3d968589d8	618	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
Kojto	90:cb3d968589d8	619	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
Kojto	90:cb3d968589d8	620	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
Kojto	90:cb3d968589d8	621	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
Kojto	90:cb3d968589d8	622	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
Kojto	90:cb3d968589d8	623	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
Kojto	90:cb3d968589d8	624
Kojto	90:cb3d968589d8	625	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
Kojto	90:cb3d968589d8	626	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
Kojto	90:cb3d968589d8	627	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
Kojto	90:cb3d968589d8	628	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
Kojto	90:cb3d968589d8	629
Kojto	90:cb3d968589d8	630	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	631	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	632	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	633
Kojto	90:cb3d968589d8	634	/**
Kojto	90:cb3d968589d8	635	* @}
Kojto	90:cb3d968589d8	636	*/
Kojto	90:cb3d968589d8	637
Kojto	90:cb3d968589d8	638	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	639	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	640	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	641
Kojto	90:cb3d968589d8	642	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
Kojto	90:cb3d968589d8	643	* @{
Kojto	90:cb3d968589d8	644	*/
Kojto	90:cb3d968589d8	645	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
Kojto	90:cb3d968589d8	646	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
Kojto	90:cb3d968589d8	647	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
Kojto	90:cb3d968589d8	648
Kojto	90:cb3d968589d8	649	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
Kojto	90:cb3d968589d8	650	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	651	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
Kojto	90:cb3d968589d8	652	/**
Kojto	90:cb3d968589d8	653	* @}
Kojto	90:cb3d968589d8	654	*/
Kojto	90:cb3d968589d8	655
Kojto	90:cb3d968589d8	656	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
Kojto	90:cb3d968589d8	657	* @{
Kojto	90:cb3d968589d8	658	*/
Kojto	90:cb3d968589d8	659	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
Kojto	90:cb3d968589d8	660	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
Kojto	90:cb3d968589d8	661	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
Kojto	90:cb3d968589d8	662	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
Kojto	90:cb3d968589d8	663	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
Kojto	90:cb3d968589d8	664	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
Kojto	90:cb3d968589d8	665	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
Kojto	90:cb3d968589d8	666	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
Kojto	90:cb3d968589d8	667
Kojto	90:cb3d968589d8	668	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
Kojto	90:cb3d968589d8	669	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
Kojto	90:cb3d968589d8	670	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
Kojto	90:cb3d968589d8	671	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
Kojto	90:cb3d968589d8	672	/**
Kojto	90:cb3d968589d8	673	* @}
Kojto	90:cb3d968589d8	674	*/
Kojto	90:cb3d968589d8	675
Kojto	90:cb3d968589d8	676	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
Kojto	90:cb3d968589d8	677	* @{
Kojto	90:cb3d968589d8	678	*/
Kojto	90:cb3d968589d8	679	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
Kojto	90:cb3d968589d8	680	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
Kojto	90:cb3d968589d8	681
Kojto	90:cb3d968589d8	682	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
Kojto	90:cb3d968589d8	683	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto	90:cb3d968589d8	684	/**
Kojto	90:cb3d968589d8	685	* @}
Kojto	90:cb3d968589d8	686	*/
Kojto	90:cb3d968589d8	687
Kojto	90:cb3d968589d8	688	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
Kojto	90:cb3d968589d8	689	* @{
Kojto	90:cb3d968589d8	690	*/
Kojto	90:cb3d968589d8	691	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
Kojto	90:cb3d968589d8	692	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
Kojto	90:cb3d968589d8	693
Kojto	90:cb3d968589d8	694	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
Kojto	90:cb3d968589d8	695	/**
Kojto	90:cb3d968589d8	696	* @}
Kojto	90:cb3d968589d8	697	*/
Kojto	90:cb3d968589d8	698
Kojto	90:cb3d968589d8	699	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
Kojto	90:cb3d968589d8	700	* @{
Kojto	90:cb3d968589d8	701	*/
Kojto	90:cb3d968589d8	702	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
Kojto	90:cb3d968589d8	703
Kojto	90:cb3d968589d8	704	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
Kojto	90:cb3d968589d8	705	/**
Kojto	90:cb3d968589d8	706	* @}
Kojto	90:cb3d968589d8	707	*/
Kojto	90:cb3d968589d8	708
Kojto	90:cb3d968589d8	709	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
Kojto	90:cb3d968589d8	710	* @{
Kojto	90:cb3d968589d8	711	*/
Kojto	90:cb3d968589d8	712	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto	90:cb3d968589d8	713	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto	90:cb3d968589d8	714	corresponds to a higher output frequency */
Kojto	90:cb3d968589d8	715
Kojto	90:cb3d968589d8	716	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
Kojto	90:cb3d968589d8	717	/**
Kojto	90:cb3d968589d8	718	* @}
Kojto	90:cb3d968589d8	719	*/
Kojto	90:cb3d968589d8	720
Kojto	90:cb3d968589d8	721	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
Kojto	90:cb3d968589d8	722	* @{
Kojto	90:cb3d968589d8	723	*/
Kojto	90:cb3d968589d8	724	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
Kojto	90:cb3d968589d8	725	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
Kojto	90:cb3d968589d8	726
Kojto	90:cb3d968589d8	727	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
Kojto	90:cb3d968589d8	728	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto	90:cb3d968589d8	729	/**
Kojto	90:cb3d968589d8	730	* @}
Kojto	90:cb3d968589d8	731	*/
Kojto	90:cb3d968589d8	732
Kojto	90:cb3d968589d8	733	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
Kojto	90:cb3d968589d8	734	* @{
Kojto	90:cb3d968589d8	735	*/
Kojto	90:cb3d968589d8	736	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
Kojto	90:cb3d968589d8	737	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
Kojto	90:cb3d968589d8	738	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
Kojto	90:cb3d968589d8	739	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
Kojto	90:cb3d968589d8	740	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
Kojto	90:cb3d968589d8	741	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
Kojto	90:cb3d968589d8	742	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
Kojto	90:cb3d968589d8	743
Kojto	90:cb3d968589d8	744	/**
Kojto	90:cb3d968589d8	745	* @}
Kojto	90:cb3d968589d8	746	*/
Kojto	90:cb3d968589d8	747
Kojto	90:cb3d968589d8	748	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
Kojto	90:cb3d968589d8	749	* @{
Kojto	90:cb3d968589d8	750	*/
Kojto	90:cb3d968589d8	751	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
Kojto	90:cb3d968589d8	752	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
Kojto	90:cb3d968589d8	753	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
Kojto	90:cb3d968589d8	754	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
Kojto	90:cb3d968589d8	755	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
Kojto	90:cb3d968589d8	756	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
Kojto	90:cb3d968589d8	757	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
Kojto	90:cb3d968589d8	758
Kojto	90:cb3d968589d8	759	/**
Kojto	90:cb3d968589d8	760	* @}
Kojto	90:cb3d968589d8	761	*/
Kojto	90:cb3d968589d8	762
Kojto	90:cb3d968589d8	763	/**
Kojto	90:cb3d968589d8	764	* @}
Kojto	90:cb3d968589d8	765	*/
Kojto	90:cb3d968589d8	766
Kojto	90:cb3d968589d8	767	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	768	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	769	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	770
Kojto	90:cb3d968589d8	771	/* Exported macros ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	772	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	90:cb3d968589d8	773	* @{
Kojto	90:cb3d968589d8	774	*/
Kojto	90:cb3d968589d8	775
Kojto	90:cb3d968589d8	776	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto	90:cb3d968589d8	777	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	90:cb3d968589d8	778	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	779	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	780	* using it.
Kojto	90:cb3d968589d8	781	* @{
Kojto	90:cb3d968589d8	782	*/
Kojto	90:cb3d968589d8	783	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
Kojto	90:cb3d968589d8	784	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	785	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	786	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	787
Kojto	90:cb3d968589d8	788	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
Kojto	90:cb3d968589d8	789
Kojto	90:cb3d968589d8	790	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto	90:cb3d968589d8	791
Kojto	90:cb3d968589d8	792	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	90:cb3d968589d8	793	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	794	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|[ */
Kojto	90:cb3d968589d8	795	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	796
Kojto	90:cb3d968589d8	797	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	798	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	799
Kojto	90:cb3d968589d8	800	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
Kojto	90:cb3d968589d8	801
Kojto	90:cb3d968589d8	802	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto	90:cb3d968589d8	803
Kojto	90:cb3d968589d8	804	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	805	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	806
Kojto	90:cb3d968589d8	807	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	808	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	809	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	810	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	811
Kojto	90:cb3d968589d8	812	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
Kojto	90:cb3d968589d8	813
Kojto	90:cb3d968589d8	814	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
Kojto	90:cb3d968589d8	815
Kojto	90:cb3d968589d8	816	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	817	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	818	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	819	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	820
Kojto	90:cb3d968589d8	821	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	822
Kojto	90:cb3d968589d8	823	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
Kojto	90:cb3d968589d8	824
Kojto	90:cb3d968589d8	825	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto	90:cb3d968589d8	826
Kojto	90:cb3d968589d8	827	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	828
Kojto	90:cb3d968589d8	829	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	90:cb3d968589d8	830	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	831	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	832	* using it.
Kojto	90:cb3d968589d8	833	*/
Kojto	90:cb3d968589d8	834	#if defined(STM32F030x8) \|\| \
Kojto	90:cb3d968589d8	835	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	836	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	837	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	838	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	839
Kojto	90:cb3d968589d8	840	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
Kojto	90:cb3d968589d8	841	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	842
Kojto	90:cb3d968589d8	843	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	90:cb3d968589d8	844	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	845
Kojto	90:cb3d968589d8	846	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	847	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	848	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	849	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	850
Kojto	90:cb3d968589d8	851	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
Kojto	90:cb3d968589d8	852	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	853	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	854	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	855	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	856
Kojto	90:cb3d968589d8	857	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
Kojto	90:cb3d968589d8	858
Kojto	90:cb3d968589d8	859	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	90:cb3d968589d8	860
Kojto	90:cb3d968589d8	861	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	90:cb3d968589d8	862	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	863	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	864	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	865	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	866
Kojto	90:cb3d968589d8	867	#if defined(STM32F030x8) \|\| \
Kojto	90:cb3d968589d8	868	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	869	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	870	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	871
Kojto	90:cb3d968589d8	872	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
Kojto	90:cb3d968589d8	873	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	874
Kojto	90:cb3d968589d8	875	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	90:cb3d968589d8	876	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	877
Kojto	90:cb3d968589d8	878	#endif /* STM32F030x8 \|\| */
Kojto	90:cb3d968589d8	879	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	880	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	881	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	882
Kojto	90:cb3d968589d8	883	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	884	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	885	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	886
Kojto	90:cb3d968589d8	887	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
Kojto	90:cb3d968589d8	888
Kojto	90:cb3d968589d8	889	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	90:cb3d968589d8	890
Kojto	90:cb3d968589d8	891	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	892	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	893	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	894
Kojto	90:cb3d968589d8	895	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	896	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	897	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	898	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	899
Kojto	90:cb3d968589d8	900	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
Kojto	90:cb3d968589d8	901
Kojto	90:cb3d968589d8	902	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	90:cb3d968589d8	903
Kojto	90:cb3d968589d8	904	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	905	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	906	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	907	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	908
Kojto	90:cb3d968589d8	909	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	910	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	911
Kojto	90:cb3d968589d8	912	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
Kojto	90:cb3d968589d8	913	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
Kojto	90:cb3d968589d8	914	#define __USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
Kojto	90:cb3d968589d8	915
Kojto	90:cb3d968589d8	916	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	90:cb3d968589d8	917	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	90:cb3d968589d8	918	#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
Kojto	90:cb3d968589d8	919
Kojto	90:cb3d968589d8	920	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	921	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	922
Kojto	90:cb3d968589d8	923	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	924	defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
Kojto	90:cb3d968589d8	927
Kojto	90:cb3d968589d8	928	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto	90:cb3d968589d8	929
Kojto	90:cb3d968589d8	930	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	931	/* STM32F072xB \|\| STM32F078xx */
Kojto	90:cb3d968589d8	932
Kojto	90:cb3d968589d8	933	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
Kojto	90:cb3d968589d8	934	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	935
Kojto	90:cb3d968589d8	936	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
Kojto	90:cb3d968589d8	937	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
Kojto	90:cb3d968589d8	938
Kojto	90:cb3d968589d8	939	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
Kojto	90:cb3d968589d8	940	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	941
Kojto	90:cb3d968589d8	942	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	943	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	944	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	945
Kojto	90:cb3d968589d8	946	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
Kojto	90:cb3d968589d8	947
Kojto	90:cb3d968589d8	948	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
Kojto	90:cb3d968589d8	949
Kojto	90:cb3d968589d8	950	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	951	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	952	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	953
Kojto	90:cb3d968589d8	954	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	955
Kojto	90:cb3d968589d8	956	#define __USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
Kojto	90:cb3d968589d8	957
Kojto	90:cb3d968589d8	958	#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
Kojto	90:cb3d968589d8	959
Kojto	90:cb3d968589d8	960	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	961
Kojto	90:cb3d968589d8	962	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	90:cb3d968589d8	963	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	964	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	965	* using it.
Kojto	90:cb3d968589d8	966	*/
Kojto	90:cb3d968589d8	967	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	968	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	969	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	970	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	971
Kojto	90:cb3d968589d8	972	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
Kojto	90:cb3d968589d8	973
Kojto	90:cb3d968589d8	974	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto	90:cb3d968589d8	975
Kojto	90:cb3d968589d8	976	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	977	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	978	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	979	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	980
Kojto	90:cb3d968589d8	981	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	982
Kojto	90:cb3d968589d8	983	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
Kojto	90:cb3d968589d8	984	#define __USART7_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART7EN))
Kojto	90:cb3d968589d8	985	#define __USART8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART8EN))
Kojto	90:cb3d968589d8	986
Kojto	90:cb3d968589d8	987	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	90:cb3d968589d8	988	#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
Kojto	90:cb3d968589d8	989	#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
Kojto	90:cb3d968589d8	990
Kojto	90:cb3d968589d8	991	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	992
Kojto	90:cb3d968589d8	993	/**
Kojto	90:cb3d968589d8	994	* @}
Kojto	90:cb3d968589d8	995	*/
Kojto	90:cb3d968589d8	996
Kojto	90:cb3d968589d8	997
Kojto	90:cb3d968589d8	998	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto	90:cb3d968589d8	999	* @brief Forces or releases peripheral reset.
Kojto	90:cb3d968589d8	1000	* @{
Kojto	90:cb3d968589d8	1001	*/
Kojto	90:cb3d968589d8	1002
Kojto	90:cb3d968589d8	1003	/** @brief Force or release AHB peripheral reset.
Kojto	90:cb3d968589d8	1004	*/
Kojto	90:cb3d968589d8	1005	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
Kojto	90:cb3d968589d8	1006	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1007	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1008	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1009
Kojto	90:cb3d968589d8	1010	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
Kojto	90:cb3d968589d8	1011
Kojto	90:cb3d968589d8	1012	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto	90:cb3d968589d8	1013
Kojto	90:cb3d968589d8	1014	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	90:cb3d968589d8	1015	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1016	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1017	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1018
Kojto	90:cb3d968589d8	1019	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1020	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1021
Kojto	90:cb3d968589d8	1022	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
Kojto	90:cb3d968589d8	1023
Kojto	90:cb3d968589d8	1024	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto	90:cb3d968589d8	1025
Kojto	90:cb3d968589d8	1026	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1027	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1028
Kojto	90:cb3d968589d8	1029	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1030	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1031	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1032	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1033
Kojto	90:cb3d968589d8	1034	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
Kojto	90:cb3d968589d8	1035
Kojto	90:cb3d968589d8	1036	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
Kojto	90:cb3d968589d8	1037
Kojto	90:cb3d968589d8	1038	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1039	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1040	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1041	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1042
Kojto	90:cb3d968589d8	1043	/** @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	1044	*/
Kojto	90:cb3d968589d8	1045	#if defined(STM32F030x8) \|\| \
Kojto	90:cb3d968589d8	1046	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1047	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1048	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1049	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1050
Kojto	90:cb3d968589d8	1051	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	90:cb3d968589d8	1052	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	1053
Kojto	90:cb3d968589d8	1054	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	90:cb3d968589d8	1055	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	1056
Kojto	90:cb3d968589d8	1057	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1058	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1059	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1060	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1061
Kojto	90:cb3d968589d8	1062	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
Kojto	90:cb3d968589d8	1063	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1064	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1065	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1066	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1067
Kojto	90:cb3d968589d8	1068	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	90:cb3d968589d8	1069
Kojto	90:cb3d968589d8	1070	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	90:cb3d968589d8	1071
Kojto	90:cb3d968589d8	1072	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	90:cb3d968589d8	1073	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1074	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1075	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1076	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1077
Kojto	90:cb3d968589d8	1078	#if defined(STM32F030x8) \|\| \
Kojto	90:cb3d968589d8	1079	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1080	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1081	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1082
Kojto	90:cb3d968589d8	1083	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	90:cb3d968589d8	1084	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	1085
Kojto	90:cb3d968589d8	1086	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	90:cb3d968589d8	1087	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	#endif /* STM32F030x8 \|\| */
Kojto	90:cb3d968589d8	1090	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1091	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1092	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1093
Kojto	90:cb3d968589d8	1094	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1095	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1096	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1097
Kojto	90:cb3d968589d8	1098	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	90:cb3d968589d8	1099
Kojto	90:cb3d968589d8	1100	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	90:cb3d968589d8	1101
Kojto	90:cb3d968589d8	1102	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1103	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1104	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1105
Kojto	90:cb3d968589d8	1106	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1107	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1108	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1109	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1110
Kojto	90:cb3d968589d8	1111	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	90:cb3d968589d8	1112
Kojto	90:cb3d968589d8	1113	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	90:cb3d968589d8	1114
Kojto	90:cb3d968589d8	1115	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1116	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1117	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1118	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1119
Kojto	90:cb3d968589d8	1120	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1121	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1122
Kojto	90:cb3d968589d8	1123	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	90:cb3d968589d8	1124	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	90:cb3d968589d8	1125	#define __USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
Kojto	90:cb3d968589d8	1126
Kojto	90:cb3d968589d8	1127	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	90:cb3d968589d8	1128	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	90:cb3d968589d8	1129	#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
Kojto	90:cb3d968589d8	1130
Kojto	90:cb3d968589d8	1131	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1132	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1133
Kojto	90:cb3d968589d8	1134	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1135	defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	90:cb3d968589d8	1136
Kojto	90:cb3d968589d8	1137	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
Kojto	90:cb3d968589d8	1138
Kojto	90:cb3d968589d8	1139	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto	90:cb3d968589d8	1140
Kojto	90:cb3d968589d8	1141	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1142	/* STM32F072xB \|\| STM32F078xx */
Kojto	90:cb3d968589d8	1143
Kojto	90:cb3d968589d8	1144	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
Kojto	90:cb3d968589d8	1145	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1146
Kojto	90:cb3d968589d8	1147	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
Kojto	90:cb3d968589d8	1148
Kojto	90:cb3d968589d8	1149	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
Kojto	90:cb3d968589d8	1150
Kojto	90:cb3d968589d8	1151	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
Kojto	90:cb3d968589d8	1152	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1153
Kojto	90:cb3d968589d8	1154	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1155	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1156	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1157
Kojto	90:cb3d968589d8	1158	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
Kojto	90:cb3d968589d8	1159
Kojto	90:cb3d968589d8	1160	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
Kojto	90:cb3d968589d8	1161
Kojto	90:cb3d968589d8	1162	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1163	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1164	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1165
Kojto	90:cb3d968589d8	1166	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1167
Kojto	90:cb3d968589d8	1168	#define __USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
Kojto	90:cb3d968589d8	1169
Kojto	90:cb3d968589d8	1170	#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
Kojto	90:cb3d968589d8	1171
Kojto	90:cb3d968589d8	1172	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1173
Kojto	90:cb3d968589d8	1174
Kojto	90:cb3d968589d8	1175	/** @brief Force or release APB2 peripheral reset.
Kojto	90:cb3d968589d8	1176	*/
Kojto	90:cb3d968589d8	1177	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1178	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1179	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1180	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1181
Kojto	90:cb3d968589d8	1182	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
Kojto	90:cb3d968589d8	1183
Kojto	90:cb3d968589d8	1184	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto	90:cb3d968589d8	1185
Kojto	90:cb3d968589d8	1186	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1187	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1188	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1189	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1190
Kojto	90:cb3d968589d8	1191	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1192
Kojto	90:cb3d968589d8	1193	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	90:cb3d968589d8	1194	#define __USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
Kojto	90:cb3d968589d8	1195	#define __USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
Kojto	90:cb3d968589d8	1196
Kojto	90:cb3d968589d8	1197	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	90:cb3d968589d8	1198	#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
Kojto	90:cb3d968589d8	1199	#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
Kojto	90:cb3d968589d8	1200
Kojto	90:cb3d968589d8	1201	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1202
Kojto	90:cb3d968589d8	1203	/**
Kojto	90:cb3d968589d8	1204	* @}
Kojto	90:cb3d968589d8	1205	*/
Kojto	90:cb3d968589d8	1206
Kojto	90:cb3d968589d8	1207	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
Kojto	90:cb3d968589d8	1208	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
Kojto	90:cb3d968589d8	1209	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	1210	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
Kojto	90:cb3d968589d8	1211	* you have to select another source of the system clock then stop the HSI14.
Kojto	90:cb3d968589d8	1212	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
Kojto	90:cb3d968589d8	1213	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
Kojto	90:cb3d968589d8	1214	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
Kojto	90:cb3d968589d8	1215	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
Kojto	90:cb3d968589d8	1216	* clock cycles.
Kojto	90:cb3d968589d8	1217	* @{
Kojto	90:cb3d968589d8	1218	*/
Kojto	90:cb3d968589d8	1219	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1220	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1221	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1222
Kojto	90:cb3d968589d8	1223	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto	90:cb3d968589d8	1224	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto	90:cb3d968589d8	1225
Kojto	90:cb3d968589d8	1226	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto	90:cb3d968589d8	1227	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	1228	* @arg RCC_HSI48_ON: HSI48 enabled
Kojto	90:cb3d968589d8	1229	* @arg RCC_HSI48_OFF: HSI48 disabled
Kojto	90:cb3d968589d8	1230	*/
Kojto	90:cb3d968589d8	1231	#define __HAL_RCC_GET_HSI48_STATE() \
Kojto	90:cb3d968589d8	1232	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
Kojto	90:cb3d968589d8	1233
Kojto	90:cb3d968589d8	1234	#else
Kojto	90:cb3d968589d8	1235
Kojto	90:cb3d968589d8	1236	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto	90:cb3d968589d8	1237	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	1238	* @arg RCC_HSI_OFF: HSI48 disabled
Kojto	90:cb3d968589d8	1239	*/
Kojto	90:cb3d968589d8	1240	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
Kojto	90:cb3d968589d8	1241
Kojto	90:cb3d968589d8	1242	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1243	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1244	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1245
Kojto	90:cb3d968589d8	1246	/**
Kojto	90:cb3d968589d8	1247	* @}
Kojto	90:cb3d968589d8	1248	*/
Kojto	90:cb3d968589d8	1249
Kojto	90:cb3d968589d8	1250	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
Kojto	90:cb3d968589d8	1251	* @{
Kojto	90:cb3d968589d8	1252	*/
Kojto	90:cb3d968589d8	1253	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1254	defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	90:cb3d968589d8	1255
Kojto	90:cb3d968589d8	1256	/** @brief Macro to configure the USB clock (USBCLK).
Kojto	90:cb3d968589d8	1257	* @param __USBCLKSource__: specifies the USB clock source.
Kojto	90:cb3d968589d8	1258	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1259	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
Kojto	90:cb3d968589d8	1260	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto	90:cb3d968589d8	1261	*/
Kojto	90:cb3d968589d8	1262	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto	90:cb3d968589d8	1263	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
Kojto	90:cb3d968589d8	1264
Kojto	90:cb3d968589d8	1265	/** @brief Macro to get the USB clock source.
Kojto	90:cb3d968589d8	1266	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	1267	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
Kojto	90:cb3d968589d8	1268	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto	90:cb3d968589d8	1269	*/
Kojto	90:cb3d968589d8	1270	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
Kojto	90:cb3d968589d8	1271
Kojto	90:cb3d968589d8	1272	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1273	/* STM32F072xB \|\| STM32F078xx */
Kojto	90:cb3d968589d8	1274
Kojto	90:cb3d968589d8	1275	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1276	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	90:cb3d968589d8	1277	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1278	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1279
Kojto	90:cb3d968589d8	1280	/** @brief Macro to configure the CEC clock.
Kojto	90:cb3d968589d8	1281	* @param __CECCLKSource__: specifies the CEC clock source.
Kojto	90:cb3d968589d8	1282	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1283	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	90:cb3d968589d8	1284	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	90:cb3d968589d8	1285	*/
Kojto	90:cb3d968589d8	1286	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
Kojto	90:cb3d968589d8	1287	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Kojto	90:cb3d968589d8	1288
Kojto	90:cb3d968589d8	1289	/** @brief Macro to get the HDMI CEC clock source.
Kojto	90:cb3d968589d8	1290	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	1291	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	90:cb3d968589d8	1292	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	90:cb3d968589d8	1293	*/
Kojto	90:cb3d968589d8	1294	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Kojto	90:cb3d968589d8	1295
Kojto	90:cb3d968589d8	1296	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1297	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	90:cb3d968589d8	1298	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1299	/* STM32F091xC \|\| defined(STM32F098xx) */
Kojto	90:cb3d968589d8	1300
Kojto	90:cb3d968589d8	1301	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
Kojto	90:cb3d968589d8	1302	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1303	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1304	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1305
Kojto	90:cb3d968589d8	1306	/** @brief Macro to configure the MCO clock.
Kojto	90:cb3d968589d8	1307	* @param __MCOCLKSource__: specifies the MCO clock source.
Kojto	90:cb3d968589d8	1308	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1309	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto	90:cb3d968589d8	1310	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto	90:cb3d968589d8	1311	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto	90:cb3d968589d8	1312	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto	90:cb3d968589d8	1313	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
Kojto	90:cb3d968589d8	1314	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto	90:cb3d968589d8	1315	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto	90:cb3d968589d8	1316	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto	90:cb3d968589d8	1317	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto	90:cb3d968589d8	1318	* @param __MCODiv__: specifies the MCO clock prescaler.
Kojto	90:cb3d968589d8	1319	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1320	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
Kojto	90:cb3d968589d8	1321	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
Kojto	90:cb3d968589d8	1322	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
Kojto	90:cb3d968589d8	1323	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
Kojto	90:cb3d968589d8	1324	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
Kojto	90:cb3d968589d8	1325	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
Kojto	90:cb3d968589d8	1326	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
Kojto	90:cb3d968589d8	1327	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
Kojto	90:cb3d968589d8	1328	*/
Kojto	90:cb3d968589d8	1329	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	90:cb3d968589d8	1330	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
Kojto	90:cb3d968589d8	1331	#else
Kojto	90:cb3d968589d8	1332
Kojto	90:cb3d968589d8	1333	/** @brief Macro to configure the MCO clock.
Kojto	90:cb3d968589d8	1334	* @param __MCOCLKSource__: specifies the MCO clock source.
Kojto	90:cb3d968589d8	1335	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1336	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto	90:cb3d968589d8	1337	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto	90:cb3d968589d8	1338	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto	90:cb3d968589d8	1339	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto	90:cb3d968589d8	1340	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto	90:cb3d968589d8	1341	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto	90:cb3d968589d8	1342	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto	90:cb3d968589d8	1343	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto	90:cb3d968589d8	1344	* @param __MCODiv__: specifies the MCO clock prescaler.
Kojto	90:cb3d968589d8	1345	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1346	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
Kojto	90:cb3d968589d8	1347	*/
Kojto	90:cb3d968589d8	1348	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	90:cb3d968589d8	1349	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
Kojto	90:cb3d968589d8	1350
Kojto	90:cb3d968589d8	1351	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	90:cb3d968589d8	1352	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1353	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1354	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1355
Kojto	90:cb3d968589d8	1356	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1357	/** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto	90:cb3d968589d8	1358	* @param __USART3CLKSource__: specifies the USART3 clock source.
Kojto	90:cb3d968589d8	1359	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1360	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	90:cb3d968589d8	1361	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	90:cb3d968589d8	1362	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	90:cb3d968589d8	1363	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	90:cb3d968589d8	1364	*/
Kojto	90:cb3d968589d8	1365	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
Kojto	90:cb3d968589d8	1366	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
Kojto	90:cb3d968589d8	1367
Kojto	90:cb3d968589d8	1368	/** @brief Macro to get the USART3 clock source.
Kojto	90:cb3d968589d8	1369	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	1370	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	90:cb3d968589d8	1371	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	90:cb3d968589d8	1372	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	90:cb3d968589d8	1373	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	90:cb3d968589d8	1374	*/
Kojto	90:cb3d968589d8	1375	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Kojto	90:cb3d968589d8	1376
Kojto	90:cb3d968589d8	1377	#endif /STM32F091xC \|\| STM32F098xx/
Kojto	90:cb3d968589d8	1378	/**
Kojto	90:cb3d968589d8	1379	* @}
Kojto	90:cb3d968589d8	1380	*/
Kojto	90:cb3d968589d8	1381
Kojto	90:cb3d968589d8	1382	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1383	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1384	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1385
Kojto	90:cb3d968589d8	1386	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
Kojto	90:cb3d968589d8	1387	* @{
Kojto	90:cb3d968589d8	1388	*/
Kojto	90:cb3d968589d8	1389	/* Interrupt & Flag management */
Kojto	90:cb3d968589d8	1390
Kojto	90:cb3d968589d8	1391	/**
Kojto	90:cb3d968589d8	1392	* @brief Enables the specified CRS interrupts.
Kojto	90:cb3d968589d8	1393	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
Kojto	90:cb3d968589d8	1394	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1395	* @arg RCC_CRS_IT_SYNCOK
Kojto	90:cb3d968589d8	1396	* @arg RCC_CRS_IT_SYNCWARN
Kojto	90:cb3d968589d8	1397	* @arg RCC_CRS_IT_ERR
Kojto	90:cb3d968589d8	1398	* @arg RCC_CRS_IT_ESYNC
Kojto	90:cb3d968589d8	1399	* @retval None
Kojto	90:cb3d968589d8	1400	*/
Kojto	90:cb3d968589d8	1401	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
Kojto	90:cb3d968589d8	1402
Kojto	90:cb3d968589d8	1403	/**
Kojto	90:cb3d968589d8	1404	* @brief Disables the specified CRS interrupts.
Kojto	90:cb3d968589d8	1405	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
Kojto	90:cb3d968589d8	1406	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1407	* @arg RCC_CRS_IT_SYNCOK
Kojto	90:cb3d968589d8	1408	* @arg RCC_CRS_IT_SYNCWARN
Kojto	90:cb3d968589d8	1409	* @arg RCC_CRS_IT_ERR
Kojto	90:cb3d968589d8	1410	* @arg RCC_CRS_IT_ESYNC
Kojto	90:cb3d968589d8	1411	* @retval None
Kojto	90:cb3d968589d8	1412	*/
Kojto	90:cb3d968589d8	1413	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
Kojto	90:cb3d968589d8	1414
Kojto	90:cb3d968589d8	1415	/** @brief Check the CRS's interrupt has occurred or not.
Kojto	90:cb3d968589d8	1416	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
Kojto	90:cb3d968589d8	1417	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1418	* @arg RCC_CRS_IT_SYNCOK
Kojto	90:cb3d968589d8	1419	* @arg RCC_CRS_IT_SYNCWARN
Kojto	90:cb3d968589d8	1420	* @arg RCC_CRS_IT_ERR
Kojto	90:cb3d968589d8	1421	* @arg RCC_CRS_IT_ESYNC
Kojto	90:cb3d968589d8	1422	* @retval The new state of __INTERRUPT__ (SET or RESET).
Kojto	90:cb3d968589d8	1423	*/
Kojto	90:cb3d968589d8	1424	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
Kojto	90:cb3d968589d8	1425
Kojto	90:cb3d968589d8	1426	/** @brief Clear the CRS's interrupt pending bits
Kojto	90:cb3d968589d8	1427	* bits to clear the selected interrupt pending bits.
Kojto	90:cb3d968589d8	1428	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	90:cb3d968589d8	1429	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1430	* @arg RCC_CRS_IT_SYNCOK
Kojto	90:cb3d968589d8	1431	* @arg RCC_CRS_IT_SYNCWARN
Kojto	90:cb3d968589d8	1432	* @arg RCC_CRS_IT_ERR
Kojto	90:cb3d968589d8	1433	* @arg RCC_CRS_IT_ESYNC
Kojto	90:cb3d968589d8	1434	* @arg RCC_CRS_IT_TRIMOVF
Kojto	90:cb3d968589d8	1435	* @arg RCC_CRS_IT_SYNCERR
Kojto	90:cb3d968589d8	1436	* @arg RCC_CRS_IT_SYNCMISS
Kojto	90:cb3d968589d8	1437	*/
Kojto	90:cb3d968589d8	1438	/* CRS IT Error Mask */
Kojto	90:cb3d968589d8	1439	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
Kojto	90:cb3d968589d8	1440
Kojto	90:cb3d968589d8	1441	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
Kojto	90:cb3d968589d8	1442	(CRS->ICR \|= (__INTERRUPT__)))
Kojto	90:cb3d968589d8	1443
Kojto	90:cb3d968589d8	1444	/**
Kojto	90:cb3d968589d8	1445	* @brief Checks whether the specified CRS flag is set or not.
Kojto	90:cb3d968589d8	1446	* @param _FLAG_: specifies the flag to check.
Kojto	90:cb3d968589d8	1447	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1448	* @arg RCC_CRS_FLAG_SYNCOK
Kojto	90:cb3d968589d8	1449	* @arg RCC_CRS_FLAG_SYNCWARN
Kojto	90:cb3d968589d8	1450	* @arg RCC_CRS_FLAG_ERR
Kojto	90:cb3d968589d8	1451	* @arg RCC_CRS_FLAG_ESYNC
Kojto	90:cb3d968589d8	1452	* @arg RCC_CRS_FLAG_TRIMOVF
Kojto	90:cb3d968589d8	1453	* @arg RCC_CRS_FLAG_SYNCERR
Kojto	90:cb3d968589d8	1454	* @arg RCC_CRS_FLAG_SYNCMISS
Kojto	90:cb3d968589d8	1455	* @retval The new state of _FLAG_ (TRUE or FALSE).
Kojto	90:cb3d968589d8	1456	*/
Kojto	90:cb3d968589d8	1457	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
Kojto	90:cb3d968589d8	1458
Kojto	90:cb3d968589d8	1459	/**
Kojto	90:cb3d968589d8	1460	* @brief Clears the CRS specified FLAG.
Kojto	90:cb3d968589d8	1461	* @param _FLAG_: specifies the flag to clear.
Kojto	90:cb3d968589d8	1462	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1463	* @arg RCC_CRS_FLAG_SYNCOK
Kojto	90:cb3d968589d8	1464	* @arg RCC_CRS_FLAG_SYNCWARN
Kojto	90:cb3d968589d8	1465	* @arg RCC_CRS_FLAG_ERR
Kojto	90:cb3d968589d8	1466	* @arg RCC_CRS_FLAG_ESYNC
Kojto	90:cb3d968589d8	1467	* @arg RCC_CRS_FLAG_TRIMOVF
Kojto	90:cb3d968589d8	1468	* @arg RCC_CRS_FLAG_SYNCERR
Kojto	90:cb3d968589d8	1469	* @arg RCC_CRS_FLAG_SYNCMISS
Kojto	90:cb3d968589d8	1470	* @retval None
Kojto	90:cb3d968589d8	1471	*/
Kojto	90:cb3d968589d8	1472
Kojto	90:cb3d968589d8	1473	/* CRS Flag Error Mask */
Kojto	90:cb3d968589d8	1474	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
Kojto	90:cb3d968589d8	1475
Kojto	90:cb3d968589d8	1476	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
Kojto	90:cb3d968589d8	1477	(CRS->ICR \|= (__FLAG__)))
Kojto	90:cb3d968589d8	1478
Kojto	90:cb3d968589d8	1479	/**
Kojto	90:cb3d968589d8	1480	* @}
Kojto	90:cb3d968589d8	1481	*/
Kojto	90:cb3d968589d8	1482
Kojto	90:cb3d968589d8	1483	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
Kojto	90:cb3d968589d8	1484	* @{
Kojto	90:cb3d968589d8	1485	*/
Kojto	90:cb3d968589d8	1486	/**
Kojto	90:cb3d968589d8	1487	* @brief Enables the oscillator clock for frequency error counter.
Kojto	90:cb3d968589d8	1488	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
Kojto	90:cb3d968589d8	1489	* @retval None
Kojto	90:cb3d968589d8	1490	*/
Kojto	90:cb3d968589d8	1491	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
Kojto	90:cb3d968589d8	1492
Kojto	90:cb3d968589d8	1493	/**
Kojto	90:cb3d968589d8	1494	* @brief Disables the oscillator clock for frequency error counter.
Kojto	90:cb3d968589d8	1495	* @retval None
Kojto	90:cb3d968589d8	1496	*/
Kojto	90:cb3d968589d8	1497	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
Kojto	90:cb3d968589d8	1498
Kojto	90:cb3d968589d8	1499	/**
Kojto	90:cb3d968589d8	1500	* @brief Enables the automatic hardware adjustement of TRIM bits.
Kojto	90:cb3d968589d8	1501	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Kojto	90:cb3d968589d8	1502	* @retval None
Kojto	90:cb3d968589d8	1503	*/
Kojto	90:cb3d968589d8	1504	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
Kojto	90:cb3d968589d8	1505
Kojto	90:cb3d968589d8	1506	/**
Kojto	90:cb3d968589d8	1507	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
Kojto	90:cb3d968589d8	1508	* @retval None
Kojto	90:cb3d968589d8	1509	*/
Kojto	90:cb3d968589d8	1510	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
Kojto	90:cb3d968589d8	1511
Kojto	90:cb3d968589d8	1512	/**
Kojto	90:cb3d968589d8	1513	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
Kojto	90:cb3d968589d8	1514	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
Kojto	90:cb3d968589d8	1515	* of the synchronization source after prescaling. It is then decreased by one in order to
Kojto	90:cb3d968589d8	1516	* reach the expected synchronization on the zero value. The formula is the following:
Kojto	90:cb3d968589d8	1517	* RELOAD = (fTARGET / fSYNC) -1
Kojto	90:cb3d968589d8	1518	* @param _FTARGET_ Target frequency (value in Hz)
Kojto	90:cb3d968589d8	1519	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
Kojto	90:cb3d968589d8	1520	* @retval None
Kojto	90:cb3d968589d8	1521	*/
Kojto	90:cb3d968589d8	1522	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
Kojto	90:cb3d968589d8	1523
Kojto	90:cb3d968589d8	1524	/**
Kojto	90:cb3d968589d8	1525	* @}
Kojto	90:cb3d968589d8	1526	*/
Kojto	90:cb3d968589d8	1527
Kojto	90:cb3d968589d8	1528	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1529	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1530	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1531
Kojto	90:cb3d968589d8	1532	/**
Kojto	90:cb3d968589d8	1533	* @}
Kojto	90:cb3d968589d8	1534	*/
Kojto	90:cb3d968589d8	1535
Kojto	90:cb3d968589d8	1536	/* Exported functions --------------------------------------------------------*/
Kojto	90:cb3d968589d8	1537	/** @addtogroup RCCEx_Exported_Functions
Kojto	90:cb3d968589d8	1538	* @{
Kojto	90:cb3d968589d8	1539	*/
Kojto	90:cb3d968589d8	1540
Kojto	90:cb3d968589d8	1541	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	90:cb3d968589d8	1542	* @{
Kojto	90:cb3d968589d8	1543	*/
Kojto	90:cb3d968589d8	1544
Kojto	90:cb3d968589d8	1545	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	90:cb3d968589d8	1546	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	90:cb3d968589d8	1547
Kojto	90:cb3d968589d8	1548	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	90:cb3d968589d8	1549	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	90:cb3d968589d8	1550	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	90:cb3d968589d8	1551	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto	90:cb3d968589d8	1552	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto	90:cb3d968589d8	1553	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto	90:cb3d968589d8	1554	RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto	90:cb3d968589d8	1555	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	90:cb3d968589d8	1556	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	90:cb3d968589d8	1557	/* STM32F091xC \|\| STM32F098xx */
Kojto	90:cb3d968589d8	1558
Kojto	90:cb3d968589d8	1559
Kojto	90:cb3d968589d8	1560	/**
Kojto	90:cb3d968589d8	1561	* @}
Kojto	90:cb3d968589d8	1562	*/
Kojto	90:cb3d968589d8	1563
Kojto	90:cb3d968589d8	1564	/**
Kojto	90:cb3d968589d8	1565	* @}
Kojto	90:cb3d968589d8	1566	*/
Kojto	90:cb3d968589d8	1567
Kojto	90:cb3d968589d8	1568	/**
Kojto	90:cb3d968589d8	1569	* @}
Kojto	90:cb3d968589d8	1570	*/
Kojto	90:cb3d968589d8	1571
Kojto	90:cb3d968589d8	1572	/**
Kojto	90:cb3d968589d8	1573	* @}
Kojto	90:cb3d968589d8	1574	*/
Kojto	90:cb3d968589d8	1575
Kojto	90:cb3d968589d8	1576	#ifdef __cplusplus
Kojto	90:cb3d968589d8	1577	}
Kojto	90:cb3d968589d8	1578	#endif
Kojto	90:cb3d968589d8	1579
Kojto	90:cb3d968589d8	1580	#endif /* __STM32F0xx_HAL_RCC_EX_H */
Kojto	90:cb3d968589d8	1581
Kojto	90:cb3d968589d8	1582	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	31 Mar 2015
Imports:	13
Forks:	0
Commits:	99
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TARGET_NUCLEO_F091RC/stm32f0xx_hal_rcc_ex.h@90:cb3d968589d8, 2014-10-28 (annotated)

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