雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_nor.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_nor.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of NOR HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_NOR_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_NOR_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 92:4fc01daae5a5 48 #include "stm32f4xx_ll_fsmc.h"
bogdanm 92:4fc01daae5a5 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 92:4fc01daae5a5 52 #include "stm32f4xx_ll_fmc.h"
bogdanm 92:4fc01daae5a5 53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 56 * @{
bogdanm 92:4fc01daae5a5 57 */
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /** @addtogroup NOR
bogdanm 92:4fc01daae5a5 60 * @{
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 /* Exported typedef ----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 66 /**
bogdanm 92:4fc01daae5a5 67 * @brief HAL SRAM State structures definition
bogdanm 92:4fc01daae5a5 68 */
bogdanm 92:4fc01daae5a5 69 typedef enum
bogdanm 92:4fc01daae5a5 70 {
bogdanm 92:4fc01daae5a5 71 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 72 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
bogdanm 92:4fc01daae5a5 73 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
bogdanm 92:4fc01daae5a5 74 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
bogdanm 92:4fc01daae5a5 75 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
bogdanm 92:4fc01daae5a5 76 }HAL_NOR_StateTypeDef;
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 /**
bogdanm 92:4fc01daae5a5 79 * @brief FMC NOR Status typedef
bogdanm 92:4fc01daae5a5 80 */
bogdanm 92:4fc01daae5a5 81 typedef enum
bogdanm 92:4fc01daae5a5 82 {
bogdanm 92:4fc01daae5a5 83 NOR_SUCCESS = 0,
bogdanm 92:4fc01daae5a5 84 NOR_ONGOING,
bogdanm 92:4fc01daae5a5 85 NOR_ERROR,
bogdanm 92:4fc01daae5a5 86 NOR_TIMEOUT
bogdanm 92:4fc01daae5a5 87 }NOR_StatusTypedef;
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89 /**
bogdanm 92:4fc01daae5a5 90 * @brief FMC NOR ID typedef
bogdanm 92:4fc01daae5a5 91 */
bogdanm 92:4fc01daae5a5 92 typedef struct
bogdanm 92:4fc01daae5a5 93 {
bogdanm 92:4fc01daae5a5 94 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
bogdanm 92:4fc01daae5a5 95
bogdanm 92:4fc01daae5a5 96 uint16_t Device_Code1;
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 uint16_t Device_Code2;
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100 uint16_t Device_Code3; /*!< Defines the devices' codes used to identify the memory.
bogdanm 92:4fc01daae5a5 101 These codes can be accessed by performing read operations with specific
bogdanm 92:4fc01daae5a5 102 control signals and addresses set.They can also be accessed by issuing
bogdanm 92:4fc01daae5a5 103 an Auto Select command */
bogdanm 92:4fc01daae5a5 104 }NOR_IDTypeDef;
bogdanm 92:4fc01daae5a5 105
bogdanm 92:4fc01daae5a5 106 /**
bogdanm 92:4fc01daae5a5 107 * @brief FMC NOR CFI typedef
bogdanm 92:4fc01daae5a5 108 */
bogdanm 92:4fc01daae5a5 109 typedef struct
bogdanm 92:4fc01daae5a5 110 {
bogdanm 92:4fc01daae5a5 111 /*!< Defines the information stored in the memory's Common flash interface
bogdanm 92:4fc01daae5a5 112 which contains a description of various electrical and timing parameters,
bogdanm 92:4fc01daae5a5 113 density information and functions supported by the memory */
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 uint16_t CFI_1;
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 uint16_t CFI_2;
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 uint16_t CFI_3;
bogdanm 92:4fc01daae5a5 120
bogdanm 92:4fc01daae5a5 121 uint16_t CFI_4;
bogdanm 92:4fc01daae5a5 122 }NOR_CFITypeDef;
bogdanm 92:4fc01daae5a5 123
bogdanm 92:4fc01daae5a5 124 /**
bogdanm 92:4fc01daae5a5 125 * @brief NOR handle Structure definition
bogdanm 92:4fc01daae5a5 126 */
bogdanm 92:4fc01daae5a5 127 typedef struct
bogdanm 92:4fc01daae5a5 128 {
bogdanm 92:4fc01daae5a5 129 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
bogdanm 92:4fc01daae5a5 134
bogdanm 92:4fc01daae5a5 135 HAL_LockTypeDef Lock; /*!< NOR locking object */
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
bogdanm 92:4fc01daae5a5 138
bogdanm 92:4fc01daae5a5 139 }NOR_HandleTypeDef;
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 142 /** @defgroup NOR_Exported_Constants
bogdanm 92:4fc01daae5a5 143 * @{
bogdanm 92:4fc01daae5a5 144 */
bogdanm 92:4fc01daae5a5 145 /* NOR device IDs addresses */
bogdanm 92:4fc01daae5a5 146 #define MC_ADDRESS ((uint16_t)0x0000)
bogdanm 92:4fc01daae5a5 147 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
bogdanm 92:4fc01daae5a5 148 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
bogdanm 92:4fc01daae5a5 149 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 /* NOR CFI IDs addresses */
bogdanm 92:4fc01daae5a5 152 #define CFI1_ADDRESS ((uint16_t)0x61)
bogdanm 92:4fc01daae5a5 153 #define CFI2_ADDRESS ((uint16_t)0x62)
bogdanm 92:4fc01daae5a5 154 #define CFI3_ADDRESS ((uint16_t)0x63)
bogdanm 92:4fc01daae5a5 155 #define CFI4_ADDRESS ((uint16_t)0x64)
bogdanm 92:4fc01daae5a5 156
bogdanm 92:4fc01daae5a5 157 /* NOR operation wait timeout */
bogdanm 92:4fc01daae5a5 158 #define NOR_TMEOUT ((uint16_t)0xFFFF)
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 /* NOR memory data width */
bogdanm 92:4fc01daae5a5 161 #define NOR_MEMORY_8B ((uint8_t)0x0)
bogdanm 92:4fc01daae5a5 162 #define NOR_MEMORY_16B ((uint8_t)0x1)
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 /* NOR memory device read/write start address */
bogdanm 92:4fc01daae5a5 165 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
bogdanm 92:4fc01daae5a5 166 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
bogdanm 92:4fc01daae5a5 167 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
bogdanm 92:4fc01daae5a5 168 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
bogdanm 92:4fc01daae5a5 169
bogdanm 92:4fc01daae5a5 170 /**
bogdanm 92:4fc01daae5a5 171 * @}
bogdanm 92:4fc01daae5a5 172 */
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 175
bogdanm 92:4fc01daae5a5 176 /** @brief Reset NOR handle state
bogdanm 92:4fc01daae5a5 177 * @param __HANDLE__: specifies the NOR handle.
bogdanm 92:4fc01daae5a5 178 * @retval None
bogdanm 92:4fc01daae5a5 179 */
bogdanm 92:4fc01daae5a5 180 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 /**
bogdanm 92:4fc01daae5a5 183 * @brief NOR memory address shifting.
bogdanm 92:4fc01daae5a5 184 * @param __ADDRESS__: NOR memory address
bogdanm 92:4fc01daae5a5 185 * @retval NOR shifted address value
bogdanm 92:4fc01daae5a5 186 */
bogdanm 92:4fc01daae5a5 187 #define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) (((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):\
bogdanm 92:4fc01daae5a5 188 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))
bogdanm 92:4fc01daae5a5 189
bogdanm 92:4fc01daae5a5 190 /**
bogdanm 92:4fc01daae5a5 191 * @brief NOR memory write data to specified address.
bogdanm 92:4fc01daae5a5 192 * @param __ADDRESS__: NOR memory address
bogdanm 92:4fc01daae5a5 193 * @param __DATA__: Data to write
bogdanm 92:4fc01daae5a5 194 * @retval None
bogdanm 92:4fc01daae5a5 195 */
bogdanm 92:4fc01daae5a5 196 #define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 199
bogdanm 92:4fc01daae5a5 200 /* Initialization/de-initialization functions ********************************/
bogdanm 92:4fc01daae5a5 201 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
bogdanm 92:4fc01daae5a5 202 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
bogdanm 92:4fc01daae5a5 203 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
bogdanm 92:4fc01daae5a5 204 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
bogdanm 92:4fc01daae5a5 205 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 206
bogdanm 92:4fc01daae5a5 207 /* I/O operation functions ***************************************************/
bogdanm 92:4fc01daae5a5 208 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
bogdanm 92:4fc01daae5a5 209 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
bogdanm 92:4fc01daae5a5 210 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
bogdanm 92:4fc01daae5a5 211 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
bogdanm 92:4fc01daae5a5 212
bogdanm 92:4fc01daae5a5 213 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
bogdanm 92:4fc01daae5a5 214 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
bogdanm 92:4fc01daae5a5 215
bogdanm 92:4fc01daae5a5 216 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
bogdanm 92:4fc01daae5a5 217 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
bogdanm 92:4fc01daae5a5 218 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
bogdanm 92:4fc01daae5a5 219
bogdanm 92:4fc01daae5a5 220 /* NOR Control functions *****************************************************/
bogdanm 92:4fc01daae5a5 221 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
bogdanm 92:4fc01daae5a5 222 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
bogdanm 92:4fc01daae5a5 223
bogdanm 92:4fc01daae5a5 224 /* NOR State functions ********************************************************/
bogdanm 92:4fc01daae5a5 225 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
bogdanm 92:4fc01daae5a5 226 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 227
bogdanm 92:4fc01daae5a5 228 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 92:4fc01daae5a5 229 /**
bogdanm 92:4fc01daae5a5 230 * @}
bogdanm 92:4fc01daae5a5 231 */
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233 /**
bogdanm 92:4fc01daae5a5 234 * @}
bogdanm 92:4fc01daae5a5 235 */
bogdanm 92:4fc01daae5a5 236
bogdanm 92:4fc01daae5a5 237 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 238 }
bogdanm 92:4fc01daae5a5 239 #endif
bogdanm 92:4fc01daae5a5 240
bogdanm 92:4fc01daae5a5 241 #endif /* __STM32F4xx_HAL_NOR_H */
bogdanm 92:4fc01daae5a5 242
bogdanm 92:4fc01daae5a5 243 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/