mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Parent:
89:552587b429a1
Release 92 of the mbed libray

Main changes:

- nRF51822: fixed pin assignment issues
- ST targets moving to the STM32Cube driver
- LPC1439: fixed serial interrupt issue
- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_tim.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief Header file of TIM HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_TIM_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_TIM_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup TIM
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58
bogdanm 89:552587b429a1 59 /**
bogdanm 89:552587b429a1 60 * @brief TIM Time base Configuration Structure definition
bogdanm 89:552587b429a1 61 */
bogdanm 89:552587b429a1 62 typedef struct
bogdanm 89:552587b429a1 63 {
bogdanm 89:552587b429a1 64 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm 89:552587b429a1 65 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 89:552587b429a1 66
bogdanm 89:552587b429a1 67 uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm 89:552587b429a1 68 This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm 89:552587b429a1 69
bogdanm 89:552587b429a1 70 uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm 89:552587b429a1 71 Auto-Reload Register at the next update event.
bogdanm 89:552587b429a1 72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm 89:552587b429a1 73
bogdanm 89:552587b429a1 74 uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm 89:552587b429a1 75 This parameter can be a value of @ref TIM_ClockDivision */
bogdanm 89:552587b429a1 76
bogdanm 89:552587b429a1 77 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm 89:552587b429a1 78 reaches zero, an update event is generated and counting restarts
bogdanm 89:552587b429a1 79 from the RCR value (N).
bogdanm 89:552587b429a1 80 This means in PWM mode that (N+1) corresponds to:
bogdanm 89:552587b429a1 81 - the number of PWM periods in edge-aligned mode
bogdanm 89:552587b429a1 82 - the number of half PWM period in center-aligned mode
bogdanm 89:552587b429a1 83 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm 89:552587b429a1 84 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 89:552587b429a1 85 } TIM_Base_InitTypeDef;
bogdanm 89:552587b429a1 86
bogdanm 89:552587b429a1 87 /**
bogdanm 89:552587b429a1 88 * @brief TIM Output Compare Configuration Structure definition
bogdanm 89:552587b429a1 89 */
bogdanm 89:552587b429a1 90
bogdanm 89:552587b429a1 91 typedef struct
bogdanm 89:552587b429a1 92 {
bogdanm 89:552587b429a1 93 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 89:552587b429a1 94 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 89:552587b429a1 95
bogdanm 89:552587b429a1 96 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 89:552587b429a1 97 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 89:552587b429a1 98
bogdanm 89:552587b429a1 99 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 89:552587b429a1 100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 89:552587b429a1 101
bogdanm 89:552587b429a1 102 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 89:552587b429a1 103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 89:552587b429a1 104 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm 89:552587b429a1 107 This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm 89:552587b429a1 108 @note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm 89:552587b429a1 109
bogdanm 89:552587b429a1 110
bogdanm 89:552587b429a1 111 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 89:552587b429a1 112 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 89:552587b429a1 113 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 89:552587b429a1 114
bogdanm 89:552587b429a1 115 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 89:552587b429a1 116 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 89:552587b429a1 117 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 89:552587b429a1 118 } TIM_OC_InitTypeDef;
bogdanm 89:552587b429a1 119
bogdanm 89:552587b429a1 120 /**
bogdanm 89:552587b429a1 121 * @brief TIM One Pulse Mode Configuration Structure definition
bogdanm 89:552587b429a1 122 */
bogdanm 89:552587b429a1 123 typedef struct
bogdanm 89:552587b429a1 124 {
bogdanm 89:552587b429a1 125 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 89:552587b429a1 126 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 89:552587b429a1 127
bogdanm 89:552587b429a1 128 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 89:552587b429a1 129 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 89:552587b429a1 130
bogdanm 89:552587b429a1 131 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 89:552587b429a1 132 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 89:552587b429a1 133
bogdanm 89:552587b429a1 134 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 89:552587b429a1 135 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 89:552587b429a1 136 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 89:552587b429a1 137
bogdanm 89:552587b429a1 138 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 89:552587b429a1 139 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 89:552587b429a1 140 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 89:552587b429a1 141
bogdanm 89:552587b429a1 142 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 89:552587b429a1 143 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 89:552587b429a1 144 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 89:552587b429a1 145
bogdanm 89:552587b429a1 146 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 89:552587b429a1 147 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 89:552587b429a1 148
bogdanm 89:552587b429a1 149 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 89:552587b429a1 150 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 89:552587b429a1 151
bogdanm 89:552587b429a1 152 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 89:552587b429a1 153 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 89:552587b429a1 154 } TIM_OnePulse_InitTypeDef;
bogdanm 89:552587b429a1 155
bogdanm 89:552587b429a1 156
bogdanm 89:552587b429a1 157 /**
bogdanm 89:552587b429a1 158 * @brief TIM Input Capture Configuration Structure definition
bogdanm 89:552587b429a1 159 */
bogdanm 89:552587b429a1 160
bogdanm 89:552587b429a1 161 typedef struct
bogdanm 89:552587b429a1 162 {
bogdanm 89:552587b429a1 163 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 89:552587b429a1 164 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 89:552587b429a1 165
bogdanm 89:552587b429a1 166 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 89:552587b429a1 167 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 89:552587b429a1 168
bogdanm 89:552587b429a1 169 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 89:552587b429a1 170 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 89:552587b429a1 171
bogdanm 89:552587b429a1 172 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 89:552587b429a1 173 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 89:552587b429a1 174 } TIM_IC_InitTypeDef;
bogdanm 89:552587b429a1 175
bogdanm 89:552587b429a1 176 /**
bogdanm 89:552587b429a1 177 * @brief TIM Encoder Configuration Structure definition
bogdanm 89:552587b429a1 178 */
bogdanm 89:552587b429a1 179
bogdanm 89:552587b429a1 180 typedef struct
bogdanm 89:552587b429a1 181 {
bogdanm 89:552587b429a1 182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm 89:552587b429a1 183 This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm 89:552587b429a1 184
bogdanm 89:552587b429a1 185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 89:552587b429a1 186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 89:552587b429a1 187
bogdanm 89:552587b429a1 188 uint32_t IC1Selection; /*!< Specifies the input.
bogdanm 89:552587b429a1 189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 89:552587b429a1 190
bogdanm 89:552587b429a1 191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 89:552587b429a1 192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 89:552587b429a1 193
bogdanm 89:552587b429a1 194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm 89:552587b429a1 195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 89:552587b429a1 196
bogdanm 89:552587b429a1 197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 89:552587b429a1 198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 89:552587b429a1 199
bogdanm 89:552587b429a1 200 uint32_t IC2Selection; /*!< Specifies the input.
bogdanm 89:552587b429a1 201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 89:552587b429a1 202
bogdanm 89:552587b429a1 203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 89:552587b429a1 204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 89:552587b429a1 205
bogdanm 89:552587b429a1 206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm 89:552587b429a1 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 89:552587b429a1 208 } TIM_Encoder_InitTypeDef;
bogdanm 89:552587b429a1 209
bogdanm 89:552587b429a1 210 /**
bogdanm 89:552587b429a1 211 * @brief Clock Configuration Handle Structure definition
bogdanm 89:552587b429a1 212 */
bogdanm 89:552587b429a1 213 typedef struct
bogdanm 89:552587b429a1 214 {
bogdanm 89:552587b429a1 215 uint32_t ClockSource; /*!< TIM clock sources.
bogdanm 89:552587b429a1 216 This parameter can be a value of @ref TIM_Clock_Source */
bogdanm 89:552587b429a1 217 uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm 89:552587b429a1 218 This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm 89:552587b429a1 219 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm 89:552587b429a1 220 This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm 89:552587b429a1 221 uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm 89:552587b429a1 222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 89:552587b429a1 223 }TIM_ClockConfigTypeDef;
bogdanm 89:552587b429a1 224
bogdanm 89:552587b429a1 225 /**
bogdanm 89:552587b429a1 226 * @brief Clear Input Configuration Handle Structure definition
bogdanm 89:552587b429a1 227 */
bogdanm 89:552587b429a1 228 typedef struct
bogdanm 89:552587b429a1 229 {
bogdanm 89:552587b429a1 230 uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm 89:552587b429a1 231 This parameter can be ENABLE or DISABLE */
bogdanm 89:552587b429a1 232 uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm 89:552587b429a1 233 This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm 89:552587b429a1 234 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm 89:552587b429a1 235 This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm 89:552587b429a1 236 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm 89:552587b429a1 237 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm 89:552587b429a1 238 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm 89:552587b429a1 239 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 89:552587b429a1 240 }TIM_ClearInputConfigTypeDef;
bogdanm 89:552587b429a1 241
bogdanm 89:552587b429a1 242 /**
bogdanm 89:552587b429a1 243 * @brief TIM Slave configuration Structure definition
bogdanm 89:552587b429a1 244 */
bogdanm 89:552587b429a1 245 typedef struct {
bogdanm 89:552587b429a1 246 uint32_t SlaveMode; /*!< Slave mode selection
bogdanm 89:552587b429a1 247 This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm 89:552587b429a1 248 uint32_t InputTrigger; /*!< Input Trigger source
bogdanm 89:552587b429a1 249 This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm 89:552587b429a1 250 uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm 89:552587b429a1 251 This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm 89:552587b429a1 252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm 89:552587b429a1 253 This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm 89:552587b429a1 254 uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm 89:552587b429a1 255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 89:552587b429a1 256
bogdanm 89:552587b429a1 257 }TIM_SlaveConfigTypeDef;
bogdanm 89:552587b429a1 258
bogdanm 89:552587b429a1 259 /**
bogdanm 89:552587b429a1 260 * @brief HAL State structures definition
bogdanm 89:552587b429a1 261 */
bogdanm 89:552587b429a1 262 typedef enum
bogdanm 89:552587b429a1 263 {
bogdanm 89:552587b429a1 264 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
bogdanm 89:552587b429a1 265 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 89:552587b429a1 266 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 89:552587b429a1 267 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 89:552587b429a1 268 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
bogdanm 89:552587b429a1 269 }HAL_TIM_StateTypeDef;
bogdanm 89:552587b429a1 270
bogdanm 89:552587b429a1 271 /**
bogdanm 89:552587b429a1 272 * @brief HAL Active channel structures definition
bogdanm 89:552587b429a1 273 */
bogdanm 89:552587b429a1 274 typedef enum
bogdanm 89:552587b429a1 275 {
bogdanm 89:552587b429a1 276 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
bogdanm 89:552587b429a1 277 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
bogdanm 89:552587b429a1 278 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
bogdanm 89:552587b429a1 279 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
bogdanm 89:552587b429a1 280 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
bogdanm 89:552587b429a1 281 }HAL_TIM_ActiveChannel;
bogdanm 89:552587b429a1 282
bogdanm 89:552587b429a1 283 /**
bogdanm 89:552587b429a1 284 * @brief TIM Time Base Handle Structure definition
bogdanm 89:552587b429a1 285 */
bogdanm 89:552587b429a1 286 typedef struct
bogdanm 89:552587b429a1 287 {
bogdanm 89:552587b429a1 288 TIM_TypeDef *Instance; /*!< Register base address */
bogdanm 89:552587b429a1 289 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
bogdanm 89:552587b429a1 290 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
bogdanm 89:552587b429a1 291 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
bogdanm 89:552587b429a1 292 This array is accessed by a @ref DMA_Handle_index */
bogdanm 89:552587b429a1 293 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 89:552587b429a1 294 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
bogdanm 89:552587b429a1 295 }TIM_HandleTypeDef;
bogdanm 89:552587b429a1 296
bogdanm 89:552587b429a1 297 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 298 /** @defgroup TIM_Exported_Constants
bogdanm 89:552587b429a1 299 * @{
bogdanm 89:552587b429a1 300 */
bogdanm 89:552587b429a1 301
bogdanm 89:552587b429a1 302 /** @defgroup TIM_Input_Channel_Polarity
bogdanm 89:552587b429a1 303 * @{
bogdanm 89:552587b429a1 304 */
bogdanm 89:552587b429a1 305 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
bogdanm 89:552587b429a1 306 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
bogdanm 89:552587b429a1 307 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
bogdanm 89:552587b429a1 308 /**
bogdanm 89:552587b429a1 309 * @}
bogdanm 89:552587b429a1 310 */
bogdanm 89:552587b429a1 311
bogdanm 89:552587b429a1 312 /** @defgroup TIM_ETR_Polarity
bogdanm 89:552587b429a1 313 * @{
bogdanm 89:552587b429a1 314 */
bogdanm 89:552587b429a1 315 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
bogdanm 89:552587b429a1 316 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
bogdanm 89:552587b429a1 317 /**
bogdanm 89:552587b429a1 318 * @}
bogdanm 89:552587b429a1 319 */
bogdanm 89:552587b429a1 320
bogdanm 89:552587b429a1 321 /** @defgroup TIM_ETR_Prescaler
bogdanm 89:552587b429a1 322 * @{
bogdanm 89:552587b429a1 323 */
bogdanm 89:552587b429a1 324 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
bogdanm 89:552587b429a1 325 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
bogdanm 89:552587b429a1 326 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
bogdanm 89:552587b429a1 327 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
bogdanm 89:552587b429a1 328 /**
bogdanm 89:552587b429a1 329 * @}
bogdanm 89:552587b429a1 330 */
bogdanm 89:552587b429a1 331
bogdanm 89:552587b429a1 332 /** @defgroup TIM_Counter_Mode
bogdanm 89:552587b429a1 333 * @{
bogdanm 89:552587b429a1 334 */
bogdanm 89:552587b429a1 335 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm 89:552587b429a1 336 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm 89:552587b429a1 337 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm 89:552587b429a1 338 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm 89:552587b429a1 339 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm 89:552587b429a1 340
bogdanm 89:552587b429a1 341 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
bogdanm 89:552587b429a1 342 ((MODE) == TIM_COUNTERMODE_DOWN) || \
bogdanm 89:552587b429a1 343 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
bogdanm 89:552587b429a1 344 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
bogdanm 89:552587b429a1 345 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm 89:552587b429a1 346 /**
bogdanm 89:552587b429a1 347 * @}
bogdanm 89:552587b429a1 348 */
bogdanm 89:552587b429a1 349
bogdanm 89:552587b429a1 350 /** @defgroup TIM_ClockDivision
bogdanm 89:552587b429a1 351 * @{
bogdanm 89:552587b429a1 352 */
bogdanm 89:552587b429a1 353 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm 89:552587b429a1 354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm 89:552587b429a1 355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm 89:552587b429a1 356
bogdanm 89:552587b429a1 357 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
bogdanm 89:552587b429a1 358 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
bogdanm 89:552587b429a1 359 ((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm 89:552587b429a1 360 /**
bogdanm 89:552587b429a1 361 * @}
bogdanm 89:552587b429a1 362 */
bogdanm 89:552587b429a1 363
bogdanm 89:552587b429a1 364 /** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm 89:552587b429a1 365 * @{
bogdanm 89:552587b429a1 366 */
bogdanm 89:552587b429a1 367 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm 89:552587b429a1 368 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm 89:552587b429a1 369 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm 89:552587b429a1 370 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
bogdanm 89:552587b429a1 371 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
bogdanm 89:552587b429a1 372 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm 89:552587b429a1 373 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
bogdanm 89:552587b429a1 374 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm 89:552587b429a1 375
bogdanm 89:552587b429a1 376 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
bogdanm 89:552587b429a1 377 ((MODE) == TIM_OCMODE_PWM2))
bogdanm 89:552587b429a1 378
bogdanm 89:552587b429a1 379 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
bogdanm 89:552587b429a1 380 ((MODE) == TIM_OCMODE_ACTIVE) || \
bogdanm 89:552587b429a1 381 ((MODE) == TIM_OCMODE_INACTIVE) || \
bogdanm 89:552587b429a1 382 ((MODE) == TIM_OCMODE_TOGGLE) || \
bogdanm 89:552587b429a1 383 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
bogdanm 89:552587b429a1 384 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm 89:552587b429a1 385 /**
bogdanm 89:552587b429a1 386 * @}
bogdanm 89:552587b429a1 387 */
bogdanm 89:552587b429a1 388
bogdanm 89:552587b429a1 389 /** @defgroup TIM_Output_Compare_State
bogdanm 89:552587b429a1 390 * @{
bogdanm 89:552587b429a1 391 */
bogdanm 89:552587b429a1 392 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 393 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm 89:552587b429a1 394
bogdanm 89:552587b429a1 395 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
bogdanm 89:552587b429a1 396 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm 89:552587b429a1 397 /**
bogdanm 89:552587b429a1 398 * @}
bogdanm 89:552587b429a1 399 */
bogdanm 89:552587b429a1 400
bogdanm 89:552587b429a1 401 /** @defgroup TIM_Output_Fast_State
bogdanm 89:552587b429a1 402 * @{
bogdanm 89:552587b429a1 403 */
bogdanm 89:552587b429a1 404 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 405 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm 89:552587b429a1 406
bogdanm 89:552587b429a1 407 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
bogdanm 89:552587b429a1 408 ((STATE) == TIM_OCFAST_ENABLE))
bogdanm 89:552587b429a1 409 /**
bogdanm 89:552587b429a1 410 * @}
bogdanm 89:552587b429a1 411 */
bogdanm 89:552587b429a1 412
bogdanm 89:552587b429a1 413 /** @defgroup TIM_Output_Compare_N_State
bogdanm 89:552587b429a1 414 * @{
bogdanm 89:552587b429a1 415 */
bogdanm 89:552587b429a1 416 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 417 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm 89:552587b429a1 418
bogdanm 89:552587b429a1 419 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
bogdanm 89:552587b429a1 420 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm 89:552587b429a1 421 /**
bogdanm 89:552587b429a1 422 * @}
bogdanm 89:552587b429a1 423 */
bogdanm 89:552587b429a1 424
bogdanm 89:552587b429a1 425 /** @defgroup TIM_Output_Compare_Polarity
bogdanm 89:552587b429a1 426 * @{
bogdanm 89:552587b429a1 427 */
bogdanm 89:552587b429a1 428 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 89:552587b429a1 429 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm 89:552587b429a1 430
bogdanm 89:552587b429a1 431 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
bogdanm 89:552587b429a1 432 ((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm 89:552587b429a1 433 /**
bogdanm 89:552587b429a1 434 * @}
bogdanm 89:552587b429a1 435 */
bogdanm 89:552587b429a1 436
bogdanm 89:552587b429a1 437 /** @defgroup TIM_Output_Compare_N_Polarity
bogdanm 89:552587b429a1 438 * @{
bogdanm 89:552587b429a1 439 */
bogdanm 89:552587b429a1 440 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 89:552587b429a1 441 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm 89:552587b429a1 442
bogdanm 89:552587b429a1 443 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
bogdanm 89:552587b429a1 444 ((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm 89:552587b429a1 445 /**
bogdanm 89:552587b429a1 446 * @}
bogdanm 89:552587b429a1 447 */
bogdanm 89:552587b429a1 448
bogdanm 89:552587b429a1 449 /** @defgroup TIM_Output_Compare_Idle_State
bogdanm 89:552587b429a1 450 * @{
bogdanm 89:552587b429a1 451 */
bogdanm 89:552587b429a1 452 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm 89:552587b429a1 453 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 89:552587b429a1 454 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
bogdanm 89:552587b429a1 455 ((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm 89:552587b429a1 456 /**
bogdanm 89:552587b429a1 457 * @}
bogdanm 89:552587b429a1 458 */
bogdanm 89:552587b429a1 459
bogdanm 89:552587b429a1 460 /** @defgroup TIM_Output_Compare_N_Idle_State
bogdanm 89:552587b429a1 461 * @{
bogdanm 89:552587b429a1 462 */
bogdanm 89:552587b429a1 463 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm 89:552587b429a1 464 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 89:552587b429a1 465 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
bogdanm 89:552587b429a1 466 ((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm 89:552587b429a1 467 /**
bogdanm 89:552587b429a1 468 * @}
bogdanm 89:552587b429a1 469 */
bogdanm 89:552587b429a1 470
bogdanm 89:552587b429a1 471 /** @defgroup TIM_Channel
bogdanm 89:552587b429a1 472 * @{
bogdanm 89:552587b429a1 473 */
bogdanm 89:552587b429a1 474 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm 89:552587b429a1 475 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm 89:552587b429a1 476 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm 89:552587b429a1 477 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm 89:552587b429a1 478 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm 89:552587b429a1 479
bogdanm 89:552587b429a1 480 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 481 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 482 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 89:552587b429a1 483 ((CHANNEL) == TIM_CHANNEL_4) || \
bogdanm 89:552587b429a1 484 ((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm 89:552587b429a1 485
bogdanm 89:552587b429a1 486 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 487 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 89:552587b429a1 488
bogdanm 89:552587b429a1 489 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 490 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 89:552587b429a1 491
bogdanm 89:552587b429a1 492 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 89:552587b429a1 493 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 89:552587b429a1 494 ((CHANNEL) == TIM_CHANNEL_3))
bogdanm 89:552587b429a1 495 /**
bogdanm 89:552587b429a1 496 * @}
bogdanm 89:552587b429a1 497 */
bogdanm 89:552587b429a1 498
bogdanm 89:552587b429a1 499 /** @defgroup TIM_Input_Capture_Polarity
bogdanm 89:552587b429a1 500 * @{
bogdanm 89:552587b429a1 501 */
bogdanm 89:552587b429a1 502 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm 89:552587b429a1 503 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm 89:552587b429a1 504 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm 89:552587b429a1 505
bogdanm 89:552587b429a1 506 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
bogdanm 89:552587b429a1 507 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
bogdanm 89:552587b429a1 508 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm 89:552587b429a1 509 /**
bogdanm 89:552587b429a1 510 * @}
bogdanm 89:552587b429a1 511 */
bogdanm 89:552587b429a1 512
bogdanm 89:552587b429a1 513 /** @defgroup TIM_Input_Capture_Selection
bogdanm 89:552587b429a1 514 * @{
bogdanm 89:552587b429a1 515 */
bogdanm 89:552587b429a1 516 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 89:552587b429a1 517 connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm 89:552587b429a1 518 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 89:552587b429a1 519 connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm 89:552587b429a1 520 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
bogdanm 89:552587b429a1 521
bogdanm 89:552587b429a1 522 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
bogdanm 89:552587b429a1 523 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
bogdanm 89:552587b429a1 524 ((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm 89:552587b429a1 525 /**
bogdanm 89:552587b429a1 526 * @}
bogdanm 89:552587b429a1 527 */
bogdanm 89:552587b429a1 528
bogdanm 89:552587b429a1 529 /** @defgroup TIM_Input_Capture_Prescaler
bogdanm 89:552587b429a1 530 * @{
bogdanm 89:552587b429a1 531 */
bogdanm 89:552587b429a1 532 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
bogdanm 89:552587b429a1 533 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
bogdanm 89:552587b429a1 534 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
bogdanm 89:552587b429a1 535 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
bogdanm 89:552587b429a1 536
bogdanm 89:552587b429a1 537 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
bogdanm 89:552587b429a1 538 ((PRESCALER) == TIM_ICPSC_DIV2) || \
bogdanm 89:552587b429a1 539 ((PRESCALER) == TIM_ICPSC_DIV4) || \
bogdanm 89:552587b429a1 540 ((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm 89:552587b429a1 541 /**
bogdanm 89:552587b429a1 542 * @}
bogdanm 89:552587b429a1 543 */
bogdanm 89:552587b429a1 544
bogdanm 89:552587b429a1 545 /** @defgroup TIM_One_Pulse_Mode
bogdanm 89:552587b429a1 546 * @{
bogdanm 89:552587b429a1 547 */
bogdanm 89:552587b429a1 548 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm 89:552587b429a1 549 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 550 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
bogdanm 89:552587b429a1 551 ((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm 89:552587b429a1 552 /**
bogdanm 89:552587b429a1 553 * @}
bogdanm 89:552587b429a1 554 */
bogdanm 89:552587b429a1 555
bogdanm 89:552587b429a1 556 /** @defgroup TIM_Encoder_Mode
bogdanm 89:552587b429a1 557 * @{
bogdanm 89:552587b429a1 558 */
bogdanm 89:552587b429a1 559 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm 89:552587b429a1 560 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm 89:552587b429a1 561 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
bogdanm 89:552587b429a1 562 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
bogdanm 89:552587b429a1 563 ((MODE) == TIM_ENCODERMODE_TI2) || \
bogdanm 89:552587b429a1 564 ((MODE) == TIM_ENCODERMODE_TI12))
bogdanm 89:552587b429a1 565 /**
bogdanm 89:552587b429a1 566 * @}
bogdanm 89:552587b429a1 567 */
bogdanm 89:552587b429a1 568
bogdanm 89:552587b429a1 569 /** @defgroup TIM_Interrupt_definition
bogdanm 89:552587b429a1 570 * @{
bogdanm 89:552587b429a1 571 */
bogdanm 89:552587b429a1 572 #define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm 89:552587b429a1 573 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm 89:552587b429a1 574 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm 89:552587b429a1 575 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm 89:552587b429a1 576 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm 89:552587b429a1 577 #define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm 89:552587b429a1 578 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm 89:552587b429a1 579 #define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm 89:552587b429a1 580
bogdanm 89:552587b429a1 581 #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 89:552587b429a1 582
bogdanm 89:552587b429a1 583 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
bogdanm 89:552587b429a1 584 ((IT) == TIM_IT_CC1) || \
bogdanm 89:552587b429a1 585 ((IT) == TIM_IT_CC2) || \
bogdanm 89:552587b429a1 586 ((IT) == TIM_IT_CC3) || \
bogdanm 89:552587b429a1 587 ((IT) == TIM_IT_CC4) || \
bogdanm 89:552587b429a1 588 ((IT) == TIM_IT_COM) || \
bogdanm 89:552587b429a1 589 ((IT) == TIM_IT_TRIGGER) || \
bogdanm 89:552587b429a1 590 ((IT) == TIM_IT_BREAK))
bogdanm 89:552587b429a1 591 /**
bogdanm 89:552587b429a1 592 * @}
bogdanm 89:552587b429a1 593 */
bogdanm 92:4fc01daae5a5 594 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm 92:4fc01daae5a5 595 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 596
bogdanm 89:552587b429a1 597 /** @defgroup TIM_DMA_sources
bogdanm 89:552587b429a1 598 * @{
bogdanm 89:552587b429a1 599 */
bogdanm 89:552587b429a1 600 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm 89:552587b429a1 601 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm 89:552587b429a1 602 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm 89:552587b429a1 603 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm 89:552587b429a1 604 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm 89:552587b429a1 605 #define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm 89:552587b429a1 606 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm 89:552587b429a1 607 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 89:552587b429a1 608 /**
bogdanm 89:552587b429a1 609 * @}
bogdanm 89:552587b429a1 610 */
bogdanm 89:552587b429a1 611
bogdanm 89:552587b429a1 612 /** @defgroup TIM_Event_Source
bogdanm 89:552587b429a1 613 * @{
bogdanm 89:552587b429a1 614 */
bogdanm 89:552587b429a1 615 #define TIM_EventSource_Update TIM_EGR_UG
bogdanm 89:552587b429a1 616 #define TIM_EventSource_CC1 TIM_EGR_CC1G
bogdanm 89:552587b429a1 617 #define TIM_EventSource_CC2 TIM_EGR_CC2G
bogdanm 89:552587b429a1 618 #define TIM_EventSource_CC3 TIM_EGR_CC3G
bogdanm 89:552587b429a1 619 #define TIM_EventSource_CC4 TIM_EGR_CC4G
bogdanm 89:552587b429a1 620 #define TIM_EventSource_COM TIM_EGR_COMG
bogdanm 89:552587b429a1 621 #define TIM_EventSource_Trigger TIM_EGR_TG
bogdanm 89:552587b429a1 622 #define TIM_EventSource_Break TIM_EGR_BG
bogdanm 89:552587b429a1 623 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 89:552587b429a1 624 /**
bogdanm 89:552587b429a1 625 * @}
bogdanm 89:552587b429a1 626 */
bogdanm 89:552587b429a1 627
bogdanm 89:552587b429a1 628 /** @defgroup TIM_Flag_definition
bogdanm 89:552587b429a1 629 * @{
bogdanm 89:552587b429a1 630 */
bogdanm 89:552587b429a1 631 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm 89:552587b429a1 632 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm 89:552587b429a1 633 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm 89:552587b429a1 634 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm 89:552587b429a1 635 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm 89:552587b429a1 636 #define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm 89:552587b429a1 637 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm 89:552587b429a1 638 #define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm 89:552587b429a1 639 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm 89:552587b429a1 640 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm 89:552587b429a1 641 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm 89:552587b429a1 642 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm 89:552587b429a1 643
bogdanm 89:552587b429a1 644 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
bogdanm 89:552587b429a1 645 ((FLAG) == TIM_FLAG_CC1) || \
bogdanm 89:552587b429a1 646 ((FLAG) == TIM_FLAG_CC2) || \
bogdanm 89:552587b429a1 647 ((FLAG) == TIM_FLAG_CC3) || \
bogdanm 89:552587b429a1 648 ((FLAG) == TIM_FLAG_CC4) || \
bogdanm 89:552587b429a1 649 ((FLAG) == TIM_FLAG_COM) || \
bogdanm 89:552587b429a1 650 ((FLAG) == TIM_FLAG_TRIGGER) || \
bogdanm 89:552587b429a1 651 ((FLAG) == TIM_FLAG_BREAK) || \
bogdanm 89:552587b429a1 652 ((FLAG) == TIM_FLAG_CC1OF) || \
bogdanm 89:552587b429a1 653 ((FLAG) == TIM_FLAG_CC2OF) || \
bogdanm 89:552587b429a1 654 ((FLAG) == TIM_FLAG_CC3OF) || \
bogdanm 89:552587b429a1 655 ((FLAG) == TIM_FLAG_CC4OF))
bogdanm 89:552587b429a1 656 /**
bogdanm 89:552587b429a1 657 * @}
bogdanm 89:552587b429a1 658 */
bogdanm 89:552587b429a1 659
bogdanm 89:552587b429a1 660 /** @defgroup TIM_Clock_Source
bogdanm 89:552587b429a1 661 * @{
bogdanm 89:552587b429a1 662 */
bogdanm 89:552587b429a1 663 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm 89:552587b429a1 664 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm 89:552587b429a1 665 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm 89:552587b429a1 666 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm 89:552587b429a1 667 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm 89:552587b429a1 668 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
bogdanm 89:552587b429a1 669 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm 89:552587b429a1 670 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
bogdanm 89:552587b429a1 671 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
bogdanm 89:552587b429a1 672 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm 89:552587b429a1 673
bogdanm 89:552587b429a1 674 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
bogdanm 89:552587b429a1 675 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
bogdanm 89:552587b429a1 676 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
bogdanm 89:552587b429a1 677 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
bogdanm 89:552587b429a1 678 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
bogdanm 89:552587b429a1 679 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
bogdanm 89:552587b429a1 680 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
bogdanm 89:552587b429a1 681 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
bogdanm 89:552587b429a1 682 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
bogdanm 89:552587b429a1 683 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm 89:552587b429a1 684 /**
bogdanm 89:552587b429a1 685 * @}
bogdanm 89:552587b429a1 686 */
bogdanm 89:552587b429a1 687
bogdanm 89:552587b429a1 688 /** @defgroup TIM_Clock_Polarity
bogdanm 89:552587b429a1 689 * @{
bogdanm 89:552587b429a1 690 */
bogdanm 89:552587b429a1 691 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
bogdanm 89:552587b429a1 692 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
bogdanm 89:552587b429a1 693 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
bogdanm 89:552587b429a1 694 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
bogdanm 89:552587b429a1 695 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
bogdanm 89:552587b429a1 696
bogdanm 89:552587b429a1 697 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
bogdanm 89:552587b429a1 698 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
bogdanm 89:552587b429a1 699 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
bogdanm 89:552587b429a1 700 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
bogdanm 89:552587b429a1 701 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm 89:552587b429a1 702 /**
bogdanm 89:552587b429a1 703 * @}
bogdanm 89:552587b429a1 704 */
bogdanm 89:552587b429a1 705
bogdanm 89:552587b429a1 706 /** @defgroup TIM_Clock_Prescaler
bogdanm 89:552587b429a1 707 * @{
bogdanm 89:552587b429a1 708 */
bogdanm 89:552587b429a1 709 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 89:552587b429a1 710 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
bogdanm 89:552587b429a1 711 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
bogdanm 89:552587b429a1 712 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
bogdanm 89:552587b429a1 713
bogdanm 89:552587b429a1 714 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
bogdanm 89:552587b429a1 715 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
bogdanm 89:552587b429a1 716 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
bogdanm 89:552587b429a1 717 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm 89:552587b429a1 718 /**
bogdanm 89:552587b429a1 719 * @}
bogdanm 89:552587b429a1 720 */
bogdanm 89:552587b429a1 721
bogdanm 89:552587b429a1 722 /** @defgroup TIM_Clock_Filter
bogdanm 89:552587b429a1 723 * @{
bogdanm 89:552587b429a1 724 */
bogdanm 89:552587b429a1 725 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 89:552587b429a1 726 /**
bogdanm 89:552587b429a1 727 * @}
bogdanm 89:552587b429a1 728 */
bogdanm 89:552587b429a1 729
bogdanm 89:552587b429a1 730 /** @defgroup TIM_ClearInput_Source
bogdanm 89:552587b429a1 731 * @{
bogdanm 89:552587b429a1 732 */
bogdanm 89:552587b429a1 733 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm 89:552587b429a1 734 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 735
bogdanm 89:552587b429a1 736 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
bogdanm 89:552587b429a1 737 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm 89:552587b429a1 738 /**
bogdanm 89:552587b429a1 739 * @}
bogdanm 89:552587b429a1 740 */
bogdanm 89:552587b429a1 741
bogdanm 89:552587b429a1 742 /** @defgroup TIM_ClearInput_Polarity
bogdanm 89:552587b429a1 743 * @{
bogdanm 89:552587b429a1 744 */
bogdanm 89:552587b429a1 745 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
bogdanm 89:552587b429a1 746 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
bogdanm 89:552587b429a1 747 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
bogdanm 89:552587b429a1 748 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm 89:552587b429a1 749 /**
bogdanm 89:552587b429a1 750 * @}
bogdanm 89:552587b429a1 751 */
bogdanm 89:552587b429a1 752
bogdanm 89:552587b429a1 753 /** @defgroup TIM_ClearInput_Prescaler
bogdanm 89:552587b429a1 754 * @{
bogdanm 89:552587b429a1 755 */
bogdanm 89:552587b429a1 756 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 89:552587b429a1 757 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
bogdanm 89:552587b429a1 758 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
bogdanm 89:552587b429a1 759 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
bogdanm 89:552587b429a1 760 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
bogdanm 89:552587b429a1 761 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
bogdanm 89:552587b429a1 762 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
bogdanm 89:552587b429a1 763 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm 89:552587b429a1 764 /**
bogdanm 89:552587b429a1 765 * @}
bogdanm 89:552587b429a1 766 */
bogdanm 89:552587b429a1 767
bogdanm 89:552587b429a1 768 /** @defgroup TIM_ClearInput_Filter
bogdanm 89:552587b429a1 769 * @{
bogdanm 89:552587b429a1 770 */
bogdanm 89:552587b429a1 771 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 89:552587b429a1 772 /**
bogdanm 89:552587b429a1 773 * @}
bogdanm 89:552587b429a1 774 */
bogdanm 89:552587b429a1 775
bogdanm 92:4fc01daae5a5 776 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
bogdanm 92:4fc01daae5a5 777 * @{
bogdanm 92:4fc01daae5a5 778 */
bogdanm 92:4fc01daae5a5 779 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm 92:4fc01daae5a5 780 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 781
bogdanm 92:4fc01daae5a5 782 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
bogdanm 92:4fc01daae5a5 783 ((STATE) == TIM_OSSR_DISABLE))
bogdanm 92:4fc01daae5a5 784 /**
bogdanm 92:4fc01daae5a5 785 * @}
bogdanm 92:4fc01daae5a5 786 */
bogdanm 92:4fc01daae5a5 787
bogdanm 92:4fc01daae5a5 788 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm 92:4fc01daae5a5 789 * @{
bogdanm 92:4fc01daae5a5 790 */
bogdanm 92:4fc01daae5a5 791 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm 92:4fc01daae5a5 792 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 793
bogdanm 92:4fc01daae5a5 794 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
bogdanm 92:4fc01daae5a5 795 ((STATE) == TIM_OSSI_DISABLE))
bogdanm 92:4fc01daae5a5 796 /**
bogdanm 92:4fc01daae5a5 797 * @}
bogdanm 92:4fc01daae5a5 798 */
bogdanm 92:4fc01daae5a5 799 /** @defgroup TIM_Lock_level
bogdanm 92:4fc01daae5a5 800 * @{
bogdanm 92:4fc01daae5a5 801 */
bogdanm 92:4fc01daae5a5 802 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 803 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm 92:4fc01daae5a5 804 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm 92:4fc01daae5a5 805 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm 92:4fc01daae5a5 806
bogdanm 92:4fc01daae5a5 807 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
bogdanm 92:4fc01daae5a5 808 ((LEVEL) == TIM_LOCKLEVEL_1) || \
bogdanm 92:4fc01daae5a5 809 ((LEVEL) == TIM_LOCKLEVEL_2) || \
bogdanm 92:4fc01daae5a5 810 ((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm 92:4fc01daae5a5 811 /**
bogdanm 92:4fc01daae5a5 812 * @}
bogdanm 92:4fc01daae5a5 813 */
bogdanm 92:4fc01daae5a5 814 /** @defgroup TIM_Break_Input_enable_disable
bogdanm 92:4fc01daae5a5 815 * @{
bogdanm 92:4fc01daae5a5 816 */
bogdanm 92:4fc01daae5a5 817 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm 92:4fc01daae5a5 818 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 819
bogdanm 92:4fc01daae5a5 820 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
bogdanm 92:4fc01daae5a5 821 ((STATE) == TIM_BREAK_DISABLE))
bogdanm 92:4fc01daae5a5 822 /**
bogdanm 92:4fc01daae5a5 823 * @}
bogdanm 92:4fc01daae5a5 824 */
bogdanm 92:4fc01daae5a5 825 /** @defgroup TIM_Break_Polarity
bogdanm 92:4fc01daae5a5 826 * @{
bogdanm 92:4fc01daae5a5 827 */
bogdanm 92:4fc01daae5a5 828 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 829 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm 92:4fc01daae5a5 830
bogdanm 92:4fc01daae5a5 831 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
bogdanm 92:4fc01daae5a5 832 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm 92:4fc01daae5a5 833 /**
bogdanm 92:4fc01daae5a5 834 * @}
bogdanm 92:4fc01daae5a5 835 */
bogdanm 92:4fc01daae5a5 836 /** @defgroup TIM_AOE_Bit_Set_Reset
bogdanm 92:4fc01daae5a5 837 * @{
bogdanm 92:4fc01daae5a5 838 */
bogdanm 92:4fc01daae5a5 839 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm 92:4fc01daae5a5 840 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 841
bogdanm 92:4fc01daae5a5 842 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
bogdanm 92:4fc01daae5a5 843 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm 92:4fc01daae5a5 844 /**
bogdanm 92:4fc01daae5a5 845 * @}
bogdanm 92:4fc01daae5a5 846 */
bogdanm 92:4fc01daae5a5 847
bogdanm 92:4fc01daae5a5 848 /** @defgroup TIM_Master_Mode_Selection
bogdanm 92:4fc01daae5a5 849 * @{
bogdanm 92:4fc01daae5a5 850 */
bogdanm 92:4fc01daae5a5 851 #define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 852 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm 92:4fc01daae5a5 853 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm 92:4fc01daae5a5 854 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 92:4fc01daae5a5 855 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm 92:4fc01daae5a5 856 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
bogdanm 92:4fc01daae5a5 857 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
bogdanm 92:4fc01daae5a5 858 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 92:4fc01daae5a5 859
bogdanm 92:4fc01daae5a5 860 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
bogdanm 92:4fc01daae5a5 861 ((SOURCE) == TIM_TRGO_ENABLE) || \
bogdanm 92:4fc01daae5a5 862 ((SOURCE) == TIM_TRGO_UPDATE) || \
bogdanm 92:4fc01daae5a5 863 ((SOURCE) == TIM_TRGO_OC1) || \
bogdanm 92:4fc01daae5a5 864 ((SOURCE) == TIM_TRGO_OC1REF) || \
bogdanm 92:4fc01daae5a5 865 ((SOURCE) == TIM_TRGO_OC2REF) || \
bogdanm 92:4fc01daae5a5 866 ((SOURCE) == TIM_TRGO_OC3REF) || \
bogdanm 92:4fc01daae5a5 867 ((SOURCE) == TIM_TRGO_OC4REF))
bogdanm 92:4fc01daae5a5 868
bogdanm 92:4fc01daae5a5 869
bogdanm 92:4fc01daae5a5 870 /**
bogdanm 92:4fc01daae5a5 871 * @}
bogdanm 92:4fc01daae5a5 872 */
bogdanm 89:552587b429a1 873 /** @defgroup TIM_Slave_Mode
bogdanm 89:552587b429a1 874 * @{
bogdanm 89:552587b429a1 875 */
bogdanm 89:552587b429a1 876 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 877 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm 89:552587b429a1 878 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm 89:552587b429a1 879 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm 89:552587b429a1 880 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm 89:552587b429a1 881
bogdanm 89:552587b429a1 882 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
bogdanm 89:552587b429a1 883 ((MODE) == TIM_SLAVEMODE_GATED) || \
bogdanm 89:552587b429a1 884 ((MODE) == TIM_SLAVEMODE_RESET) || \
bogdanm 89:552587b429a1 885 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
bogdanm 89:552587b429a1 886 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm 89:552587b429a1 887 /**
bogdanm 89:552587b429a1 888 * @}
bogdanm 89:552587b429a1 889 */
bogdanm 89:552587b429a1 890
bogdanm 92:4fc01daae5a5 891 /** @defgroup TIM_Master_Slave_Mode
bogdanm 92:4fc01daae5a5 892 * @{
bogdanm 92:4fc01daae5a5 893 */
bogdanm 92:4fc01daae5a5 894
bogdanm 92:4fc01daae5a5 895 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm 92:4fc01daae5a5 896 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 92:4fc01daae5a5 897 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
bogdanm 92:4fc01daae5a5 898 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm 92:4fc01daae5a5 899 /**
bogdanm 92:4fc01daae5a5 900 * @}
bogdanm 92:4fc01daae5a5 901 */
bogdanm 89:552587b429a1 902 /** @defgroup TIM_Trigger_Selection
bogdanm 89:552587b429a1 903 * @{
bogdanm 89:552587b429a1 904 */
bogdanm 89:552587b429a1 905 #define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm 89:552587b429a1 906 #define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm 89:552587b429a1 907 #define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm 89:552587b429a1 908 #define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm 89:552587b429a1 909 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm 89:552587b429a1 910 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm 89:552587b429a1 911 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm 89:552587b429a1 912 #define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm 89:552587b429a1 913 #define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm 89:552587b429a1 914 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 89:552587b429a1 915 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 89:552587b429a1 916 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 89:552587b429a1 917 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 89:552587b429a1 918 ((SELECTION) == TIM_TS_TI1F_ED) || \
bogdanm 89:552587b429a1 919 ((SELECTION) == TIM_TS_TI1FP1) || \
bogdanm 89:552587b429a1 920 ((SELECTION) == TIM_TS_TI2FP2) || \
bogdanm 89:552587b429a1 921 ((SELECTION) == TIM_TS_ETRF))
bogdanm 89:552587b429a1 922 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 89:552587b429a1 923 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 89:552587b429a1 924 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 89:552587b429a1 925 ((SELECTION) == TIM_TS_ITR3))
bogdanm 89:552587b429a1 926 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 89:552587b429a1 927 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 89:552587b429a1 928 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 89:552587b429a1 929 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 89:552587b429a1 930 ((SELECTION) == TIM_TS_NONE))
bogdanm 89:552587b429a1 931 /**
bogdanm 89:552587b429a1 932 * @}
bogdanm 89:552587b429a1 933 */
bogdanm 89:552587b429a1 934
bogdanm 89:552587b429a1 935 /** @defgroup TIM_Trigger_Polarity
bogdanm 89:552587b429a1 936 * @{
bogdanm 89:552587b429a1 937 */
bogdanm 89:552587b429a1 938 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 89:552587b429a1 939 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 89:552587b429a1 940 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 89:552587b429a1 941 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 89:552587b429a1 942 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 89:552587b429a1 943
bogdanm 89:552587b429a1 944 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
bogdanm 89:552587b429a1 945 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
bogdanm 89:552587b429a1 946 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
bogdanm 89:552587b429a1 947 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
bogdanm 89:552587b429a1 948 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm 89:552587b429a1 949 /**
bogdanm 89:552587b429a1 950 * @}
bogdanm 89:552587b429a1 951 */
bogdanm 89:552587b429a1 952
bogdanm 89:552587b429a1 953 /** @defgroup TIM_Trigger_Prescaler
bogdanm 89:552587b429a1 954 * @{
bogdanm 89:552587b429a1 955 */
bogdanm 89:552587b429a1 956 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 89:552587b429a1 957 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
bogdanm 89:552587b429a1 958 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
bogdanm 89:552587b429a1 959 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
bogdanm 89:552587b429a1 960
bogdanm 89:552587b429a1 961 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
bogdanm 89:552587b429a1 962 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
bogdanm 89:552587b429a1 963 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
bogdanm 89:552587b429a1 964 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm 89:552587b429a1 965 /**
bogdanm 89:552587b429a1 966 * @}
bogdanm 89:552587b429a1 967 */
bogdanm 89:552587b429a1 968
bogdanm 89:552587b429a1 969 /** @defgroup TIM_Trigger_Filter
bogdanm 89:552587b429a1 970 * @{
bogdanm 89:552587b429a1 971 */
bogdanm 89:552587b429a1 972 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 89:552587b429a1 973 /**
bogdanm 89:552587b429a1 974 * @}
bogdanm 89:552587b429a1 975 */
bogdanm 89:552587b429a1 976
bogdanm 89:552587b429a1 977 /** @defgroup TIM_TI1_Selection
bogdanm 89:552587b429a1 978 * @{
bogdanm 89:552587b429a1 979 */
bogdanm 89:552587b429a1 980 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm 89:552587b429a1 981 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm 89:552587b429a1 982
bogdanm 89:552587b429a1 983 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
bogdanm 89:552587b429a1 984 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm 89:552587b429a1 985 /**
bogdanm 89:552587b429a1 986 * @}
bogdanm 89:552587b429a1 987 */
bogdanm 89:552587b429a1 988
bogdanm 89:552587b429a1 989 /** @defgroup TIM_DMA_Base_address
bogdanm 89:552587b429a1 990 * @{
bogdanm 89:552587b429a1 991 */
bogdanm 89:552587b429a1 992 #define TIM_DMABase_CR1 (0x00000000)
bogdanm 89:552587b429a1 993 #define TIM_DMABase_CR2 (0x00000001)
bogdanm 89:552587b429a1 994 #define TIM_DMABase_SMCR (0x00000002)
bogdanm 89:552587b429a1 995 #define TIM_DMABase_DIER (0x00000003)
bogdanm 89:552587b429a1 996 #define TIM_DMABase_SR (0x00000004)
bogdanm 89:552587b429a1 997 #define TIM_DMABase_EGR (0x00000005)
bogdanm 89:552587b429a1 998 #define TIM_DMABase_CCMR1 (0x00000006)
bogdanm 89:552587b429a1 999 #define TIM_DMABase_CCMR2 (0x00000007)
bogdanm 89:552587b429a1 1000 #define TIM_DMABase_CCER (0x00000008)
bogdanm 89:552587b429a1 1001 #define TIM_DMABase_CNT (0x00000009)
bogdanm 89:552587b429a1 1002 #define TIM_DMABase_PSC (0x0000000A)
bogdanm 89:552587b429a1 1003 #define TIM_DMABase_ARR (0x0000000B)
bogdanm 89:552587b429a1 1004 #define TIM_DMABase_RCR (0x0000000C)
bogdanm 89:552587b429a1 1005 #define TIM_DMABase_CCR1 (0x0000000D)
bogdanm 89:552587b429a1 1006 #define TIM_DMABase_CCR2 (0x0000000E)
bogdanm 89:552587b429a1 1007 #define TIM_DMABase_CCR3 (0x0000000F)
bogdanm 89:552587b429a1 1008 #define TIM_DMABase_CCR4 (0x00000010)
bogdanm 89:552587b429a1 1009 #define TIM_DMABase_BDTR (0x00000011)
bogdanm 89:552587b429a1 1010 #define TIM_DMABase_DCR (0x00000012)
bogdanm 89:552587b429a1 1011 #define TIM_DMABase_OR (0x00000013)
bogdanm 89:552587b429a1 1012 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
bogdanm 89:552587b429a1 1013 ((BASE) == TIM_DMABase_CR2) || \
bogdanm 89:552587b429a1 1014 ((BASE) == TIM_DMABase_SMCR) || \
bogdanm 89:552587b429a1 1015 ((BASE) == TIM_DMABase_DIER) || \
bogdanm 89:552587b429a1 1016 ((BASE) == TIM_DMABase_SR) || \
bogdanm 89:552587b429a1 1017 ((BASE) == TIM_DMABase_EGR) || \
bogdanm 89:552587b429a1 1018 ((BASE) == TIM_DMABase_CCMR1) || \
bogdanm 89:552587b429a1 1019 ((BASE) == TIM_DMABase_CCMR2) || \
bogdanm 89:552587b429a1 1020 ((BASE) == TIM_DMABase_CCER) || \
bogdanm 89:552587b429a1 1021 ((BASE) == TIM_DMABase_CNT) || \
bogdanm 89:552587b429a1 1022 ((BASE) == TIM_DMABase_PSC) || \
bogdanm 89:552587b429a1 1023 ((BASE) == TIM_DMABase_ARR) || \
bogdanm 89:552587b429a1 1024 ((BASE) == TIM_DMABase_RCR) || \
bogdanm 89:552587b429a1 1025 ((BASE) == TIM_DMABase_CCR1) || \
bogdanm 89:552587b429a1 1026 ((BASE) == TIM_DMABase_CCR2) || \
bogdanm 89:552587b429a1 1027 ((BASE) == TIM_DMABase_CCR3) || \
bogdanm 89:552587b429a1 1028 ((BASE) == TIM_DMABase_CCR4) || \
bogdanm 89:552587b429a1 1029 ((BASE) == TIM_DMABase_BDTR) || \
bogdanm 89:552587b429a1 1030 ((BASE) == TIM_DMABase_DCR) || \
bogdanm 89:552587b429a1 1031 ((BASE) == TIM_DMABase_OR))
bogdanm 89:552587b429a1 1032 /**
bogdanm 89:552587b429a1 1033 * @}
bogdanm 89:552587b429a1 1034 */
bogdanm 89:552587b429a1 1035
bogdanm 89:552587b429a1 1036 /** @defgroup TIM_DMA_Burst_Length
bogdanm 89:552587b429a1 1037 * @{
bogdanm 89:552587b429a1 1038 */
bogdanm 89:552587b429a1 1039 #define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm 89:552587b429a1 1040 #define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm 89:552587b429a1 1041 #define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm 89:552587b429a1 1042 #define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm 89:552587b429a1 1043 #define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm 89:552587b429a1 1044 #define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm 89:552587b429a1 1045 #define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm 89:552587b429a1 1046 #define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm 89:552587b429a1 1047 #define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm 89:552587b429a1 1048 #define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm 89:552587b429a1 1049 #define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm 89:552587b429a1 1050 #define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm 89:552587b429a1 1051 #define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm 89:552587b429a1 1052 #define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm 89:552587b429a1 1053 #define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm 89:552587b429a1 1054 #define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm 89:552587b429a1 1055 #define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm 89:552587b429a1 1056 #define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm 89:552587b429a1 1057 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
bogdanm 89:552587b429a1 1058 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
bogdanm 89:552587b429a1 1059 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
bogdanm 89:552587b429a1 1060 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
bogdanm 89:552587b429a1 1061 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
bogdanm 89:552587b429a1 1062 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
bogdanm 89:552587b429a1 1063 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
bogdanm 89:552587b429a1 1064 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
bogdanm 89:552587b429a1 1065 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
bogdanm 89:552587b429a1 1066 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
bogdanm 89:552587b429a1 1067 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
bogdanm 89:552587b429a1 1068 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
bogdanm 89:552587b429a1 1069 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
bogdanm 89:552587b429a1 1070 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
bogdanm 89:552587b429a1 1071 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
bogdanm 89:552587b429a1 1072 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
bogdanm 89:552587b429a1 1073 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
bogdanm 89:552587b429a1 1074 ((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm 89:552587b429a1 1075 /**
bogdanm 89:552587b429a1 1076 * @}
bogdanm 89:552587b429a1 1077 */
bogdanm 89:552587b429a1 1078
bogdanm 89:552587b429a1 1079 /** @defgroup TIM_Input_Capture_Filer_Value
bogdanm 89:552587b429a1 1080 * @{
bogdanm 89:552587b429a1 1081 */
bogdanm 89:552587b429a1 1082 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 89:552587b429a1 1083 /**
bogdanm 89:552587b429a1 1084 * @}
bogdanm 89:552587b429a1 1085 */
bogdanm 89:552587b429a1 1086
bogdanm 89:552587b429a1 1087 /** @defgroup DMA_Handle_index
bogdanm 89:552587b429a1 1088 * @{
bogdanm 89:552587b429a1 1089 */
bogdanm 89:552587b429a1 1090 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
bogdanm 89:552587b429a1 1091 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
bogdanm 89:552587b429a1 1092 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
bogdanm 89:552587b429a1 1093 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
bogdanm 89:552587b429a1 1094 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
bogdanm 89:552587b429a1 1095 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
bogdanm 89:552587b429a1 1096 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
bogdanm 89:552587b429a1 1097 /**
bogdanm 89:552587b429a1 1098 * @}
bogdanm 89:552587b429a1 1099 */
bogdanm 89:552587b429a1 1100
bogdanm 89:552587b429a1 1101 /** @defgroup Channel_CC_State
bogdanm 89:552587b429a1 1102 * @{
bogdanm 89:552587b429a1 1103 */
bogdanm 89:552587b429a1 1104 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm 89:552587b429a1 1105 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 1106 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm 89:552587b429a1 1107 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm 89:552587b429a1 1108 /**
bogdanm 89:552587b429a1 1109 * @}
bogdanm 89:552587b429a1 1110 */
bogdanm 89:552587b429a1 1111
bogdanm 89:552587b429a1 1112 /**
bogdanm 89:552587b429a1 1113 * @}
bogdanm 89:552587b429a1 1114 */
bogdanm 89:552587b429a1 1115
bogdanm 89:552587b429a1 1116 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 1117
bogdanm 89:552587b429a1 1118 /** @brief Reset TIM handle state
bogdanm 89:552587b429a1 1119 * @param __HANDLE__: TIM handle
bogdanm 89:552587b429a1 1120 * @retval None
bogdanm 89:552587b429a1 1121 */
bogdanm 89:552587b429a1 1122 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm 89:552587b429a1 1123
bogdanm 89:552587b429a1 1124 /**
bogdanm 89:552587b429a1 1125 * @brief Enable the TIM peripheral.
bogdanm 89:552587b429a1 1126 * @param __HANDLE__: TIM handle
bogdanm 89:552587b429a1 1127 * @retval None
bogdanm 89:552587b429a1 1128 */
bogdanm 89:552587b429a1 1129 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
bogdanm 89:552587b429a1 1130
bogdanm 89:552587b429a1 1131 /**
bogdanm 89:552587b429a1 1132 * @brief Enable the TIM main Output.
bogdanm 89:552587b429a1 1133 * @param __HANDLE__: TIM handle
bogdanm 89:552587b429a1 1134 * @retval None
bogdanm 89:552587b429a1 1135 */
bogdanm 89:552587b429a1 1136 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
bogdanm 89:552587b429a1 1137
bogdanm 89:552587b429a1 1138
bogdanm 89:552587b429a1 1139 /* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm 89:552587b429a1 1140 channels have been disabled */
bogdanm 89:552587b429a1 1141 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
bogdanm 89:552587b429a1 1142 #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
bogdanm 89:552587b429a1 1143
bogdanm 89:552587b429a1 1144 /**
bogdanm 89:552587b429a1 1145 * @brief Disable the TIM peripheral.
bogdanm 89:552587b429a1 1146 * @param __HANDLE__: TIM handle
bogdanm 89:552587b429a1 1147 * @retval None
bogdanm 89:552587b429a1 1148 */
bogdanm 89:552587b429a1 1149 #define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm 89:552587b429a1 1150 do { \
bogdanm 89:552587b429a1 1151 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 89:552587b429a1 1152 { \
bogdanm 89:552587b429a1 1153 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 89:552587b429a1 1154 { \
bogdanm 89:552587b429a1 1155 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm 89:552587b429a1 1156 } \
bogdanm 89:552587b429a1 1157 } \
bogdanm 89:552587b429a1 1158 } while(0)
bogdanm 89:552587b429a1 1159
bogdanm 89:552587b429a1 1160 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
bogdanm 89:552587b429a1 1161 channels have been disabled */
bogdanm 89:552587b429a1 1162 /**
bogdanm 89:552587b429a1 1163 * @brief Disable the TIM main Output.
bogdanm 89:552587b429a1 1164 * @param __HANDLE__: TIM handle
bogdanm 89:552587b429a1 1165 * @retval None
bogdanm 89:552587b429a1 1166 */
bogdanm 89:552587b429a1 1167 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm 89:552587b429a1 1168 do { \
bogdanm 89:552587b429a1 1169 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 89:552587b429a1 1170 { \
bogdanm 89:552587b429a1 1171 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 89:552587b429a1 1172 { \
bogdanm 89:552587b429a1 1173 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm 89:552587b429a1 1174 } \
bogdanm 89:552587b429a1 1175 } \
bogdanm 89:552587b429a1 1176 } while(0)
bogdanm 89:552587b429a1 1177
bogdanm 89:552587b429a1 1178 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
bogdanm 89:552587b429a1 1179 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
bogdanm 89:552587b429a1 1180 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 1181 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm 89:552587b429a1 1182 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 1183 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm 89:552587b429a1 1184
bogdanm 89:552587b429a1 1185 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 92:4fc01daae5a5 1186 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm 89:552587b429a1 1187
bogdanm 89:552587b429a1 1188 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm 92:4fc01daae5a5 1189 #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm 89:552587b429a1 1190
bogdanm 89:552587b429a1 1191 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 89:552587b429a1 1192 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
bogdanm 89:552587b429a1 1193 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
bogdanm 89:552587b429a1 1194 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
bogdanm 89:552587b429a1 1195 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
bogdanm 89:552587b429a1 1196
bogdanm 89:552587b429a1 1197 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm 89:552587b429a1 1198 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm 89:552587b429a1 1199 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm 89:552587b429a1 1200 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm 89:552587b429a1 1201 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm 89:552587b429a1 1202
bogdanm 89:552587b429a1 1203 /**
bogdanm 89:552587b429a1 1204 * @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm 89:552587b429a1 1205 * calling another time ConfigChannel function.
bogdanm 89:552587b429a1 1206 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1207 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 89:552587b429a1 1208 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1209 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 89:552587b429a1 1210 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 89:552587b429a1 1211 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 89:552587b429a1 1212 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 89:552587b429a1 1213 * @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm 89:552587b429a1 1214 * @retval None
bogdanm 89:552587b429a1 1215 */
bogdanm 89:552587b429a1 1216 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm 89:552587b429a1 1217 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm 89:552587b429a1 1218
bogdanm 89:552587b429a1 1219 /**
bogdanm 89:552587b429a1 1220 * @brief Gets the TIM Capture Compare Register value on runtime
bogdanm 89:552587b429a1 1221 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1222 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm 89:552587b429a1 1223 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1224 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm 89:552587b429a1 1225 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm 89:552587b429a1 1226 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm 89:552587b429a1 1227 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm 89:552587b429a1 1228 * @retval None
bogdanm 89:552587b429a1 1229 */
bogdanm 89:552587b429a1 1230 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm 89:552587b429a1 1231 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm 89:552587b429a1 1232
bogdanm 89:552587b429a1 1233 /**
bogdanm 89:552587b429a1 1234 * @brief Sets the TIM Counter Register value on runtime.
bogdanm 89:552587b429a1 1235 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1236 * @param __COUNTER__: specifies the Counter register new value.
bogdanm 89:552587b429a1 1237 * @retval None
bogdanm 89:552587b429a1 1238 */
bogdanm 89:552587b429a1 1239 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm 89:552587b429a1 1240
bogdanm 89:552587b429a1 1241 /**
bogdanm 89:552587b429a1 1242 * @brief Gets the TIM Counter Register value on runtime.
bogdanm 89:552587b429a1 1243 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1244 * @retval None
bogdanm 89:552587b429a1 1245 */
bogdanm 89:552587b429a1 1246 #define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm 89:552587b429a1 1247
bogdanm 89:552587b429a1 1248 /**
bogdanm 89:552587b429a1 1249 * @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm 89:552587b429a1 1250 * another time any Init function.
bogdanm 89:552587b429a1 1251 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1252 * @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm 89:552587b429a1 1253 * @retval None
bogdanm 89:552587b429a1 1254 */
bogdanm 89:552587b429a1 1255 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm 89:552587b429a1 1256 do{ \
bogdanm 89:552587b429a1 1257 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm 89:552587b429a1 1258 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm 89:552587b429a1 1259 } while(0)
bogdanm 89:552587b429a1 1260 /**
bogdanm 89:552587b429a1 1261 * @brief Gets the TIM Autoreload Register value on runtime
bogdanm 89:552587b429a1 1262 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1263 * @retval None
bogdanm 89:552587b429a1 1264 */
bogdanm 89:552587b429a1 1265 #define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm 89:552587b429a1 1266
bogdanm 89:552587b429a1 1267 /**
bogdanm 89:552587b429a1 1268 * @brief Sets the TIM Clock Division value on runtime without calling
bogdanm 89:552587b429a1 1269 * another time any Init function.
bogdanm 89:552587b429a1 1270 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1271 * @param __CKD__: specifies the clock division value.
bogdanm 89:552587b429a1 1272 * This parameter can be one of the following value:
bogdanm 89:552587b429a1 1273 * @arg TIM_CLOCKDIVISION_DIV1
bogdanm 89:552587b429a1 1274 * @arg TIM_CLOCKDIVISION_DIV2
bogdanm 89:552587b429a1 1275 * @arg TIM_CLOCKDIVISION_DIV4
bogdanm 89:552587b429a1 1276 * @retval None
bogdanm 89:552587b429a1 1277 */
bogdanm 89:552587b429a1 1278 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm 89:552587b429a1 1279 do{ \
bogdanm 89:552587b429a1 1280 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm 89:552587b429a1 1281 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
bogdanm 89:552587b429a1 1282 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm 89:552587b429a1 1283 } while(0)
bogdanm 89:552587b429a1 1284 /**
bogdanm 89:552587b429a1 1285 * @brief Gets the TIM Clock Division value on runtime
bogdanm 89:552587b429a1 1286 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1287 * @retval None
bogdanm 89:552587b429a1 1288 */
bogdanm 89:552587b429a1 1289 #define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm 89:552587b429a1 1290
bogdanm 89:552587b429a1 1291 /**
bogdanm 89:552587b429a1 1292 * @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm 89:552587b429a1 1293 * another time HAL_TIM_IC_ConfigChannel() function.
bogdanm 89:552587b429a1 1294 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1295 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 89:552587b429a1 1296 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1297 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 89:552587b429a1 1298 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 89:552587b429a1 1299 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 89:552587b429a1 1300 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 89:552587b429a1 1301 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm 89:552587b429a1 1302 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1303 * @arg TIM_ICPSC_DIV1: no prescaler
bogdanm 89:552587b429a1 1304 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm 89:552587b429a1 1305 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm 89:552587b429a1 1306 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm 89:552587b429a1 1307 * @retval None
bogdanm 89:552587b429a1 1308 */
bogdanm 89:552587b429a1 1309 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 89:552587b429a1 1310 do{ \
bogdanm 89:552587b429a1 1311 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm 89:552587b429a1 1312 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm 89:552587b429a1 1313 } while(0)
bogdanm 89:552587b429a1 1314
bogdanm 89:552587b429a1 1315 /**
bogdanm 89:552587b429a1 1316 * @brief Gets the TIM Input Capture prescaler on runtime
bogdanm 89:552587b429a1 1317 * @param __HANDLE__: TIM handle.
bogdanm 89:552587b429a1 1318 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 89:552587b429a1 1319 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1320 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm 89:552587b429a1 1321 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm 89:552587b429a1 1322 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm 89:552587b429a1 1323 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm 89:552587b429a1 1324 * @retval None
bogdanm 89:552587b429a1 1325 */
bogdanm 89:552587b429a1 1326 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm 89:552587b429a1 1327 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm 89:552587b429a1 1328 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm 89:552587b429a1 1329 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm 89:552587b429a1 1330 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm 89:552587b429a1 1331 /**
bogdanm 89:552587b429a1 1332 * @}
bogdanm 89:552587b429a1 1333 */
bogdanm 89:552587b429a1 1334
bogdanm 89:552587b429a1 1335 /* Include TIM HAL Extension module */
bogdanm 89:552587b429a1 1336 #include "stm32f4xx_hal_tim_ex.h"
bogdanm 89:552587b429a1 1337
bogdanm 89:552587b429a1 1338 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 1339
bogdanm 89:552587b429a1 1340 /* Time Base functions ********************************************************/
bogdanm 89:552587b429a1 1341 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1342 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1343 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1344 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1345 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 1346 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1347 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1348 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 1349 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1350 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1351 /* Non-Blocking mode: DMA */
bogdanm 89:552587b429a1 1352 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
bogdanm 89:552587b429a1 1353 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1354
bogdanm 89:552587b429a1 1355 /* Timer Output Compare functions **********************************************/
bogdanm 89:552587b429a1 1356 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1357 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1358 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1359 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1360 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 1361 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1362 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1363 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 1364 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1365 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1366 /* Non-Blocking mode: DMA */
bogdanm 89:552587b429a1 1367 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 89:552587b429a1 1368 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1369
bogdanm 89:552587b429a1 1370 /* Timer PWM functions *********************************************************/
bogdanm 89:552587b429a1 1371 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1372 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1373 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1374 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1375 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 1376 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1377 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1378 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 1379 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1380 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1381 /* Non-Blocking mode: DMA */
bogdanm 89:552587b429a1 1382 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 89:552587b429a1 1383 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1384
bogdanm 89:552587b429a1 1385 /* Timer Input Capture functions ***********************************************/
bogdanm 89:552587b429a1 1386 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1387 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1388 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1389 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1390 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 1391 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1392 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1393 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 1394 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1395 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1396 /* Non-Blocking mode: DMA */
bogdanm 89:552587b429a1 1397 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 89:552587b429a1 1398 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1399
bogdanm 89:552587b429a1 1400 /* Timer One Pulse functions ***************************************************/
bogdanm 89:552587b429a1 1401 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm 89:552587b429a1 1402 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1403 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1404 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1405 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 1406 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 89:552587b429a1 1407 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 89:552587b429a1 1408
bogdanm 89:552587b429a1 1409 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 1410 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 89:552587b429a1 1411 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 89:552587b429a1 1412
bogdanm 89:552587b429a1 1413 /* Timer Encoder functions *****************************************************/
bogdanm 89:552587b429a1 1414 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
bogdanm 89:552587b429a1 1415 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1416 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1417 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1418 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 1419 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1420 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1421 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 1422 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1423 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1424 /* Non-Blocking mode: DMA */
bogdanm 89:552587b429a1 1425 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
bogdanm 89:552587b429a1 1426 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1427
bogdanm 89:552587b429a1 1428 /* Interrupt Handler functions **********************************************/
bogdanm 89:552587b429a1 1429 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1430
bogdanm 89:552587b429a1 1431 /* Control functions *********************************************************/
bogdanm 89:552587b429a1 1432 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 89:552587b429a1 1433 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 89:552587b429a1 1434 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 89:552587b429a1 1435 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm 89:552587b429a1 1436 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
bogdanm 89:552587b429a1 1437 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
bogdanm 89:552587b429a1 1438 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm 89:552587b429a1 1439 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm 89:552587b429a1 1440 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 89:552587b429a1 1441 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 89:552587b429a1 1442 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 89:552587b429a1 1443 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 89:552587b429a1 1444 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 89:552587b429a1 1445 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 89:552587b429a1 1446 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm 89:552587b429a1 1447 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 89:552587b429a1 1448
bogdanm 89:552587b429a1 1449 /* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm 89:552587b429a1 1450 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1451 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1452 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1453 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1454 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1455 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1456
bogdanm 89:552587b429a1 1457 /* Peripheral State functions **************************************************/
bogdanm 89:552587b429a1 1458 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1459 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1460 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1461 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1462 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1463 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm 89:552587b429a1 1464
bogdanm 89:552587b429a1 1465 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
bogdanm 89:552587b429a1 1466 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm 89:552587b429a1 1467 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 89:552587b429a1 1468 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 1469 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 1470 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 1471 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm 89:552587b429a1 1472
bogdanm 89:552587b429a1 1473 /**
bogdanm 89:552587b429a1 1474 * @}
bogdanm 89:552587b429a1 1475 */
bogdanm 89:552587b429a1 1476
bogdanm 89:552587b429a1 1477 /**
bogdanm 89:552587b429a1 1478 * @}
bogdanm 89:552587b429a1 1479 */
bogdanm 89:552587b429a1 1480
bogdanm 89:552587b429a1 1481 #ifdef __cplusplus
bogdanm 89:552587b429a1 1482 }
bogdanm 89:552587b429a1 1483 #endif
bogdanm 89:552587b429a1 1484
bogdanm 89:552587b429a1 1485 #endif /* __STM32F4xx_HAL_TIM_H */
bogdanm 89:552587b429a1 1486
bogdanm 89:552587b429a1 1487 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/